2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 int mce_disabled __read_mostly;
51 #define MISC_MCELOG_MINOR 227
53 #define SPINUNIT 100 /* 100ns */
57 DEFINE_PER_CPU(unsigned, mce_exception_count);
61 * 0: always panic on uncorrected errors, log corrected errors
62 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
63 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
64 * 3: never panic or SIGBUS, log all errors (for testing only)
66 static int tolerant __read_mostly = 1;
67 static int banks __read_mostly;
68 static int rip_msr __read_mostly;
69 static int mce_bootlog __read_mostly = -1;
70 static int monarch_timeout __read_mostly = -1;
71 static int mce_panic_timeout __read_mostly;
72 static int mce_dont_log_ce __read_mostly;
73 int mce_cmci_disabled __read_mostly;
74 int mce_ignore_ce __read_mostly;
75 int mce_ser __read_mostly;
77 struct mce_bank *mce_banks __read_mostly;
79 /* User mode helper program triggered by machine check event */
80 static unsigned long mce_need_notify;
81 static char mce_helper[128];
82 static char *mce_helper_argv[2] = { mce_helper, NULL };
84 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static int cpu_missing;
88 static void default_decode_mce(struct mce *m)
90 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
91 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
95 * CPU/chipset specific EDAC code can register a callback here to print
96 * MCE errors in a human-readable form:
98 void (*x86_mce_decode_callback)(struct mce *m) = default_decode_mce;
99 EXPORT_SYMBOL(x86_mce_decode_callback);
101 /* MCA banks polled by the period polling timer for corrected events */
102 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
103 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
106 static DEFINE_PER_CPU(struct work_struct, mce_work);
108 /* Do initial initialization of a struct mce */
109 void mce_setup(struct mce *m)
111 memset(m, 0, sizeof(struct mce));
112 m->cpu = m->extcpu = smp_processor_id();
114 /* We hope get_seconds stays lockless */
115 m->time = get_seconds();
116 m->cpuvendor = boot_cpu_data.x86_vendor;
117 m->cpuid = cpuid_eax(1);
119 m->socketid = cpu_data(m->extcpu).phys_proc_id;
121 m->apicid = cpu_data(m->extcpu).initial_apicid;
122 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
125 DEFINE_PER_CPU(struct mce, injectm);
126 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
129 * Lockless MCE logging infrastructure.
130 * This avoids deadlocks on printk locks without having to break locks. Also
131 * separate MCEs from kernel messages to avoid bogus bug reports.
134 static struct mce_log mcelog = {
135 .signature = MCE_LOG_SIGNATURE,
137 .recordlen = sizeof(struct mce),
140 void mce_log(struct mce *mce)
142 unsigned next, entry;
147 entry = rcu_dereference(mcelog.next);
150 * When the buffer fills up discard new entries.
151 * Assume that the earlier errors are the more
154 if (entry >= MCE_LOG_LEN) {
155 set_bit(MCE_OVERFLOW,
156 (unsigned long *)&mcelog.flags);
159 /* Old left over entry. Skip: */
160 if (mcelog.entry[entry].finished) {
168 if (cmpxchg(&mcelog.next, entry, next) == entry)
171 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
173 mcelog.entry[entry].finished = 1;
177 set_bit(0, &mce_need_notify);
180 static void print_mce(struct mce *m)
182 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
183 m->extcpu, m->mcgstatus, m->bank, m->status);
186 pr_emerg("RIP%s %02x:<%016Lx> ",
187 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
190 if (m->cs == __KERNEL_CS)
191 print_symbol("{%s}", m->ip);
195 pr_emerg("TSC %llx ", m->tsc);
197 pr_cont("ADDR %llx ", m->addr);
199 pr_cont("MISC %llx ", m->misc);
202 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
203 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
206 * Print out human-readable details about the MCE error,
207 * (if the CPU has an implementation for that):
209 x86_mce_decode_callback(m);
212 static void print_mce_head(void)
214 pr_emerg("\nHARDWARE ERROR\n");
217 static void print_mce_tail(void)
219 pr_emerg("This is not a software problem!\n");
222 #define PANIC_TIMEOUT 5 /* 5 seconds */
224 static atomic_t mce_paniced;
226 static int fake_panic;
227 static atomic_t mce_fake_paniced;
229 /* Panic in progress. Enable interrupts and wait for final IPI */
230 static void wait_for_panic(void)
232 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
236 while (timeout-- > 0)
238 if (panic_timeout == 0)
239 panic_timeout = mce_panic_timeout;
240 panic("Panicing machine check CPU died");
243 static void mce_panic(char *msg, struct mce *final, char *exp)
249 * Make sure only one CPU runs in machine check panic
251 if (atomic_inc_return(&mce_paniced) > 1)
258 /* Don't log too much for fake panic */
259 if (atomic_inc_return(&mce_fake_paniced) > 1)
263 /* First print corrected ones that are still unlogged */
264 for (i = 0; i < MCE_LOG_LEN; i++) {
265 struct mce *m = &mcelog.entry[i];
266 if (!(m->status & MCI_STATUS_VAL))
268 if (!(m->status & MCI_STATUS_UC))
271 /* Now print uncorrected but with the final one last */
272 for (i = 0; i < MCE_LOG_LEN; i++) {
273 struct mce *m = &mcelog.entry[i];
274 if (!(m->status & MCI_STATUS_VAL))
276 if (!(m->status & MCI_STATUS_UC))
278 if (!final || memcmp(m, final, sizeof(struct mce)))
284 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
287 printk(KERN_EMERG "Machine check: %s\n", exp);
289 if (panic_timeout == 0)
290 panic_timeout = mce_panic_timeout;
293 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
296 /* Support code for software error injection */
298 static int msr_to_offset(u32 msr)
300 unsigned bank = __get_cpu_var(injectm.bank);
303 return offsetof(struct mce, ip);
304 if (msr == MSR_IA32_MCx_STATUS(bank))
305 return offsetof(struct mce, status);
306 if (msr == MSR_IA32_MCx_ADDR(bank))
307 return offsetof(struct mce, addr);
308 if (msr == MSR_IA32_MCx_MISC(bank))
309 return offsetof(struct mce, misc);
310 if (msr == MSR_IA32_MCG_STATUS)
311 return offsetof(struct mce, mcgstatus);
315 /* MSR access wrappers used for error injection */
316 static u64 mce_rdmsrl(u32 msr)
320 if (__get_cpu_var(injectm).finished) {
321 int offset = msr_to_offset(msr);
325 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
328 if (rdmsrl_safe(msr, &v)) {
329 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
331 * Return zero in case the access faulted. This should
332 * not happen normally but can happen if the CPU does
333 * something weird, or if the code is buggy.
341 static void mce_wrmsrl(u32 msr, u64 v)
343 if (__get_cpu_var(injectm).finished) {
344 int offset = msr_to_offset(msr);
347 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
354 * Simple lockless ring to communicate PFNs from the exception handler with the
355 * process context work function. This is vastly simplified because there's
356 * only a single reader and a single writer.
358 #define MCE_RING_SIZE 16 /* we use one entry less */
361 unsigned short start;
363 unsigned long ring[MCE_RING_SIZE];
365 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
367 /* Runs with CPU affinity in workqueue */
368 static int mce_ring_empty(void)
370 struct mce_ring *r = &__get_cpu_var(mce_ring);
372 return r->start == r->end;
375 static int mce_ring_get(unsigned long *pfn)
382 r = &__get_cpu_var(mce_ring);
383 if (r->start == r->end)
385 *pfn = r->ring[r->start];
386 r->start = (r->start + 1) % MCE_RING_SIZE;
393 /* Always runs in MCE context with preempt off */
394 static int mce_ring_add(unsigned long pfn)
396 struct mce_ring *r = &__get_cpu_var(mce_ring);
399 next = (r->end + 1) % MCE_RING_SIZE;
400 if (next == r->start)
402 r->ring[r->end] = pfn;
408 int mce_available(struct cpuinfo_x86 *c)
412 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
415 static void mce_schedule_work(void)
417 if (!mce_ring_empty()) {
418 struct work_struct *work = &__get_cpu_var(mce_work);
419 if (!work_pending(work))
425 * Get the address of the instruction at the time of the machine check
428 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
431 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
439 m->ip = mce_rdmsrl(rip_msr);
442 #ifdef CONFIG_X86_LOCAL_APIC
444 * Called after interrupts have been reenabled again
445 * when a MCE happened during an interrupts off region
448 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
459 static void mce_report_event(struct pt_regs *regs)
461 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
464 * Triggering the work queue here is just an insurance
465 * policy in case the syscall exit notify handler
466 * doesn't run soon enough or ends up running on the
467 * wrong CPU (can happen when audit sleeps)
473 #ifdef CONFIG_X86_LOCAL_APIC
475 * Without APIC do not notify. The event will be picked
482 * When interrupts are disabled we cannot use
483 * kernel services safely. Trigger an self interrupt
484 * through the APIC to instead do the notification
485 * after interrupts are reenabled again.
487 apic->send_IPI_self(MCE_SELF_VECTOR);
490 * Wait for idle afterwards again so that we don't leave the
491 * APIC in a non idle state because the normal APIC writes
494 apic_wait_icr_idle();
498 DEFINE_PER_CPU(unsigned, mce_poll_count);
501 * Poll for corrected events or events that happened before reset.
502 * Those are just logged through /dev/mcelog.
504 * This is executed in standard interrupt context.
506 * Note: spec recommends to panic for fatal unsignalled
507 * errors here. However this would be quite problematic --
508 * we would need to reimplement the Monarch handling and
509 * it would mess up the exclusion between exception handler
510 * and poll hander -- * so we skip this for now.
511 * These cases should not happen anyways, or only when the CPU
512 * is already totally * confused. In this case it's likely it will
513 * not fully execute the machine check handler either.
515 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
520 __get_cpu_var(mce_poll_count)++;
524 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
525 for (i = 0; i < banks; i++) {
526 if (!mce_banks[i].ctl || !test_bit(i, *b))
535 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
536 if (!(m.status & MCI_STATUS_VAL))
540 * Uncorrected or signalled events are handled by the exception
541 * handler when it is enabled, so don't process those here.
543 * TBD do the same check for MCI_STATUS_EN here?
545 if (!(flags & MCP_UC) &&
546 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
549 if (m.status & MCI_STATUS_MISCV)
550 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
551 if (m.status & MCI_STATUS_ADDRV)
552 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
554 if (!(flags & MCP_TIMESTAMP))
557 * Don't get the IP here because it's unlikely to
558 * have anything to do with the actual error location.
560 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
562 add_taint(TAINT_MACHINE_CHECK);
566 * Clear state for this bank.
568 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
572 * Don't clear MCG_STATUS here because it's only defined for
578 EXPORT_SYMBOL_GPL(machine_check_poll);
581 * Do a quick check if any of the events requires a panic.
582 * This decides if we keep the events around or clear them.
584 static int mce_no_way_out(struct mce *m, char **msg)
588 for (i = 0; i < banks; i++) {
589 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
590 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
597 * Variable to establish order between CPUs while scanning.
598 * Each CPU spins initially until executing is equal its number.
600 static atomic_t mce_executing;
603 * Defines order of CPUs on entry. First CPU becomes Monarch.
605 static atomic_t mce_callin;
608 * Check if a timeout waiting for other CPUs happened.
610 static int mce_timed_out(u64 *t)
613 * The others already did panic for some reason.
614 * Bail out like in a timeout.
615 * rmb() to tell the compiler that system_state
616 * might have been modified by someone else.
619 if (atomic_read(&mce_paniced))
621 if (!monarch_timeout)
623 if ((s64)*t < SPINUNIT) {
624 /* CHECKME: Make panic default for 1 too? */
626 mce_panic("Timeout synchronizing machine check over CPUs",
633 touch_nmi_watchdog();
638 * The Monarch's reign. The Monarch is the CPU who entered
639 * the machine check handler first. It waits for the others to
640 * raise the exception too and then grades them. When any
641 * error is fatal panic. Only then let the others continue.
643 * The other CPUs entering the MCE handler will be controlled by the
644 * Monarch. They are called Subjects.
646 * This way we prevent any potential data corruption in a unrecoverable case
647 * and also makes sure always all CPU's errors are examined.
649 * Also this detects the case of a machine check event coming from outer
650 * space (not detected by any CPUs) In this case some external agent wants
651 * us to shut down, so panic too.
653 * The other CPUs might still decide to panic if the handler happens
654 * in a unrecoverable place, but in this case the system is in a semi-stable
655 * state and won't corrupt anything by itself. It's ok to let the others
656 * continue for a bit first.
658 * All the spin loops have timeouts; when a timeout happens a CPU
659 * typically elects itself to be Monarch.
661 static void mce_reign(void)
664 struct mce *m = NULL;
665 int global_worst = 0;
670 * This CPU is the Monarch and the other CPUs have run
671 * through their handlers.
672 * Grade the severity of the errors of all the CPUs.
674 for_each_possible_cpu(cpu) {
675 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
677 if (severity > global_worst) {
679 global_worst = severity;
680 m = &per_cpu(mces_seen, cpu);
685 * Cannot recover? Panic here then.
686 * This dumps all the mces in the log buffer and stops the
689 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
690 mce_panic("Fatal Machine check", m, msg);
693 * For UC somewhere we let the CPU who detects it handle it.
694 * Also must let continue the others, otherwise the handling
695 * CPU could deadlock on a lock.
699 * No machine check event found. Must be some external
700 * source or one CPU is hung. Panic.
702 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
703 mce_panic("Machine check from unknown source", NULL, NULL);
706 * Now clear all the mces_seen so that they don't reappear on
709 for_each_possible_cpu(cpu)
710 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
713 static atomic_t global_nwo;
716 * Start of Monarch synchronization. This waits until all CPUs have
717 * entered the exception handler and then determines if any of them
718 * saw a fatal event that requires panic. Then it executes them
719 * in the entry order.
720 * TBD double check parallel CPU hotunplug
722 static int mce_start(int *no_way_out)
725 int cpus = num_online_cpus();
726 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
731 atomic_add(*no_way_out, &global_nwo);
733 * global_nwo should be updated before mce_callin
736 order = atomic_inc_return(&mce_callin);
741 while (atomic_read(&mce_callin) != cpus) {
742 if (mce_timed_out(&timeout)) {
743 atomic_set(&global_nwo, 0);
750 * mce_callin should be read before global_nwo
756 * Monarch: Starts executing now, the others wait.
758 atomic_set(&mce_executing, 1);
761 * Subject: Now start the scanning loop one by one in
762 * the original callin order.
763 * This way when there are any shared banks it will be
764 * only seen by one CPU before cleared, avoiding duplicates.
766 while (atomic_read(&mce_executing) < order) {
767 if (mce_timed_out(&timeout)) {
768 atomic_set(&global_nwo, 0);
776 * Cache the global no_way_out state.
778 *no_way_out = atomic_read(&global_nwo);
784 * Synchronize between CPUs after main scanning loop.
785 * This invokes the bulk of the Monarch processing.
787 static int mce_end(int order)
790 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
798 * Allow others to run.
800 atomic_inc(&mce_executing);
803 /* CHECKME: Can this race with a parallel hotplug? */
804 int cpus = num_online_cpus();
807 * Monarch: Wait for everyone to go through their scanning
810 while (atomic_read(&mce_executing) <= cpus) {
811 if (mce_timed_out(&timeout))
821 * Subject: Wait for Monarch to finish.
823 while (atomic_read(&mce_executing) != 0) {
824 if (mce_timed_out(&timeout))
830 * Don't reset anything. That's done by the Monarch.
836 * Reset all global state.
839 atomic_set(&global_nwo, 0);
840 atomic_set(&mce_callin, 0);
844 * Let others run again.
846 atomic_set(&mce_executing, 0);
851 * Check if the address reported by the CPU is in a format we can parse.
852 * It would be possible to add code for most other cases, but all would
853 * be somewhat complicated (e.g. segment offset would require an instruction
854 * parser). So only support physical addresses upto page granuality for now.
856 static int mce_usable_address(struct mce *m)
858 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
860 if ((m->misc & 0x3f) > PAGE_SHIFT)
862 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
867 static void mce_clear_state(unsigned long *toclear)
871 for (i = 0; i < banks; i++) {
872 if (test_bit(i, toclear))
873 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
878 * The actual machine check handler. This only handles real
879 * exceptions when something got corrupted coming in through int 18.
881 * This is executed in NMI context not subject to normal locking rules. This
882 * implies that most kernel services cannot be safely used. Don't even
883 * think about putting a printk in there!
885 * On Intel systems this is entered on all CPUs in parallel through
886 * MCE broadcast. However some CPUs might be broken beyond repair,
887 * so be always careful when synchronizing with others.
889 void do_machine_check(struct pt_regs *regs, long error_code)
891 struct mce m, *final;
896 * Establish sequential order between the CPUs entering the machine
901 * If no_way_out gets set, there is no safe way to recover from this
902 * MCE. If tolerant is cranked up, we'll try anyway.
906 * If kill_it gets set, there might be a way to recover from this
910 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
911 char *msg = "Unknown";
913 atomic_inc(&mce_entry);
915 __get_cpu_var(mce_exception_count)++;
917 if (notify_die(DIE_NMI, "machine check", regs, error_code,
918 18, SIGKILL) == NOTIFY_STOP)
925 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
926 final = &__get_cpu_var(mces_seen);
929 no_way_out = mce_no_way_out(&m, &msg);
934 * When no restart IP must always kill or panic.
936 if (!(m.mcgstatus & MCG_STATUS_RIPV))
940 * Go through all the banks in exclusion of the other CPUs.
941 * This way we don't report duplicated events on shared banks
942 * because the first one to see it will clear it.
944 order = mce_start(&no_way_out);
945 for (i = 0; i < banks; i++) {
946 __clear_bit(i, toclear);
947 if (!mce_banks[i].ctl)
954 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
955 if ((m.status & MCI_STATUS_VAL) == 0)
959 * Non uncorrected or non signaled errors are handled by
960 * machine_check_poll. Leave them alone, unless this panics.
962 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
967 * Set taint even when machine check was not enabled.
969 add_taint(TAINT_MACHINE_CHECK);
971 severity = mce_severity(&m, tolerant, NULL);
974 * When machine check was for corrected handler don't touch,
975 * unless we're panicing.
977 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
979 __set_bit(i, toclear);
980 if (severity == MCE_NO_SEVERITY) {
982 * Machine check event was not enabled. Clear, but
989 * Kill on action required.
991 if (severity == MCE_AR_SEVERITY)
994 if (m.status & MCI_STATUS_MISCV)
995 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
996 if (m.status & MCI_STATUS_ADDRV)
997 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1000 * Action optional error. Queue address for later processing.
1001 * When the ring overflows we just ignore the AO error.
1002 * RED-PEN add some logging mechanism when
1003 * usable_address or mce_add_ring fails.
1004 * RED-PEN don't ignore overflow for tolerant == 0
1006 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1007 mce_ring_add(m.addr >> PAGE_SHIFT);
1009 mce_get_rip(&m, regs);
1012 if (severity > worst) {
1019 mce_clear_state(toclear);
1022 * Do most of the synchronization with other CPUs.
1023 * When there's any problem use only local no_way_out state.
1025 if (mce_end(order) < 0)
1026 no_way_out = worst >= MCE_PANIC_SEVERITY;
1029 * If we have decided that we just CAN'T continue, and the user
1030 * has not set tolerant to an insane level, give up and die.
1032 * This is mainly used in the case when the system doesn't
1033 * support MCE broadcasting or it has been disabled.
1035 if (no_way_out && tolerant < 3)
1036 mce_panic("Fatal machine check on current CPU", final, msg);
1039 * If the error seems to be unrecoverable, something should be
1040 * done. Try to kill as little as possible. If we can kill just
1041 * one task, do that. If the user has set the tolerance very
1042 * high, don't try to do anything at all.
1045 if (kill_it && tolerant < 3)
1046 force_sig(SIGBUS, current);
1048 /* notify userspace ASAP */
1049 set_thread_flag(TIF_MCE_NOTIFY);
1052 mce_report_event(regs);
1053 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1055 atomic_dec(&mce_entry);
1058 EXPORT_SYMBOL_GPL(do_machine_check);
1060 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1061 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1063 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1067 * Called after mce notification in process context. This code
1068 * is allowed to sleep. Call the high level VM handler to process
1069 * any corrupted pages.
1070 * Assume that the work queue code only calls this one at a time
1072 * Note we don't disable preemption, so this code might run on the wrong
1073 * CPU. In this case the event is picked up by the scheduled work queue.
1074 * This is merely a fast path to expedite processing in some common
1077 void mce_notify_process(void)
1081 while (mce_ring_get(&pfn))
1082 memory_failure(pfn, MCE_VECTOR);
1085 static void mce_process_work(struct work_struct *dummy)
1087 mce_notify_process();
1090 #ifdef CONFIG_X86_MCE_INTEL
1092 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1093 * @cpu: The CPU on which the event occurred.
1094 * @status: Event status information
1096 * This function should be called by the thermal interrupt after the
1097 * event has been processed and the decision was made to log the event
1100 * The status parameter will be saved to the 'status' field of 'struct mce'
1101 * and historically has been the register value of the
1102 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1104 void mce_log_therm_throt_event(__u64 status)
1109 m.bank = MCE_THERMAL_BANK;
1113 #endif /* CONFIG_X86_MCE_INTEL */
1116 * Periodic polling timer for "silent" machine check errors. If the
1117 * poller finds an MCE, poll 2x faster. When the poller finds no more
1118 * errors, poll 2x slower (up to check_interval seconds).
1120 static int check_interval = 5 * 60; /* 5 minutes */
1122 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1123 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1125 static void mcheck_timer(unsigned long data)
1127 struct timer_list *t = &per_cpu(mce_timer, data);
1130 WARN_ON(smp_processor_id() != data);
1132 if (mce_available(¤t_cpu_data)) {
1133 machine_check_poll(MCP_TIMESTAMP,
1134 &__get_cpu_var(mce_poll_banks));
1138 * Alert userspace if needed. If we logged an MCE, reduce the
1139 * polling interval, otherwise increase the polling interval.
1141 n = &__get_cpu_var(mce_next_interval);
1142 if (mce_notify_irq())
1143 *n = max(*n/2, HZ/100);
1145 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1147 t->expires = jiffies + *n;
1148 add_timer_on(t, smp_processor_id());
1151 static void mce_do_trigger(struct work_struct *work)
1153 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1156 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1159 * Notify the user(s) about new machine check events.
1160 * Can be called from interrupt context, but not from machine check/NMI
1163 int mce_notify_irq(void)
1165 /* Not more than two messages every minute */
1166 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1168 clear_thread_flag(TIF_MCE_NOTIFY);
1170 if (test_and_clear_bit(0, &mce_need_notify)) {
1171 wake_up_interruptible(&mce_wait);
1174 * There is no risk of missing notifications because
1175 * work_pending is always cleared before the function is
1178 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1179 schedule_work(&mce_trigger_work);
1181 if (__ratelimit(&ratelimit))
1182 printk(KERN_INFO "Machine check events logged\n");
1188 EXPORT_SYMBOL_GPL(mce_notify_irq);
1190 static int mce_banks_init(void)
1194 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1197 for (i = 0; i < banks; i++) {
1198 struct mce_bank *b = &mce_banks[i];
1207 * Initialize Machine Checks for a CPU.
1209 static int __cpuinit mce_cap_init(void)
1214 rdmsrl(MSR_IA32_MCG_CAP, cap);
1216 b = cap & MCG_BANKCNT_MASK;
1218 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1220 if (b > MAX_NR_BANKS) {
1222 "MCE: Using only %u machine check banks out of %u\n",
1227 /* Don't support asymmetric configurations today */
1228 WARN_ON(banks != 0 && b != banks);
1231 int err = mce_banks_init();
1237 /* Use accurate RIP reporting if available. */
1238 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1239 rip_msr = MSR_IA32_MCG_EIP;
1241 if (cap & MCG_SER_P)
1247 static void mce_init(void)
1249 mce_banks_t all_banks;
1254 * Log the machine checks left over from the previous reset.
1256 bitmap_fill(all_banks, MAX_NR_BANKS);
1257 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1259 set_in_cr4(X86_CR4_MCE);
1261 rdmsrl(MSR_IA32_MCG_CAP, cap);
1262 if (cap & MCG_CTL_P)
1263 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1265 for (i = 0; i < banks; i++) {
1266 struct mce_bank *b = &mce_banks[i];
1270 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1271 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1275 /* Add per CPU specific workarounds here */
1276 static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
1278 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1279 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1283 /* This should be disabled by the BIOS, but isn't always */
1284 if (c->x86_vendor == X86_VENDOR_AMD) {
1285 if (c->x86 == 15 && banks > 4) {
1287 * disable GART TBL walk error reporting, which
1288 * trips off incorrectly with the IOMMU & 3ware
1291 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1293 if (c->x86 <= 17 && mce_bootlog < 0) {
1295 * Lots of broken BIOS around that don't clear them
1296 * by default and leave crap in there. Don't log:
1301 * Various K7s with broken bank 0 around. Always disable
1304 if (c->x86 == 6 && banks > 0)
1305 mce_banks[0].ctl = 0;
1308 if (c->x86_vendor == X86_VENDOR_INTEL) {
1310 * SDM documents that on family 6 bank 0 should not be written
1311 * because it aliases to another special BIOS controlled
1313 * But it's not aliased anymore on model 0x1a+
1314 * Don't ignore bank 0 completely because there could be a
1315 * valid event later, merely don't write CTL0.
1318 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1319 mce_banks[0].init = 0;
1322 * All newer Intel systems support MCE broadcasting. Enable
1323 * synchronization with a one second timeout.
1325 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1326 monarch_timeout < 0)
1327 monarch_timeout = USEC_PER_SEC;
1330 * There are also broken BIOSes on some Pentium M and
1333 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1336 if (monarch_timeout < 0)
1337 monarch_timeout = 0;
1338 if (mce_bootlog != 0)
1339 mce_panic_timeout = 30;
1344 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1348 switch (c->x86_vendor) {
1349 case X86_VENDOR_INTEL:
1350 intel_p5_mcheck_init(c);
1352 case X86_VENDOR_CENTAUR:
1353 winchip_mcheck_init(c);
1358 static void mce_cpu_features(struct cpuinfo_x86 *c)
1360 switch (c->x86_vendor) {
1361 case X86_VENDOR_INTEL:
1362 mce_intel_feature_init(c);
1364 case X86_VENDOR_AMD:
1365 mce_amd_feature_init(c);
1372 static void mce_init_timer(void)
1374 struct timer_list *t = &__get_cpu_var(mce_timer);
1375 int *n = &__get_cpu_var(mce_next_interval);
1380 *n = check_interval * HZ;
1383 setup_timer(t, mcheck_timer, smp_processor_id());
1384 t->expires = round_jiffies(jiffies + *n);
1385 add_timer_on(t, smp_processor_id());
1388 /* Handle unconfigured int18 (should never happen) */
1389 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1391 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1392 smp_processor_id());
1395 /* Call the installed machine check handler for this CPU setup. */
1396 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1397 unexpected_machine_check;
1400 * Called for each booted CPU to set up machine checks.
1401 * Must be called with preempt off:
1403 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1408 mce_ancient_init(c);
1410 if (!mce_available(c))
1413 if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
1418 machine_check_vector = do_machine_check;
1421 mce_cpu_features(c);
1423 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1427 * Character device to read and clear the MCE log.
1430 static DEFINE_SPINLOCK(mce_state_lock);
1431 static int open_count; /* #times opened */
1432 static int open_exclu; /* already open exclusive? */
1434 static int mce_open(struct inode *inode, struct file *file)
1436 spin_lock(&mce_state_lock);
1438 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1439 spin_unlock(&mce_state_lock);
1444 if (file->f_flags & O_EXCL)
1448 spin_unlock(&mce_state_lock);
1450 return nonseekable_open(inode, file);
1453 static int mce_release(struct inode *inode, struct file *file)
1455 spin_lock(&mce_state_lock);
1460 spin_unlock(&mce_state_lock);
1465 static void collect_tscs(void *data)
1467 unsigned long *cpu_tsc = (unsigned long *)data;
1469 rdtscll(cpu_tsc[smp_processor_id()]);
1472 static DEFINE_MUTEX(mce_read_mutex);
1474 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1477 char __user *buf = ubuf;
1478 unsigned long *cpu_tsc;
1479 unsigned prev, next;
1482 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1486 mutex_lock(&mce_read_mutex);
1487 next = rcu_dereference(mcelog.next);
1489 /* Only supports full reads right now */
1490 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1491 mutex_unlock(&mce_read_mutex);
1500 for (i = prev; i < next; i++) {
1501 unsigned long start = jiffies;
1503 while (!mcelog.entry[i].finished) {
1504 if (time_after_eq(jiffies, start + 2)) {
1505 memset(mcelog.entry + i, 0,
1506 sizeof(struct mce));
1512 err |= copy_to_user(buf, mcelog.entry + i,
1513 sizeof(struct mce));
1514 buf += sizeof(struct mce);
1519 memset(mcelog.entry + prev, 0,
1520 (next - prev) * sizeof(struct mce));
1522 next = cmpxchg(&mcelog.next, prev, 0);
1523 } while (next != prev);
1525 synchronize_sched();
1528 * Collect entries that were still getting written before the
1531 on_each_cpu(collect_tscs, cpu_tsc, 1);
1533 for (i = next; i < MCE_LOG_LEN; i++) {
1534 if (mcelog.entry[i].finished &&
1535 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1536 err |= copy_to_user(buf, mcelog.entry+i,
1537 sizeof(struct mce));
1539 buf += sizeof(struct mce);
1540 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1543 mutex_unlock(&mce_read_mutex);
1546 return err ? -EFAULT : buf - ubuf;
1549 static unsigned int mce_poll(struct file *file, poll_table *wait)
1551 poll_wait(file, &mce_wait, wait);
1552 if (rcu_dereference(mcelog.next))
1553 return POLLIN | POLLRDNORM;
1557 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1559 int __user *p = (int __user *)arg;
1561 if (!capable(CAP_SYS_ADMIN))
1565 case MCE_GET_RECORD_LEN:
1566 return put_user(sizeof(struct mce), p);
1567 case MCE_GET_LOG_LEN:
1568 return put_user(MCE_LOG_LEN, p);
1569 case MCE_GETCLEAR_FLAGS: {
1573 flags = mcelog.flags;
1574 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1576 return put_user(flags, p);
1583 /* Modified in mce-inject.c, so not static or const */
1584 struct file_operations mce_chrdev_ops = {
1586 .release = mce_release,
1589 .unlocked_ioctl = mce_ioctl,
1591 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1593 static struct miscdevice mce_log_device = {
1600 * mce=off Disables machine check
1601 * mce=no_cmci Disables CMCI
1602 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1603 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1604 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1605 * monarchtimeout is how long to wait for other CPUs on machine
1606 * check, or 0 to not wait
1607 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1608 * mce=nobootlog Don't log MCEs from before booting.
1610 static int __init mcheck_enable(char *str)
1618 if (!strcmp(str, "off"))
1620 else if (!strcmp(str, "no_cmci"))
1621 mce_cmci_disabled = 1;
1622 else if (!strcmp(str, "dont_log_ce"))
1623 mce_dont_log_ce = 1;
1624 else if (!strcmp(str, "ignore_ce"))
1626 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1627 mce_bootlog = (str[0] == 'b');
1628 else if (isdigit(str[0])) {
1629 get_option(&str, &tolerant);
1632 get_option(&str, &monarch_timeout);
1635 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1641 __setup("mce", mcheck_enable);
1648 * Disable machine checks on suspend and shutdown. We can't really handle
1651 static int mce_disable(void)
1655 for (i = 0; i < banks; i++) {
1656 struct mce_bank *b = &mce_banks[i];
1659 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1664 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1666 return mce_disable();
1669 static int mce_shutdown(struct sys_device *dev)
1671 return mce_disable();
1675 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1676 * Only one CPU is active at this time, the others get re-added later using
1679 static int mce_resume(struct sys_device *dev)
1682 mce_cpu_features(¤t_cpu_data);
1687 static void mce_cpu_restart(void *data)
1689 del_timer_sync(&__get_cpu_var(mce_timer));
1690 if (!mce_available(¤t_cpu_data))
1696 /* Reinit MCEs after user configuration changes */
1697 static void mce_restart(void)
1699 on_each_cpu(mce_cpu_restart, NULL, 1);
1702 /* Toggle features for corrected errors */
1703 static void mce_disable_ce(void *all)
1705 if (!mce_available(¤t_cpu_data))
1708 del_timer_sync(&__get_cpu_var(mce_timer));
1712 static void mce_enable_ce(void *all)
1714 if (!mce_available(¤t_cpu_data))
1722 static struct sysdev_class mce_sysclass = {
1723 .suspend = mce_suspend,
1724 .shutdown = mce_shutdown,
1725 .resume = mce_resume,
1726 .name = "machinecheck",
1729 DEFINE_PER_CPU(struct sys_device, mce_dev);
1732 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1734 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1736 return container_of(attr, struct mce_bank, attr);
1739 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1742 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1745 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1746 const char *buf, size_t size)
1750 if (strict_strtoull(buf, 0, &new) < 0)
1753 attr_to_bank(attr)->ctl = new;
1760 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1762 strcpy(buf, mce_helper);
1764 return strlen(mce_helper) + 1;
1767 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1768 const char *buf, size_t siz)
1772 strncpy(mce_helper, buf, sizeof(mce_helper));
1773 mce_helper[sizeof(mce_helper)-1] = 0;
1774 p = strchr(mce_helper, '\n');
1779 return strlen(mce_helper) + !!p;
1782 static ssize_t set_ignore_ce(struct sys_device *s,
1783 struct sysdev_attribute *attr,
1784 const char *buf, size_t size)
1788 if (strict_strtoull(buf, 0, &new) < 0)
1791 if (mce_ignore_ce ^ !!new) {
1793 /* disable ce features */
1794 on_each_cpu(mce_disable_ce, (void *)1, 1);
1797 /* enable ce features */
1799 on_each_cpu(mce_enable_ce, (void *)1, 1);
1805 static ssize_t set_cmci_disabled(struct sys_device *s,
1806 struct sysdev_attribute *attr,
1807 const char *buf, size_t size)
1811 if (strict_strtoull(buf, 0, &new) < 0)
1814 if (mce_cmci_disabled ^ !!new) {
1817 on_each_cpu(mce_disable_ce, NULL, 1);
1818 mce_cmci_disabled = 1;
1821 mce_cmci_disabled = 0;
1822 on_each_cpu(mce_enable_ce, NULL, 1);
1828 static ssize_t store_int_with_restart(struct sys_device *s,
1829 struct sysdev_attribute *attr,
1830 const char *buf, size_t size)
1832 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1837 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1838 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1839 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1840 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1842 static struct sysdev_ext_attribute attr_check_interval = {
1843 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1844 store_int_with_restart),
1848 static struct sysdev_ext_attribute attr_ignore_ce = {
1849 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1853 static struct sysdev_ext_attribute attr_cmci_disabled = {
1854 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1858 static struct sysdev_attribute *mce_attrs[] = {
1859 &attr_tolerant.attr,
1860 &attr_check_interval.attr,
1862 &attr_monarch_timeout.attr,
1863 &attr_dont_log_ce.attr,
1864 &attr_ignore_ce.attr,
1865 &attr_cmci_disabled.attr,
1869 static cpumask_var_t mce_dev_initialized;
1871 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1872 static __cpuinit int mce_create_device(unsigned int cpu)
1877 if (!mce_available(&boot_cpu_data))
1880 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1881 per_cpu(mce_dev, cpu).id = cpu;
1882 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1884 err = sysdev_register(&per_cpu(mce_dev, cpu));
1888 for (i = 0; mce_attrs[i]; i++) {
1889 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1893 for (j = 0; j < banks; j++) {
1894 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1895 &mce_banks[j].attr);
1899 cpumask_set_cpu(cpu, mce_dev_initialized);
1904 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1907 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1909 sysdev_unregister(&per_cpu(mce_dev, cpu));
1914 static __cpuinit void mce_remove_device(unsigned int cpu)
1918 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1921 for (i = 0; mce_attrs[i]; i++)
1922 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1924 for (i = 0; i < banks; i++)
1925 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1927 sysdev_unregister(&per_cpu(mce_dev, cpu));
1928 cpumask_clear_cpu(cpu, mce_dev_initialized);
1931 /* Make sure there are no machine checks on offlined CPUs. */
1932 static void mce_disable_cpu(void *h)
1934 unsigned long action = *(unsigned long *)h;
1937 if (!mce_available(¤t_cpu_data))
1939 if (!(action & CPU_TASKS_FROZEN))
1941 for (i = 0; i < banks; i++) {
1942 struct mce_bank *b = &mce_banks[i];
1945 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1949 static void mce_reenable_cpu(void *h)
1951 unsigned long action = *(unsigned long *)h;
1954 if (!mce_available(¤t_cpu_data))
1957 if (!(action & CPU_TASKS_FROZEN))
1959 for (i = 0; i < banks; i++) {
1960 struct mce_bank *b = &mce_banks[i];
1963 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1967 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1968 static int __cpuinit
1969 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1971 unsigned int cpu = (unsigned long)hcpu;
1972 struct timer_list *t = &per_cpu(mce_timer, cpu);
1976 case CPU_ONLINE_FROZEN:
1977 mce_create_device(cpu);
1978 if (threshold_cpu_callback)
1979 threshold_cpu_callback(action, cpu);
1982 case CPU_DEAD_FROZEN:
1983 if (threshold_cpu_callback)
1984 threshold_cpu_callback(action, cpu);
1985 mce_remove_device(cpu);
1987 case CPU_DOWN_PREPARE:
1988 case CPU_DOWN_PREPARE_FROZEN:
1990 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1992 case CPU_DOWN_FAILED:
1993 case CPU_DOWN_FAILED_FROZEN:
1994 if (!mce_ignore_ce && check_interval) {
1995 t->expires = round_jiffies(jiffies +
1996 __get_cpu_var(mce_next_interval));
1997 add_timer_on(t, cpu);
1999 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2002 /* intentionally ignoring frozen here */
2003 cmci_rediscover(cpu);
2009 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2010 .notifier_call = mce_cpu_callback,
2013 static __init void mce_init_banks(void)
2017 for (i = 0; i < banks; i++) {
2018 struct mce_bank *b = &mce_banks[i];
2019 struct sysdev_attribute *a = &b->attr;
2021 a->attr.name = b->attrname;
2022 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2024 a->attr.mode = 0644;
2025 a->show = show_bank;
2026 a->store = set_bank;
2030 static __init int mce_init_device(void)
2035 if (!mce_available(&boot_cpu_data))
2038 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2042 err = sysdev_class_register(&mce_sysclass);
2046 for_each_online_cpu(i) {
2047 err = mce_create_device(i);
2052 register_hotcpu_notifier(&mce_cpu_notifier);
2053 misc_register(&mce_log_device);
2058 device_initcall(mce_init_device);
2061 * Old style boot options parsing. Only for compatibility.
2063 static int __init mcheck_disable(char *str)
2068 __setup("nomce", mcheck_disable);
2070 #ifdef CONFIG_DEBUG_FS
2071 struct dentry *mce_get_debugfs_dir(void)
2073 static struct dentry *dmce;
2076 dmce = debugfs_create_dir("mce", NULL);
2081 static void mce_reset(void)
2084 atomic_set(&mce_fake_paniced, 0);
2085 atomic_set(&mce_executing, 0);
2086 atomic_set(&mce_callin, 0);
2087 atomic_set(&global_nwo, 0);
2090 static int fake_panic_get(void *data, u64 *val)
2096 static int fake_panic_set(void *data, u64 val)
2103 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2104 fake_panic_set, "%llu\n");
2106 static int __init mce_debugfs_init(void)
2108 struct dentry *dmce, *ffake_panic;
2110 dmce = mce_get_debugfs_dir();
2113 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2120 late_initcall(mce_debugfs_init);