2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/device.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
98 /* MCA banks polled by the period polling timer for corrected events */
99 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
100 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
103 static DEFINE_PER_CPU(struct work_struct, mce_work);
106 * CPU/chipset specific EDAC code can register a notifier call here to print
107 * MCE errors in a human-readable form.
109 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
111 /* Do initial initialization of a struct mce */
112 void mce_setup(struct mce *m)
114 memset(m, 0, sizeof(struct mce));
115 m->cpu = m->extcpu = smp_processor_id();
117 /* We hope get_seconds stays lockless */
118 m->time = get_seconds();
119 m->cpuvendor = boot_cpu_data.x86_vendor;
120 m->cpuid = cpuid_eax(1);
122 m->socketid = cpu_data(m->extcpu).phys_proc_id;
123 m->apicid = cpu_data(m->extcpu).initial_apicid;
125 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
128 DEFINE_PER_CPU(struct mce, injectm);
129 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
132 * Lockless MCE logging infrastructure.
133 * This avoids deadlocks on printk locks without having to break locks. Also
134 * separate MCEs from kernel messages to avoid bogus bug reports.
137 static struct mce_log mcelog = {
138 .signature = MCE_LOG_SIGNATURE,
140 .recordlen = sizeof(struct mce),
143 void mce_log(struct mce *mce)
145 unsigned next, entry;
148 /* Emit the trace record: */
149 trace_mce_record(mce);
151 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
152 if (ret == NOTIFY_STOP)
158 entry = rcu_dereference_check_mce(mcelog.next);
162 * When the buffer fills up discard new entries.
163 * Assume that the earlier errors are the more
166 if (entry >= MCE_LOG_LEN) {
167 set_bit(MCE_OVERFLOW,
168 (unsigned long *)&mcelog.flags);
171 /* Old left over entry. Skip: */
172 if (mcelog.entry[entry].finished) {
180 if (cmpxchg(&mcelog.next, entry, next) == entry)
183 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
185 mcelog.entry[entry].finished = 1;
189 set_bit(0, &mce_need_notify);
192 static void drain_mcelog_buffer(void)
194 unsigned int next, i, prev = 0;
196 next = ACCESS_ONCE(mcelog.next);
201 /* drain what was logged during boot */
202 for (i = prev; i < next; i++) {
203 unsigned long start = jiffies;
204 unsigned retries = 1;
206 m = &mcelog.entry[i];
208 while (!m->finished) {
209 if (time_after_eq(jiffies, start + 2*retries))
214 if (!m->finished && retries >= 4) {
215 pr_err("MCE: skipping error being logged currently!\n");
220 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
223 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
225 next = cmpxchg(&mcelog.next, prev, 0);
226 } while (next != prev);
230 void mce_register_decode_chain(struct notifier_block *nb)
232 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
233 drain_mcelog_buffer();
235 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
237 void mce_unregister_decode_chain(struct notifier_block *nb)
239 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
241 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
243 static void print_mce(struct mce *m)
247 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
248 m->extcpu, m->mcgstatus, m->bank, m->status);
251 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
252 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
255 if (m->cs == __KERNEL_CS)
256 print_symbol("{%s}", m->ip);
260 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
262 pr_cont("ADDR %llx ", m->addr);
264 pr_cont("MISC %llx ", m->misc);
268 * Note this output is parsed by external tools and old fields
269 * should not be changed.
272 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
273 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
274 cpu_data(m->extcpu).microcode);
276 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
277 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
281 * Print out human-readable details about the MCE error,
282 * (if the CPU has an implementation for that)
284 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
285 if (ret == NOTIFY_STOP)
288 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
291 #define PANIC_TIMEOUT 5 /* 5 seconds */
293 static atomic_t mce_paniced;
295 static int fake_panic;
296 static atomic_t mce_fake_paniced;
298 /* Panic in progress. Enable interrupts and wait for final IPI */
299 static void wait_for_panic(void)
301 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
305 while (timeout-- > 0)
307 if (panic_timeout == 0)
308 panic_timeout = mce_panic_timeout;
309 panic("Panicing machine check CPU died");
312 static void mce_panic(char *msg, struct mce *final, char *exp)
318 * Make sure only one CPU runs in machine check panic
320 if (atomic_inc_return(&mce_paniced) > 1)
327 /* Don't log too much for fake panic */
328 if (atomic_inc_return(&mce_fake_paniced) > 1)
331 /* First print corrected ones that are still unlogged */
332 for (i = 0; i < MCE_LOG_LEN; i++) {
333 struct mce *m = &mcelog.entry[i];
334 if (!(m->status & MCI_STATUS_VAL))
336 if (!(m->status & MCI_STATUS_UC)) {
339 apei_err = apei_write_mce(m);
342 /* Now print uncorrected but with the final one last */
343 for (i = 0; i < MCE_LOG_LEN; i++) {
344 struct mce *m = &mcelog.entry[i];
345 if (!(m->status & MCI_STATUS_VAL))
347 if (!(m->status & MCI_STATUS_UC))
349 if (!final || memcmp(m, final, sizeof(struct mce))) {
352 apei_err = apei_write_mce(m);
358 apei_err = apei_write_mce(final);
361 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
363 pr_emerg(HW_ERR "Machine check: %s\n", exp);
365 if (panic_timeout == 0)
366 panic_timeout = mce_panic_timeout;
369 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
372 /* Support code for software error injection */
374 static int msr_to_offset(u32 msr)
376 unsigned bank = __this_cpu_read(injectm.bank);
379 return offsetof(struct mce, ip);
380 if (msr == MSR_IA32_MCx_STATUS(bank))
381 return offsetof(struct mce, status);
382 if (msr == MSR_IA32_MCx_ADDR(bank))
383 return offsetof(struct mce, addr);
384 if (msr == MSR_IA32_MCx_MISC(bank))
385 return offsetof(struct mce, misc);
386 if (msr == MSR_IA32_MCG_STATUS)
387 return offsetof(struct mce, mcgstatus);
391 /* MSR access wrappers used for error injection */
392 static u64 mce_rdmsrl(u32 msr)
396 if (__this_cpu_read(injectm.finished)) {
397 int offset = msr_to_offset(msr);
401 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
404 if (rdmsrl_safe(msr, &v)) {
405 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
407 * Return zero in case the access faulted. This should
408 * not happen normally but can happen if the CPU does
409 * something weird, or if the code is buggy.
417 static void mce_wrmsrl(u32 msr, u64 v)
419 if (__this_cpu_read(injectm.finished)) {
420 int offset = msr_to_offset(msr);
423 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
430 * Collect all global (w.r.t. this processor) status about this machine
431 * check into our "mce" struct so that we can use it later to assess
432 * the severity of the problem as we read per-bank specific details.
434 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
438 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
441 * Get the address of the instruction at the time of
442 * the machine check error.
444 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
448 /* Use accurate RIP reporting if available. */
450 m->ip = mce_rdmsrl(rip_msr);
455 * Simple lockless ring to communicate PFNs from the exception handler with the
456 * process context work function. This is vastly simplified because there's
457 * only a single reader and a single writer.
459 #define MCE_RING_SIZE 16 /* we use one entry less */
462 unsigned short start;
464 unsigned long ring[MCE_RING_SIZE];
466 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
468 /* Runs with CPU affinity in workqueue */
469 static int mce_ring_empty(void)
471 struct mce_ring *r = &__get_cpu_var(mce_ring);
473 return r->start == r->end;
476 static int mce_ring_get(unsigned long *pfn)
483 r = &__get_cpu_var(mce_ring);
484 if (r->start == r->end)
486 *pfn = r->ring[r->start];
487 r->start = (r->start + 1) % MCE_RING_SIZE;
494 /* Always runs in MCE context with preempt off */
495 static int mce_ring_add(unsigned long pfn)
497 struct mce_ring *r = &__get_cpu_var(mce_ring);
500 next = (r->end + 1) % MCE_RING_SIZE;
501 if (next == r->start)
503 r->ring[r->end] = pfn;
509 int mce_available(struct cpuinfo_x86 *c)
513 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
516 static void mce_schedule_work(void)
518 if (!mce_ring_empty()) {
519 struct work_struct *work = &__get_cpu_var(mce_work);
520 if (!work_pending(work))
525 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
527 static void mce_irq_work_cb(struct irq_work *entry)
533 static void mce_report_event(struct pt_regs *regs)
535 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
538 * Triggering the work queue here is just an insurance
539 * policy in case the syscall exit notify handler
540 * doesn't run soon enough or ends up running on the
541 * wrong CPU (can happen when audit sleeps)
547 irq_work_queue(&__get_cpu_var(mce_irq_work));
551 * Read ADDR and MISC registers.
553 static void mce_read_aux(struct mce *m, int i)
555 if (m->status & MCI_STATUS_MISCV)
556 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
557 if (m->status & MCI_STATUS_ADDRV) {
558 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
561 * Mask the reported address by the reported granularity.
563 if (mce_ser && (m->status & MCI_STATUS_MISCV)) {
564 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
571 DEFINE_PER_CPU(unsigned, mce_poll_count);
574 * Poll for corrected events or events that happened before reset.
575 * Those are just logged through /dev/mcelog.
577 * This is executed in standard interrupt context.
579 * Note: spec recommends to panic for fatal unsignalled
580 * errors here. However this would be quite problematic --
581 * we would need to reimplement the Monarch handling and
582 * it would mess up the exclusion between exception handler
583 * and poll hander -- * so we skip this for now.
584 * These cases should not happen anyways, or only when the CPU
585 * is already totally * confused. In this case it's likely it will
586 * not fully execute the machine check handler either.
588 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
593 percpu_inc(mce_poll_count);
595 mce_gather_info(&m, NULL);
597 for (i = 0; i < banks; i++) {
598 if (!mce_banks[i].ctl || !test_bit(i, *b))
607 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
608 if (!(m.status & MCI_STATUS_VAL))
612 * Uncorrected or signalled events are handled by the exception
613 * handler when it is enabled, so don't process those here.
615 * TBD do the same check for MCI_STATUS_EN here?
617 if (!(flags & MCP_UC) &&
618 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
623 if (!(flags & MCP_TIMESTAMP))
626 * Don't get the IP here because it's unlikely to
627 * have anything to do with the actual error location.
629 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
633 * Clear state for this bank.
635 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
639 * Don't clear MCG_STATUS here because it's only defined for
645 EXPORT_SYMBOL_GPL(machine_check_poll);
648 * Do a quick check if any of the events requires a panic.
649 * This decides if we keep the events around or clear them.
651 static int mce_no_way_out(struct mce *m, char **msg)
655 for (i = 0; i < banks; i++) {
656 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
657 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
664 * Variable to establish order between CPUs while scanning.
665 * Each CPU spins initially until executing is equal its number.
667 static atomic_t mce_executing;
670 * Defines order of CPUs on entry. First CPU becomes Monarch.
672 static atomic_t mce_callin;
675 * Check if a timeout waiting for other CPUs happened.
677 static int mce_timed_out(u64 *t)
680 * The others already did panic for some reason.
681 * Bail out like in a timeout.
682 * rmb() to tell the compiler that system_state
683 * might have been modified by someone else.
686 if (atomic_read(&mce_paniced))
688 if (!monarch_timeout)
690 if ((s64)*t < SPINUNIT) {
691 /* CHECKME: Make panic default for 1 too? */
693 mce_panic("Timeout synchronizing machine check over CPUs",
700 touch_nmi_watchdog();
705 * The Monarch's reign. The Monarch is the CPU who entered
706 * the machine check handler first. It waits for the others to
707 * raise the exception too and then grades them. When any
708 * error is fatal panic. Only then let the others continue.
710 * The other CPUs entering the MCE handler will be controlled by the
711 * Monarch. They are called Subjects.
713 * This way we prevent any potential data corruption in a unrecoverable case
714 * and also makes sure always all CPU's errors are examined.
716 * Also this detects the case of a machine check event coming from outer
717 * space (not detected by any CPUs) In this case some external agent wants
718 * us to shut down, so panic too.
720 * The other CPUs might still decide to panic if the handler happens
721 * in a unrecoverable place, but in this case the system is in a semi-stable
722 * state and won't corrupt anything by itself. It's ok to let the others
723 * continue for a bit first.
725 * All the spin loops have timeouts; when a timeout happens a CPU
726 * typically elects itself to be Monarch.
728 static void mce_reign(void)
731 struct mce *m = NULL;
732 int global_worst = 0;
737 * This CPU is the Monarch and the other CPUs have run
738 * through their handlers.
739 * Grade the severity of the errors of all the CPUs.
741 for_each_possible_cpu(cpu) {
742 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
744 if (severity > global_worst) {
746 global_worst = severity;
747 m = &per_cpu(mces_seen, cpu);
752 * Cannot recover? Panic here then.
753 * This dumps all the mces in the log buffer and stops the
756 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
757 mce_panic("Fatal Machine check", m, msg);
760 * For UC somewhere we let the CPU who detects it handle it.
761 * Also must let continue the others, otherwise the handling
762 * CPU could deadlock on a lock.
766 * No machine check event found. Must be some external
767 * source or one CPU is hung. Panic.
769 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
770 mce_panic("Machine check from unknown source", NULL, NULL);
773 * Now clear all the mces_seen so that they don't reappear on
776 for_each_possible_cpu(cpu)
777 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
780 static atomic_t global_nwo;
783 * Start of Monarch synchronization. This waits until all CPUs have
784 * entered the exception handler and then determines if any of them
785 * saw a fatal event that requires panic. Then it executes them
786 * in the entry order.
787 * TBD double check parallel CPU hotunplug
789 static int mce_start(int *no_way_out)
792 int cpus = num_online_cpus();
793 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
798 atomic_add(*no_way_out, &global_nwo);
800 * global_nwo should be updated before mce_callin
803 order = atomic_inc_return(&mce_callin);
808 while (atomic_read(&mce_callin) != cpus) {
809 if (mce_timed_out(&timeout)) {
810 atomic_set(&global_nwo, 0);
817 * mce_callin should be read before global_nwo
823 * Monarch: Starts executing now, the others wait.
825 atomic_set(&mce_executing, 1);
828 * Subject: Now start the scanning loop one by one in
829 * the original callin order.
830 * This way when there are any shared banks it will be
831 * only seen by one CPU before cleared, avoiding duplicates.
833 while (atomic_read(&mce_executing) < order) {
834 if (mce_timed_out(&timeout)) {
835 atomic_set(&global_nwo, 0);
843 * Cache the global no_way_out state.
845 *no_way_out = atomic_read(&global_nwo);
851 * Synchronize between CPUs after main scanning loop.
852 * This invokes the bulk of the Monarch processing.
854 static int mce_end(int order)
857 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
865 * Allow others to run.
867 atomic_inc(&mce_executing);
870 /* CHECKME: Can this race with a parallel hotplug? */
871 int cpus = num_online_cpus();
874 * Monarch: Wait for everyone to go through their scanning
877 while (atomic_read(&mce_executing) <= cpus) {
878 if (mce_timed_out(&timeout))
888 * Subject: Wait for Monarch to finish.
890 while (atomic_read(&mce_executing) != 0) {
891 if (mce_timed_out(&timeout))
897 * Don't reset anything. That's done by the Monarch.
903 * Reset all global state.
906 atomic_set(&global_nwo, 0);
907 atomic_set(&mce_callin, 0);
911 * Let others run again.
913 atomic_set(&mce_executing, 0);
918 * Check if the address reported by the CPU is in a format we can parse.
919 * It would be possible to add code for most other cases, but all would
920 * be somewhat complicated (e.g. segment offset would require an instruction
921 * parser). So only support physical addresses up to page granuality for now.
923 static int mce_usable_address(struct mce *m)
925 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
927 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
929 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
934 static void mce_clear_state(unsigned long *toclear)
938 for (i = 0; i < banks; i++) {
939 if (test_bit(i, toclear))
940 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
945 * Need to save faulting physical address associated with a process
946 * in the machine check handler some place where we can grab it back
947 * later in mce_notify_process()
949 #define MCE_INFO_MAX 16
953 struct task_struct *t;
956 } mce_info[MCE_INFO_MAX];
958 static void mce_save_info(__u64 addr, int c)
962 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) {
963 if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
971 mce_panic("Too many concurrent recoverable errors", NULL, NULL);
974 static struct mce_info *mce_find_info(void)
978 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++)
979 if (atomic_read(&mi->inuse) && mi->t == current)
984 static void mce_clear_info(struct mce_info *mi)
986 atomic_set(&mi->inuse, 0);
990 * The actual machine check handler. This only handles real
991 * exceptions when something got corrupted coming in through int 18.
993 * This is executed in NMI context not subject to normal locking rules. This
994 * implies that most kernel services cannot be safely used. Don't even
995 * think about putting a printk in there!
997 * On Intel systems this is entered on all CPUs in parallel through
998 * MCE broadcast. However some CPUs might be broken beyond repair,
999 * so be always careful when synchronizing with others.
1001 void do_machine_check(struct pt_regs *regs, long error_code)
1003 struct mce m, *final;
1008 * Establish sequential order between the CPUs entering the machine
1013 * If no_way_out gets set, there is no safe way to recover from this
1014 * MCE. If tolerant is cranked up, we'll try anyway.
1018 * If kill_it gets set, there might be a way to recover from this
1022 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1023 char *msg = "Unknown";
1025 atomic_inc(&mce_entry);
1027 percpu_inc(mce_exception_count);
1032 mce_gather_info(&m, regs);
1034 final = &__get_cpu_var(mces_seen);
1037 no_way_out = mce_no_way_out(&m, &msg);
1042 * When no restart IP might need to kill or panic.
1043 * Assume the worst for now, but if we find the
1044 * severity is MCE_AR_SEVERITY we have other options.
1046 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1050 * Go through all the banks in exclusion of the other CPUs.
1051 * This way we don't report duplicated events on shared banks
1052 * because the first one to see it will clear it.
1054 order = mce_start(&no_way_out);
1055 for (i = 0; i < banks; i++) {
1056 __clear_bit(i, toclear);
1057 if (!mce_banks[i].ctl)
1064 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1065 if ((m.status & MCI_STATUS_VAL) == 0)
1069 * Non uncorrected or non signaled errors are handled by
1070 * machine_check_poll. Leave them alone, unless this panics.
1072 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1077 * Set taint even when machine check was not enabled.
1079 add_taint(TAINT_MACHINE_CHECK);
1081 severity = mce_severity(&m, tolerant, NULL);
1084 * When machine check was for corrected handler don't touch,
1085 * unless we're panicing.
1087 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1089 __set_bit(i, toclear);
1090 if (severity == MCE_NO_SEVERITY) {
1092 * Machine check event was not enabled. Clear, but
1098 mce_read_aux(&m, i);
1101 * Action optional error. Queue address for later processing.
1102 * When the ring overflows we just ignore the AO error.
1103 * RED-PEN add some logging mechanism when
1104 * usable_address or mce_add_ring fails.
1105 * RED-PEN don't ignore overflow for tolerant == 0
1107 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1108 mce_ring_add(m.addr >> PAGE_SHIFT);
1112 if (severity > worst) {
1118 /* mce_clear_state will clear *final, save locally for use later */
1122 mce_clear_state(toclear);
1125 * Do most of the synchronization with other CPUs.
1126 * When there's any problem use only local no_way_out state.
1128 if (mce_end(order) < 0)
1129 no_way_out = worst >= MCE_PANIC_SEVERITY;
1132 * At insane "tolerant" levels we take no action. Otherwise
1133 * we only die if we have no other choice. For less serious
1134 * issues we try to recover, or limit damage to the current
1139 mce_panic("Fatal machine check on current CPU", &m, msg);
1140 if (worst == MCE_AR_SEVERITY) {
1141 /* schedule action before return to userland */
1142 mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV);
1143 set_thread_flag(TIF_MCE_NOTIFY);
1144 } else if (kill_it) {
1145 force_sig(SIGBUS, current);
1150 mce_report_event(regs);
1151 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1153 atomic_dec(&mce_entry);
1156 EXPORT_SYMBOL_GPL(do_machine_check);
1158 #ifndef CONFIG_MEMORY_FAILURE
1159 int memory_failure(unsigned long pfn, int vector, int flags)
1161 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1162 BUG_ON(flags & MF_ACTION_REQUIRED);
1163 printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n"
1164 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn);
1171 * Called in process context that interrupted by MCE and marked with
1172 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1173 * This code is allowed to sleep.
1174 * Attempt possible recovery such as calling the high level VM handler to
1175 * process any corrupted pages, and kill/signal current process if required.
1176 * Action required errors are handled here.
1178 void mce_notify_process(void)
1181 struct mce_info *mi = mce_find_info();
1184 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
1185 pfn = mi->paddr >> PAGE_SHIFT;
1187 clear_thread_flag(TIF_MCE_NOTIFY);
1189 pr_err("Uncorrected hardware memory error in user-access at %llx",
1192 * We must call memory_failure() here even if the current process is
1193 * doomed. We still need to mark the page as poisoned and alert any
1194 * other users of the page.
1196 if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0 ||
1197 mi->restartable == 0) {
1198 pr_err("Memory error not recovered");
1199 force_sig(SIGBUS, current);
1205 * Action optional processing happens here (picking up
1206 * from the list of faulting pages that do_machine_check()
1207 * placed into the "ring").
1209 static void mce_process_work(struct work_struct *dummy)
1213 while (mce_ring_get(&pfn))
1214 memory_failure(pfn, MCE_VECTOR, 0);
1217 #ifdef CONFIG_X86_MCE_INTEL
1219 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1220 * @cpu: The CPU on which the event occurred.
1221 * @status: Event status information
1223 * This function should be called by the thermal interrupt after the
1224 * event has been processed and the decision was made to log the event
1227 * The status parameter will be saved to the 'status' field of 'struct mce'
1228 * and historically has been the register value of the
1229 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1231 void mce_log_therm_throt_event(__u64 status)
1236 m.bank = MCE_THERMAL_BANK;
1240 #endif /* CONFIG_X86_MCE_INTEL */
1243 * Periodic polling timer for "silent" machine check errors. If the
1244 * poller finds an MCE, poll 2x faster. When the poller finds no more
1245 * errors, poll 2x slower (up to check_interval seconds).
1247 * We will disable polling in DOM0 since all CMCI/Polling
1248 * mechanism will be done in XEN for Intel CPUs
1250 #if defined (CONFIG_X86_XEN_MCE)
1251 static int check_interval = 0; /* disable polling */
1253 static int check_interval = 5 * 60; /* 5 minutes */
1256 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1257 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1259 static void mce_start_timer(unsigned long data)
1261 struct timer_list *t = &per_cpu(mce_timer, data);
1264 WARN_ON(smp_processor_id() != data);
1266 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1267 machine_check_poll(MCP_TIMESTAMP,
1268 &__get_cpu_var(mce_poll_banks));
1272 * Alert userspace if needed. If we logged an MCE, reduce the
1273 * polling interval, otherwise increase the polling interval.
1275 n = &__get_cpu_var(mce_next_interval);
1276 if (mce_notify_irq())
1277 *n = max(*n/2, HZ/100);
1279 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1281 t->expires = jiffies + *n;
1282 add_timer_on(t, smp_processor_id());
1285 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1286 static void mce_timer_delete_all(void)
1290 for_each_online_cpu(cpu)
1291 del_timer_sync(&per_cpu(mce_timer, cpu));
1294 static void mce_do_trigger(struct work_struct *work)
1296 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1299 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1302 * Notify the user(s) about new machine check events.
1303 * Can be called from interrupt context, but not from machine check/NMI
1306 int mce_notify_irq(void)
1308 /* Not more than two messages every minute */
1309 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1311 if (test_and_clear_bit(0, &mce_need_notify)) {
1312 /* wake processes polling /dev/mcelog */
1313 wake_up_interruptible(&mce_chrdev_wait);
1316 * There is no risk of missing notifications because
1317 * work_pending is always cleared before the function is
1320 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1321 schedule_work(&mce_trigger_work);
1323 if (__ratelimit(&ratelimit))
1324 pr_info(HW_ERR "Machine check events logged\n");
1330 EXPORT_SYMBOL_GPL(mce_notify_irq);
1332 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1336 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1339 for (i = 0; i < banks; i++) {
1340 struct mce_bank *b = &mce_banks[i];
1349 * Initialize Machine Checks for a CPU.
1351 static int __cpuinit __mcheck_cpu_cap_init(void)
1356 rdmsrl(MSR_IA32_MCG_CAP, cap);
1358 b = cap & MCG_BANKCNT_MASK;
1360 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1362 if (b > MAX_NR_BANKS) {
1364 "MCE: Using only %u machine check banks out of %u\n",
1369 /* Don't support asymmetric configurations today */
1370 WARN_ON(banks != 0 && b != banks);
1373 int err = __mcheck_cpu_mce_banks_init();
1379 /* Use accurate RIP reporting if available. */
1380 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1381 rip_msr = MSR_IA32_MCG_EIP;
1383 if (cap & MCG_SER_P)
1389 static void __mcheck_cpu_init_generic(void)
1391 mce_banks_t all_banks;
1396 * Log the machine checks left over from the previous reset.
1398 bitmap_fill(all_banks, MAX_NR_BANKS);
1399 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1401 set_in_cr4(X86_CR4_MCE);
1403 rdmsrl(MSR_IA32_MCG_CAP, cap);
1404 if (cap & MCG_CTL_P)
1405 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1407 for (i = 0; i < banks; i++) {
1408 struct mce_bank *b = &mce_banks[i];
1412 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1413 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1417 /* Add per CPU specific workarounds here */
1418 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1420 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1421 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1425 /* This should be disabled by the BIOS, but isn't always */
1426 if (c->x86_vendor == X86_VENDOR_AMD) {
1428 if (c->x86 == 15 && banks > 4) {
1430 * disable GART TBL walk error reporting, which
1431 * trips off incorrectly with the IOMMU & 3ware
1434 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1437 if (c->x86 <= 17 && mce_bootlog < 0) {
1439 * Lots of broken BIOS around that don't clear them
1440 * by default and leave crap in there. Don't log:
1445 * Various K7s with broken bank 0 around. Always disable
1448 if (c->x86 == 6 && banks > 0)
1449 mce_banks[0].ctl = 0;
1452 if (c->x86_vendor == X86_VENDOR_INTEL) {
1454 * SDM documents that on family 6 bank 0 should not be written
1455 * because it aliases to another special BIOS controlled
1457 * But it's not aliased anymore on model 0x1a+
1458 * Don't ignore bank 0 completely because there could be a
1459 * valid event later, merely don't write CTL0.
1462 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1463 mce_banks[0].init = 0;
1466 * All newer Intel systems support MCE broadcasting. Enable
1467 * synchronization with a one second timeout.
1469 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1470 monarch_timeout < 0)
1471 monarch_timeout = USEC_PER_SEC;
1474 * There are also broken BIOSes on some Pentium M and
1477 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1480 if (monarch_timeout < 0)
1481 monarch_timeout = 0;
1482 if (mce_bootlog != 0)
1483 mce_panic_timeout = 30;
1488 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1493 switch (c->x86_vendor) {
1494 case X86_VENDOR_INTEL:
1495 intel_p5_mcheck_init(c);
1498 case X86_VENDOR_CENTAUR:
1499 winchip_mcheck_init(c);
1507 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1509 #ifndef CONFIG_X86_64_XEN
1510 switch (c->x86_vendor) {
1511 case X86_VENDOR_INTEL:
1512 mce_intel_feature_init(c);
1514 case X86_VENDOR_AMD:
1515 mce_amd_feature_init(c);
1523 static void __mcheck_cpu_init_timer(void)
1525 struct timer_list *t = &__get_cpu_var(mce_timer);
1526 int *n = &__get_cpu_var(mce_next_interval);
1528 setup_timer(t, mce_start_timer, smp_processor_id());
1533 *n = check_interval * HZ;
1536 t->expires = round_jiffies(jiffies + *n);
1537 add_timer_on(t, smp_processor_id());
1540 /* Handle unconfigured int18 (should never happen) */
1541 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1543 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1544 smp_processor_id());
1547 /* Call the installed machine check handler for this CPU setup. */
1548 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1549 unexpected_machine_check;
1552 * Called for each booted CPU to set up machine checks.
1553 * Must be called with preempt off:
1555 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1560 if (__mcheck_cpu_ancient_init(c))
1563 if (!mce_available(c))
1566 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1571 machine_check_vector = do_machine_check;
1573 __mcheck_cpu_init_generic();
1574 __mcheck_cpu_init_vendor(c);
1575 __mcheck_cpu_init_timer();
1576 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1577 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1581 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1584 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1585 static int mce_chrdev_open_count; /* #times opened */
1586 static int mce_chrdev_open_exclu; /* already open exclusive? */
1588 static int mce_chrdev_open(struct inode *inode, struct file *file)
1590 spin_lock(&mce_chrdev_state_lock);
1592 if (mce_chrdev_open_exclu ||
1593 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1594 spin_unlock(&mce_chrdev_state_lock);
1599 if (file->f_flags & O_EXCL)
1600 mce_chrdev_open_exclu = 1;
1601 mce_chrdev_open_count++;
1603 spin_unlock(&mce_chrdev_state_lock);
1605 return nonseekable_open(inode, file);
1608 static int mce_chrdev_release(struct inode *inode, struct file *file)
1610 spin_lock(&mce_chrdev_state_lock);
1612 mce_chrdev_open_count--;
1613 mce_chrdev_open_exclu = 0;
1615 spin_unlock(&mce_chrdev_state_lock);
1620 static void collect_tscs(void *data)
1622 unsigned long *cpu_tsc = (unsigned long *)data;
1624 rdtscll(cpu_tsc[smp_processor_id()]);
1627 static int mce_apei_read_done;
1629 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1630 static int __mce_read_apei(char __user **ubuf, size_t usize)
1636 if (usize < sizeof(struct mce))
1639 rc = apei_read_mce(&m, &record_id);
1640 /* Error or no more MCE record */
1642 mce_apei_read_done = 1;
1644 * When ERST is disabled, mce_chrdev_read() should return
1645 * "no record" instead of "no device."
1652 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1655 * In fact, we should have cleared the record after that has
1656 * been flushed to the disk or sent to network in
1657 * /sbin/mcelog, but we have no interface to support that now,
1658 * so just clear it to avoid duplication.
1660 rc = apei_clear_mce(record_id);
1662 mce_apei_read_done = 1;
1665 *ubuf += sizeof(struct mce);
1670 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1671 size_t usize, loff_t *off)
1673 char __user *buf = ubuf;
1674 unsigned long *cpu_tsc;
1675 unsigned prev, next;
1678 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1682 mutex_lock(&mce_chrdev_read_mutex);
1684 if (!mce_apei_read_done) {
1685 err = __mce_read_apei(&buf, usize);
1686 if (err || buf != ubuf)
1690 next = rcu_dereference_check_mce(mcelog.next);
1692 /* Only supports full reads right now */
1694 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1700 for (i = prev; i < next; i++) {
1701 unsigned long start = jiffies;
1702 struct mce *m = &mcelog.entry[i];
1704 while (!m->finished) {
1705 if (time_after_eq(jiffies, start + 2)) {
1706 memset(m, 0, sizeof(*m));
1712 err |= copy_to_user(buf, m, sizeof(*m));
1718 memset(mcelog.entry + prev, 0,
1719 (next - prev) * sizeof(struct mce));
1721 next = cmpxchg(&mcelog.next, prev, 0);
1722 } while (next != prev);
1724 synchronize_sched();
1727 * Collect entries that were still getting written before the
1730 on_each_cpu(collect_tscs, cpu_tsc, 1);
1732 for (i = next; i < MCE_LOG_LEN; i++) {
1733 struct mce *m = &mcelog.entry[i];
1735 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1736 err |= copy_to_user(buf, m, sizeof(*m));
1739 memset(m, 0, sizeof(*m));
1747 mutex_unlock(&mce_chrdev_read_mutex);
1750 return err ? err : buf - ubuf;
1753 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1755 poll_wait(file, &mce_chrdev_wait, wait);
1756 if (rcu_access_index(mcelog.next))
1757 return POLLIN | POLLRDNORM;
1758 if (!mce_apei_read_done && apei_check_mce())
1759 return POLLIN | POLLRDNORM;
1763 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1766 int __user *p = (int __user *)arg;
1768 if (!capable(CAP_SYS_ADMIN))
1772 case MCE_GET_RECORD_LEN:
1773 return put_user(sizeof(struct mce), p);
1774 case MCE_GET_LOG_LEN:
1775 return put_user(MCE_LOG_LEN, p);
1776 case MCE_GETCLEAR_FLAGS: {
1780 flags = mcelog.flags;
1781 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1783 return put_user(flags, p);
1790 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1791 size_t usize, loff_t *off);
1793 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1794 const char __user *ubuf,
1795 size_t usize, loff_t *off))
1799 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1801 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1802 size_t usize, loff_t *off)
1805 return mce_write(filp, ubuf, usize, off);
1810 static const struct file_operations mce_chrdev_ops = {
1811 .open = mce_chrdev_open,
1812 .release = mce_chrdev_release,
1813 .read = mce_chrdev_read,
1814 .write = mce_chrdev_write,
1815 .poll = mce_chrdev_poll,
1816 .unlocked_ioctl = mce_chrdev_ioctl,
1817 .llseek = no_llseek,
1820 static struct miscdevice mce_chrdev_device = {
1827 * mce=off Disables machine check
1828 * mce=no_cmci Disables CMCI
1829 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1830 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1831 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1832 * monarchtimeout is how long to wait for other CPUs on machine
1833 * check, or 0 to not wait
1834 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1835 * mce=nobootlog Don't log MCEs from before booting.
1837 static int __init mcheck_enable(char *str)
1845 if (!strcmp(str, "off"))
1847 else if (!strcmp(str, "no_cmci"))
1848 mce_cmci_disabled = 1;
1849 else if (!strcmp(str, "dont_log_ce"))
1850 mce_dont_log_ce = 1;
1851 else if (!strcmp(str, "ignore_ce"))
1853 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1854 mce_bootlog = (str[0] == 'b');
1855 else if (isdigit(str[0])) {
1856 get_option(&str, &tolerant);
1859 get_option(&str, &monarch_timeout);
1862 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1868 __setup("mce", mcheck_enable);
1870 int __init mcheck_init(void)
1872 mcheck_intel_therm_init();
1878 * mce_syscore: PM support
1882 * Disable machine checks on suspend and shutdown. We can't really handle
1885 static int mce_disable_error_reporting(void)
1889 for (i = 0; i < banks; i++) {
1890 struct mce_bank *b = &mce_banks[i];
1893 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1898 static int mce_syscore_suspend(void)
1900 return mce_disable_error_reporting();
1903 static void mce_syscore_shutdown(void)
1905 mce_disable_error_reporting();
1909 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1910 * Only one CPU is active at this time, the others get re-added later using
1913 static void mce_syscore_resume(void)
1915 __mcheck_cpu_init_generic();
1916 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1919 static struct syscore_ops mce_syscore_ops = {
1920 .suspend = mce_syscore_suspend,
1921 .shutdown = mce_syscore_shutdown,
1922 .resume = mce_syscore_resume,
1926 * mce_device: Sysfs support
1929 static void mce_cpu_restart(void *data)
1931 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1933 __mcheck_cpu_init_generic();
1934 __mcheck_cpu_init_timer();
1937 /* Reinit MCEs after user configuration changes */
1938 static void mce_restart(void)
1940 mce_timer_delete_all();
1941 on_each_cpu(mce_cpu_restart, NULL, 1);
1944 /* Toggle features for corrected errors */
1945 static void mce_disable_cmci(void *data)
1947 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1952 static void mce_enable_ce(void *all)
1954 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1959 __mcheck_cpu_init_timer();
1962 static struct bus_type mce_subsys = {
1963 .name = "machinecheck",
1964 .dev_name = "machinecheck",
1967 DEFINE_PER_CPU(struct device *, mce_device);
1970 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1972 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
1974 return container_of(attr, struct mce_bank, attr);
1977 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
1980 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1983 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
1984 const char *buf, size_t size)
1988 if (strict_strtoull(buf, 0, &new) < 0)
1991 attr_to_bank(attr)->ctl = new;
1998 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2000 strcpy(buf, mce_helper);
2002 return strlen(mce_helper) + 1;
2005 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2006 const char *buf, size_t siz)
2010 strncpy(mce_helper, buf, sizeof(mce_helper));
2011 mce_helper[sizeof(mce_helper)-1] = 0;
2012 p = strchr(mce_helper, '\n');
2017 return strlen(mce_helper) + !!p;
2020 static ssize_t set_ignore_ce(struct device *s,
2021 struct device_attribute *attr,
2022 const char *buf, size_t size)
2026 if (strict_strtoull(buf, 0, &new) < 0)
2029 if (mce_ignore_ce ^ !!new) {
2031 /* disable ce features */
2032 mce_timer_delete_all();
2033 on_each_cpu(mce_disable_cmci, NULL, 1);
2036 /* enable ce features */
2038 on_each_cpu(mce_enable_ce, (void *)1, 1);
2044 static ssize_t set_cmci_disabled(struct device *s,
2045 struct device_attribute *attr,
2046 const char *buf, size_t size)
2050 if (strict_strtoull(buf, 0, &new) < 0)
2053 if (mce_cmci_disabled ^ !!new) {
2056 on_each_cpu(mce_disable_cmci, NULL, 1);
2057 mce_cmci_disabled = 1;
2060 mce_cmci_disabled = 0;
2061 on_each_cpu(mce_enable_ce, NULL, 1);
2067 static ssize_t store_int_with_restart(struct device *s,
2068 struct device_attribute *attr,
2069 const char *buf, size_t size)
2071 ssize_t ret = device_store_int(s, attr, buf, size);
2076 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2077 static DEVICE_INT_ATTR(tolerant, 0644, tolerant);
2078 static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
2079 static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
2081 static struct dev_ext_attribute dev_attr_check_interval = {
2082 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2086 static struct dev_ext_attribute dev_attr_ignore_ce = {
2087 __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce),
2091 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2092 __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled),
2096 static struct device_attribute *mce_device_attrs[] = {
2097 &dev_attr_tolerant.attr,
2098 &dev_attr_check_interval.attr,
2100 &dev_attr_monarch_timeout.attr,
2101 &dev_attr_dont_log_ce.attr,
2102 &dev_attr_ignore_ce.attr,
2103 &dev_attr_cmci_disabled.attr,
2107 static cpumask_var_t mce_device_initialized;
2109 static void mce_device_release(struct device *dev)
2114 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2115 static __cpuinit int mce_device_create(unsigned int cpu)
2121 if (!mce_available(&boot_cpu_data))
2124 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2128 dev->bus = &mce_subsys;
2129 dev->release = &mce_device_release;
2131 err = device_register(dev);
2135 for (i = 0; mce_device_attrs[i]; i++) {
2136 err = device_create_file(dev, mce_device_attrs[i]);
2140 for (j = 0; j < banks; j++) {
2141 err = device_create_file(dev, &mce_banks[j].attr);
2145 cpumask_set_cpu(cpu, mce_device_initialized);
2146 per_cpu(mce_device, cpu) = dev;
2151 device_remove_file(dev, &mce_banks[j].attr);
2154 device_remove_file(dev, mce_device_attrs[i]);
2156 device_unregister(dev);
2161 static __cpuinit void mce_device_remove(unsigned int cpu)
2163 struct device *dev = per_cpu(mce_device, cpu);
2166 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2169 for (i = 0; mce_device_attrs[i]; i++)
2170 device_remove_file(dev, mce_device_attrs[i]);
2172 for (i = 0; i < banks; i++)
2173 device_remove_file(dev, &mce_banks[i].attr);
2175 device_unregister(dev);
2176 cpumask_clear_cpu(cpu, mce_device_initialized);
2177 per_cpu(mce_device, cpu) = NULL;
2180 /* Make sure there are no machine checks on offlined CPUs. */
2181 static void __cpuinit mce_disable_cpu(void *h)
2183 unsigned long action = *(unsigned long *)h;
2186 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2189 if (!(action & CPU_TASKS_FROZEN))
2191 for (i = 0; i < banks; i++) {
2192 struct mce_bank *b = &mce_banks[i];
2195 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2199 static void __cpuinit mce_reenable_cpu(void *h)
2201 unsigned long action = *(unsigned long *)h;
2204 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2207 if (!(action & CPU_TASKS_FROZEN))
2209 for (i = 0; i < banks; i++) {
2210 struct mce_bank *b = &mce_banks[i];
2213 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2217 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2218 static int __cpuinit
2219 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2221 unsigned int cpu = (unsigned long)hcpu;
2222 struct timer_list *t = &per_cpu(mce_timer, cpu);
2226 case CPU_ONLINE_FROZEN:
2227 mce_device_create(cpu);
2228 if (threshold_cpu_callback)
2229 threshold_cpu_callback(action, cpu);
2232 case CPU_DEAD_FROZEN:
2233 if (threshold_cpu_callback)
2234 threshold_cpu_callback(action, cpu);
2235 mce_device_remove(cpu);
2237 case CPU_DOWN_PREPARE:
2238 case CPU_DOWN_PREPARE_FROZEN:
2240 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2242 case CPU_DOWN_FAILED:
2243 case CPU_DOWN_FAILED_FROZEN:
2244 if (!mce_ignore_ce && check_interval) {
2245 t->expires = round_jiffies(jiffies +
2246 __get_cpu_var(mce_next_interval));
2247 add_timer_on(t, cpu);
2249 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2252 /* intentionally ignoring frozen here */
2253 cmci_rediscover(cpu);
2259 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2260 .notifier_call = mce_cpu_callback,
2263 static __init void mce_init_banks(void)
2267 for (i = 0; i < banks; i++) {
2268 struct mce_bank *b = &mce_banks[i];
2269 struct device_attribute *a = &b->attr;
2271 sysfs_attr_init(&a->attr);
2272 a->attr.name = b->attrname;
2273 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2275 a->attr.mode = 0644;
2276 a->show = show_bank;
2277 a->store = set_bank;
2281 static __init int mcheck_init_device(void)
2286 if (!mce_available(&boot_cpu_data))
2289 zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL);
2293 err = subsys_system_register(&mce_subsys, NULL);
2297 for_each_online_cpu(i) {
2298 err = mce_device_create(i);
2303 register_syscore_ops(&mce_syscore_ops);
2304 register_hotcpu_notifier(&mce_cpu_notifier);
2306 /* register character device /dev/mcelog */
2307 misc_register(&mce_chrdev_device);
2309 #ifdef CONFIG_X86_XEN_MCE
2310 if (is_initial_xendomain()) {
2311 /* Register vIRQ handler for MCE LOG processing */
2312 extern int bind_virq_for_mce(void);
2314 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2315 bind_virq_for_mce();
2321 device_initcall(mcheck_init_device);
2324 * Old style boot options parsing. Only for compatibility.
2326 static int __init mcheck_disable(char *str)
2331 __setup("nomce", mcheck_disable);
2333 #ifdef CONFIG_DEBUG_FS
2334 struct dentry *mce_get_debugfs_dir(void)
2336 static struct dentry *dmce;
2339 dmce = debugfs_create_dir("mce", NULL);
2344 static void mce_reset(void)
2347 atomic_set(&mce_fake_paniced, 0);
2348 atomic_set(&mce_executing, 0);
2349 atomic_set(&mce_callin, 0);
2350 atomic_set(&global_nwo, 0);
2353 static int fake_panic_get(void *data, u64 *val)
2359 static int fake_panic_set(void *data, u64 val)
2366 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2367 fake_panic_set, "%llu\n");
2369 static int __init mcheck_debugfs_init(void)
2371 struct dentry *dmce, *ffake_panic;
2373 dmce = mce_get_debugfs_dir();
2376 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2383 late_initcall(mcheck_debugfs_init);