drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <linux/delay.h>
  25 #include <asm/smp.h>
  26 #include "agp.h"
  27 #include "intel-agp.h"
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_INTEL_IOMMU
  37 #define USE_PCI_DMA_API 1
  38 #else
  39 #define USE_PCI_DMA_API 0
  40 #endif
  41
  42 struct intel_gtt_driver {
  43         unsigned int gen : 8;
  44         unsigned int is_g33 : 1;
  45         unsigned int is_pineview : 1;
  46         unsigned int is_ironlake : 1;
  47         unsigned int has_pgtbl_enable : 1;
  48         unsigned int dma_mask_size : 8;
  49         /* Chipset specific GTT setup */
  50         int (*setup)(void);
  51         /* This should undo anything done in ->setup() save the unmapping
  52          * of the mmio register file, that's done in the generic code. */
  53         void (*cleanup)(void);
  54         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  55         /* Flags is a more or less chipset specific opaque value.
  56          * For chipsets that need to support old ums (non-gem) code, this
  57          * needs to be identical to the various supported agp memory types! */
  58         bool (*check_flags)(unsigned int flags);
  59         void (*chipset_flush)(void);
  60 };
  61
  62 static struct _intel_private {
  63         struct intel_gtt base;
  64         const struct intel_gtt_driver *driver;
  65         struct pci_dev *pcidev; /* device one */
  66         struct pci_dev *bridge_dev;
  67         u8 __iomem *registers;
  68         phys_addr_t gtt_bus_addr;
  69         phys_addr_t gma_bus_addr;
  70         u32 PGETBL_save;
  71         u32 __iomem *gtt;               /* I915G */
  72         bool clear_fake_agp; /* on first access via agp, fill with scratch */
  73         int num_dcache_entries;
  74         void __iomem *i9xx_flush_page;
  75         char *i81x_gtt_table;
  76         struct resource ifp_resource;
  77         int resource_valid;
  78         struct page *scratch_page;
  79         dma_addr_t scratch_page_dma;
  80 } intel_private;
  81
  82 #define INTEL_GTT_GEN   intel_private.driver->gen
  83 #define IS_G33          intel_private.driver->is_g33
  84 #define IS_PINEVIEW     intel_private.driver->is_pineview
  85 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  86 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  87
  88 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
  89                          struct scatterlist **sg_list, int *num_sg)
  90 {
  91         struct sg_table st;
  92         struct scatterlist *sg;
  93         int i;
  94
  95         if (*sg_list)
  96                 return 0; /* already mapped (for e.g. resume */
  97
  98         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
  99
 100         if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
 101                 goto err;
 102
 103         *sg_list = sg = st.sgl;
 104
 105         for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
 106                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
 107
 108         *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
 109                                  num_entries, PCI_DMA_BIDIRECTIONAL);
 110         if (unlikely(!*num_sg))
 111                 goto err;
 112
 113         return 0;
 114
 115 err:
 116         sg_free_table(&st);
 117         return -ENOMEM;
 118 }
 119 EXPORT_SYMBOL(intel_gtt_map_memory);
 120
 121 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
 122 {
 123         struct sg_table st;
 124         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 125
 126         pci_unmap_sg(intel_private.pcidev, sg_list,
 127                      num_sg, PCI_DMA_BIDIRECTIONAL);
 128
 129         st.sgl = sg_list;
 130         st.orig_nents = st.nents = num_sg;
 131
 132         sg_free_table(&st);
 133 }
 134 EXPORT_SYMBOL(intel_gtt_unmap_memory);
 135
 136 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 137 {
 138         return;
 139 }
 140
 141 /* Exists to support ARGB cursors */
 142 static struct page *i8xx_alloc_pages(void)
 143 {
 144         struct page *page;
 145
 146         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 147         if (page == NULL)
 148                 return NULL;
 149
 150 #ifdef CONFIG_XEN
 151         if (xen_create_contiguous_region((unsigned long)page_address(page), 2, 32)) {
 152                 __free_pages(page, 2);
 153                 return NULL;
 154         }
 155 #endif
 156
 157         if (set_pages_uc(page, 4) < 0) {
 158                 set_pages_wb(page, 4);
 159 #ifdef CONFIG_XEN
 160                 xen_destroy_contiguous_region((unsigned long)page_address(page),
 161                                               2);
 162 #endif
 163                 __free_pages(page, 2);
 164                 return NULL;
 165         }
 166         get_page(page);
 167         atomic_inc(&agp_bridge->current_memory_agp);
 168         return page;
 169 }
 170
 171 static void i8xx_destroy_pages(struct page *page)
 172 {
 173         if (page == NULL)
 174                 return;
 175
 176         set_pages_wb(page, 4);
 177 #ifdef CONFIG_XEN
 178         xen_destroy_contiguous_region((unsigned long)page_address(page), 2);
 179 #endif
 180         put_page(page);
 181         __free_pages(page, 2);
 182         atomic_dec(&agp_bridge->current_memory_agp);
 183 }
 184
 185 #define I810_GTT_ORDER 4
 186 static int i810_setup(void)
 187 {
 188         u32 reg_addr;
 189         char *gtt_table;
 190
 191         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 192         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 193         if (gtt_table == NULL)
 194                 return -ENOMEM;
 195         intel_private.i81x_gtt_table = gtt_table;
 196
 197         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 198         reg_addr &= 0xfff80000;
 199
 200         intel_private.registers = ioremap(reg_addr, KB(64));
 201         if (!intel_private.registers)
 202                 return -ENOMEM;
 203
 204         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 205                intel_private.registers+I810_PGETBL_CTL);
 206
 207         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 208
 209         if ((readl(intel_private.registers+I810_DRAM_CTL)
 210                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 211                 dev_info(&intel_private.pcidev->dev,
 212                          "detected 4MB dedicated video ram\n");
 213                 intel_private.num_dcache_entries = 1024;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void i810_cleanup(void)
 220 {
 221         writel(0, intel_private.registers+I810_PGETBL_CTL);
 222         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 223 }
 224
 225 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 226                                       int type)
 227 {
 228         int i;
 229
 230         if ((pg_start + mem->page_count)
 231                         > intel_private.num_dcache_entries)
 232                 return -EINVAL;
 233
 234         if (!mem->is_flushed)
 235                 global_cache_flush();
 236
 237         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 238                 dma_addr_t addr = i << PAGE_SHIFT;
 239                 intel_private.driver->write_entry(addr,
 240                                                   i, type);
 241         }
 242         readl(intel_private.gtt+i-1);
 243
 244         return 0;
 245 }
 246
 247 /*
 248  * The i810/i830 requires a physical address to program its mouse
 249  * pointer into hardware.
 250  * However the Xserver still writes to it through the agp aperture.
 251  */
 252 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 253 {
 254         struct agp_memory *new;
 255         struct page *page;
 256
 257         switch (pg_count) {
 258         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 259                 break;
 260         case 4:
 261                 /* kludge to get 4 physical pages for ARGB cursor */
 262                 page = i8xx_alloc_pages();
 263                 break;
 264         default:
 265                 return NULL;
 266         }
 267
 268         if (page == NULL)
 269                 return NULL;
 270
 271         new = agp_create_memory(pg_count);
 272         if (new == NULL)
 273                 return NULL;
 274
 275         new->pages[0] = page;
 276         if (pg_count == 4) {
 277                 /* kludge to get 4 physical pages for ARGB cursor */
 278                 new->pages[1] = new->pages[0] + 1;
 279                 new->pages[2] = new->pages[1] + 1;
 280                 new->pages[3] = new->pages[2] + 1;
 281         }
 282         new->page_count = pg_count;
 283         new->num_scratch_pages = pg_count;
 284         new->type = AGP_PHYS_MEMORY;
 285 #ifndef CONFIG_XEN
 286         new->physical = page_to_phys(new->pages[0]);
 287 #else
 288         new->physical = page_to_pseudophys(new->pages[0]);
 289 #endif
 290         return new;
 291 }
 292
 293 static void intel_i810_free_by_type(struct agp_memory *curr)
 294 {
 295         agp_free_key(curr->key);
 296         if (curr->type == AGP_PHYS_MEMORY) {
 297                 if (curr->page_count == 4)
 298                         i8xx_destroy_pages(curr->pages[0]);
 299                 else {
 300                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 301                                                              AGP_PAGE_DESTROY_UNMAP);
 302                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 303                                                              AGP_PAGE_DESTROY_FREE);
 304                 }
 305                 agp_free_page_array(curr);
 306         }
 307         kfree(curr);
 308 }
 309
 310 static int intel_gtt_setup_scratch_page(void)
 311 {
 312         struct page *page;
 313         dma_addr_t dma_addr;
 314
 315         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 316         if (page == NULL)
 317                 return -ENOMEM;
 318         get_page(page);
 319         set_pages_uc(page, 1);
 320
 321         if (intel_private.base.needs_dmar) {
 322                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 323                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 324                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 325                         return -EINVAL;
 326
 327                 intel_private.scratch_page_dma = dma_addr;
 328         } else
 329                 intel_private.scratch_page_dma = page_to_phys(page);
 330
 331         intel_private.scratch_page = page;
 332
 333         return 0;
 334 }
 335
 336 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 337                              unsigned int flags)
 338 {
 339         u32 pte_flags = I810_PTE_VALID;
 340
 341         switch (flags) {
 342         case AGP_DCACHE_MEMORY:
 343                 pte_flags |= I810_PTE_LOCAL;
 344                 break;
 345         case AGP_USER_CACHED_MEMORY:
 346                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 347                 break;
 348         }
 349
 350         writel(addr | pte_flags, intel_private.gtt + entry);
 351 }
 352
 353 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
 354         {32, 8192, 3},
 355         {64, 16384, 4},
 356         {128, 32768, 5},
 357         {256, 65536, 6},
 358         {512, 131072, 7},
 359 };
 360
 361 static unsigned int intel_gtt_stolen_size(void)
 362 {
 363         u16 gmch_ctrl;
 364         u8 rdct;
 365         int local = 0;
 366         static const int ddt[4] = { 0, 16, 32, 64 };
 367         unsigned int stolen_size = 0;
 368
 369         if (INTEL_GTT_GEN == 1)
 370                 return 0; /* no stolen mem on i81x */
 371
 372         pci_read_config_word(intel_private.bridge_dev,
 373                              I830_GMCH_CTRL, &gmch_ctrl);
 374
 375         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 376             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 377                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 378                 case I830_GMCH_GMS_STOLEN_512:
 379                         stolen_size = KB(512);
 380                         break;
 381                 case I830_GMCH_GMS_STOLEN_1024:
 382                         stolen_size = MB(1);
 383                         break;
 384                 case I830_GMCH_GMS_STOLEN_8192:
 385                         stolen_size = MB(8);
 386                         break;
 387                 case I830_GMCH_GMS_LOCAL:
 388                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 389                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 390                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 391                         local = 1;
 392                         break;
 393                 default:
 394                         stolen_size = 0;
 395                         break;
 396                 }
 397         } else if (INTEL_GTT_GEN == 6) {
 398                 /*
 399                  * SandyBridge has new memory control reg at 0x50.w
 400                  */
 401                 u16 snb_gmch_ctl;
 402                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 403                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 404                 case SNB_GMCH_GMS_STOLEN_32M:
 405                         stolen_size = MB(32);
 406                         break;
 407                 case SNB_GMCH_GMS_STOLEN_64M:
 408                         stolen_size = MB(64);
 409                         break;
 410                 case SNB_GMCH_GMS_STOLEN_96M:
 411                         stolen_size = MB(96);
 412                         break;
 413                 case SNB_GMCH_GMS_STOLEN_128M:
 414                         stolen_size = MB(128);
 415                         break;
 416                 case SNB_GMCH_GMS_STOLEN_160M:
 417                         stolen_size = MB(160);
 418                         break;
 419                 case SNB_GMCH_GMS_STOLEN_192M:
 420                         stolen_size = MB(192);
 421                         break;
 422                 case SNB_GMCH_GMS_STOLEN_224M:
 423                         stolen_size = MB(224);
 424                         break;
 425                 case SNB_GMCH_GMS_STOLEN_256M:
 426                         stolen_size = MB(256);
 427                         break;
 428                 case SNB_GMCH_GMS_STOLEN_288M:
 429                         stolen_size = MB(288);
 430                         break;
 431                 case SNB_GMCH_GMS_STOLEN_320M:
 432                         stolen_size = MB(320);
 433                         break;
 434                 case SNB_GMCH_GMS_STOLEN_352M:
 435                         stolen_size = MB(352);
 436                         break;
 437                 case SNB_GMCH_GMS_STOLEN_384M:
 438                         stolen_size = MB(384);
 439                         break;
 440                 case SNB_GMCH_GMS_STOLEN_416M:
 441                         stolen_size = MB(416);
 442                         break;
 443                 case SNB_GMCH_GMS_STOLEN_448M:
 444                         stolen_size = MB(448);
 445                         break;
 446                 case SNB_GMCH_GMS_STOLEN_480M:
 447                         stolen_size = MB(480);
 448                         break;
 449                 case SNB_GMCH_GMS_STOLEN_512M:
 450                         stolen_size = MB(512);
 451                         break;
 452                 }
 453         } else {
 454                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 455                 case I855_GMCH_GMS_STOLEN_1M:
 456                         stolen_size = MB(1);
 457                         break;
 458                 case I855_GMCH_GMS_STOLEN_4M:
 459                         stolen_size = MB(4);
 460                         break;
 461                 case I855_GMCH_GMS_STOLEN_8M:
 462                         stolen_size = MB(8);
 463                         break;
 464                 case I855_GMCH_GMS_STOLEN_16M:
 465                         stolen_size = MB(16);
 466                         break;
 467                 case I855_GMCH_GMS_STOLEN_32M:
 468                         stolen_size = MB(32);
 469                         break;
 470                 case I915_GMCH_GMS_STOLEN_48M:
 471                         stolen_size = MB(48);
 472                         break;
 473                 case I915_GMCH_GMS_STOLEN_64M:
 474                         stolen_size = MB(64);
 475                         break;
 476                 case G33_GMCH_GMS_STOLEN_128M:
 477                         stolen_size = MB(128);
 478                         break;
 479                 case G33_GMCH_GMS_STOLEN_256M:
 480                         stolen_size = MB(256);
 481                         break;
 482                 case INTEL_GMCH_GMS_STOLEN_96M:
 483                         stolen_size = MB(96);
 484                         break;
 485                 case INTEL_GMCH_GMS_STOLEN_160M:
 486                         stolen_size = MB(160);
 487                         break;
 488                 case INTEL_GMCH_GMS_STOLEN_224M:
 489                         stolen_size = MB(224);
 490                         break;
 491                 case INTEL_GMCH_GMS_STOLEN_352M:
 492                         stolen_size = MB(352);
 493                         break;
 494                 default:
 495                         stolen_size = 0;
 496                         break;
 497                 }
 498         }
 499
 500         if (stolen_size > 0) {
 501                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 502                        stolen_size / KB(1), local ? "local" : "stolen");
 503         } else {
 504                 dev_info(&intel_private.bridge_dev->dev,
 505                        "no pre-allocated video memory detected\n");
 506                 stolen_size = 0;
 507         }
 508
 509         return stolen_size;
 510 }
 511
 512 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 513 {
 514         u32 pgetbl_ctl, pgetbl_ctl2;
 515
 516         /* ensure that ppgtt is disabled */
 517         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 518         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 519         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 520
 521         /* write the new ggtt size */
 522         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 523         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 524         pgetbl_ctl |= size_flag;
 525         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 526 }
 527
 528 static unsigned int i965_gtt_total_entries(void)
 529 {
 530         int size;
 531         u32 pgetbl_ctl;
 532         u16 gmch_ctl;
 533
 534         pci_read_config_word(intel_private.bridge_dev,
 535                              I830_GMCH_CTRL, &gmch_ctl);
 536
 537         if (INTEL_GTT_GEN == 5) {
 538                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 539                 case G4x_GMCH_SIZE_1M:
 540                 case G4x_GMCH_SIZE_VT_1M:
 541                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 542                         break;
 543                 case G4x_GMCH_SIZE_VT_1_5M:
 544                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 545                         break;
 546                 case G4x_GMCH_SIZE_2M:
 547                 case G4x_GMCH_SIZE_VT_2M:
 548                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 549                         break;
 550                 }
 551         }
 552
 553         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 554
 555         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 556         case I965_PGETBL_SIZE_128KB:
 557                 size = KB(128);
 558                 break;
 559         case I965_PGETBL_SIZE_256KB:
 560                 size = KB(256);
 561                 break;
 562         case I965_PGETBL_SIZE_512KB:
 563                 size = KB(512);
 564                 break;
 565         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 566         case I965_PGETBL_SIZE_1MB:
 567                 size = KB(1024);
 568                 break;
 569         case I965_PGETBL_SIZE_2MB:
 570                 size = KB(2048);
 571                 break;
 572         case I965_PGETBL_SIZE_1_5MB:
 573                 size = KB(1024 + 512);
 574                 break;
 575         default:
 576                 dev_info(&intel_private.pcidev->dev,
 577                          "unknown page table size, assuming 512KB\n");
 578                 size = KB(512);
 579         }
 580
 581         return size/4;
 582 }
 583
 584 static unsigned int intel_gtt_total_entries(void)
 585 {
 586         int size;
 587
 588         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 589                 return i965_gtt_total_entries();
 590         else if (INTEL_GTT_GEN == 6) {
 591                 u16 snb_gmch_ctl;
 592
 593                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 594                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
 595                 default:
 596                 case SNB_GTT_SIZE_0M:
 597                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
 598                         size = MB(0);
 599                         break;
 600                 case SNB_GTT_SIZE_1M:
 601                         size = MB(1);
 602                         break;
 603                 case SNB_GTT_SIZE_2M:
 604                         size = MB(2);
 605                         break;
 606                 }
 607                 return size/4;
 608         } else {
 609                 /* On previous hardware, the GTT size was just what was
 610                  * required to map the aperture.
 611                  */
 612                 return intel_private.base.gtt_mappable_entries;
 613         }
 614 }
 615
 616 static unsigned int intel_gtt_mappable_entries(void)
 617 {
 618         unsigned int aperture_size;
 619
 620         if (INTEL_GTT_GEN == 1) {
 621                 u32 smram_miscc;
 622
 623                 pci_read_config_dword(intel_private.bridge_dev,
 624                                       I810_SMRAM_MISCC, &smram_miscc);
 625
 626                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 627                                 == I810_GFX_MEM_WIN_32M)
 628                         aperture_size = MB(32);
 629                 else
 630                         aperture_size = MB(64);
 631         } else if (INTEL_GTT_GEN == 2) {
 632                 u16 gmch_ctrl;
 633
 634                 pci_read_config_word(intel_private.bridge_dev,
 635                                      I830_GMCH_CTRL, &gmch_ctrl);
 636
 637                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 638                         aperture_size = MB(64);
 639                 else
 640                         aperture_size = MB(128);
 641         } else {
 642                 /* 9xx supports large sizes, just look at the length */
 643                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 644         }
 645
 646         return aperture_size >> PAGE_SHIFT;
 647 }
 648
 649 static void intel_gtt_teardown_scratch_page(void)
 650 {
 651         set_pages_wb(intel_private.scratch_page, 1);
 652         pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
 653                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 654         put_page(intel_private.scratch_page);
 655         __free_page(intel_private.scratch_page);
 656 }
 657
 658 static void intel_gtt_cleanup(void)
 659 {
 660         intel_private.driver->cleanup();
 661
 662         iounmap(intel_private.gtt);
 663         iounmap(intel_private.registers);
 664
 665         intel_gtt_teardown_scratch_page();
 666 }
 667
 668 static int intel_gtt_init(void)
 669 {
 670         u32 gtt_map_size;
 671         int ret;
 672
 673         ret = intel_private.driver->setup();
 674         if (ret != 0)
 675                 return ret;
 676
 677         intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
 678         intel_private.base.gtt_total_entries = intel_gtt_total_entries();
 679
 680         /* save the PGETBL reg for resume */
 681         intel_private.PGETBL_save =
 682                 readl(intel_private.registers+I810_PGETBL_CTL)
 683                         & ~I810_PGETBL_ENABLED;
 684         /* we only ever restore the register when enabling the PGTBL... */
 685         if (HAS_PGTBL_EN)
 686                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 687
 688         dev_info(&intel_private.bridge_dev->dev,
 689                         "detected gtt size: %dK total, %dK mappable\n",
 690                         intel_private.base.gtt_total_entries * 4,
 691                         intel_private.base.gtt_mappable_entries * 4);
 692
 693         gtt_map_size = intel_private.base.gtt_total_entries * 4;
 694
 695         intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
 696                                     gtt_map_size);
 697         if (!intel_private.gtt) {
 698                 intel_private.driver->cleanup();
 699                 iounmap(intel_private.registers);
 700                 return -ENOMEM;
 701         }
 702
 703         global_cache_flush();   /* FIXME: ? */
 704
 705         intel_private.base.stolen_size = intel_gtt_stolen_size();
 706
 707         intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
 708
 709         ret = intel_gtt_setup_scratch_page();
 710         if (ret != 0) {
 711                 intel_gtt_cleanup();
 712                 return ret;
 713         }
 714
 715         return 0;
 716 }
 717
 718 static int intel_fake_agp_fetch_size(void)
 719 {
 720         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 721         unsigned int aper_size;
 722         int i;
 723
 724         aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
 725                     / MB(1);
 726
 727         for (i = 0; i < num_sizes; i++) {
 728                 if (aper_size == intel_fake_agp_sizes[i].size) {
 729                         agp_bridge->current_size =
 730                                 (void *) (intel_fake_agp_sizes + i);
 731                         return aper_size;
 732                 }
 733         }
 734
 735         return 0;
 736 }
 737
 738 static void i830_cleanup(void)
 739 {
 740 }
 741
 742 /* The chipset_flush interface needs to get data that has already been
 743  * flushed out of the CPU all the way out to main memory, because the GPU
 744  * doesn't snoop those buffers.
 745  *
 746  * The 8xx series doesn't have the same lovely interface for flushing the
 747  * chipset write buffers that the later chips do. According to the 865
 748  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 749  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 750  * that it'll push whatever was in there out.  It appears to work.
 751  */
 752 static void i830_chipset_flush(void)
 753 {
 754         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 755
 756         /* Forcibly evict everything from the CPU write buffers.
 757          * clflush appears to be insufficient.
 758          */
 759         wbinvd_on_all_cpus();
 760
 761         /* Now we've only seen documents for this magic bit on 855GM,
 762          * we hope it exists for the other gen2 chipsets...
 763          *
 764          * Also works as advertised on my 845G.
 765          */
 766         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
 767                intel_private.registers+I830_HIC);
 768
 769         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
 770                 if (time_after(jiffies, timeout))
 771                         break;
 772
 773                 udelay(50);
 774         }
 775 }
 776
 777 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 778                              unsigned int flags)
 779 {
 780         u32 pte_flags = I810_PTE_VALID;
 781
 782         if (flags ==  AGP_USER_CACHED_MEMORY)
 783                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 784
 785         writel(addr | pte_flags, intel_private.gtt + entry);
 786 }
 787
 788 static bool intel_enable_gtt(void)
 789 {
 790         u32 gma_addr;
 791         u8 __iomem *reg;
 792
 793         if (INTEL_GTT_GEN <= 2)
 794                 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
 795                                       &gma_addr);
 796         else
 797                 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
 798                                       &gma_addr);
 799
 800         intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 801
 802         if (INTEL_GTT_GEN >= 6)
 803             return true;
 804
 805         if (INTEL_GTT_GEN == 2) {
 806                 u16 gmch_ctrl;
 807
 808                 pci_read_config_word(intel_private.bridge_dev,
 809                                      I830_GMCH_CTRL, &gmch_ctrl);
 810                 gmch_ctrl |= I830_GMCH_ENABLED;
 811                 pci_write_config_word(intel_private.bridge_dev,
 812                                       I830_GMCH_CTRL, gmch_ctrl);
 813
 814                 pci_read_config_word(intel_private.bridge_dev,
 815                                      I830_GMCH_CTRL, &gmch_ctrl);
 816                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 817                         dev_err(&intel_private.pcidev->dev,
 818                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 819                                 gmch_ctrl);
 820                         return false;
 821                 }
 822         }
 823
 824         /* On the resume path we may be adjusting the PGTBL value, so
 825          * be paranoid and flush all chipset write buffers...
 826          */
 827         if (INTEL_GTT_GEN >= 3)
 828                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 829
 830         reg = intel_private.registers+I810_PGETBL_CTL;
 831         writel(intel_private.PGETBL_save, reg);
 832         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 833                 dev_err(&intel_private.pcidev->dev,
 834                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 835                         readl(reg), intel_private.PGETBL_save);
 836                 return false;
 837         }
 838
 839         if (INTEL_GTT_GEN >= 3)
 840                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 841
 842         return true;
 843 }
 844
 845 static int i830_setup(void)
 846 {
 847         u32 reg_addr;
 848
 849         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 850         reg_addr &= 0xfff80000;
 851
 852         intel_private.registers = ioremap(reg_addr, KB(64));
 853         if (!intel_private.registers)
 854                 return -ENOMEM;
 855
 856         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 857
 858         return 0;
 859 }
 860
 861 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 862 {
 863         agp_bridge->gatt_table_real = NULL;
 864         agp_bridge->gatt_table = NULL;
 865         agp_bridge->gatt_bus_addr = 0;
 866
 867         return 0;
 868 }
 869
 870 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 871 {
 872         return 0;
 873 }
 874
 875 static int intel_fake_agp_configure(void)
 876 {
 877         if (!intel_enable_gtt())
 878             return -EIO;
 879
 880         intel_private.clear_fake_agp = true;
 881         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
 882
 883         return 0;
 884 }
 885
 886 static bool i830_check_flags(unsigned int flags)
 887 {
 888         switch (flags) {
 889         case 0:
 890         case AGP_PHYS_MEMORY:
 891         case AGP_USER_CACHED_MEMORY:
 892         case AGP_USER_MEMORY:
 893                 return true;
 894         }
 895
 896         return false;
 897 }
 898
 899 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
 900                                  unsigned int sg_len,
 901                                  unsigned int pg_start,
 902                                  unsigned int flags)
 903 {
 904         struct scatterlist *sg;
 905         unsigned int len, m;
 906         int i, j;
 907
 908         j = pg_start;
 909
 910         /* sg may merge pages, but we have to separate
 911          * per-page addr for GTT */
 912         for_each_sg(sg_list, sg, sg_len, i) {
 913                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 914                 for (m = 0; m < len; m++) {
 915                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 916                         intel_private.driver->write_entry(addr,
 917                                                           j, flags);
 918                         j++;
 919                 }
 920         }
 921         readl(intel_private.gtt+j-1);
 922 }
 923 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 924
 925 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
 926                             struct page **pages, unsigned int flags)
 927 {
 928         int i, j;
 929
 930         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
 931                 dma_addr_t addr = page_to_phys(pages[i]);
 932                 intel_private.driver->write_entry(addr,
 933                                                   j, flags);
 934         }
 935         readl(intel_private.gtt+j-1);
 936 }
 937 EXPORT_SYMBOL(intel_gtt_insert_pages);
 938
 939 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 940                                          off_t pg_start, int type)
 941 {
 942         int ret = -EINVAL;
 943
 944         if (intel_private.base.do_idle_maps)
 945                 return -ENODEV;
 946
 947         if (intel_private.clear_fake_agp) {
 948                 int start = intel_private.base.stolen_size / PAGE_SIZE;
 949                 int end = intel_private.base.gtt_mappable_entries;
 950                 intel_gtt_clear_range(start, end - start);
 951                 intel_private.clear_fake_agp = false;
 952         }
 953
 954         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 955                 return i810_insert_dcache_entries(mem, pg_start, type);
 956
 957         if (mem->page_count == 0)
 958                 goto out;
 959
 960         if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
 961                 goto out_err;
 962
 963         if (type != mem->type)
 964                 goto out_err;
 965
 966         if (!intel_private.driver->check_flags(type))
 967                 goto out_err;
 968
 969         if (!mem->is_flushed)
 970                 global_cache_flush();
 971
 972         if (intel_private.base.needs_dmar) {
 973                 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
 974                                            &mem->sg_list, &mem->num_sg);
 975                 if (ret != 0)
 976                         return ret;
 977
 978                 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
 979                                             pg_start, type);
 980         } else
 981                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
 982                                        type);
 983
 984 out:
 985         ret = 0;
 986 out_err:
 987         mem->is_flushed = true;
 988         return ret;
 989 }
 990
 991 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 992 {
 993         unsigned int i;
 994
 995         for (i = first_entry; i < (first_entry + num_entries); i++) {
 996                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
 997                                                   i, 0);
 998         }
 999         readl(intel_private.gtt+i-1);
1000 }
1001 EXPORT_SYMBOL(intel_gtt_clear_range);
1002
1003 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
1004                                          off_t pg_start, int type)
1005 {
1006         if (mem->page_count == 0)
1007                 return 0;
1008
1009         if (intel_private.base.do_idle_maps)
1010                 return -ENODEV;
1011
1012         intel_gtt_clear_range(pg_start, mem->page_count);
1013
1014         if (intel_private.base.needs_dmar) {
1015                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
1016                 mem->sg_list = NULL;
1017                 mem->num_sg = 0;
1018         }
1019
1020         return 0;
1021 }
1022
1023 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1024                                                        int type)
1025 {
1026         struct agp_memory *new;
1027
1028         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1029                 if (pg_count != intel_private.num_dcache_entries)
1030                         return NULL;
1031
1032                 new = agp_create_memory(1);
1033                 if (new == NULL)
1034                         return NULL;
1035
1036                 new->type = AGP_DCACHE_MEMORY;
1037                 new->page_count = pg_count;
1038                 new->num_scratch_pages = 0;
1039                 agp_free_page_array(new);
1040                 return new;
1041         }
1042         if (type == AGP_PHYS_MEMORY)
1043                 return alloc_agpphysmem_i8xx(pg_count, type);
1044         /* always return NULL for other allocation types for now */
1045         return NULL;
1046 }
1047
1048 static int intel_alloc_chipset_flush_resource(void)
1049 {
1050         int ret;
1051         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1052                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1053                                      pcibios_align_resource, intel_private.bridge_dev);
1054
1055         return ret;
1056 }
1057
1058 static void intel_i915_setup_chipset_flush(void)
1059 {
1060         int ret;
1061         u32 temp;
1062
1063         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1064         if (!(temp & 0x1)) {
1065                 intel_alloc_chipset_flush_resource();
1066                 intel_private.resource_valid = 1;
1067                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1068         } else {
1069                 temp &= ~1;
1070
1071                 intel_private.resource_valid = 1;
1072                 intel_private.ifp_resource.start = temp;
1073                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1074                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1075                 /* some BIOSes reserve this area in a pnp some don't */
1076                 if (ret)
1077                         intel_private.resource_valid = 0;
1078         }
1079 }
1080
1081 static void intel_i965_g33_setup_chipset_flush(void)
1082 {
1083         u32 temp_hi, temp_lo;
1084         int ret;
1085
1086         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1087         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1088
1089         if (!(temp_lo & 0x1)) {
1090
1091                 intel_alloc_chipset_flush_resource();
1092
1093                 intel_private.resource_valid = 1;
1094                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1095                         upper_32_bits(intel_private.ifp_resource.start));
1096                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1097         } else {
1098                 u64 l64;
1099
1100                 temp_lo &= ~0x1;
1101                 l64 = ((u64)temp_hi << 32) | temp_lo;
1102
1103                 intel_private.resource_valid = 1;
1104                 intel_private.ifp_resource.start = l64;
1105                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1106                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1107                 /* some BIOSes reserve this area in a pnp some don't */
1108                 if (ret)
1109                         intel_private.resource_valid = 0;
1110         }
1111 }
1112
1113 static void intel_i9xx_setup_flush(void)
1114 {
1115         /* return if already configured */
1116         if (intel_private.ifp_resource.start)
1117                 return;
1118
1119         if (INTEL_GTT_GEN == 6)
1120                 return;
1121
1122         /* setup a resource for this object */
1123         intel_private.ifp_resource.name = "Intel Flush Page";
1124         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1125
1126         /* Setup chipset flush for 915 */
1127         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1128                 intel_i965_g33_setup_chipset_flush();
1129         } else {
1130                 intel_i915_setup_chipset_flush();
1131         }
1132
1133         if (intel_private.ifp_resource.start)
1134                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1135         if (!intel_private.i9xx_flush_page)
1136                 dev_err(&intel_private.pcidev->dev,
1137                         "can't ioremap flush page - no chipset flushing\n");
1138 }
1139
1140 static void i9xx_cleanup(void)
1141 {
1142         if (intel_private.i9xx_flush_page)
1143                 iounmap(intel_private.i9xx_flush_page);
1144         if (intel_private.resource_valid)
1145                 release_resource(&intel_private.ifp_resource);
1146         intel_private.ifp_resource.start = 0;
1147         intel_private.resource_valid = 0;
1148 }
1149
1150 static void i9xx_chipset_flush(void)
1151 {
1152         if (intel_private.i9xx_flush_page)
1153                 writel(1, intel_private.i9xx_flush_page);
1154 }
1155
1156 static void i965_write_entry(dma_addr_t addr,
1157                              unsigned int entry,
1158                              unsigned int flags)
1159 {
1160         u32 pte_flags;
1161
1162         pte_flags = I810_PTE_VALID;
1163         if (flags == AGP_USER_CACHED_MEMORY)
1164                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1165
1166         /* Shift high bits down */
1167         addr |= (addr >> 28) & 0xf0;
1168         writel(addr | pte_flags, intel_private.gtt + entry);
1169 }
1170
1171 static bool gen6_check_flags(unsigned int flags)
1172 {
1173         return true;
1174 }
1175
1176 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1177                              unsigned int flags)
1178 {
1179         unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1180         unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1181         u32 pte_flags;
1182
1183         if (type_mask == AGP_USER_MEMORY)
1184                 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1185         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1186                 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1187                 if (gfdt)
1188                         pte_flags |= GEN6_PTE_GFDT;
1189         } else { /* set 'normal'/'cached' to LLC by default */
1190                 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1191                 if (gfdt)
1192                         pte_flags |= GEN6_PTE_GFDT;
1193         }
1194
1195         /* gen6 has bit11-4 for physical addr bit39-32 */
1196         addr |= (addr >> 28) & 0xff0;
1197         writel(addr | pte_flags, intel_private.gtt + entry);
1198 }
1199
1200 static void gen6_cleanup(void)
1201 {
1202 }
1203
1204 /* Certain Gen5 chipsets require require idling the GPU before
1205  * unmapping anything from the GTT when VT-d is enabled.
1206  */
1207 static inline int needs_idle_maps(void)
1208 {
1209 #ifdef CONFIG_INTEL_IOMMU
1210         const unsigned short gpu_devid = intel_private.pcidev->device;
1211         extern int intel_iommu_gfx_mapped;
1212
1213         /* Query intel_iommu to see if we need the workaround. Presumably that
1214          * was loaded first.
1215          */
1216         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1217              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1218              intel_iommu_gfx_mapped)
1219                 return 1;
1220 #endif
1221         return 0;
1222 }
1223
1224 static int i9xx_setup(void)
1225 {
1226         u32 reg_addr;
1227
1228         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1229
1230         reg_addr &= 0xfff80000;
1231
1232         intel_private.registers = ioremap(reg_addr, 128 * 4096);
1233         if (!intel_private.registers)
1234                 return -ENOMEM;
1235
1236         if (INTEL_GTT_GEN == 3) {
1237                 u32 gtt_addr;
1238
1239                 pci_read_config_dword(intel_private.pcidev,
1240                                       I915_PTEADDR, &gtt_addr);
1241                 intel_private.gtt_bus_addr = gtt_addr;
1242         } else {
1243                 u32 gtt_offset;
1244
1245                 switch (INTEL_GTT_GEN) {
1246                 case 5:
1247                 case 6:
1248                         gtt_offset = MB(2);
1249                         break;
1250                 case 4:
1251                 default:
1252                         gtt_offset =  KB(512);
1253                         break;
1254                 }
1255                 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1256         }
1257
1258         if (needs_idle_maps())
1259                 intel_private.base.do_idle_maps = 1;
1260
1261         intel_i9xx_setup_flush();
1262
1263         return 0;
1264 }
1265
1266 static const struct agp_bridge_driver intel_fake_agp_driver = {
1267         .owner                  = THIS_MODULE,
1268         .size_type              = FIXED_APER_SIZE,
1269         .aperture_sizes         = intel_fake_agp_sizes,
1270         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1271         .configure              = intel_fake_agp_configure,
1272         .fetch_size             = intel_fake_agp_fetch_size,
1273         .cleanup                = intel_gtt_cleanup,
1274         .agp_enable             = intel_fake_agp_enable,
1275         .cache_flush            = global_cache_flush,
1276         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1277         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1278         .insert_memory          = intel_fake_agp_insert_entries,
1279         .remove_memory          = intel_fake_agp_remove_entries,
1280         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1281         .free_by_type           = intel_i810_free_by_type,
1282         .agp_alloc_page         = agp_generic_alloc_page,
1283         .agp_alloc_pages        = agp_generic_alloc_pages,
1284         .agp_destroy_page       = agp_generic_destroy_page,
1285         .agp_destroy_pages      = agp_generic_destroy_pages,
1286 };
1287
1288 static const struct intel_gtt_driver i81x_gtt_driver = {
1289         .gen = 1,
1290         .has_pgtbl_enable = 1,
1291         .dma_mask_size = 32,
1292         .setup = i810_setup,
1293         .cleanup = i810_cleanup,
1294         .check_flags = i830_check_flags,
1295         .write_entry = i810_write_entry,
1296 };
1297 static const struct intel_gtt_driver i8xx_gtt_driver = {
1298         .gen = 2,
1299         .has_pgtbl_enable = 1,
1300         .setup = i830_setup,
1301         .cleanup = i830_cleanup,
1302         .write_entry = i830_write_entry,
1303         .dma_mask_size = 32,
1304         .check_flags = i830_check_flags,
1305         .chipset_flush = i830_chipset_flush,
1306 };
1307 static const struct intel_gtt_driver i915_gtt_driver = {
1308         .gen = 3,
1309         .has_pgtbl_enable = 1,
1310         .setup = i9xx_setup,
1311         .cleanup = i9xx_cleanup,
1312         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1313         .write_entry = i830_write_entry,
1314         .dma_mask_size = 32,
1315         .check_flags = i830_check_flags,
1316         .chipset_flush = i9xx_chipset_flush,
1317 };
1318 static const struct intel_gtt_driver g33_gtt_driver = {
1319         .gen = 3,
1320         .is_g33 = 1,
1321         .setup = i9xx_setup,
1322         .cleanup = i9xx_cleanup,
1323         .write_entry = i965_write_entry,
1324         .dma_mask_size = 36,
1325         .check_flags = i830_check_flags,
1326         .chipset_flush = i9xx_chipset_flush,
1327 };
1328 static const struct intel_gtt_driver pineview_gtt_driver = {
1329         .gen = 3,
1330         .is_pineview = 1, .is_g33 = 1,
1331         .setup = i9xx_setup,
1332         .cleanup = i9xx_cleanup,
1333         .write_entry = i965_write_entry,
1334         .dma_mask_size = 36,
1335         .check_flags = i830_check_flags,
1336         .chipset_flush = i9xx_chipset_flush,
1337 };
1338 static const struct intel_gtt_driver i965_gtt_driver = {
1339         .gen = 4,
1340         .has_pgtbl_enable = 1,
1341         .setup = i9xx_setup,
1342         .cleanup = i9xx_cleanup,
1343         .write_entry = i965_write_entry,
1344         .dma_mask_size = 36,
1345         .check_flags = i830_check_flags,
1346         .chipset_flush = i9xx_chipset_flush,
1347 };
1348 static const struct intel_gtt_driver g4x_gtt_driver = {
1349         .gen = 5,
1350         .setup = i9xx_setup,
1351         .cleanup = i9xx_cleanup,
1352         .write_entry = i965_write_entry,
1353         .dma_mask_size = 36,
1354         .check_flags = i830_check_flags,
1355         .chipset_flush = i9xx_chipset_flush,
1356 };
1357 static const struct intel_gtt_driver ironlake_gtt_driver = {
1358         .gen = 5,
1359         .is_ironlake = 1,
1360         .setup = i9xx_setup,
1361         .cleanup = i9xx_cleanup,
1362         .write_entry = i965_write_entry,
1363         .dma_mask_size = 36,
1364         .check_flags = i830_check_flags,
1365         .chipset_flush = i9xx_chipset_flush,
1366 };
1367 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1368         .gen = 6,
1369         .setup = i9xx_setup,
1370         .cleanup = gen6_cleanup,
1371         .write_entry = gen6_write_entry,
1372         .dma_mask_size = 40,
1373         .check_flags = gen6_check_flags,
1374         .chipset_flush = i9xx_chipset_flush,
1375 };
1376
1377 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1378  * driver and gmch_driver must be non-null, and find_gmch will determine
1379  * which one should be used if a gmch_chip_id is present.
1380  */
1381 static const struct intel_gtt_driver_description {
1382         unsigned int gmch_chip_id;
1383         char *name;
1384         const struct intel_gtt_driver *gtt_driver;
1385 } intel_gtt_chipsets[] = {
1386         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1387                 &i81x_gtt_driver},
1388         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1389                 &i81x_gtt_driver},
1390         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1391                 &i81x_gtt_driver},
1392         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1393                 &i81x_gtt_driver},
1394         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1395                 &i8xx_gtt_driver},
1396         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1397                 &i8xx_gtt_driver},
1398         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1399                 &i8xx_gtt_driver},
1400         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1401                 &i8xx_gtt_driver},
1402         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1403                 &i8xx_gtt_driver},
1404         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1405                 &i915_gtt_driver },
1406         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1407                 &i915_gtt_driver },
1408         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1409                 &i915_gtt_driver },
1410         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1411                 &i915_gtt_driver },
1412         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1413                 &i915_gtt_driver },
1414         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1415                 &i915_gtt_driver },
1416         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1417                 &i965_gtt_driver },
1418         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1419                 &i965_gtt_driver },
1420         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1421                 &i965_gtt_driver },
1422         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1423                 &i965_gtt_driver },
1424         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1425                 &i965_gtt_driver },
1426         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1427                 &i965_gtt_driver },
1428         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1429                 &g33_gtt_driver },
1430         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1431                 &g33_gtt_driver },
1432         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1433                 &g33_gtt_driver },
1434         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1435                 &pineview_gtt_driver },
1436         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1437                 &pineview_gtt_driver },
1438         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1439                 &g4x_gtt_driver },
1440         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1441                 &g4x_gtt_driver },
1442         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1443                 &g4x_gtt_driver },
1444         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1445                 &g4x_gtt_driver },
1446         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1447                 &g4x_gtt_driver },
1448         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1449                 &g4x_gtt_driver },
1450         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1451                 &g4x_gtt_driver },
1452         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1453             "HD Graphics", &ironlake_gtt_driver },
1454         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1455             "HD Graphics", &ironlake_gtt_driver },
1456         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1457             "Sandybridge", &sandybridge_gtt_driver },
1458         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1459             "Sandybridge", &sandybridge_gtt_driver },
1460         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1461             "Sandybridge", &sandybridge_gtt_driver },
1462         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1463             "Sandybridge", &sandybridge_gtt_driver },
1464         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1465             "Sandybridge", &sandybridge_gtt_driver },
1466         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1467             "Sandybridge", &sandybridge_gtt_driver },
1468         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1469             "Sandybridge", &sandybridge_gtt_driver },
1470         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
1471             "Ivybridge", &sandybridge_gtt_driver },
1472         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
1473             "Ivybridge", &sandybridge_gtt_driver },
1474         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
1475             "Ivybridge", &sandybridge_gtt_driver },
1476         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
1477             "Ivybridge", &sandybridge_gtt_driver },
1478         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
1479             "Ivybridge", &sandybridge_gtt_driver },
1480         { 0, NULL, NULL }
1481 };
1482
1483 static int find_gmch(u16 device)
1484 {
1485         struct pci_dev *gmch_device;
1486
1487         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1488         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1489                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1490                                              device, gmch_device);
1491         }
1492
1493         if (!gmch_device)
1494                 return 0;
1495
1496         intel_private.pcidev = gmch_device;
1497         return 1;
1498 }
1499
1500 int intel_gmch_probe(struct pci_dev *pdev,
1501                                       struct agp_bridge_data *bridge)
1502 {
1503         int i, mask;
1504         intel_private.driver = NULL;
1505
1506         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1507                 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1508                         intel_private.driver =
1509                                 intel_gtt_chipsets[i].gtt_driver;
1510                         break;
1511                 }
1512         }
1513
1514         if (!intel_private.driver)
1515                 return 0;
1516
1517         bridge->driver = &intel_fake_agp_driver;
1518         bridge->dev_private_data = &intel_private;
1519         bridge->dev = pdev;
1520
1521         intel_private.bridge_dev = pci_dev_get(pdev);
1522
1523         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1524
1525         mask = intel_private.driver->dma_mask_size;
1526         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1527                 dev_err(&intel_private.pcidev->dev,
1528                         "set gfx device dma mask %d-bit failed!\n", mask);
1529         else
1530                 pci_set_consistent_dma_mask(intel_private.pcidev,
1531                                             DMA_BIT_MASK(mask));
1532
1533         /*if (bridge->driver == &intel_810_driver)
1534                 return 1;*/
1535
1536         if (intel_gtt_init() != 0)
1537                 return 0;
1538
1539         return 1;
1540 }
1541 EXPORT_SYMBOL(intel_gmch_probe);
1542
1543 const struct intel_gtt *intel_gtt_get(void)
1544 {
1545         return &intel_private.base;
1546 }
1547 EXPORT_SYMBOL(intel_gtt_get);
1548
1549 void intel_gtt_chipset_flush(void)
1550 {
1551         if (intel_private.driver->chipset_flush)
1552                 intel_private.driver->chipset_flush();
1553 }
1554 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1555
1556 void intel_gmch_remove(struct pci_dev *pdev)
1557 {
1558         if (intel_private.pcidev)
1559                 pci_dev_put(intel_private.pcidev);
1560         if (intel_private.bridge_dev)
1561                 pci_dev_put(intel_private.bridge_dev);
1562 }
1563 EXPORT_SYMBOL(intel_gmch_remove);
1564
1565 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1566 MODULE_LICENSE("GPL and additional rights");