drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <linux/delay.h>
  25 #include <asm/smp.h>
  26 #include "agp.h"
  27 #include "intel-agp.h"
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_INTEL_IOMMU
  37 #define USE_PCI_DMA_API 1
  38 #else
  39 #define USE_PCI_DMA_API 0
  40 #endif
  41
  42 struct intel_gtt_driver {
  43         unsigned int gen : 8;
  44         unsigned int is_g33 : 1;
  45         unsigned int is_pineview : 1;
  46         unsigned int is_ironlake : 1;
  47         unsigned int has_pgtbl_enable : 1;
  48         unsigned int dma_mask_size : 8;
  49         /* Chipset specific GTT setup */
  50         int (*setup)(void);
  51         /* This should undo anything done in ->setup() save the unmapping
  52          * of the mmio register file, that's done in the generic code. */
  53         void (*cleanup)(void);
  54         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  55         /* Flags is a more or less chipset specific opaque value.
  56          * For chipsets that need to support old ums (non-gem) code, this
  57          * needs to be identical to the various supported agp memory types! */
  58         bool (*check_flags)(unsigned int flags);
  59         void (*chipset_flush)(void);
  60 };
  61
  62 static struct _intel_private {
  63         struct intel_gtt base;
  64         const struct intel_gtt_driver *driver;
  65         struct pci_dev *pcidev; /* device one */
  66         struct pci_dev *bridge_dev;
  67         u8 __iomem *registers;
  68         phys_addr_t gtt_bus_addr;
  69         phys_addr_t gma_bus_addr;
  70         u32 PGETBL_save;
  71         u32 __iomem *gtt;               /* I915G */
  72         bool clear_fake_agp; /* on first access via agp, fill with scratch */
  73         int num_dcache_entries;
  74         void __iomem *i9xx_flush_page;
  75         char *i81x_gtt_table;
  76         struct resource ifp_resource;
  77         int resource_valid;
  78         struct page *scratch_page;
  79 } intel_private;
  80
  81 #define INTEL_GTT_GEN   intel_private.driver->gen
  82 #define IS_G33          intel_private.driver->is_g33
  83 #define IS_PINEVIEW     intel_private.driver->is_pineview
  84 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  85 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  86
  87 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
  88                          struct scatterlist **sg_list, int *num_sg)
  89 {
  90         struct sg_table st;
  91         struct scatterlist *sg;
  92         int i;
  93
  94         if (*sg_list)
  95                 return 0; /* already mapped (for e.g. resume */
  96
  97         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
  98
  99         if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
 100                 goto err;
 101
 102         *sg_list = sg = st.sgl;
 103
 104         for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
 105                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
 106
 107         *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
 108                                  num_entries, PCI_DMA_BIDIRECTIONAL);
 109         if (unlikely(!*num_sg))
 110                 goto err;
 111
 112         return 0;
 113
 114 err:
 115         sg_free_table(&st);
 116         return -ENOMEM;
 117 }
 118 EXPORT_SYMBOL(intel_gtt_map_memory);
 119
 120 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
 121 {
 122         struct sg_table st;
 123         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 124
 125         pci_unmap_sg(intel_private.pcidev, sg_list,
 126                      num_sg, PCI_DMA_BIDIRECTIONAL);
 127
 128         st.sgl = sg_list;
 129         st.orig_nents = st.nents = num_sg;
 130
 131         sg_free_table(&st);
 132 }
 133 EXPORT_SYMBOL(intel_gtt_unmap_memory);
 134
 135 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 136 {
 137         return;
 138 }
 139
 140 /* Exists to support ARGB cursors */
 141 static struct page *i8xx_alloc_pages(void)
 142 {
 143         struct page *page;
 144
 145         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 146         if (page == NULL)
 147                 return NULL;
 148
 149 #ifdef CONFIG_XEN
 150         if (xen_create_contiguous_region((unsigned long)page_address(page), 2, 32)) {
 151                 __free_pages(page, 2);
 152                 return NULL;
 153         }
 154 #endif
 155
 156         if (set_pages_uc(page, 4) < 0) {
 157                 set_pages_wb(page, 4);
 158 #ifdef CONFIG_XEN
 159                 xen_destroy_contiguous_region((unsigned long)page_address(page),
 160                                               2);
 161 #endif
 162                 __free_pages(page, 2);
 163                 return NULL;
 164         }
 165         get_page(page);
 166         atomic_inc(&agp_bridge->current_memory_agp);
 167         return page;
 168 }
 169
 170 static void i8xx_destroy_pages(struct page *page)
 171 {
 172         if (page == NULL)
 173                 return;
 174
 175         set_pages_wb(page, 4);
 176 #ifdef CONFIG_XEN
 177         xen_destroy_contiguous_region((unsigned long)page_address(page), 2);
 178 #endif
 179         put_page(page);
 180         __free_pages(page, 2);
 181         atomic_dec(&agp_bridge->current_memory_agp);
 182 }
 183
 184 #define I810_GTT_ORDER 4
 185 static int i810_setup(void)
 186 {
 187         u32 reg_addr;
 188         char *gtt_table;
 189
 190         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 191         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 192         if (gtt_table == NULL)
 193                 return -ENOMEM;
 194         intel_private.i81x_gtt_table = gtt_table;
 195
 196         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 197         reg_addr &= 0xfff80000;
 198
 199         intel_private.registers = ioremap(reg_addr, KB(64));
 200         if (!intel_private.registers)
 201                 return -ENOMEM;
 202
 203         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 204                intel_private.registers+I810_PGETBL_CTL);
 205
 206         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 207
 208         if ((readl(intel_private.registers+I810_DRAM_CTL)
 209                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 210                 dev_info(&intel_private.pcidev->dev,
 211                          "detected 4MB dedicated video ram\n");
 212                 intel_private.num_dcache_entries = 1024;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static void i810_cleanup(void)
 219 {
 220         writel(0, intel_private.registers+I810_PGETBL_CTL);
 221         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 222 }
 223
 224 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 225                                       int type)
 226 {
 227         int i;
 228
 229         if ((pg_start + mem->page_count)
 230                         > intel_private.num_dcache_entries)
 231                 return -EINVAL;
 232
 233         if (!mem->is_flushed)
 234                 global_cache_flush();
 235
 236         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 237                 dma_addr_t addr = i << PAGE_SHIFT;
 238                 intel_private.driver->write_entry(addr,
 239                                                   i, type);
 240         }
 241         readl(intel_private.gtt+i-1);
 242
 243         return 0;
 244 }
 245
 246 /*
 247  * The i810/i830 requires a physical address to program its mouse
 248  * pointer into hardware.
 249  * However the Xserver still writes to it through the agp aperture.
 250  */
 251 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 252 {
 253         struct agp_memory *new;
 254         struct page *page;
 255
 256         switch (pg_count) {
 257         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 258                 break;
 259         case 4:
 260                 /* kludge to get 4 physical pages for ARGB cursor */
 261                 page = i8xx_alloc_pages();
 262                 break;
 263         default:
 264                 return NULL;
 265         }
 266
 267         if (page == NULL)
 268                 return NULL;
 269
 270         new = agp_create_memory(pg_count);
 271         if (new == NULL)
 272                 return NULL;
 273
 274         new->pages[0] = page;
 275         if (pg_count == 4) {
 276                 /* kludge to get 4 physical pages for ARGB cursor */
 277                 new->pages[1] = new->pages[0] + 1;
 278                 new->pages[2] = new->pages[1] + 1;
 279                 new->pages[3] = new->pages[2] + 1;
 280         }
 281         new->page_count = pg_count;
 282         new->num_scratch_pages = pg_count;
 283         new->type = AGP_PHYS_MEMORY;
 284 #ifndef CONFIG_XEN
 285         new->physical = page_to_phys(new->pages[0]);
 286 #else
 287         new->physical = page_to_pseudophys(new->pages[0]);
 288 #endif
 289         return new;
 290 }
 291
 292 static void intel_i810_free_by_type(struct agp_memory *curr)
 293 {
 294         agp_free_key(curr->key);
 295         if (curr->type == AGP_PHYS_MEMORY) {
 296                 if (curr->page_count == 4)
 297                         i8xx_destroy_pages(curr->pages[0]);
 298                 else {
 299                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 300                                                              AGP_PAGE_DESTROY_UNMAP);
 301                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 302                                                              AGP_PAGE_DESTROY_FREE);
 303                 }
 304                 agp_free_page_array(curr);
 305         }
 306         kfree(curr);
 307 }
 308
 309 static int intel_gtt_setup_scratch_page(void)
 310 {
 311         struct page *page;
 312         dma_addr_t dma_addr;
 313
 314         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 315         if (page == NULL)
 316                 return -ENOMEM;
 317         get_page(page);
 318         set_pages_uc(page, 1);
 319
 320         if (intel_private.base.needs_dmar) {
 321                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 322                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 323                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 324                         return -EINVAL;
 325
 326                 intel_private.base.scratch_page_dma = dma_addr;
 327         } else
 328                 intel_private.base.scratch_page_dma = page_to_phys(page);
 329
 330         intel_private.scratch_page = page;
 331
 332         return 0;
 333 }
 334
 335 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 336                              unsigned int flags)
 337 {
 338         u32 pte_flags = I810_PTE_VALID;
 339
 340         switch (flags) {
 341         case AGP_DCACHE_MEMORY:
 342                 pte_flags |= I810_PTE_LOCAL;
 343                 break;
 344         case AGP_USER_CACHED_MEMORY:
 345                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 346                 break;
 347         }
 348
 349         writel(addr | pte_flags, intel_private.gtt + entry);
 350 }
 351
 352 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
 353         {32, 8192, 3},
 354         {64, 16384, 4},
 355         {128, 32768, 5},
 356         {256, 65536, 6},
 357         {512, 131072, 7},
 358 };
 359
 360 static unsigned int intel_gtt_stolen_size(void)
 361 {
 362         u16 gmch_ctrl;
 363         u8 rdct;
 364         int local = 0;
 365         static const int ddt[4] = { 0, 16, 32, 64 };
 366         unsigned int stolen_size = 0;
 367
 368         if (INTEL_GTT_GEN == 1)
 369                 return 0; /* no stolen mem on i81x */
 370
 371         pci_read_config_word(intel_private.bridge_dev,
 372                              I830_GMCH_CTRL, &gmch_ctrl);
 373
 374         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 375             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 376                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 377                 case I830_GMCH_GMS_STOLEN_512:
 378                         stolen_size = KB(512);
 379                         break;
 380                 case I830_GMCH_GMS_STOLEN_1024:
 381                         stolen_size = MB(1);
 382                         break;
 383                 case I830_GMCH_GMS_STOLEN_8192:
 384                         stolen_size = MB(8);
 385                         break;
 386                 case I830_GMCH_GMS_LOCAL:
 387                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 388                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 389                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 390                         local = 1;
 391                         break;
 392                 default:
 393                         stolen_size = 0;
 394                         break;
 395                 }
 396         } else if (INTEL_GTT_GEN == 6) {
 397                 /*
 398                  * SandyBridge has new memory control reg at 0x50.w
 399                  */
 400                 u16 snb_gmch_ctl;
 401                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 402                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 403                 case SNB_GMCH_GMS_STOLEN_32M:
 404                         stolen_size = MB(32);
 405                         break;
 406                 case SNB_GMCH_GMS_STOLEN_64M:
 407                         stolen_size = MB(64);
 408                         break;
 409                 case SNB_GMCH_GMS_STOLEN_96M:
 410                         stolen_size = MB(96);
 411                         break;
 412                 case SNB_GMCH_GMS_STOLEN_128M:
 413                         stolen_size = MB(128);
 414                         break;
 415                 case SNB_GMCH_GMS_STOLEN_160M:
 416                         stolen_size = MB(160);
 417                         break;
 418                 case SNB_GMCH_GMS_STOLEN_192M:
 419                         stolen_size = MB(192);
 420                         break;
 421                 case SNB_GMCH_GMS_STOLEN_224M:
 422                         stolen_size = MB(224);
 423                         break;
 424                 case SNB_GMCH_GMS_STOLEN_256M:
 425                         stolen_size = MB(256);
 426                         break;
 427                 case SNB_GMCH_GMS_STOLEN_288M:
 428                         stolen_size = MB(288);
 429                         break;
 430                 case SNB_GMCH_GMS_STOLEN_320M:
 431                         stolen_size = MB(320);
 432                         break;
 433                 case SNB_GMCH_GMS_STOLEN_352M:
 434                         stolen_size = MB(352);
 435                         break;
 436                 case SNB_GMCH_GMS_STOLEN_384M:
 437                         stolen_size = MB(384);
 438                         break;
 439                 case SNB_GMCH_GMS_STOLEN_416M:
 440                         stolen_size = MB(416);
 441                         break;
 442                 case SNB_GMCH_GMS_STOLEN_448M:
 443                         stolen_size = MB(448);
 444                         break;
 445                 case SNB_GMCH_GMS_STOLEN_480M:
 446                         stolen_size = MB(480);
 447                         break;
 448                 case SNB_GMCH_GMS_STOLEN_512M:
 449                         stolen_size = MB(512);
 450                         break;
 451                 }
 452         } else {
 453                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 454                 case I855_GMCH_GMS_STOLEN_1M:
 455                         stolen_size = MB(1);
 456                         break;
 457                 case I855_GMCH_GMS_STOLEN_4M:
 458                         stolen_size = MB(4);
 459                         break;
 460                 case I855_GMCH_GMS_STOLEN_8M:
 461                         stolen_size = MB(8);
 462                         break;
 463                 case I855_GMCH_GMS_STOLEN_16M:
 464                         stolen_size = MB(16);
 465                         break;
 466                 case I855_GMCH_GMS_STOLEN_32M:
 467                         stolen_size = MB(32);
 468                         break;
 469                 case I915_GMCH_GMS_STOLEN_48M:
 470                         stolen_size = MB(48);
 471                         break;
 472                 case I915_GMCH_GMS_STOLEN_64M:
 473                         stolen_size = MB(64);
 474                         break;
 475                 case G33_GMCH_GMS_STOLEN_128M:
 476                         stolen_size = MB(128);
 477                         break;
 478                 case G33_GMCH_GMS_STOLEN_256M:
 479                         stolen_size = MB(256);
 480                         break;
 481                 case INTEL_GMCH_GMS_STOLEN_96M:
 482                         stolen_size = MB(96);
 483                         break;
 484                 case INTEL_GMCH_GMS_STOLEN_160M:
 485                         stolen_size = MB(160);
 486                         break;
 487                 case INTEL_GMCH_GMS_STOLEN_224M:
 488                         stolen_size = MB(224);
 489                         break;
 490                 case INTEL_GMCH_GMS_STOLEN_352M:
 491                         stolen_size = MB(352);
 492                         break;
 493                 default:
 494                         stolen_size = 0;
 495                         break;
 496                 }
 497         }
 498
 499         if (stolen_size > 0) {
 500                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 501                        stolen_size / KB(1), local ? "local" : "stolen");
 502         } else {
 503                 dev_info(&intel_private.bridge_dev->dev,
 504                        "no pre-allocated video memory detected\n");
 505                 stolen_size = 0;
 506         }
 507
 508         return stolen_size;
 509 }
 510
 511 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 512 {
 513         u32 pgetbl_ctl, pgetbl_ctl2;
 514
 515         /* ensure that ppgtt is disabled */
 516         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 517         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 518         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 519
 520         /* write the new ggtt size */
 521         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 522         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 523         pgetbl_ctl |= size_flag;
 524         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 525 }
 526
 527 static unsigned int i965_gtt_total_entries(void)
 528 {
 529         int size;
 530         u32 pgetbl_ctl;
 531         u16 gmch_ctl;
 532
 533         pci_read_config_word(intel_private.bridge_dev,
 534                              I830_GMCH_CTRL, &gmch_ctl);
 535
 536         if (INTEL_GTT_GEN == 5) {
 537                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 538                 case G4x_GMCH_SIZE_1M:
 539                 case G4x_GMCH_SIZE_VT_1M:
 540                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 541                         break;
 542                 case G4x_GMCH_SIZE_VT_1_5M:
 543                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 544                         break;
 545                 case G4x_GMCH_SIZE_2M:
 546                 case G4x_GMCH_SIZE_VT_2M:
 547                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 548                         break;
 549                 }
 550         }
 551
 552         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 553
 554         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 555         case I965_PGETBL_SIZE_128KB:
 556                 size = KB(128);
 557                 break;
 558         case I965_PGETBL_SIZE_256KB:
 559                 size = KB(256);
 560                 break;
 561         case I965_PGETBL_SIZE_512KB:
 562                 size = KB(512);
 563                 break;
 564         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 565         case I965_PGETBL_SIZE_1MB:
 566                 size = KB(1024);
 567                 break;
 568         case I965_PGETBL_SIZE_2MB:
 569                 size = KB(2048);
 570                 break;
 571         case I965_PGETBL_SIZE_1_5MB:
 572                 size = KB(1024 + 512);
 573                 break;
 574         default:
 575                 dev_info(&intel_private.pcidev->dev,
 576                          "unknown page table size, assuming 512KB\n");
 577                 size = KB(512);
 578         }
 579
 580         return size/4;
 581 }
 582
 583 static unsigned int intel_gtt_total_entries(void)
 584 {
 585         int size;
 586
 587         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 588                 return i965_gtt_total_entries();
 589         else if (INTEL_GTT_GEN == 6) {
 590                 u16 snb_gmch_ctl;
 591
 592                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 593                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
 594                 default:
 595                 case SNB_GTT_SIZE_0M:
 596                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
 597                         size = MB(0);
 598                         break;
 599                 case SNB_GTT_SIZE_1M:
 600                         size = MB(1);
 601                         break;
 602                 case SNB_GTT_SIZE_2M:
 603                         size = MB(2);
 604                         break;
 605                 }
 606                 return size/4;
 607         } else {
 608                 /* On previous hardware, the GTT size was just what was
 609                  * required to map the aperture.
 610                  */
 611                 return intel_private.base.gtt_mappable_entries;
 612         }
 613 }
 614
 615 static unsigned int intel_gtt_mappable_entries(void)
 616 {
 617         unsigned int aperture_size;
 618
 619         if (INTEL_GTT_GEN == 1) {
 620                 u32 smram_miscc;
 621
 622                 pci_read_config_dword(intel_private.bridge_dev,
 623                                       I810_SMRAM_MISCC, &smram_miscc);
 624
 625                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 626                                 == I810_GFX_MEM_WIN_32M)
 627                         aperture_size = MB(32);
 628                 else
 629                         aperture_size = MB(64);
 630         } else if (INTEL_GTT_GEN == 2) {
 631                 u16 gmch_ctrl;
 632
 633                 pci_read_config_word(intel_private.bridge_dev,
 634                                      I830_GMCH_CTRL, &gmch_ctrl);
 635
 636                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 637                         aperture_size = MB(64);
 638                 else
 639                         aperture_size = MB(128);
 640         } else {
 641                 /* 9xx supports large sizes, just look at the length */
 642                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 643         }
 644
 645         return aperture_size >> PAGE_SHIFT;
 646 }
 647
 648 static void intel_gtt_teardown_scratch_page(void)
 649 {
 650         set_pages_wb(intel_private.scratch_page, 1);
 651         pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
 652                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 653         put_page(intel_private.scratch_page);
 654         __free_page(intel_private.scratch_page);
 655 }
 656
 657 static void intel_gtt_cleanup(void)
 658 {
 659         intel_private.driver->cleanup();
 660
 661         iounmap(intel_private.gtt);
 662         iounmap(intel_private.registers);
 663
 664         intel_gtt_teardown_scratch_page();
 665 }
 666
 667 static int intel_gtt_init(void)
 668 {
 669         u32 gtt_map_size;
 670         int ret;
 671
 672         ret = intel_private.driver->setup();
 673         if (ret != 0)
 674                 return ret;
 675
 676         intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
 677         intel_private.base.gtt_total_entries = intel_gtt_total_entries();
 678
 679         /* save the PGETBL reg for resume */
 680         intel_private.PGETBL_save =
 681                 readl(intel_private.registers+I810_PGETBL_CTL)
 682                         & ~I810_PGETBL_ENABLED;
 683         /* we only ever restore the register when enabling the PGTBL... */
 684         if (HAS_PGTBL_EN)
 685                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 686
 687         dev_info(&intel_private.bridge_dev->dev,
 688                         "detected gtt size: %dK total, %dK mappable\n",
 689                         intel_private.base.gtt_total_entries * 4,
 690                         intel_private.base.gtt_mappable_entries * 4);
 691
 692         gtt_map_size = intel_private.base.gtt_total_entries * 4;
 693
 694         intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
 695                                     gtt_map_size);
 696         if (!intel_private.gtt) {
 697                 intel_private.driver->cleanup();
 698                 iounmap(intel_private.registers);
 699                 return -ENOMEM;
 700         }
 701         intel_private.base.gtt = intel_private.gtt;
 702
 703         global_cache_flush();   /* FIXME: ? */
 704
 705         intel_private.base.stolen_size = intel_gtt_stolen_size();
 706
 707         intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
 708
 709         ret = intel_gtt_setup_scratch_page();
 710         if (ret != 0) {
 711                 intel_gtt_cleanup();
 712                 return ret;
 713         }
 714
 715         return 0;
 716 }
 717
 718 static int intel_fake_agp_fetch_size(void)
 719 {
 720         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 721         unsigned int aper_size;
 722         int i;
 723
 724         aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
 725                     / MB(1);
 726
 727         for (i = 0; i < num_sizes; i++) {
 728                 if (aper_size == intel_fake_agp_sizes[i].size) {
 729                         agp_bridge->current_size =
 730                                 (void *) (intel_fake_agp_sizes + i);
 731                         return aper_size;
 732                 }
 733         }
 734
 735         return 0;
 736 }
 737
 738 static void i830_cleanup(void)
 739 {
 740 }
 741
 742 /* The chipset_flush interface needs to get data that has already been
 743  * flushed out of the CPU all the way out to main memory, because the GPU
 744  * doesn't snoop those buffers.
 745  *
 746  * The 8xx series doesn't have the same lovely interface for flushing the
 747  * chipset write buffers that the later chips do. According to the 865
 748  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 749  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 750  * that it'll push whatever was in there out.  It appears to work.
 751  */
 752 static void i830_chipset_flush(void)
 753 {
 754         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 755
 756         /* Forcibly evict everything from the CPU write buffers.
 757          * clflush appears to be insufficient.
 758          */
 759         wbinvd_on_all_cpus();
 760
 761         /* Now we've only seen documents for this magic bit on 855GM,
 762          * we hope it exists for the other gen2 chipsets...
 763          *
 764          * Also works as advertised on my 845G.
 765          */
 766         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
 767                intel_private.registers+I830_HIC);
 768
 769         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
 770                 if (time_after(jiffies, timeout))
 771                         break;
 772
 773                 udelay(50);
 774         }
 775 }
 776
 777 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 778                              unsigned int flags)
 779 {
 780         u32 pte_flags = I810_PTE_VALID;
 781
 782         if (flags ==  AGP_USER_CACHED_MEMORY)
 783                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 784
 785         writel(addr | pte_flags, intel_private.gtt + entry);
 786 }
 787
 788 static bool intel_enable_gtt(void)
 789 {
 790         u32 gma_addr;
 791         u8 __iomem *reg;
 792
 793         if (INTEL_GTT_GEN <= 2)
 794                 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
 795                                       &gma_addr);
 796         else
 797                 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
 798                                       &gma_addr);
 799
 800         intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 801
 802         if (INTEL_GTT_GEN >= 6)
 803             return true;
 804
 805         if (INTEL_GTT_GEN == 2) {
 806                 u16 gmch_ctrl;
 807
 808                 pci_read_config_word(intel_private.bridge_dev,
 809                                      I830_GMCH_CTRL, &gmch_ctrl);
 810                 gmch_ctrl |= I830_GMCH_ENABLED;
 811                 pci_write_config_word(intel_private.bridge_dev,
 812                                       I830_GMCH_CTRL, gmch_ctrl);
 813
 814                 pci_read_config_word(intel_private.bridge_dev,
 815                                      I830_GMCH_CTRL, &gmch_ctrl);
 816                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 817                         dev_err(&intel_private.pcidev->dev,
 818                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 819                                 gmch_ctrl);
 820                         return false;
 821                 }
 822         }
 823
 824         /* On the resume path we may be adjusting the PGTBL value, so
 825          * be paranoid and flush all chipset write buffers...
 826          */
 827         if (INTEL_GTT_GEN >= 3)
 828                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 829
 830         reg = intel_private.registers+I810_PGETBL_CTL;
 831         writel(intel_private.PGETBL_save, reg);
 832         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 833                 dev_err(&intel_private.pcidev->dev,
 834                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 835                         readl(reg), intel_private.PGETBL_save);
 836                 return false;
 837         }
 838
 839         if (INTEL_GTT_GEN >= 3)
 840                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 841
 842         return true;
 843 }
 844
 845 static int i830_setup(void)
 846 {
 847         u32 reg_addr;
 848
 849         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 850         reg_addr &= 0xfff80000;
 851
 852         intel_private.registers = ioremap(reg_addr, KB(64));
 853         if (!intel_private.registers)
 854                 return -ENOMEM;
 855
 856         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 857
 858         return 0;
 859 }
 860
 861 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 862 {
 863         agp_bridge->gatt_table_real = NULL;
 864         agp_bridge->gatt_table = NULL;
 865         agp_bridge->gatt_bus_addr = 0;
 866
 867         return 0;
 868 }
 869
 870 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 871 {
 872         return 0;
 873 }
 874
 875 static int intel_fake_agp_configure(void)
 876 {
 877         if (!intel_enable_gtt())
 878             return -EIO;
 879
 880         intel_private.clear_fake_agp = true;
 881         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
 882
 883         return 0;
 884 }
 885
 886 static bool i830_check_flags(unsigned int flags)
 887 {
 888         switch (flags) {
 889         case 0:
 890         case AGP_PHYS_MEMORY:
 891         case AGP_USER_CACHED_MEMORY:
 892         case AGP_USER_MEMORY:
 893                 return true;
 894         }
 895
 896         return false;
 897 }
 898
 899 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
 900                                  unsigned int sg_len,
 901                                  unsigned int pg_start,
 902                                  unsigned int flags)
 903 {
 904         struct scatterlist *sg;
 905         unsigned int len, m;
 906         int i, j;
 907
 908         j = pg_start;
 909
 910         /* sg may merge pages, but we have to separate
 911          * per-page addr for GTT */
 912         for_each_sg(sg_list, sg, sg_len, i) {
 913                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 914                 for (m = 0; m < len; m++) {
 915                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 916                         intel_private.driver->write_entry(addr,
 917                                                           j, flags);
 918                         j++;
 919                 }
 920         }
 921         readl(intel_private.gtt+j-1);
 922 }
 923 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 924
 925 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
 926                             struct page **pages, unsigned int flags)
 927 {
 928         int i, j;
 929
 930         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
 931                 dma_addr_t addr = page_to_phys(pages[i]);
 932                 intel_private.driver->write_entry(addr,
 933                                                   j, flags);
 934         }
 935         readl(intel_private.gtt+j-1);
 936 }
 937 EXPORT_SYMBOL(intel_gtt_insert_pages);
 938
 939 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 940                                          off_t pg_start, int type)
 941 {
 942         int ret = -EINVAL;
 943
 944         if (intel_private.base.do_idle_maps)
 945                 return -ENODEV;
 946
 947         if (intel_private.clear_fake_agp) {
 948                 int start = intel_private.base.stolen_size / PAGE_SIZE;
 949                 int end = intel_private.base.gtt_mappable_entries;
 950                 intel_gtt_clear_range(start, end - start);
 951                 intel_private.clear_fake_agp = false;
 952         }
 953
 954         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 955                 return i810_insert_dcache_entries(mem, pg_start, type);
 956
 957         if (mem->page_count == 0)
 958                 goto out;
 959
 960         if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
 961                 goto out_err;
 962
 963         if (type != mem->type)
 964                 goto out_err;
 965
 966         if (!intel_private.driver->check_flags(type))
 967                 goto out_err;
 968
 969         if (!mem->is_flushed)
 970                 global_cache_flush();
 971
 972         if (intel_private.base.needs_dmar) {
 973                 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
 974                                            &mem->sg_list, &mem->num_sg);
 975                 if (ret != 0)
 976                         return ret;
 977
 978                 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
 979                                             pg_start, type);
 980         } else
 981                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
 982                                        type);
 983
 984 out:
 985         ret = 0;
 986 out_err:
 987         mem->is_flushed = true;
 988         return ret;
 989 }
 990
 991 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 992 {
 993         unsigned int i;
 994
 995         for (i = first_entry; i < (first_entry + num_entries); i++) {
 996                 intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
 997                                                   i, 0);
 998         }
 999         readl(intel_private.gtt+i-1);
1000 }
1001 EXPORT_SYMBOL(intel_gtt_clear_range);
1002
1003 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
1004                                          off_t pg_start, int type)
1005 {
1006         if (mem->page_count == 0)
1007                 return 0;
1008
1009         if (intel_private.base.do_idle_maps)
1010                 return -ENODEV;
1011
1012         intel_gtt_clear_range(pg_start, mem->page_count);
1013
1014         if (intel_private.base.needs_dmar) {
1015                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
1016                 mem->sg_list = NULL;
1017                 mem->num_sg = 0;
1018         }
1019
1020         return 0;
1021 }
1022
1023 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1024                                                        int type)
1025 {
1026         struct agp_memory *new;
1027
1028         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1029                 if (pg_count != intel_private.num_dcache_entries)
1030                         return NULL;
1031
1032                 new = agp_create_memory(1);
1033                 if (new == NULL)
1034                         return NULL;
1035
1036                 new->type = AGP_DCACHE_MEMORY;
1037                 new->page_count = pg_count;
1038                 new->num_scratch_pages = 0;
1039                 agp_free_page_array(new);
1040                 return new;
1041         }
1042         if (type == AGP_PHYS_MEMORY)
1043                 return alloc_agpphysmem_i8xx(pg_count, type);
1044         /* always return NULL for other allocation types for now */
1045         return NULL;
1046 }
1047
1048 static int intel_alloc_chipset_flush_resource(void)
1049 {
1050         int ret;
1051         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1052                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1053                                      pcibios_align_resource, intel_private.bridge_dev);
1054
1055         return ret;
1056 }
1057
1058 static void intel_i915_setup_chipset_flush(void)
1059 {
1060         int ret;
1061         u32 temp;
1062
1063         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1064         if (!(temp & 0x1)) {
1065                 intel_alloc_chipset_flush_resource();
1066                 intel_private.resource_valid = 1;
1067                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1068         } else {
1069                 temp &= ~1;
1070
1071                 intel_private.resource_valid = 1;
1072                 intel_private.ifp_resource.start = temp;
1073                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1074                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1075                 /* some BIOSes reserve this area in a pnp some don't */
1076                 if (ret)
1077                         intel_private.resource_valid = 0;
1078         }
1079 }
1080
1081 static void intel_i965_g33_setup_chipset_flush(void)
1082 {
1083         u32 temp_hi, temp_lo;
1084         int ret;
1085
1086         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1087         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1088
1089         if (!(temp_lo & 0x1)) {
1090
1091                 intel_alloc_chipset_flush_resource();
1092
1093                 intel_private.resource_valid = 1;
1094                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1095                         upper_32_bits(intel_private.ifp_resource.start));
1096                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1097         } else {
1098                 u64 l64;
1099
1100                 temp_lo &= ~0x1;
1101                 l64 = ((u64)temp_hi << 32) | temp_lo;
1102
1103                 intel_private.resource_valid = 1;
1104                 intel_private.ifp_resource.start = l64;
1105                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1106                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1107                 /* some BIOSes reserve this area in a pnp some don't */
1108                 if (ret)
1109                         intel_private.resource_valid = 0;
1110         }
1111 }
1112
1113 static void intel_i9xx_setup_flush(void)
1114 {
1115         /* return if already configured */
1116         if (intel_private.ifp_resource.start)
1117                 return;
1118
1119         if (INTEL_GTT_GEN == 6)
1120                 return;
1121
1122         /* setup a resource for this object */
1123         intel_private.ifp_resource.name = "Intel Flush Page";
1124         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1125
1126         /* Setup chipset flush for 915 */
1127         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1128                 intel_i965_g33_setup_chipset_flush();
1129         } else {
1130                 intel_i915_setup_chipset_flush();
1131         }
1132
1133         if (intel_private.ifp_resource.start)
1134                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1135         if (!intel_private.i9xx_flush_page)
1136                 dev_err(&intel_private.pcidev->dev,
1137                         "can't ioremap flush page - no chipset flushing\n");
1138 }
1139
1140 static void i9xx_cleanup(void)
1141 {
1142         if (intel_private.i9xx_flush_page)
1143                 iounmap(intel_private.i9xx_flush_page);
1144         if (intel_private.resource_valid)
1145                 release_resource(&intel_private.ifp_resource);
1146         intel_private.ifp_resource.start = 0;
1147         intel_private.resource_valid = 0;
1148 }
1149
1150 static void i9xx_chipset_flush(void)
1151 {
1152         if (intel_private.i9xx_flush_page)
1153                 writel(1, intel_private.i9xx_flush_page);
1154 }
1155
1156 static void i965_write_entry(dma_addr_t addr,
1157                              unsigned int entry,
1158                              unsigned int flags)
1159 {
1160         u32 pte_flags;
1161
1162         pte_flags = I810_PTE_VALID;
1163         if (flags == AGP_USER_CACHED_MEMORY)
1164                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1165
1166         /* Shift high bits down */
1167         addr |= (addr >> 28) & 0xf0;
1168         writel(addr | pte_flags, intel_private.gtt + entry);
1169 }
1170
1171 static bool gen6_check_flags(unsigned int flags)
1172 {
1173         return true;
1174 }
1175
1176 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1177                              unsigned int flags)
1178 {
1179         unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1180         unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1181         u32 pte_flags;
1182
1183         if (type_mask == AGP_USER_MEMORY)
1184                 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1185         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1186                 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1187                 if (gfdt)
1188                         pte_flags |= GEN6_PTE_GFDT;
1189         } else { /* set 'normal'/'cached' to LLC by default */
1190                 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1191                 if (gfdt)
1192                         pte_flags |= GEN6_PTE_GFDT;
1193         }
1194
1195         /* gen6 has bit11-4 for physical addr bit39-32 */
1196         addr |= (addr >> 28) & 0xff0;
1197         writel(addr | pte_flags, intel_private.gtt + entry);
1198 }
1199
1200 static void gen6_cleanup(void)
1201 {
1202 }
1203
1204 /* Certain Gen5 chipsets require require idling the GPU before
1205  * unmapping anything from the GTT when VT-d is enabled.
1206  */
1207 static inline int needs_idle_maps(void)
1208 {
1209 #ifdef CONFIG_INTEL_IOMMU
1210         const unsigned short gpu_devid = intel_private.pcidev->device;
1211
1212         /* Query intel_iommu to see if we need the workaround. Presumably that
1213          * was loaded first.
1214          */
1215         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1216              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1217              intel_iommu_gfx_mapped)
1218                 return 1;
1219 #endif
1220         return 0;
1221 }
1222
1223 static int i9xx_setup(void)
1224 {
1225         u32 reg_addr;
1226
1227         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1228
1229         reg_addr &= 0xfff80000;
1230
1231         intel_private.registers = ioremap(reg_addr, 128 * 4096);
1232         if (!intel_private.registers)
1233                 return -ENOMEM;
1234
1235         if (INTEL_GTT_GEN == 3) {
1236                 u32 gtt_addr;
1237
1238                 pci_read_config_dword(intel_private.pcidev,
1239                                       I915_PTEADDR, &gtt_addr);
1240                 intel_private.gtt_bus_addr = gtt_addr;
1241         } else {
1242                 u32 gtt_offset;
1243
1244                 switch (INTEL_GTT_GEN) {
1245                 case 5:
1246                 case 6:
1247                         gtt_offset = MB(2);
1248                         break;
1249                 case 4:
1250                 default:
1251                         gtt_offset =  KB(512);
1252                         break;
1253                 }
1254                 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1255         }
1256
1257         if (needs_idle_maps())
1258                 intel_private.base.do_idle_maps = 1;
1259
1260         intel_i9xx_setup_flush();
1261
1262         return 0;
1263 }
1264
1265 static const struct agp_bridge_driver intel_fake_agp_driver = {
1266         .owner                  = THIS_MODULE,
1267         .size_type              = FIXED_APER_SIZE,
1268         .aperture_sizes         = intel_fake_agp_sizes,
1269         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1270         .configure              = intel_fake_agp_configure,
1271         .fetch_size             = intel_fake_agp_fetch_size,
1272         .cleanup                = intel_gtt_cleanup,
1273         .agp_enable             = intel_fake_agp_enable,
1274         .cache_flush            = global_cache_flush,
1275         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1276         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1277         .insert_memory          = intel_fake_agp_insert_entries,
1278         .remove_memory          = intel_fake_agp_remove_entries,
1279         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1280         .free_by_type           = intel_i810_free_by_type,
1281         .agp_alloc_page         = agp_generic_alloc_page,
1282         .agp_alloc_pages        = agp_generic_alloc_pages,
1283         .agp_destroy_page       = agp_generic_destroy_page,
1284         .agp_destroy_pages      = agp_generic_destroy_pages,
1285 };
1286
1287 static const struct intel_gtt_driver i81x_gtt_driver = {
1288         .gen = 1,
1289         .has_pgtbl_enable = 1,
1290         .dma_mask_size = 32,
1291         .setup = i810_setup,
1292         .cleanup = i810_cleanup,
1293         .check_flags = i830_check_flags,
1294         .write_entry = i810_write_entry,
1295 };
1296 static const struct intel_gtt_driver i8xx_gtt_driver = {
1297         .gen = 2,
1298         .has_pgtbl_enable = 1,
1299         .setup = i830_setup,
1300         .cleanup = i830_cleanup,
1301         .write_entry = i830_write_entry,
1302         .dma_mask_size = 32,
1303         .check_flags = i830_check_flags,
1304         .chipset_flush = i830_chipset_flush,
1305 };
1306 static const struct intel_gtt_driver i915_gtt_driver = {
1307         .gen = 3,
1308         .has_pgtbl_enable = 1,
1309         .setup = i9xx_setup,
1310         .cleanup = i9xx_cleanup,
1311         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1312         .write_entry = i830_write_entry,
1313         .dma_mask_size = 32,
1314         .check_flags = i830_check_flags,
1315         .chipset_flush = i9xx_chipset_flush,
1316 };
1317 static const struct intel_gtt_driver g33_gtt_driver = {
1318         .gen = 3,
1319         .is_g33 = 1,
1320         .setup = i9xx_setup,
1321         .cleanup = i9xx_cleanup,
1322         .write_entry = i965_write_entry,
1323         .dma_mask_size = 36,
1324         .check_flags = i830_check_flags,
1325         .chipset_flush = i9xx_chipset_flush,
1326 };
1327 static const struct intel_gtt_driver pineview_gtt_driver = {
1328         .gen = 3,
1329         .is_pineview = 1, .is_g33 = 1,
1330         .setup = i9xx_setup,
1331         .cleanup = i9xx_cleanup,
1332         .write_entry = i965_write_entry,
1333         .dma_mask_size = 36,
1334         .check_flags = i830_check_flags,
1335         .chipset_flush = i9xx_chipset_flush,
1336 };
1337 static const struct intel_gtt_driver i965_gtt_driver = {
1338         .gen = 4,
1339         .has_pgtbl_enable = 1,
1340         .setup = i9xx_setup,
1341         .cleanup = i9xx_cleanup,
1342         .write_entry = i965_write_entry,
1343         .dma_mask_size = 36,
1344         .check_flags = i830_check_flags,
1345         .chipset_flush = i9xx_chipset_flush,
1346 };
1347 static const struct intel_gtt_driver g4x_gtt_driver = {
1348         .gen = 5,
1349         .setup = i9xx_setup,
1350         .cleanup = i9xx_cleanup,
1351         .write_entry = i965_write_entry,
1352         .dma_mask_size = 36,
1353         .check_flags = i830_check_flags,
1354         .chipset_flush = i9xx_chipset_flush,
1355 };
1356 static const struct intel_gtt_driver ironlake_gtt_driver = {
1357         .gen = 5,
1358         .is_ironlake = 1,
1359         .setup = i9xx_setup,
1360         .cleanup = i9xx_cleanup,
1361         .write_entry = i965_write_entry,
1362         .dma_mask_size = 36,
1363         .check_flags = i830_check_flags,
1364         .chipset_flush = i9xx_chipset_flush,
1365 };
1366 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1367         .gen = 6,
1368         .setup = i9xx_setup,
1369         .cleanup = gen6_cleanup,
1370         .write_entry = gen6_write_entry,
1371         .dma_mask_size = 40,
1372         .check_flags = gen6_check_flags,
1373         .chipset_flush = i9xx_chipset_flush,
1374 };
1375
1376 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1377  * driver and gmch_driver must be non-null, and find_gmch will determine
1378  * which one should be used if a gmch_chip_id is present.
1379  */
1380 static const struct intel_gtt_driver_description {
1381         unsigned int gmch_chip_id;
1382         char *name;
1383         const struct intel_gtt_driver *gtt_driver;
1384 } intel_gtt_chipsets[] = {
1385         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1386                 &i81x_gtt_driver},
1387         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1388                 &i81x_gtt_driver},
1389         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1390                 &i81x_gtt_driver},
1391         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1392                 &i81x_gtt_driver},
1393         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1394                 &i8xx_gtt_driver},
1395         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1396                 &i8xx_gtt_driver},
1397         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1398                 &i8xx_gtt_driver},
1399         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1400                 &i8xx_gtt_driver},
1401         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1402                 &i8xx_gtt_driver},
1403         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1404                 &i915_gtt_driver },
1405         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1406                 &i915_gtt_driver },
1407         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1408                 &i915_gtt_driver },
1409         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1410                 &i915_gtt_driver },
1411         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1412                 &i915_gtt_driver },
1413         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1414                 &i915_gtt_driver },
1415         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1416                 &i965_gtt_driver },
1417         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1418                 &i965_gtt_driver },
1419         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1420                 &i965_gtt_driver },
1421         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1422                 &i965_gtt_driver },
1423         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1424                 &i965_gtt_driver },
1425         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1426                 &i965_gtt_driver },
1427         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1428                 &g33_gtt_driver },
1429         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1430                 &g33_gtt_driver },
1431         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1432                 &g33_gtt_driver },
1433         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1434                 &pineview_gtt_driver },
1435         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1436                 &pineview_gtt_driver },
1437         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1438                 &g4x_gtt_driver },
1439         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1440                 &g4x_gtt_driver },
1441         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1442                 &g4x_gtt_driver },
1443         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1444                 &g4x_gtt_driver },
1445         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1446                 &g4x_gtt_driver },
1447         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1448                 &g4x_gtt_driver },
1449         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1450                 &g4x_gtt_driver },
1451         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1452             "HD Graphics", &ironlake_gtt_driver },
1453         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1454             "HD Graphics", &ironlake_gtt_driver },
1455         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1456             "Sandybridge", &sandybridge_gtt_driver },
1457         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1458             "Sandybridge", &sandybridge_gtt_driver },
1459         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1460             "Sandybridge", &sandybridge_gtt_driver },
1461         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1462             "Sandybridge", &sandybridge_gtt_driver },
1463         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1464             "Sandybridge", &sandybridge_gtt_driver },
1465         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1466             "Sandybridge", &sandybridge_gtt_driver },
1467         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1468             "Sandybridge", &sandybridge_gtt_driver },
1469         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
1470             "Ivybridge", &sandybridge_gtt_driver },
1471         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
1472             "Ivybridge", &sandybridge_gtt_driver },
1473         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
1474             "Ivybridge", &sandybridge_gtt_driver },
1475         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
1476             "Ivybridge", &sandybridge_gtt_driver },
1477         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
1478             "Ivybridge", &sandybridge_gtt_driver },
1479         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
1480             "Ivybridge", &sandybridge_gtt_driver },
1481         { 0, NULL, NULL }
1482 };
1483
1484 static int find_gmch(u16 device)
1485 {
1486         struct pci_dev *gmch_device;
1487
1488         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1489         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1490                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1491                                              device, gmch_device);
1492         }
1493
1494         if (!gmch_device)
1495                 return 0;
1496
1497         intel_private.pcidev = gmch_device;
1498         return 1;
1499 }
1500
1501 int intel_gmch_probe(struct pci_dev *pdev,
1502                                       struct agp_bridge_data *bridge)
1503 {
1504         int i, mask;
1505         intel_private.driver = NULL;
1506
1507         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1508                 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1509                         intel_private.driver =
1510                                 intel_gtt_chipsets[i].gtt_driver;
1511                         break;
1512                 }
1513         }
1514
1515         if (!intel_private.driver)
1516                 return 0;
1517
1518         bridge->driver = &intel_fake_agp_driver;
1519         bridge->dev_private_data = &intel_private;
1520         bridge->dev = pdev;
1521
1522         intel_private.bridge_dev = pci_dev_get(pdev);
1523
1524         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1525
1526         mask = intel_private.driver->dma_mask_size;
1527         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1528                 dev_err(&intel_private.pcidev->dev,
1529                         "set gfx device dma mask %d-bit failed!\n", mask);
1530         else
1531                 pci_set_consistent_dma_mask(intel_private.pcidev,
1532                                             DMA_BIT_MASK(mask));
1533
1534         /*if (bridge->driver == &intel_810_driver)
1535                 return 1;*/
1536
1537         if (intel_gtt_init() != 0)
1538                 return 0;
1539
1540         return 1;
1541 }
1542 EXPORT_SYMBOL(intel_gmch_probe);
1543
1544 const struct intel_gtt *intel_gtt_get(void)
1545 {
1546         return &intel_private.base;
1547 }
1548 EXPORT_SYMBOL(intel_gtt_get);
1549
1550 void intel_gtt_chipset_flush(void)
1551 {
1552         if (intel_private.driver->chipset_flush)
1553                 intel_private.driver->chipset_flush();
1554 }
1555 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1556
1557 void intel_gmch_remove(struct pci_dev *pdev)
1558 {
1559         if (intel_private.pcidev)
1560                 pci_dev_put(intel_private.pcidev);
1561         if (intel_private.bridge_dev)
1562                 pci_dev_put(intel_private.bridge_dev);
1563 }
1564 EXPORT_SYMBOL(intel_gmch_remove);
1565
1566 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1567 MODULE_LICENSE("GPL and additional rights");