1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/sections.h>
22 #include <linux/topology.h>
23 #include <linux/cpumask.h>
24 #include <asm/pgtable.h>
25 #include <linux/atomic.h>
26 #include <asm/proto.h>
27 #include <asm/setup.h>
32 #include <linux/numa.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/uv/uv.h>
44 #include <xen/interface/callback.h>
49 /* all of these masks are initialized in setup_cpu_local_masks() */
50 cpumask_var_t cpu_initialized_mask;
52 cpumask_var_t cpu_callout_mask;
53 cpumask_var_t cpu_callin_mask;
55 /* representing cpus for which sibling maps can be computed */
56 cpumask_var_t cpu_sibling_setup_mask;
59 /* correctly size the local cpu masks */
60 void __init setup_cpu_local_masks(void)
62 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
64 alloc_bootmem_cpumask_var(&cpu_callin_mask);
65 alloc_bootmem_cpumask_var(&cpu_callout_mask);
66 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
70 static void __cpuinit default_init(struct cpuinfo_x86 *c)
73 cpu_detect_cache_sizes(c);
75 /* Not much we can do here... */
76 /* Check if at least it has cpuid */
77 if (c->cpuid_level == -1) {
78 /* No cpuid. It must be an ancient CPU */
80 strcpy(c->x86_model_id, "486");
82 strcpy(c->x86_model_id, "386");
87 static const struct cpu_dev __cpuinitconst default_cpu = {
88 .c_init = default_init,
89 .c_vendor = "Unknown",
90 .c_x86_vendor = X86_VENDOR_UNKNOWN,
93 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
98 * We need valid kernel segments for data and code in long mode too
99 * IRET will check the segment types kkeil 2000/10/28
100 * Also sysret mandates a special GDT layout
102 * TLS descriptors are currently at a different place compared to i386.
103 * Hopefully nobody expects them at a fixed place (Wine?)
105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
118 * Segments used for calling PnP BIOS have byte granularity.
119 * They code segments and data segments have fixed 64k limits,
120 * the transfer segment sizes are set at run time.
123 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
125 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
127 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
129 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
131 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
133 * The APM segments have byte granularity and their bases
134 * are set at run time. All have 64k limits.
137 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
139 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
141 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
143 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
145 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
146 GDT_STACK_CANARY_INIT
149 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
151 static int __init x86_xsave_setup(char *s)
153 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
154 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
157 __setup("noxsave", x86_xsave_setup);
159 static int __init x86_xsaveopt_setup(char *s)
161 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
164 __setup("noxsaveopt", x86_xsaveopt_setup);
167 static int cachesize_override __cpuinitdata = -1;
169 static int __init cachesize_setup(char *str)
171 get_option(&str, &cachesize_override);
174 __setup("cachesize=", cachesize_setup);
176 static int __init x86_fxsr_setup(char *s)
178 setup_clear_cpu_cap(X86_FEATURE_FXSR);
179 setup_clear_cpu_cap(X86_FEATURE_XMM);
182 __setup("nofxsr", x86_fxsr_setup);
184 static int __init x86_sep_setup(char *s)
186 setup_clear_cpu_cap(X86_FEATURE_SEP);
189 __setup("nosep", x86_sep_setup);
192 #if defined(CONFIG_X86_32) && !defined(CONFIG_XEN)
193 /* Standard macro to see if a specific flag is changeable */
194 static inline int flag_is_changeable_p(u32 flag)
199 * Cyrix and IDT cpus allow disabling of CPUID
200 * so the code below may return different results
201 * when it is executed before and after enabling
202 * the CPUID. Add "volatile" to not allow gcc to
203 * optimize the subsequent calls to this function.
205 asm volatile ("pushfl \n\t"
216 : "=&r" (f1), "=&r" (f2)
219 return ((f1^f2) & flag) != 0;
222 /* Probe for the CPUID instruction */
223 static int __cpuinit have_cpuid_p(void)
225 return flag_is_changeable_p(X86_EFLAGS_ID);
228 static int disable_x86_serial_nr __cpuinitdata = 1;
230 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
232 unsigned long lo, hi;
234 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
237 /* Disable processor serial number: */
239 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
241 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
243 printk(KERN_NOTICE "CPU serial number disabled.\n");
244 clear_cpu_cap(c, X86_FEATURE_PN);
246 /* Disabling the serial number may affect the cpuid level */
247 c->cpuid_level = cpuid_eax(0);
250 static int __init x86_serial_nr_setup(char *s)
252 disable_x86_serial_nr = 0;
255 __setup("serialnumber", x86_serial_nr_setup);
257 static inline int flag_is_changeable_p(u32 flag)
261 /* Probe for the CPUID instruction */
262 static inline int have_cpuid_p(void)
266 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
271 static int disable_smep __cpuinitdata;
272 static __init int setup_disable_smep(char *arg)
277 __setup("nosmep", setup_disable_smep);
279 static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
281 if (cpu_has(c, X86_FEATURE_SMEP)) {
282 if (unlikely(disable_smep)) {
283 setup_clear_cpu_cap(X86_FEATURE_SMEP);
284 clear_in_cr4(X86_CR4_SMEP);
286 set_in_cr4(X86_CR4_SMEP);
291 * Some CPU features depend on higher CPUID levels, which may not always
292 * be available due to CPUID level capping or broken virtualization
293 * software. Add those features to this table to auto-disable them.
295 struct cpuid_dependent_feature {
300 static const struct cpuid_dependent_feature __cpuinitconst
301 cpuid_dependent_features[] = {
302 { X86_FEATURE_MWAIT, 0x00000005 },
303 { X86_FEATURE_DCA, 0x00000009 },
304 { X86_FEATURE_XSAVE, 0x0000000d },
308 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
310 const struct cpuid_dependent_feature *df;
312 for (df = cpuid_dependent_features; df->feature; df++) {
314 if (!cpu_has(c, df->feature))
317 * Note: cpuid_level is set to -1 if unavailable, but
318 * extended_extended_level is set to 0 if unavailable
319 * and the legitimate extended levels are all negative
320 * when signed; hence the weird messing around with
323 if (!((s32)df->level < 0 ?
324 (u32)df->level > (u32)c->extended_cpuid_level :
325 (s32)df->level > (s32)c->cpuid_level))
328 clear_cpu_cap(c, df->feature);
333 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
334 x86_cap_flags[df->feature], df->level);
339 * Naming convention should be: <Name> [(<Codename>)]
340 * This table only is used unless init_<vendor>() below doesn't set it;
341 * in particular, if CPUID levels 0x80000002..4 are supported, this
345 /* Look up CPU names by table lookup. */
346 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
348 const struct cpu_model_info *info;
350 if (c->x86_model >= 16)
351 return NULL; /* Range check */
356 info = this_cpu->c_models;
358 while (info && info->family) {
359 if (info->family == c->x86)
360 return info->model_names[c->x86_model];
363 return NULL; /* Not found */
366 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
367 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
369 void __ref load_percpu_segment(int cpu)
371 #ifdef CONFIG_XEN_VCPU_INFO_PLACEMENT
376 adjust_boot_vcpu_info();
380 loadsegment(fs, __KERNEL_PERCPU);
384 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
386 if (HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL,
387 (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)))
391 load_stack_canary_segment();
395 * Current gdt points %fs at the "master" per-cpu area: after this,
396 * it's on the real one.
398 void switch_to_new_gdt(int cpu)
400 struct desc_ptr gdt_descr;
401 unsigned long va, frames[16];
404 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
405 gdt_descr.size = GDT_SIZE - 1;
407 for (va = gdt_descr.address, f = 0;
408 va < gdt_descr.address + gdt_descr.size;
409 va += PAGE_SIZE, f++) {
410 frames[f] = arbitrary_virt_to_mfn(va);
411 make_page_readonly((void *)va,
412 XENFEAT_writable_descriptor_tables);
414 if (HYPERVISOR_set_gdt(frames, (gdt_descr.size + 1) / 8))
417 /* Reload the per-cpu base */
419 load_percpu_segment(cpu);
422 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
424 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
429 if (c->extended_cpuid_level < 0x80000004)
432 v = (unsigned int *)c->x86_model_id;
433 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
434 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
435 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
436 c->x86_model_id[48] = 0;
439 * Intel chips right-justify this string for some dumb reason;
440 * undo that brain damage:
442 p = q = &c->x86_model_id[0];
448 while (q <= &c->x86_model_id[48])
449 *q++ = '\0'; /* Zero-pad the rest */
453 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
455 unsigned int n, dummy, ebx, ecx, edx, l2size;
457 n = c->extended_cpuid_level;
459 if (n >= 0x80000005) {
460 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
461 c->x86_cache_size = (ecx>>24) + (edx>>24);
463 /* On K8 L1 TLB is inclusive, so don't count it */
468 if (n < 0x80000006) /* Some chips just has a large L1. */
471 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
475 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
477 /* do processor-specific cache resizing */
478 if (this_cpu->c_size_cache)
479 l2size = this_cpu->c_size_cache(c, l2size);
481 /* Allow user to override all this if necessary. */
482 if (cachesize_override != -1)
483 l2size = cachesize_override;
486 return; /* Again, no L2 cache is possible */
489 c->x86_cache_size = l2size;
492 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
495 u32 eax, ebx, ecx, edx;
496 int index_msb, core_bits;
499 if (!cpu_has(c, X86_FEATURE_HT))
502 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
505 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
508 cpuid(1, &eax, &ebx, &ecx, &edx);
510 smp_num_siblings = (ebx & 0xff0000) >> 16;
512 if (smp_num_siblings == 1) {
513 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
517 if (smp_num_siblings <= 1)
520 index_msb = get_count_order(smp_num_siblings);
521 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
523 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
525 index_msb = get_count_order(smp_num_siblings);
527 core_bits = get_count_order(c->x86_max_cores);
529 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
530 ((1 << core_bits) - 1);
533 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
534 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
536 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
543 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
545 char *v = c->x86_vendor_id;
548 for (i = 0; i < X86_VENDOR_NUM; i++) {
552 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
553 (cpu_devs[i]->c_ident[1] &&
554 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
556 this_cpu = cpu_devs[i];
557 c->x86_vendor = this_cpu->c_x86_vendor;
563 "CPU: vendor_id '%s' unknown, using generic init.\n" \
564 "CPU: Your system may be unstable.\n", v);
566 c->x86_vendor = X86_VENDOR_UNKNOWN;
567 this_cpu = &default_cpu;
570 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
572 /* Get vendor name */
573 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
574 (unsigned int *)&c->x86_vendor_id[0],
575 (unsigned int *)&c->x86_vendor_id[8],
576 (unsigned int *)&c->x86_vendor_id[4]);
579 /* Intel-defined flags: level 0x00000001 */
580 if (c->cpuid_level >= 0x00000001) {
581 u32 junk, tfms, cap0, misc;
583 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
584 c->x86 = (tfms >> 8) & 0xf;
585 c->x86_model = (tfms >> 4) & 0xf;
586 c->x86_mask = tfms & 0xf;
589 c->x86 += (tfms >> 20) & 0xff;
591 c->x86_model += ((tfms >> 16) & 0xf) << 4;
593 if (cap0 & (1<<19)) {
594 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
595 c->x86_cache_alignment = c->x86_clflush_size;
600 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
605 /* Intel-defined flags: level 0x00000001 */
606 if (c->cpuid_level >= 0x00000001) {
607 u32 capability, excap;
609 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
610 c->x86_capability[0] = capability;
611 c->x86_capability[4] = excap;
614 /* Additional Intel-defined flags: level 0x00000007 */
615 if (c->cpuid_level >= 0x00000007) {
616 u32 eax, ebx, ecx, edx;
618 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
620 c->x86_capability[9] = ebx;
623 /* AMD-defined flags: level 0x80000001 */
624 xlvl = cpuid_eax(0x80000000);
625 c->extended_cpuid_level = xlvl;
627 if ((xlvl & 0xffff0000) == 0x80000000) {
628 if (xlvl >= 0x80000001) {
629 c->x86_capability[1] = cpuid_edx(0x80000001);
630 c->x86_capability[6] = cpuid_ecx(0x80000001);
634 if (c->extended_cpuid_level >= 0x80000008) {
635 u32 eax = cpuid_eax(0x80000008);
637 c->x86_virt_bits = (eax >> 8) & 0xff;
638 c->x86_phys_bits = eax & 0xff;
641 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
642 c->x86_phys_bits = 36;
645 if (c->extended_cpuid_level >= 0x80000007)
646 c->x86_power = cpuid_edx(0x80000007);
648 init_scattered_cpuid_features(c);
651 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
657 * First of all, decide if this is a 486 or higher
658 * It's a 486 if we can modify the AC flag
660 if (flag_is_changeable_p(X86_EFLAGS_AC))
665 for (i = 0; i < X86_VENDOR_NUM; i++)
666 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
667 c->x86_vendor_id[0] = 0;
668 cpu_devs[i]->c_identify(c);
669 if (c->x86_vendor_id[0]) {
678 * Do minimum CPU detection early.
679 * Fields really needed: vendor, cpuid_level, family, model, mask,
681 * The others are not touched to avoid unwanted side effects.
683 * WARNING: this function is only called on the BP. Don't add code here
684 * that is supposed to run on all CPUs.
686 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
689 c->x86_clflush_size = 64;
690 c->x86_phys_bits = 36;
691 c->x86_virt_bits = 48;
693 c->x86_clflush_size = 32;
694 c->x86_phys_bits = 32;
695 c->x86_virt_bits = 32;
697 c->x86_cache_alignment = c->x86_clflush_size;
699 memset(&c->x86_capability, 0, sizeof c->x86_capability);
700 c->extended_cpuid_level = 0;
703 identify_cpu_without_cpuid(c);
705 /* cyrix could have cpuid enabled via c_identify()*/
716 x86_xsave_setup(NULL);
719 if (this_cpu->c_early_init)
720 this_cpu->c_early_init(c);
723 filter_cpuid_features(c, false);
727 if (this_cpu->c_bsp_init)
728 this_cpu->c_bsp_init(c);
731 void __init early_cpu_init(void)
733 const struct cpu_dev *const *cdev;
736 #ifdef CONFIG_PROCESSOR_SELECT
737 printk(KERN_INFO "KERNEL supported cpus:\n");
740 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
741 const struct cpu_dev *cpudev = *cdev;
743 if (count >= X86_VENDOR_NUM)
745 cpu_devs[count] = cpudev;
748 #ifdef CONFIG_PROCESSOR_SELECT
752 for (j = 0; j < 2; j++) {
753 if (!cpudev->c_ident[j])
755 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
761 early_identify_cpu(&boot_cpu_data);
765 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
766 * unfortunately, that's not true in practice because of early VIA
767 * chips and (more importantly) broken virtualizers that are not easy
768 * to detect. In the latter case it doesn't even *fail* reliably, so
769 * probing for it doesn't even work. Disable it completely on 32-bit
770 * unless we can find a reliable way to detect all the broken cases.
771 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
773 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
776 clear_cpu_cap(c, X86_FEATURE_NOPL);
778 set_cpu_cap(c, X86_FEATURE_NOPL);
782 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
784 c->extended_cpuid_level = 0;
787 identify_cpu_without_cpuid(c);
789 /* cyrix could have cpuid enabled via c_identify()*/
800 if (c->cpuid_level >= 0x00000001) {
801 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
803 # ifdef CONFIG_X86_HT
804 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
806 c->apicid = c->initial_apicid;
809 c->phys_proc_id = c->initial_apicid;
815 get_model_name(c); /* Default name */
821 * This does the hard work of actually picking apart the CPU stuff...
823 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
827 c->loops_per_jiffy = loops_per_jiffy;
828 c->x86_cache_size = -1;
829 c->x86_vendor = X86_VENDOR_UNKNOWN;
830 c->x86_model = c->x86_mask = 0; /* So far unknown... */
831 c->x86_vendor_id[0] = '\0'; /* Unset */
832 c->x86_model_id[0] = '\0'; /* Unset */
834 c->x86_max_cores = 1;
835 c->x86_coreid_bits = 0;
838 c->x86_clflush_size = 64;
839 c->x86_phys_bits = 36;
840 c->x86_virt_bits = 48;
842 c->cpuid_level = -1; /* CPUID not detected */
843 c->x86_clflush_size = 32;
844 c->x86_phys_bits = 32;
845 c->x86_virt_bits = 32;
847 c->x86_cache_alignment = c->x86_clflush_size;
848 memset(&c->x86_capability, 0, sizeof c->x86_capability);
849 if (boot_cpu_has(X86_FEATURE_SYSCALL32))
850 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
854 if (this_cpu->c_identify)
855 this_cpu->c_identify(c);
857 /* Clear/Set all flags overriden by options, after probe */
858 for (i = 0; i < NCAPINTS; i++) {
859 c->x86_capability[i] &= ~cpu_caps_cleared[i];
860 c->x86_capability[i] |= cpu_caps_set[i];
863 #if defined(CONFIG_X86_64) && !defined(CONFIG_XEN)
864 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
868 * Vendor-specific initialization. In this section we
869 * canonicalize the feature flags, meaning if there are
870 * features a certain CPU supports which CPUID doesn't
871 * tell us, CPUID claiming incorrect flags, or other bugs,
872 * we handle them here.
874 * At the end of this section, c->x86_capability better
875 * indicate the features this CPU genuinely supports!
877 if (this_cpu->c_init)
880 /* Disable the PN if appropriate */
881 squash_the_stupid_serial_number(c);
884 * The vendor-specific functions might have changed features.
885 * Now we do "generic changes."
888 /* Filter out anything that depends on CPUID levels we don't have */
889 filter_cpuid_features(c, true);
891 /* If the model name is still unset, do table lookup. */
892 if (!c->x86_model_id[0]) {
894 p = table_lookup_model(c);
896 strcpy(c->x86_model_id, p);
899 sprintf(c->x86_model_id, "%02x/%02x",
900 c->x86, c->x86_model);
911 * Clear/Set all flags overriden by options, need do it
912 * before following smp all cpus cap AND.
914 for (i = 0; i < NCAPINTS; i++) {
915 c->x86_capability[i] &= ~cpu_caps_cleared[i];
916 c->x86_capability[i] |= cpu_caps_set[i];
920 * On SMP, boot_cpu_data holds the common feature set between
921 * all CPUs; so make sure that we indicate which features are
922 * common between the CPUs. The first time this routine gets
923 * executed, c == &boot_cpu_data.
925 if (c != &boot_cpu_data) {
926 /* AND the already accumulated flags with these */
927 for (i = 0; i < NCAPINTS; i++)
928 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
931 /* Init Machine Check Exception if available. */
934 select_idle_routine(c);
937 numa_add_cpu(smp_processor_id());
942 static void vgetcpu_set_mode(void)
944 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
945 vgetcpu_mode = VGETCPU_RDTSCP;
947 vgetcpu_mode = VGETCPU_LSL;
951 void __init identify_boot_cpu(void)
953 identify_cpu(&boot_cpu_data);
954 init_amd_e400_c1e_mask();
964 void set_perf_event_pending(void) {}
967 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
969 BUG_ON(c == &boot_cpu_data);
982 static const struct msr_range msr_range_array[] __cpuinitconst = {
983 { 0x00000000, 0x00000418},
984 { 0xc0000000, 0xc000040b},
985 { 0xc0010000, 0xc0010142},
986 { 0xc0011000, 0xc001103b},
989 static void __cpuinit print_cpu_msr(void)
991 unsigned index_min, index_max;
996 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
997 index_min = msr_range_array[i].min;
998 index_max = msr_range_array[i].max;
1000 for (index = index_min; index < index_max; index++) {
1001 if (rdmsrl_amd_safe(index, &val))
1003 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1008 static int show_msr __cpuinitdata;
1010 static __init int setup_show_msr(char *arg)
1014 get_option(&arg, &num);
1020 __setup("show_msr=", setup_show_msr);
1022 static __init int setup_noclflush(char *arg)
1024 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1027 __setup("noclflush", setup_noclflush);
1029 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1031 const char *vendor = NULL;
1033 if (c->x86_vendor < X86_VENDOR_NUM) {
1034 vendor = this_cpu->c_vendor;
1036 if (c->cpuid_level >= 0)
1037 vendor = c->x86_vendor_id;
1040 if (vendor && !strstr(c->x86_model_id, vendor))
1041 printk(KERN_CONT "%s ", vendor);
1043 if (c->x86_model_id[0])
1044 printk(KERN_CONT "%s", c->x86_model_id);
1046 printk(KERN_CONT "%d86", c->x86);
1048 if (c->x86_mask || c->cpuid_level >= 0)
1049 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1051 printk(KERN_CONT "\n");
1054 if (c->cpu_index < show_msr)
1062 static __init int setup_disablecpuid(char *arg)
1066 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1067 setup_clear_cpu_cap(bit);
1073 __setup("clearcpuid=", setup_disablecpuid);
1075 #ifdef CONFIG_X86_64
1076 #ifndef CONFIG_X86_NO_IDT
1077 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1078 struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1,
1079 (unsigned long) nmi_idt_table };
1082 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1083 irq_stack_union) __aligned(PAGE_SIZE);
1085 void xen_switch_pt(void)
1088 xen_pt_switch(init_level4_pgt);
1093 * The following four percpu variables are hot. Align current_task to
1094 * cacheline size such that all four fall in the same cacheline.
1096 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1098 EXPORT_PER_CPU_SYMBOL(current_task);
1100 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1101 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1102 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1104 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1105 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1107 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1109 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1110 EXPORT_PER_CPU_SYMBOL(fpu_owner_task);
1112 #ifndef CONFIG_X86_NO_TSS
1114 * Special IST stacks which the CPU switches to when it calls
1115 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1116 * limit), all of them are 4K, except the debug stack which
1119 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1120 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1121 [DEBUG_STACK - 1] = DEBUG_STKSZ
1124 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1125 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1128 void __cpuinit syscall_init(void)
1132 * LSTAR and STAR live in a bit strange symbiosis.
1133 * They both write to the same internal register. STAR allows to
1134 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1136 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1137 wrmsrl(MSR_LSTAR, system_call);
1138 wrmsrl(MSR_CSTAR, ignore_sysret);
1141 #ifdef CONFIG_IA32_EMULATION
1142 syscall32_cpu_init();
1143 #elif defined(CONFIG_XEN)
1144 static const struct callback_register __cpuinitconst cstar = {
1145 .type = CALLBACKTYPE_syscall32,
1146 .address = (unsigned long)ignore_sysret
1149 if (HYPERVISOR_callback_op(CALLBACKOP_register, &cstar))
1150 printk(KERN_WARNING "Unable to register CSTAR callback\n");
1154 /* Flags to clear on syscall */
1155 wrmsrl(MSR_SYSCALL_MASK,
1156 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1160 unsigned long kernel_eflags;
1162 #ifndef CONFIG_X86_NO_TSS
1164 * Copies of the original ist values from the tss are only accessed during
1165 * debugging, no special alignment required.
1167 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1170 #ifndef CONFIG_X86_NO_IDT
1171 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1172 DEFINE_PER_CPU(int, debug_stack_usage);
1174 int is_debug_stack(unsigned long addr)
1176 return __get_cpu_var(debug_stack_usage) ||
1177 (addr <= __get_cpu_var(debug_stack_addr) &&
1178 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1181 void debug_stack_set_zero(void)
1183 load_idt((const struct desc_ptr *)&nmi_idt_descr);
1186 void debug_stack_reset(void)
1188 load_idt((const struct desc_ptr *)&idt_descr);
1192 #else /* CONFIG_X86_64 */
1194 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1195 EXPORT_PER_CPU_SYMBOL(current_task);
1196 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1197 EXPORT_PER_CPU_SYMBOL(fpu_owner_task);
1199 #ifdef CONFIG_CC_STACKPROTECTOR
1200 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1203 /* Make sure %fs and %gs are initialized properly in idle threads */
1204 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1206 memset(regs, 0, sizeof(struct pt_regs));
1207 regs->fs = __KERNEL_PERCPU;
1208 regs->gs = __KERNEL_STACK_CANARY;
1212 #endif /* CONFIG_X86_64 */
1215 * Clear all 6 debug registers:
1217 static void clear_all_debug_regs(void)
1221 for (i = 0; i < 8; i++) {
1222 /* Ignore db4, db5 */
1223 if ((i == 4) || (i == 5))
1232 * Restore debug regs if using kgdbwait and you have a kernel debugger
1233 * connection established.
1235 static void dbg_restore_debug_regs(void)
1237 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1238 arch_kgdb_ops.correct_hw_break();
1240 #else /* ! CONFIG_KGDB */
1241 #define dbg_restore_debug_regs()
1242 #endif /* ! CONFIG_KGDB */
1246 * Prints an error where the NUMA and configured core-number mismatch and the
1247 * platform didn't override this to fix it up
1249 void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
1251 pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
1256 * cpu_init() initializes state that is per-CPU. Some data is already
1257 * initialized (naturally) in the bootstrap process, such as the GDT
1258 * and IDT. We reload them nevertheless, this function acts as a
1259 * 'CPU state barrier', nothing should get across.
1260 * A lot of state is already set up in PDA init for 64 bit
1262 #ifdef CONFIG_X86_64
1264 void __cpuinit cpu_init(void)
1266 #ifndef CONFIG_X86_NO_TSS
1267 struct orig_ist *oist;
1268 struct tss_struct *t;
1272 struct task_struct *me;
1275 cpu = stack_smp_processor_id();
1276 /* CPU 0 is initialised in head64.c */
1279 #ifndef CONFIG_X86_NO_TSS
1280 t = &per_cpu(init_tss, cpu);
1281 oist = &per_cpu(orig_ist, cpu);
1285 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1286 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1287 set_numa_node(early_cpu_to_node(cpu));
1292 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1293 panic("CPU#%d already initialized!\n", cpu);
1295 pr_debug("Initializing CPU#%d\n", cpu);
1297 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1300 * Initialize the per-CPU GDT with the boot GDT,
1301 * and set up the GDT descriptor:
1304 switch_to_new_gdt(cpu);
1307 #ifndef CONFIG_X86_NO_IDT
1308 load_idt((const struct desc_ptr *)&idt_descr);
1311 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1314 wrmsrl(MSR_FS_BASE, 0);
1315 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1319 #ifdef CONFIG_X86_LOCAL_APIC
1324 #ifndef CONFIG_X86_NO_TSS
1326 * set up and load the per-CPU TSS
1328 if (!oist->ist[0]) {
1329 char *estacks = per_cpu(exception_stacks, cpu);
1331 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1332 estacks += exception_stack_sizes[v];
1333 oist->ist[v] = t->x86_tss.ist[v] =
1334 (unsigned long)estacks;
1335 #ifndef CONFIG_X86_NO_IDT
1336 if (v == DEBUG_STACK-1)
1337 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1342 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1345 * <= is required because the CPU will access up to
1346 * 8 bits beyond the end of the IO permission bitmap.
1348 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1349 t->io_bitmap[i] = ~0UL;
1352 atomic_inc(&init_mm.mm_count);
1353 me->active_mm = &init_mm;
1355 enter_lazy_tlb(&init_mm, me);
1357 load_sp0(t, ¤t->thread);
1358 #ifndef CONFIG_X86_NO_TSS
1359 set_tss_desc(cpu, t);
1362 load_LDT(&init_mm.context);
1364 clear_all_debug_regs();
1365 dbg_restore_debug_regs();
1371 raw_local_save_flags(kernel_eflags);
1373 asm ("pushfq; popq %0" : "=rm" (kernel_eflags));
1374 if (raw_irqs_disabled())
1375 kernel_eflags &= ~X86_EFLAGS_IF;
1378 #ifdef CONFIG_X86_LOCAL_APIC
1386 void __cpuinit cpu_init(void)
1388 int cpu = smp_processor_id();
1389 struct task_struct *curr = current;
1390 #ifndef CONFIG_X86_NO_TSS
1391 struct tss_struct *t = &per_cpu(init_tss, cpu);
1393 struct thread_struct *thread = &curr->thread;
1395 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1396 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1401 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1403 if (cpu_has_vme || cpu_has_de)
1404 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1406 switch_to_new_gdt(cpu);
1409 * Set up and load the per-CPU TSS and LDT
1411 atomic_inc(&init_mm.mm_count);
1412 curr->active_mm = &init_mm;
1414 enter_lazy_tlb(&init_mm, curr);
1416 load_sp0(t, thread);
1418 load_LDT(&init_mm.context);
1420 #ifndef CONFIG_X86_NO_TSS
1421 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1424 #ifdef CONFIG_DOUBLEFAULT
1425 /* Set up doublefault TSS pointer in the GDT */
1426 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1429 clear_all_debug_regs();
1430 dbg_restore_debug_regs();