1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/debugreg.h>
22 #include <asm/sections.h>
23 #include <linux/topology.h>
24 #include <linux/cpumask.h>
25 #include <asm/pgtable.h>
26 #include <linux/atomic.h>
27 #include <asm/proto.h>
28 #include <asm/setup.h>
32 #include <asm/fpu-internal.h>
34 #include <linux/numa.h>
41 #ifdef CONFIG_X86_LOCAL_APIC
42 #include <asm/uv/uv.h>
46 #include <xen/interface/callback.h>
51 /* all of these masks are initialized in setup_cpu_local_masks() */
52 cpumask_var_t cpu_initialized_mask;
54 cpumask_var_t cpu_callout_mask;
55 cpumask_var_t cpu_callin_mask;
57 /* representing cpus for which sibling maps can be computed */
58 cpumask_var_t cpu_sibling_setup_mask;
61 /* correctly size the local cpu masks */
62 void __init setup_cpu_local_masks(void)
64 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
66 alloc_bootmem_cpumask_var(&cpu_callin_mask);
67 alloc_bootmem_cpumask_var(&cpu_callout_mask);
68 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
72 static void __cpuinit default_init(struct cpuinfo_x86 *c)
75 cpu_detect_cache_sizes(c);
77 /* Not much we can do here... */
78 /* Check if at least it has cpuid */
79 if (c->cpuid_level == -1) {
80 /* No cpuid. It must be an ancient CPU */
82 strcpy(c->x86_model_id, "486");
84 strcpy(c->x86_model_id, "386");
89 static const struct cpu_dev __cpuinitconst default_cpu = {
90 .c_init = default_init,
91 .c_vendor = "Unknown",
92 .c_x86_vendor = X86_VENDOR_UNKNOWN,
95 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
97 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
100 * We need valid kernel segments for data and code in long mode too
101 * IRET will check the segment types kkeil 2000/10/28
102 * Also sysret mandates a special GDT layout
104 * TLS descriptors are currently at a different place compared to i386.
105 * Hopefully nobody expects them at a fixed place (Wine?)
107 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
108 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
109 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
112 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
115 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
120 * Segments used for calling PnP BIOS have byte granularity.
121 * They code segments and data segments have fixed 64k limits,
122 * the transfer segment sizes are set at run time.
125 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
127 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
129 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
131 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
133 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
135 * The APM segments have byte granularity and their bases
136 * are set at run time. All have 64k limits.
139 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
141 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
143 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
145 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
147 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
148 GDT_STACK_CANARY_INIT
151 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
153 static int __init x86_xsave_setup(char *s)
155 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
156 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
159 __setup("noxsave", x86_xsave_setup);
161 static int __init x86_xsaveopt_setup(char *s)
163 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
166 __setup("noxsaveopt", x86_xsaveopt_setup);
169 static int cachesize_override __cpuinitdata = -1;
171 static int __init cachesize_setup(char *str)
173 get_option(&str, &cachesize_override);
176 __setup("cachesize=", cachesize_setup);
178 static int __init x86_fxsr_setup(char *s)
180 setup_clear_cpu_cap(X86_FEATURE_FXSR);
181 setup_clear_cpu_cap(X86_FEATURE_XMM);
184 __setup("nofxsr", x86_fxsr_setup);
186 static int __init x86_sep_setup(char *s)
188 setup_clear_cpu_cap(X86_FEATURE_SEP);
191 __setup("nosep", x86_sep_setup);
194 #if defined(CONFIG_X86_32) && !defined(CONFIG_XEN)
195 /* Standard macro to see if a specific flag is changeable */
196 static inline int flag_is_changeable_p(u32 flag)
201 * Cyrix and IDT cpus allow disabling of CPUID
202 * so the code below may return different results
203 * when it is executed before and after enabling
204 * the CPUID. Add "volatile" to not allow gcc to
205 * optimize the subsequent calls to this function.
207 asm volatile ("pushfl \n\t"
218 : "=&r" (f1), "=&r" (f2)
221 return ((f1^f2) & flag) != 0;
224 /* Probe for the CPUID instruction */
225 static int __cpuinit have_cpuid_p(void)
227 return flag_is_changeable_p(X86_EFLAGS_ID);
230 static int disable_x86_serial_nr __cpuinitdata = 1;
232 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
234 unsigned long lo, hi;
236 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
239 /* Disable processor serial number: */
241 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
243 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
245 printk(KERN_NOTICE "CPU serial number disabled.\n");
246 clear_cpu_cap(c, X86_FEATURE_PN);
248 /* Disabling the serial number may affect the cpuid level */
249 c->cpuid_level = cpuid_eax(0);
252 static int __init x86_serial_nr_setup(char *s)
254 disable_x86_serial_nr = 0;
257 __setup("serialnumber", x86_serial_nr_setup);
259 static inline int flag_is_changeable_p(u32 flag)
263 /* Probe for the CPUID instruction */
264 static inline int have_cpuid_p(void)
268 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
273 static int disable_smep __cpuinitdata;
274 static __init int setup_disable_smep(char *arg)
279 __setup("nosmep", setup_disable_smep);
281 static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
283 if (cpu_has(c, X86_FEATURE_SMEP)) {
284 if (unlikely(disable_smep)) {
285 setup_clear_cpu_cap(X86_FEATURE_SMEP);
286 clear_in_cr4(X86_CR4_SMEP);
288 set_in_cr4(X86_CR4_SMEP);
293 * Some CPU features depend on higher CPUID levels, which may not always
294 * be available due to CPUID level capping or broken virtualization
295 * software. Add those features to this table to auto-disable them.
297 struct cpuid_dependent_feature {
302 static const struct cpuid_dependent_feature __cpuinitconst
303 cpuid_dependent_features[] = {
304 { X86_FEATURE_MWAIT, 0x00000005 },
305 { X86_FEATURE_DCA, 0x00000009 },
306 { X86_FEATURE_XSAVE, 0x0000000d },
310 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
312 const struct cpuid_dependent_feature *df;
314 for (df = cpuid_dependent_features; df->feature; df++) {
316 if (!cpu_has(c, df->feature))
319 * Note: cpuid_level is set to -1 if unavailable, but
320 * extended_extended_level is set to 0 if unavailable
321 * and the legitimate extended levels are all negative
322 * when signed; hence the weird messing around with
325 if (!((s32)df->level < 0 ?
326 (u32)df->level > (u32)c->extended_cpuid_level :
327 (s32)df->level > (s32)c->cpuid_level))
330 clear_cpu_cap(c, df->feature);
335 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
336 x86_cap_flags[df->feature], df->level);
341 * Naming convention should be: <Name> [(<Codename>)]
342 * This table only is used unless init_<vendor>() below doesn't set it;
343 * in particular, if CPUID levels 0x80000002..4 are supported, this
347 /* Look up CPU names by table lookup. */
348 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
350 const struct cpu_model_info *info;
352 if (c->x86_model >= 16)
353 return NULL; /* Range check */
358 info = this_cpu->c_models;
360 while (info && info->family) {
361 if (info->family == c->x86)
362 return info->model_names[c->x86_model];
365 return NULL; /* Not found */
368 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
369 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
371 void __ref load_percpu_segment(int cpu)
373 #ifdef CONFIG_XEN_VCPU_INFO_PLACEMENT
378 adjust_boot_vcpu_info();
382 loadsegment(fs, __KERNEL_PERCPU);
386 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
388 if (HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL,
389 (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)))
393 load_stack_canary_segment();
397 * Current gdt points %fs at the "master" per-cpu area: after this,
398 * it's on the real one.
400 void switch_to_new_gdt(int cpu)
402 struct desc_ptr gdt_descr;
403 unsigned long va, frames[16];
406 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
407 gdt_descr.size = GDT_SIZE - 1;
409 for (va = gdt_descr.address, f = 0;
410 va < gdt_descr.address + gdt_descr.size;
411 va += PAGE_SIZE, f++) {
412 frames[f] = arbitrary_virt_to_mfn(va);
413 make_page_readonly((void *)va,
414 XENFEAT_writable_descriptor_tables);
416 if (HYPERVISOR_set_gdt(frames, (gdt_descr.size + 1) / 8))
419 /* Reload the per-cpu base */
421 load_percpu_segment(cpu);
424 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
426 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
431 if (c->extended_cpuid_level < 0x80000004)
434 v = (unsigned int *)c->x86_model_id;
435 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
436 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
437 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
438 c->x86_model_id[48] = 0;
441 * Intel chips right-justify this string for some dumb reason;
442 * undo that brain damage:
444 p = q = &c->x86_model_id[0];
450 while (q <= &c->x86_model_id[48])
451 *q++ = '\0'; /* Zero-pad the rest */
455 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
457 unsigned int n, dummy, ebx, ecx, edx, l2size;
459 n = c->extended_cpuid_level;
461 if (n >= 0x80000005) {
462 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
463 c->x86_cache_size = (ecx>>24) + (edx>>24);
465 /* On K8 L1 TLB is inclusive, so don't count it */
470 if (n < 0x80000006) /* Some chips just has a large L1. */
473 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
477 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
479 /* do processor-specific cache resizing */
480 if (this_cpu->c_size_cache)
481 l2size = this_cpu->c_size_cache(c, l2size);
483 /* Allow user to override all this if necessary. */
484 if (cachesize_override != -1)
485 l2size = cachesize_override;
488 return; /* Again, no L2 cache is possible */
491 c->x86_cache_size = l2size;
494 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
497 u32 eax, ebx, ecx, edx;
498 int index_msb, core_bits;
501 if (!cpu_has(c, X86_FEATURE_HT))
504 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
507 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
510 cpuid(1, &eax, &ebx, &ecx, &edx);
512 smp_num_siblings = (ebx & 0xff0000) >> 16;
514 if (smp_num_siblings == 1) {
515 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
519 if (smp_num_siblings <= 1)
522 index_msb = get_count_order(smp_num_siblings);
523 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
525 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
527 index_msb = get_count_order(smp_num_siblings);
529 core_bits = get_count_order(c->x86_max_cores);
531 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
532 ((1 << core_bits) - 1);
535 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
536 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
538 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
545 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
547 char *v = c->x86_vendor_id;
550 for (i = 0; i < X86_VENDOR_NUM; i++) {
554 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
555 (cpu_devs[i]->c_ident[1] &&
556 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
558 this_cpu = cpu_devs[i];
559 c->x86_vendor = this_cpu->c_x86_vendor;
565 "CPU: vendor_id '%s' unknown, using generic init.\n" \
566 "CPU: Your system may be unstable.\n", v);
568 c->x86_vendor = X86_VENDOR_UNKNOWN;
569 this_cpu = &default_cpu;
572 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
574 /* Get vendor name */
575 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
576 (unsigned int *)&c->x86_vendor_id[0],
577 (unsigned int *)&c->x86_vendor_id[8],
578 (unsigned int *)&c->x86_vendor_id[4]);
581 /* Intel-defined flags: level 0x00000001 */
582 if (c->cpuid_level >= 0x00000001) {
583 u32 junk, tfms, cap0, misc;
585 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
586 c->x86 = (tfms >> 8) & 0xf;
587 c->x86_model = (tfms >> 4) & 0xf;
588 c->x86_mask = tfms & 0xf;
591 c->x86 += (tfms >> 20) & 0xff;
593 c->x86_model += ((tfms >> 16) & 0xf) << 4;
595 if (cap0 & (1<<19)) {
596 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
597 c->x86_cache_alignment = c->x86_clflush_size;
602 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
607 /* Intel-defined flags: level 0x00000001 */
608 if (c->cpuid_level >= 0x00000001) {
609 u32 capability, excap;
611 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
612 c->x86_capability[0] = capability;
613 c->x86_capability[4] = excap;
616 /* Additional Intel-defined flags: level 0x00000007 */
617 if (c->cpuid_level >= 0x00000007) {
618 u32 eax, ebx, ecx, edx;
620 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
622 c->x86_capability[9] = ebx;
625 /* AMD-defined flags: level 0x80000001 */
626 xlvl = cpuid_eax(0x80000000);
627 c->extended_cpuid_level = xlvl;
629 if ((xlvl & 0xffff0000) == 0x80000000) {
630 if (xlvl >= 0x80000001) {
631 c->x86_capability[1] = cpuid_edx(0x80000001);
632 c->x86_capability[6] = cpuid_ecx(0x80000001);
636 if (c->extended_cpuid_level >= 0x80000008) {
637 u32 eax = cpuid_eax(0x80000008);
639 c->x86_virt_bits = (eax >> 8) & 0xff;
640 c->x86_phys_bits = eax & 0xff;
643 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
644 c->x86_phys_bits = 36;
647 if (c->extended_cpuid_level >= 0x80000007)
648 c->x86_power = cpuid_edx(0x80000007);
650 init_scattered_cpuid_features(c);
653 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
659 * First of all, decide if this is a 486 or higher
660 * It's a 486 if we can modify the AC flag
662 if (flag_is_changeable_p(X86_EFLAGS_AC))
667 for (i = 0; i < X86_VENDOR_NUM; i++)
668 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
669 c->x86_vendor_id[0] = 0;
670 cpu_devs[i]->c_identify(c);
671 if (c->x86_vendor_id[0]) {
680 * Do minimum CPU detection early.
681 * Fields really needed: vendor, cpuid_level, family, model, mask,
683 * The others are not touched to avoid unwanted side effects.
685 * WARNING: this function is only called on the BP. Don't add code here
686 * that is supposed to run on all CPUs.
688 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
691 c->x86_clflush_size = 64;
692 c->x86_phys_bits = 36;
693 c->x86_virt_bits = 48;
695 c->x86_clflush_size = 32;
696 c->x86_phys_bits = 32;
697 c->x86_virt_bits = 32;
699 c->x86_cache_alignment = c->x86_clflush_size;
701 memset(&c->x86_capability, 0, sizeof c->x86_capability);
702 c->extended_cpuid_level = 0;
705 identify_cpu_without_cpuid(c);
707 /* cyrix could have cpuid enabled via c_identify()*/
718 x86_xsave_setup(NULL);
721 if (this_cpu->c_early_init)
722 this_cpu->c_early_init(c);
725 filter_cpuid_features(c, false);
729 if (this_cpu->c_bsp_init)
730 this_cpu->c_bsp_init(c);
733 void __init early_cpu_init(void)
735 const struct cpu_dev *const *cdev;
738 #ifdef CONFIG_PROCESSOR_SELECT
739 printk(KERN_INFO "KERNEL supported cpus:\n");
742 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
743 const struct cpu_dev *cpudev = *cdev;
745 if (count >= X86_VENDOR_NUM)
747 cpu_devs[count] = cpudev;
750 #ifdef CONFIG_PROCESSOR_SELECT
754 for (j = 0; j < 2; j++) {
755 if (!cpudev->c_ident[j])
757 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
763 early_identify_cpu(&boot_cpu_data);
767 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
768 * unfortunately, that's not true in practice because of early VIA
769 * chips and (more importantly) broken virtualizers that are not easy
770 * to detect. In the latter case it doesn't even *fail* reliably, so
771 * probing for it doesn't even work. Disable it completely on 32-bit
772 * unless we can find a reliable way to detect all the broken cases.
773 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
775 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
778 clear_cpu_cap(c, X86_FEATURE_NOPL);
780 set_cpu_cap(c, X86_FEATURE_NOPL);
784 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
786 c->extended_cpuid_level = 0;
789 identify_cpu_without_cpuid(c);
791 /* cyrix could have cpuid enabled via c_identify()*/
802 if (c->cpuid_level >= 0x00000001) {
803 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
805 # ifdef CONFIG_X86_HT
806 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
808 c->apicid = c->initial_apicid;
811 c->phys_proc_id = c->initial_apicid;
817 get_model_name(c); /* Default name */
823 * This does the hard work of actually picking apart the CPU stuff...
825 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
829 c->loops_per_jiffy = loops_per_jiffy;
830 c->x86_cache_size = -1;
831 c->x86_vendor = X86_VENDOR_UNKNOWN;
832 c->x86_model = c->x86_mask = 0; /* So far unknown... */
833 c->x86_vendor_id[0] = '\0'; /* Unset */
834 c->x86_model_id[0] = '\0'; /* Unset */
836 c->x86_max_cores = 1;
837 c->x86_coreid_bits = 0;
840 c->x86_clflush_size = 64;
841 c->x86_phys_bits = 36;
842 c->x86_virt_bits = 48;
844 c->cpuid_level = -1; /* CPUID not detected */
845 c->x86_clflush_size = 32;
846 c->x86_phys_bits = 32;
847 c->x86_virt_bits = 32;
849 c->x86_cache_alignment = c->x86_clflush_size;
850 memset(&c->x86_capability, 0, sizeof c->x86_capability);
851 if (boot_cpu_has(X86_FEATURE_SYSCALL32))
852 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
856 if (this_cpu->c_identify)
857 this_cpu->c_identify(c);
859 /* Clear/Set all flags overriden by options, after probe */
860 for (i = 0; i < NCAPINTS; i++) {
861 c->x86_capability[i] &= ~cpu_caps_cleared[i];
862 c->x86_capability[i] |= cpu_caps_set[i];
865 #if defined(CONFIG_X86_64) && !defined(CONFIG_XEN)
866 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
870 * Vendor-specific initialization. In this section we
871 * canonicalize the feature flags, meaning if there are
872 * features a certain CPU supports which CPUID doesn't
873 * tell us, CPUID claiming incorrect flags, or other bugs,
874 * we handle them here.
876 * At the end of this section, c->x86_capability better
877 * indicate the features this CPU genuinely supports!
879 if (this_cpu->c_init)
882 /* Disable the PN if appropriate */
883 squash_the_stupid_serial_number(c);
886 * The vendor-specific functions might have changed features.
887 * Now we do "generic changes."
890 /* Filter out anything that depends on CPUID levels we don't have */
891 filter_cpuid_features(c, true);
893 /* If the model name is still unset, do table lookup. */
894 if (!c->x86_model_id[0]) {
896 p = table_lookup_model(c);
898 strcpy(c->x86_model_id, p);
901 sprintf(c->x86_model_id, "%02x/%02x",
902 c->x86, c->x86_model);
913 * Clear/Set all flags overriden by options, need do it
914 * before following smp all cpus cap AND.
916 for (i = 0; i < NCAPINTS; i++) {
917 c->x86_capability[i] &= ~cpu_caps_cleared[i];
918 c->x86_capability[i] |= cpu_caps_set[i];
922 * On SMP, boot_cpu_data holds the common feature set between
923 * all CPUs; so make sure that we indicate which features are
924 * common between the CPUs. The first time this routine gets
925 * executed, c == &boot_cpu_data.
927 if (c != &boot_cpu_data) {
928 /* AND the already accumulated flags with these */
929 for (i = 0; i < NCAPINTS; i++)
930 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
933 /* Init Machine Check Exception if available. */
936 select_idle_routine(c);
939 numa_add_cpu(smp_processor_id());
944 static void vgetcpu_set_mode(void)
946 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
947 vgetcpu_mode = VGETCPU_RDTSCP;
949 vgetcpu_mode = VGETCPU_LSL;
953 void __init identify_boot_cpu(void)
955 identify_cpu(&boot_cpu_data);
956 init_amd_e400_c1e_mask();
966 void set_perf_event_pending(void) {}
969 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
971 BUG_ON(c == &boot_cpu_data);
984 static const struct msr_range msr_range_array[] __cpuinitconst = {
985 { 0x00000000, 0x00000418},
986 { 0xc0000000, 0xc000040b},
987 { 0xc0010000, 0xc0010142},
988 { 0xc0011000, 0xc001103b},
991 static void __cpuinit __print_cpu_msr(void)
993 unsigned index_min, index_max;
998 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
999 index_min = msr_range_array[i].min;
1000 index_max = msr_range_array[i].max;
1002 for (index = index_min; index < index_max; index++) {
1003 if (rdmsrl_amd_safe(index, &val))
1005 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1010 static int show_msr __cpuinitdata;
1012 static __init int setup_show_msr(char *arg)
1016 get_option(&arg, &num);
1022 __setup("show_msr=", setup_show_msr);
1024 static __init int setup_noclflush(char *arg)
1026 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1029 __setup("noclflush", setup_noclflush);
1031 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1033 const char *vendor = NULL;
1035 if (c->x86_vendor < X86_VENDOR_NUM) {
1036 vendor = this_cpu->c_vendor;
1038 if (c->cpuid_level >= 0)
1039 vendor = c->x86_vendor_id;
1042 if (vendor && !strstr(c->x86_model_id, vendor))
1043 printk(KERN_CONT "%s ", vendor);
1045 if (c->x86_model_id[0])
1046 printk(KERN_CONT "%s", c->x86_model_id);
1048 printk(KERN_CONT "%d86", c->x86);
1050 if (c->x86_mask || c->cpuid_level >= 0)
1051 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1053 printk(KERN_CONT "\n");
1058 void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c)
1060 if (c->cpu_index < show_msr)
1064 static __init int setup_disablecpuid(char *arg)
1068 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1069 setup_clear_cpu_cap(bit);
1075 __setup("clearcpuid=", setup_disablecpuid);
1077 #ifdef CONFIG_X86_64
1078 #ifndef CONFIG_X86_NO_IDT
1079 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1080 struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1,
1081 (unsigned long) nmi_idt_table };
1084 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1085 irq_stack_union) __aligned(PAGE_SIZE);
1087 void xen_switch_pt(void)
1090 xen_pt_switch(init_level4_pgt);
1095 * The following four percpu variables are hot. Align current_task to
1096 * cacheline size such that all four fall in the same cacheline.
1098 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1100 EXPORT_PER_CPU_SYMBOL(current_task);
1102 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1103 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1104 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1106 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1107 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1109 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1111 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1113 #ifndef CONFIG_X86_NO_TSS
1115 * Special IST stacks which the CPU switches to when it calls
1116 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1117 * limit), all of them are 4K, except the debug stack which
1120 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1121 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1122 [DEBUG_STACK - 1] = DEBUG_STKSZ
1125 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1126 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1129 void __cpuinit syscall_init(void)
1133 * LSTAR and STAR live in a bit strange symbiosis.
1134 * They both write to the same internal register. STAR allows to
1135 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1137 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1138 wrmsrl(MSR_LSTAR, system_call);
1139 wrmsrl(MSR_CSTAR, ignore_sysret);
1142 #ifdef CONFIG_IA32_EMULATION
1143 syscall32_cpu_init();
1144 #elif defined(CONFIG_XEN)
1145 struct callback_register cb = {
1146 .type = CALLBACKTYPE_syscall32,
1147 .address = (unsigned long)ignore_sysret
1150 if (HYPERVISOR_callback_op(CALLBACKOP_register, &cb))
1151 pr_warning("Unable to register CSTAR stub\n");
1152 cb.type = CALLBACKTYPE_sysenter;
1153 if (HYPERVISOR_callback_op(CALLBACKOP_register, &cb))
1154 pr_warning("Unable to register SEP stub\n");
1158 /* Flags to clear on syscall */
1159 wrmsrl(MSR_SYSCALL_MASK,
1160 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1164 unsigned long kernel_eflags;
1166 #ifndef CONFIG_X86_NO_TSS
1168 * Copies of the original ist values from the tss are only accessed during
1169 * debugging, no special alignment required.
1171 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1174 #ifndef CONFIG_X86_NO_IDT
1175 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1176 DEFINE_PER_CPU(int, debug_stack_usage);
1178 int is_debug_stack(unsigned long addr)
1180 return __get_cpu_var(debug_stack_usage) ||
1181 (addr <= __get_cpu_var(debug_stack_addr) &&
1182 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1185 void debug_stack_set_zero(void)
1187 load_idt((const struct desc_ptr *)&nmi_idt_descr);
1190 void debug_stack_reset(void)
1192 load_idt((const struct desc_ptr *)&idt_descr);
1196 #else /* CONFIG_X86_64 */
1198 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1199 EXPORT_PER_CPU_SYMBOL(current_task);
1200 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1202 #ifdef CONFIG_CC_STACKPROTECTOR
1203 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1206 /* Make sure %fs and %gs are initialized properly in idle threads */
1207 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1209 memset(regs, 0, sizeof(struct pt_regs));
1210 regs->fs = __KERNEL_PERCPU;
1211 regs->gs = __KERNEL_STACK_CANARY;
1215 #endif /* CONFIG_X86_64 */
1218 * Clear all 6 debug registers:
1220 static void clear_all_debug_regs(void)
1224 for (i = 0; i < 8; i++) {
1225 /* Ignore db4, db5 */
1226 if ((i == 4) || (i == 5))
1235 * Restore debug regs if using kgdbwait and you have a kernel debugger
1236 * connection established.
1238 static void dbg_restore_debug_regs(void)
1240 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1241 arch_kgdb_ops.correct_hw_break();
1243 #else /* ! CONFIG_KGDB */
1244 #define dbg_restore_debug_regs()
1245 #endif /* ! CONFIG_KGDB */
1248 * cpu_init() initializes state that is per-CPU. Some data is already
1249 * initialized (naturally) in the bootstrap process, such as the GDT
1250 * and IDT. We reload them nevertheless, this function acts as a
1251 * 'CPU state barrier', nothing should get across.
1252 * A lot of state is already set up in PDA init for 64 bit
1254 #ifdef CONFIG_X86_64
1256 void __cpuinit cpu_init(void)
1258 #ifndef CONFIG_X86_NO_TSS
1259 struct orig_ist *oist;
1260 struct tss_struct *t;
1264 struct task_struct *me;
1267 cpu = stack_smp_processor_id();
1268 /* CPU 0 is initialised in head64.c */
1271 #ifndef CONFIG_X86_NO_TSS
1272 t = &per_cpu(init_tss, cpu);
1273 oist = &per_cpu(orig_ist, cpu);
1277 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1278 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1279 set_numa_node(early_cpu_to_node(cpu));
1284 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1285 panic("CPU#%d already initialized!\n", cpu);
1287 pr_debug("Initializing CPU#%d\n", cpu);
1289 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1292 * Initialize the per-CPU GDT with the boot GDT,
1293 * and set up the GDT descriptor:
1296 switch_to_new_gdt(cpu);
1299 #ifndef CONFIG_X86_NO_IDT
1300 load_idt((const struct desc_ptr *)&idt_descr);
1303 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1306 wrmsrl(MSR_FS_BASE, 0);
1307 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1311 #ifdef CONFIG_X86_LOCAL_APIC
1316 #ifndef CONFIG_X86_NO_TSS
1318 * set up and load the per-CPU TSS
1320 if (!oist->ist[0]) {
1321 char *estacks = per_cpu(exception_stacks, cpu);
1323 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1324 estacks += exception_stack_sizes[v];
1325 oist->ist[v] = t->x86_tss.ist[v] =
1326 (unsigned long)estacks;
1327 #ifndef CONFIG_X86_NO_IDT
1328 if (v == DEBUG_STACK-1)
1329 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1334 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1337 * <= is required because the CPU will access up to
1338 * 8 bits beyond the end of the IO permission bitmap.
1340 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1341 t->io_bitmap[i] = ~0UL;
1344 atomic_inc(&init_mm.mm_count);
1345 me->active_mm = &init_mm;
1347 enter_lazy_tlb(&init_mm, me);
1349 load_sp0(t, ¤t->thread);
1350 #ifndef CONFIG_X86_NO_TSS
1351 set_tss_desc(cpu, t);
1354 load_LDT(&init_mm.context);
1356 clear_all_debug_regs();
1357 dbg_restore_debug_regs();
1363 raw_local_save_flags(kernel_eflags);
1365 asm ("pushfq; popq %0" : "=rm" (kernel_eflags));
1366 if (raw_irqs_disabled())
1367 kernel_eflags &= ~X86_EFLAGS_IF;
1370 #ifdef CONFIG_X86_LOCAL_APIC
1378 void __cpuinit cpu_init(void)
1380 int cpu = smp_processor_id();
1381 struct task_struct *curr = current;
1382 #ifndef CONFIG_X86_NO_TSS
1383 struct tss_struct *t = &per_cpu(init_tss, cpu);
1385 struct thread_struct *thread = &curr->thread;
1387 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1388 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1393 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1395 if (cpu_has_vme || cpu_has_de)
1396 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1398 switch_to_new_gdt(cpu);
1401 * Set up and load the per-CPU TSS and LDT
1403 atomic_inc(&init_mm.mm_count);
1404 curr->active_mm = &init_mm;
1406 enter_lazy_tlb(&init_mm, curr);
1408 load_sp0(t, thread);
1410 load_LDT(&init_mm.context);
1412 #ifndef CONFIG_X86_NO_TSS
1413 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1416 #ifdef CONFIG_DOUBLEFAULT
1417 /* Set up doublefault TSS pointer in the GDT */
1418 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1421 clear_all_debug_regs();
1422 dbg_restore_debug_regs();