1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
33 #include <xen/interface/physdev.h>
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
40 static inline void *current_text_addr(void)
44 asm volatile("mov $1f, %0; 1:":"=r" (pc));
49 #ifdef CONFIG_X86_VSMP
50 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
51 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
53 # define ARCH_MIN_TASKALIGN 16
54 # define ARCH_MIN_MMSTRUCT_ALIGN 0
58 * CPU type and hardware bug flags. Kept separately for each CPU.
59 * Members of this structure are referenced in head.S, so think twice
60 * before touching them. [mj]
64 __u8 x86; /* CPU family */
65 __u8 x86_vendor; /* CPU vendor */
69 char wp_works_ok; /* It doesn't on 386's */
71 /* Problems on some 486Dx4's and old 386's: */
84 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
90 /* CPUID returned core id bits: */
93 /* Max extended CPUID function supported: */
94 __u32 extended_cpuid_level;
95 /* Maximum supported CPUID level, -1=no CPUID: */
97 __u32 x86_capability[NCAPINTS];
98 char x86_vendor_id[16];
99 char x86_model_id[64];
100 /* in KB - valid for CPUS which support this call: */
102 int x86_cache_alignment; /* In bytes */
104 unsigned long loops_per_jiffy;
106 /* cpuid returned max cores value: */
111 u16 x86_clflush_size;
113 /* number of cores as seen by the OS: */
115 /* Physical processor id: */
119 /* Compute unit id */
122 /* Index into per_cpu list: */
127 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
129 #define X86_VENDOR_INTEL 0
130 #define X86_VENDOR_CYRIX 1
131 #define X86_VENDOR_AMD 2
132 #define X86_VENDOR_UMC 3
133 #define X86_VENDOR_CENTAUR 5
134 #define X86_VENDOR_TRANSMETA 7
135 #define X86_VENDOR_NSC 8
136 #define X86_VENDOR_NUM 9
138 #define X86_VENDOR_UNKNOWN 0xff
141 * capabilities of CPUs
143 extern struct cpuinfo_x86 boot_cpu_data;
144 extern struct cpuinfo_x86 new_cpu_data;
146 extern __u32 cpu_caps_cleared[NCAPINTS];
147 extern __u32 cpu_caps_set[NCAPINTS];
150 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
151 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
153 #define cpu_info boot_cpu_data
154 #define cpu_data(cpu) boot_cpu_data
157 extern const struct seq_operations cpuinfo_op;
159 static inline int hlt_works(int cpu)
161 #if defined(CONFIG_X86_32) && !defined(CONFIG_XEN)
162 return cpu_data(cpu).hlt_works_ok;
168 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
170 extern void cpu_detect(struct cpuinfo_x86 *c);
172 extern struct pt_regs *idle_regs(struct pt_regs *);
174 extern void early_cpu_init(void);
175 extern void identify_boot_cpu(void);
176 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
177 extern void print_cpu_info(struct cpuinfo_x86 *);
178 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
179 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
180 extern unsigned short num_cache_leaves;
182 extern void detect_extended_topology(struct cpuinfo_x86 *c);
183 extern void detect_ht(struct cpuinfo_x86 *c);
185 static inline void xen_cpuid(unsigned int *eax, unsigned int *ebx,
186 unsigned int *ecx, unsigned int *edx)
188 /* ecx is often an input as well as an output. */
189 asm volatile(XEN_CPUID
194 : "0" (*eax), "2" (*ecx)
198 static inline void load_cr3(pgd_t *pgdir)
200 write_cr3(__pa(pgdir));
203 #ifndef CONFIG_X86_NO_TSS
205 /* This is the TSS defined by the hardware. */
207 unsigned short back_link, __blh;
209 unsigned short ss0, __ss0h;
211 /* ss1 caches MSR_IA32_SYSENTER_CS: */
212 unsigned short ss1, __ss1h;
214 unsigned short ss2, __ss2h;
226 unsigned short es, __esh;
227 unsigned short cs, __csh;
228 unsigned short ss, __ssh;
229 unsigned short ds, __dsh;
230 unsigned short fs, __fsh;
231 unsigned short gs, __gsh;
232 unsigned short ldt, __ldth;
233 unsigned short trace;
234 unsigned short io_bitmap_base;
236 } __attribute__((packed));
237 extern struct tss_struct doublefault_tss;
251 } __attribute__((packed)) ____cacheline_aligned;
253 #endif /* CONFIG_X86_NO_TSS */
258 #define IO_BITMAP_BITS 65536
259 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
260 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
261 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
262 #define INVALID_IO_BITMAP_OFFSET 0x8000
264 #ifndef CONFIG_X86_NO_TSS
267 * The hardware state:
269 struct x86_hw_tss x86_tss;
272 * The extra 1 is there because the CPU will access an
273 * additional byte beyond the end of the IO permission
274 * bitmap. The extra byte must be all 1 bits, and must
275 * be within the limit.
277 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
280 * .. and then another 0x100 bytes for the emergency kernel stack:
282 unsigned long stack[64];
284 } ____cacheline_aligned;
286 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
289 * Save the original ist values for checking stack pointers during debugging
292 unsigned long ist[7];
294 #endif /* CONFIG_X86_NO_TSS */
296 #define MXCSR_DEFAULT 0x1f80
298 struct i387_fsave_struct {
299 u32 cwd; /* FPU Control Word */
300 u32 swd; /* FPU Status Word */
301 u32 twd; /* FPU Tag Word */
302 u32 fip; /* FPU IP Offset */
303 u32 fcs; /* FPU IP Selector */
304 u32 foo; /* FPU Operand Pointer Offset */
305 u32 fos; /* FPU Operand Pointer Selector */
307 /* 8*10 bytes for each FP-reg = 80 bytes: */
310 /* Software status information [not touched by FSAVE ]: */
314 struct i387_fxsave_struct {
315 u16 cwd; /* Control Word */
316 u16 swd; /* Status Word */
317 u16 twd; /* Tag Word */
318 u16 fop; /* Last Instruction Opcode */
321 u64 rip; /* Instruction Pointer */
322 u64 rdp; /* Data Pointer */
325 u32 fip; /* FPU IP Offset */
326 u32 fcs; /* FPU IP Selector */
327 u32 foo; /* FPU Operand Offset */
328 u32 fos; /* FPU Operand Selector */
331 u32 mxcsr; /* MXCSR Register State */
332 u32 mxcsr_mask; /* MXCSR Mask */
334 /* 8*16 bytes for each FP-reg = 128 bytes: */
337 /* 16*16 bytes for each XMM-reg = 256 bytes: */
347 } __attribute__((aligned(16)));
349 struct i387_soft_struct {
357 /* 8*10 bytes for each FP-reg = 80 bytes: */
365 struct math_emu_info *info;
370 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
374 struct xsave_hdr_struct {
378 } __attribute__((packed));
380 struct xsave_struct {
381 struct i387_fxsave_struct i387;
382 struct xsave_hdr_struct xsave_hdr;
383 struct ymmh_struct ymmh;
384 /* new processor state extensions will go here */
385 } __attribute__ ((packed, aligned (64)));
387 union thread_xstate {
388 struct i387_fsave_struct fsave;
389 struct i387_fxsave_struct fxsave;
390 struct i387_soft_struct soft;
391 struct xsave_struct xsave;
395 unsigned int last_cpu;
396 unsigned int has_fpu;
397 union thread_xstate *state;
401 #ifndef CONFIG_X86_NO_TSS
402 DECLARE_PER_CPU(struct orig_ist, orig_ist);
405 union irq_stack_union {
406 char irq_stack[IRQ_STACK_SIZE];
408 * GCC hardcodes the stack canary as %gs:40. Since the
409 * irq_stack is the object at %gs:0, we reserve the bottom
410 * 48 bytes of the irq stack for the canary.
414 unsigned long stack_canary;
418 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
419 DECLARE_INIT_PER_CPU(irq_stack_union);
421 DECLARE_PER_CPU(char *, irq_stack_ptr);
422 DECLARE_PER_CPU(unsigned int, irq_count);
423 extern unsigned long kernel_eflags;
424 extern asmlinkage void ignore_sysret(void);
426 #ifdef CONFIG_CC_STACKPROTECTOR
428 * Make sure stack canary segment base is cached-aligned:
429 * "For Intel Atom processors, avoid non zero segment base address
430 * that is not aligned to cache line boundary at all cost."
431 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
433 struct stack_canary {
434 char __pad[20]; /* canary at %gs:20 */
435 unsigned long canary;
437 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
441 extern unsigned int xstate_size;
442 extern void free_thread_xstate(struct task_struct *);
443 extern struct kmem_cache *task_xstate_cachep;
447 struct thread_struct {
448 /* Cached TLS descriptors: */
449 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
453 unsigned long sysenter_cs;
457 unsigned short fsindex;
458 unsigned short gsindex;
467 /* Save middle states of ptrace breakpoints */
468 struct perf_event *ptrace_bps[HBP_NUM];
469 /* Debug status used for traps, single steps, etc... */
470 unsigned long debugreg6;
471 /* Keep track of the exact dr7 value set by the user */
472 unsigned long ptrace_dr7;
475 unsigned long trap_no;
476 unsigned long error_code;
477 /* floating point and extended processor state */
480 /* Virtual 86 mode info */
481 struct vm86_struct __user *vm86_info;
482 unsigned long screen_bitmap;
483 unsigned long v86flags, v86mask, saved_sp0;
484 unsigned int saved_fs, saved_gs;
486 /* IO permissions: */
487 unsigned long *io_bitmap_ptr;
489 /* Max allowed port in the bitmap, in bytes: */
490 unsigned io_bitmap_max;
493 static inline unsigned long xen_get_debugreg(int regno)
495 return HYPERVISOR_get_debugreg(regno);
498 static inline void xen_set_debugreg(int regno, unsigned long value)
500 WARN_ON(HYPERVISOR_set_debugreg(regno, value));
504 * Set IOPL bits in EFLAGS from given mask
506 static inline void xen_set_iopl_mask(unsigned mask)
508 struct physdev_set_iopl set_iopl;
510 /* Force the change at ring 0. */
511 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
512 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl));
515 #ifndef CONFIG_X86_NO_TSS
517 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
519 tss->x86_tss.sp0 = thread->sp0;
521 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
522 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
523 tss->x86_tss.ss1 = thread->sysenter_cs;
524 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
529 #define xen_load_sp0(tss, thread) do { \
530 if (HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->sp0)) \
535 #define __cpuid xen_cpuid
536 #define paravirt_enabled() 1
539 * These special macros can be used to get or set a debugging register
541 #define get_debugreg(var, register) \
542 (var) = xen_get_debugreg(register)
543 #define set_debugreg(value, register) \
544 xen_set_debugreg(register, value)
546 #define load_sp0 xen_load_sp0
548 #define set_iopl_mask xen_set_iopl_mask
551 * Save the cr4 feature set we're using (ie
552 * Pentium 4MB enable and PPro Global page
553 * enable), so that any CPU's that boot up
554 * after us can get the correct flags.
556 extern unsigned long mmu_cr4_features;
558 static inline void set_in_cr4(unsigned long mask)
562 mmu_cr4_features |= mask;
568 static inline void clear_in_cr4(unsigned long mask)
572 mmu_cr4_features &= ~mask;
584 * create a kernel thread without removing it from tasklists
586 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
588 /* Free all resources held by a thread. */
589 extern void release_thread(struct task_struct *);
591 /* Prepare to copy thread state - unlazy all lazy state */
592 extern void prepare_to_copy(struct task_struct *tsk);
594 unsigned long get_wchan(struct task_struct *p);
597 * Generic CPUID function
598 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
599 * resulting in stale register contents being returned.
601 static inline void cpuid(unsigned int op,
602 unsigned int *eax, unsigned int *ebx,
603 unsigned int *ecx, unsigned int *edx)
607 __cpuid(eax, ebx, ecx, edx);
610 /* Some CPUID calls want 'count' to be placed in ecx */
611 static inline void cpuid_count(unsigned int op, int count,
612 unsigned int *eax, unsigned int *ebx,
613 unsigned int *ecx, unsigned int *edx)
617 __cpuid(eax, ebx, ecx, edx);
621 * CPUID functions returning a single datum
623 static inline unsigned int cpuid_eax(unsigned int op)
625 unsigned int eax, ebx, ecx, edx;
627 cpuid(op, &eax, &ebx, &ecx, &edx);
632 static inline unsigned int cpuid_ebx(unsigned int op)
634 unsigned int eax, ebx, ecx, edx;
636 cpuid(op, &eax, &ebx, &ecx, &edx);
641 static inline unsigned int cpuid_ecx(unsigned int op)
643 unsigned int eax, ebx, ecx, edx;
645 cpuid(op, &eax, &ebx, &ecx, &edx);
650 static inline unsigned int cpuid_edx(unsigned int op)
652 unsigned int eax, ebx, ecx, edx;
654 cpuid(op, &eax, &ebx, &ecx, &edx);
659 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
660 static inline void rep_nop(void)
662 asm volatile("rep; nop" ::: "memory");
665 static inline void cpu_relax(void)
670 /* Stop speculative execution and prefetching of modified code. */
671 static inline void sync_core(void)
675 #if defined(CONFIG_M386) || defined(CONFIG_M486)
676 if (boot_cpu_data.x86 < 5)
677 /* There is no speculative execution.
678 * jmp is a barrier to prefetching. */
679 asm volatile("jmp 1f\n1:\n" ::: "memory");
682 /* cpuid is a barrier to speculative execution.
683 * Prefetched instructions are automatically
684 * invalidated when modified. */
685 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
686 : "ebx", "ecx", "edx", "memory");
689 static inline void __monitor(const void *eax, unsigned long ecx,
692 /* "monitor %eax, %ecx, %edx;" */
693 asm volatile(".byte 0x0f, 0x01, 0xc8;"
694 :: "a" (eax), "c" (ecx), "d"(edx));
697 static inline void __mwait(unsigned long eax, unsigned long ecx)
699 /* "mwait %eax, %ecx;" */
700 asm volatile(".byte 0x0f, 0x01, 0xc9;"
701 :: "a" (eax), "c" (ecx));
704 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
707 /* "mwait %eax, %ecx;" */
708 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
709 :: "a" (eax), "c" (ecx));
712 extern void select_idle_routine(const struct cpuinfo_x86 *c);
713 extern void init_amd_e400_c1e_mask(void);
715 extern unsigned long boot_option_idle_override;
716 extern bool amd_e400_c1e_detected;
718 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
719 IDLE_POLL, IDLE_FORCE_MWAIT};
721 extern void enable_sep_cpu(void);
722 extern int sysenter_setup(void);
724 extern void early_trap_init(void);
726 /* Defined in head.S */
727 extern struct desc_ptr early_gdt_descr;
729 extern void cpu_set_gdt(int);
730 extern void switch_to_new_gdt(int);
731 extern void load_percpu_segment(int);
732 extern void cpu_init(void);
734 static inline unsigned long get_debugctlmsr(void)
736 unsigned long debugctlmsr = 0;
738 #ifndef CONFIG_X86_DEBUGCTLMSR
739 if (boot_cpu_data.x86 < 6)
742 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
747 static inline void update_debugctlmsr(unsigned long debugctlmsr)
749 #ifndef CONFIG_X86_DEBUGCTLMSR
750 if (boot_cpu_data.x86 < 6)
753 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
757 * from system description table in BIOS. Mostly for MCA use, but
758 * others may find it useful:
760 extern unsigned int machine_id;
761 extern unsigned int machine_submodel_id;
762 extern unsigned int BIOS_revision;
764 /* Boot loader type from the setup header: */
765 extern int bootloader_type;
766 extern int bootloader_version;
768 extern char ignore_fpu_irq;
770 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
771 #define ARCH_HAS_PREFETCHW
772 #define ARCH_HAS_SPINLOCK_PREFETCH
775 # define BASE_PREFETCH ASM_NOP4
776 # define ARCH_HAS_PREFETCH
778 # define BASE_PREFETCH "prefetcht0 (%1)"
782 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
784 * It's not worth to care about 3dnow prefetches for the K6
785 * because they are microcoded there and very slow.
787 static inline void prefetch(const void *x)
789 alternative_input(BASE_PREFETCH,
796 * 3dnow prefetch to get an exclusive cache line.
797 * Useful for spinlocks to avoid one state transition in the
798 * cache coherency protocol:
800 static inline void prefetchw(const void *x)
802 alternative_input(BASE_PREFETCH,
808 static inline void spin_lock_prefetch(const void *x)
815 * User space process size: 3GB (default).
817 #define TASK_SIZE PAGE_OFFSET
818 #define TASK_SIZE_MAX TASK_SIZE
819 #define STACK_TOP TASK_SIZE
820 #define STACK_TOP_MAX STACK_TOP
822 #define INIT_THREAD { \
823 .sp0 = sizeof(init_stack) + (long)&init_stack, \
825 .sysenter_cs = __KERNEL_CS, \
826 .io_bitmap_ptr = NULL, \
830 * Note that the .io_bitmap member must be extra-big. This is because
831 * the CPU will access an additional byte beyond the end of the IO
832 * permission bitmap. The extra byte must be all 1 bits, and must
833 * be within the limit.
837 .sp0 = sizeof(init_stack) + (long)&init_stack, \
838 .ss0 = __KERNEL_DS, \
839 .ss1 = __KERNEL_CS, \
840 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
842 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
845 extern unsigned long thread_saved_pc(struct task_struct *tsk);
847 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
848 #define KSTK_TOP(info) \
850 unsigned long *__ptr = (unsigned long *)(info); \
851 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
855 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
856 * This is necessary to guarantee that the entire "struct pt_regs"
857 * is accessible even if the CPU haven't stored the SS/ESP registers
858 * on the stack (interrupt gate does not save these registers
859 * when switching to the same priv ring).
860 * Therefore beware: accessing the ss/esp fields of the
861 * "struct pt_regs" is possible, but they may contain the
862 * completely wrong values.
864 #define task_pt_regs(task) \
866 struct pt_regs *__regs__; \
867 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
873 * User space process size. 47bits minus one guard page.
875 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
877 /* This decides where the kernel will search for a free chunk of vm
878 * space during mmap's.
880 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
881 0xc0000000 : 0xFFFFe000)
883 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
884 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
885 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
886 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
888 #define STACK_TOP TASK_SIZE
889 #define STACK_TOP_MAX TASK_SIZE_MAX
891 #define INIT_THREAD { \
892 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
896 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
900 * Return saved PC of a blocked thread.
901 * What is this good for? it will be always the scheduler or ret_from_fork.
903 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
905 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
906 #endif /* CONFIG_X86_64 */
908 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
909 unsigned long new_sp);
912 * This decides where the kernel will search for a free chunk of vm
913 * space during mmap's.
915 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
917 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
918 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
920 /* Get/set a process' ability to use the timestamp counter instruction */
921 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
922 #define SET_TSC_CTL(val) set_tsc_mode((val))
924 extern int get_tsc_mode(unsigned long adr);
925 extern int set_tsc_mode(unsigned int val);
927 extern int amd_get_nb_id(int cpu);
933 static inline void get_aperfmperf(struct aperfmperf *am)
935 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
937 rdmsrl(MSR_IA32_APERF, am->aperf);
938 rdmsrl(MSR_IA32_MPERF, am->mperf);
941 #define APERFMPERF_SHIFT 10
944 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
945 struct aperfmperf *new)
947 u64 aperf = new->aperf - old->aperf;
948 u64 mperf = new->mperf - old->mperf;
949 unsigned long ratio = aperf;
951 mperf >>= APERFMPERF_SHIFT;
953 ratio = div64_u64(aperf, mperf);
959 * AMD errata checking
961 #ifdef CONFIG_CPU_SUP_AMD
962 extern const int amd_erratum_383[];
963 extern const int amd_erratum_400[];
964 extern bool cpu_has_amd_erratum(const int *);
966 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
967 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
968 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
969 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
970 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
971 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
972 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
975 #define cpu_has_amd_erratum(x) (false)
976 #endif /* CONFIG_CPU_SUP_AMD */
978 #endif /* _ASM_X86_PROCESSOR_H */