1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
34 #include <xen/interface/physdev.h>
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
40 * Based on this we disable the IP header alignment in network drivers.
42 #define NET_IP_ALIGN 0
46 * Default implementation of macro that returns current
47 * instruction pointer ("program counter").
49 static inline void *current_text_addr(void)
53 asm volatile("mov $1f, %0; 1:":"=r" (pc));
58 #ifdef CONFIG_X86_VSMP
59 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
60 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
62 # define ARCH_MIN_TASKALIGN 16
63 # define ARCH_MIN_MMSTRUCT_ALIGN 0
67 * CPU type and hardware bug flags. Kept separately for each CPU.
68 * Members of this structure are referenced in head.S, so think twice
69 * before touching them. [mj]
73 __u8 x86; /* CPU family */
74 __u8 x86_vendor; /* CPU vendor */
78 char wp_works_ok; /* It doesn't on 386's */
80 /* Problems on some 486Dx4's and old 386's: */
93 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
99 /* CPUID returned core id bits: */
100 __u8 x86_coreid_bits;
102 /* Max extended CPUID function supported: */
103 __u32 extended_cpuid_level;
104 /* Maximum supported CPUID level, -1=no CPUID: */
106 __u32 x86_capability[NCAPINTS];
107 char x86_vendor_id[16];
108 char x86_model_id[64];
109 /* in KB - valid for CPUS which support this call: */
111 int x86_cache_alignment; /* In bytes */
113 unsigned long loops_per_jiffy;
115 /* cpuid returned max cores value: */
120 u16 x86_clflush_size;
122 /* number of cores as seen by the OS: */
124 /* Physical processor id: */
128 /* Compute unit id */
131 /* Index into per_cpu list: */
136 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
138 #define X86_VENDOR_INTEL 0
139 #define X86_VENDOR_CYRIX 1
140 #define X86_VENDOR_AMD 2
141 #define X86_VENDOR_UMC 3
142 #define X86_VENDOR_CENTAUR 5
143 #define X86_VENDOR_TRANSMETA 7
144 #define X86_VENDOR_NSC 8
145 #define X86_VENDOR_NUM 9
147 #define X86_VENDOR_UNKNOWN 0xff
150 * capabilities of CPUs
152 extern struct cpuinfo_x86 boot_cpu_data;
153 extern struct cpuinfo_x86 new_cpu_data;
155 extern __u32 cpu_caps_cleared[NCAPINTS];
156 extern __u32 cpu_caps_set[NCAPINTS];
159 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
160 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
162 #define cpu_info boot_cpu_data
163 #define cpu_data(cpu) boot_cpu_data
166 extern const struct seq_operations cpuinfo_op;
168 static inline int hlt_works(int cpu)
170 #if defined(CONFIG_X86_32) && !defined(CONFIG_XEN)
171 return cpu_data(cpu).hlt_works_ok;
177 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
179 extern void cpu_detect(struct cpuinfo_x86 *c);
181 extern struct pt_regs *idle_regs(struct pt_regs *);
183 extern void early_cpu_init(void);
184 extern void identify_boot_cpu(void);
185 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
186 extern void print_cpu_info(struct cpuinfo_x86 *);
187 void print_cpu_msr(struct cpuinfo_x86 *);
188 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
189 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
190 extern unsigned short num_cache_leaves;
192 extern void detect_extended_topology(struct cpuinfo_x86 *c);
193 extern void detect_ht(struct cpuinfo_x86 *c);
195 static inline void xen_cpuid(unsigned int *eax, unsigned int *ebx,
196 unsigned int *ecx, unsigned int *edx)
198 /* ecx is often an input as well as an output. */
199 asm volatile(XEN_CPUID
204 : "0" (*eax), "2" (*ecx)
208 static inline void load_cr3(pgd_t *pgdir)
210 write_cr3(__pa(pgdir));
213 #ifndef CONFIG_X86_NO_TSS
215 /* This is the TSS defined by the hardware. */
217 unsigned short back_link, __blh;
219 unsigned short ss0, __ss0h;
221 /* ss1 caches MSR_IA32_SYSENTER_CS: */
222 unsigned short ss1, __ss1h;
224 unsigned short ss2, __ss2h;
236 unsigned short es, __esh;
237 unsigned short cs, __csh;
238 unsigned short ss, __ssh;
239 unsigned short ds, __dsh;
240 unsigned short fs, __fsh;
241 unsigned short gs, __gsh;
242 unsigned short ldt, __ldth;
243 unsigned short trace;
244 unsigned short io_bitmap_base;
246 } __attribute__((packed));
247 extern struct tss_struct doublefault_tss;
261 } __attribute__((packed)) ____cacheline_aligned;
263 #endif /* CONFIG_X86_NO_TSS */
268 #define IO_BITMAP_BITS 65536
269 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
270 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
271 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
272 #define INVALID_IO_BITMAP_OFFSET 0x8000
274 #ifndef CONFIG_X86_NO_TSS
277 * The hardware state:
279 struct x86_hw_tss x86_tss;
282 * The extra 1 is there because the CPU will access an
283 * additional byte beyond the end of the IO permission
284 * bitmap. The extra byte must be all 1 bits, and must
285 * be within the limit.
287 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
290 * .. and then another 0x100 bytes for the emergency kernel stack:
292 unsigned long stack[64];
294 } ____cacheline_aligned;
296 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
299 * Save the original ist values for checking stack pointers during debugging
302 unsigned long ist[7];
304 #endif /* CONFIG_X86_NO_TSS */
306 #define MXCSR_DEFAULT 0x1f80
308 struct i387_fsave_struct {
309 u32 cwd; /* FPU Control Word */
310 u32 swd; /* FPU Status Word */
311 u32 twd; /* FPU Tag Word */
312 u32 fip; /* FPU IP Offset */
313 u32 fcs; /* FPU IP Selector */
314 u32 foo; /* FPU Operand Pointer Offset */
315 u32 fos; /* FPU Operand Pointer Selector */
317 /* 8*10 bytes for each FP-reg = 80 bytes: */
320 /* Software status information [not touched by FSAVE ]: */
324 struct i387_fxsave_struct {
325 u16 cwd; /* Control Word */
326 u16 swd; /* Status Word */
327 u16 twd; /* Tag Word */
328 u16 fop; /* Last Instruction Opcode */
331 u64 rip; /* Instruction Pointer */
332 u64 rdp; /* Data Pointer */
335 u32 fip; /* FPU IP Offset */
336 u32 fcs; /* FPU IP Selector */
337 u32 foo; /* FPU Operand Offset */
338 u32 fos; /* FPU Operand Selector */
341 u32 mxcsr; /* MXCSR Register State */
342 u32 mxcsr_mask; /* MXCSR Mask */
344 /* 8*16 bytes for each FP-reg = 128 bytes: */
347 /* 16*16 bytes for each XMM-reg = 256 bytes: */
357 } __attribute__((aligned(16)));
359 struct i387_soft_struct {
367 /* 8*10 bytes for each FP-reg = 80 bytes: */
375 struct math_emu_info *info;
380 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
384 struct xsave_hdr_struct {
388 } __attribute__((packed));
390 struct xsave_struct {
391 struct i387_fxsave_struct i387;
392 struct xsave_hdr_struct xsave_hdr;
393 struct ymmh_struct ymmh;
394 /* new processor state extensions will go here */
395 } __attribute__ ((packed, aligned (64)));
397 union thread_xstate {
398 struct i387_fsave_struct fsave;
399 struct i387_fxsave_struct fxsave;
400 struct i387_soft_struct soft;
401 struct xsave_struct xsave;
405 unsigned int last_cpu;
406 unsigned int has_fpu;
407 union thread_xstate *state;
411 #ifndef CONFIG_X86_NO_TSS
412 DECLARE_PER_CPU(struct orig_ist, orig_ist);
415 union irq_stack_union {
416 char irq_stack[IRQ_STACK_SIZE];
418 * GCC hardcodes the stack canary as %gs:40. Since the
419 * irq_stack is the object at %gs:0, we reserve the bottom
420 * 48 bytes of the irq stack for the canary.
424 unsigned long stack_canary;
428 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
429 DECLARE_INIT_PER_CPU(irq_stack_union);
431 DECLARE_PER_CPU(char *, irq_stack_ptr);
432 DECLARE_PER_CPU(unsigned int, irq_count);
433 extern unsigned long kernel_eflags;
434 extern asmlinkage void ignore_sysret(void);
436 #ifdef CONFIG_CC_STACKPROTECTOR
438 * Make sure stack canary segment base is cached-aligned:
439 * "For Intel Atom processors, avoid non zero segment base address
440 * that is not aligned to cache line boundary at all cost."
441 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
443 struct stack_canary {
444 char __pad[20]; /* canary at %gs:20 */
445 unsigned long canary;
447 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
451 extern unsigned int xstate_size;
452 extern void free_thread_xstate(struct task_struct *);
453 extern struct kmem_cache *task_xstate_cachep;
457 struct thread_struct {
458 /* Cached TLS descriptors: */
459 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
463 unsigned long sysenter_cs;
467 unsigned short fsindex;
468 unsigned short gsindex;
477 /* Save middle states of ptrace breakpoints */
478 struct perf_event *ptrace_bps[HBP_NUM];
479 /* Debug status used for traps, single steps, etc... */
480 unsigned long debugreg6;
481 /* Keep track of the exact dr7 value set by the user */
482 unsigned long ptrace_dr7;
485 unsigned long trap_nr;
486 unsigned long error_code;
487 /* floating point and extended processor state */
490 /* Virtual 86 mode info */
491 struct vm86_struct __user *vm86_info;
492 unsigned long screen_bitmap;
493 unsigned long v86flags, v86mask, saved_sp0;
494 unsigned int saved_fs, saved_gs;
496 /* IO permissions: */
497 unsigned long *io_bitmap_ptr;
499 /* Max allowed port in the bitmap, in bytes: */
500 unsigned io_bitmap_max;
504 * Set IOPL bits in EFLAGS from given mask
506 static inline void xen_set_iopl_mask(unsigned mask)
508 struct physdev_set_iopl set_iopl;
510 /* Force the change at ring 0. */
511 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
512 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl));
515 #ifndef CONFIG_X86_NO_TSS
517 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
519 tss->x86_tss.sp0 = thread->sp0;
521 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
522 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
523 tss->x86_tss.ss1 = thread->sysenter_cs;
524 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
529 #define xen_load_sp0(tss, thread) do { \
530 if (HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->sp0)) \
535 #define __cpuid xen_cpuid
536 #define paravirt_enabled() 1
538 #define load_sp0 xen_load_sp0
540 #define set_iopl_mask xen_set_iopl_mask
543 * Save the cr4 feature set we're using (ie
544 * Pentium 4MB enable and PPro Global page
545 * enable), so that any CPU's that boot up
546 * after us can get the correct flags.
548 extern unsigned long mmu_cr4_features;
550 static inline void set_in_cr4(unsigned long mask)
554 mmu_cr4_features |= mask;
560 static inline void clear_in_cr4(unsigned long mask)
564 mmu_cr4_features &= ~mask;
576 * create a kernel thread without removing it from tasklists
578 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
580 /* Free all resources held by a thread. */
581 extern void release_thread(struct task_struct *);
583 /* Prepare to copy thread state - unlazy all lazy state */
584 extern void prepare_to_copy(struct task_struct *tsk);
586 unsigned long get_wchan(struct task_struct *p);
589 * Generic CPUID function
590 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
591 * resulting in stale register contents being returned.
593 static inline void cpuid(unsigned int op,
594 unsigned int *eax, unsigned int *ebx,
595 unsigned int *ecx, unsigned int *edx)
599 __cpuid(eax, ebx, ecx, edx);
602 /* Some CPUID calls want 'count' to be placed in ecx */
603 static inline void cpuid_count(unsigned int op, int count,
604 unsigned int *eax, unsigned int *ebx,
605 unsigned int *ecx, unsigned int *edx)
609 __cpuid(eax, ebx, ecx, edx);
613 * CPUID functions returning a single datum
615 static inline unsigned int cpuid_eax(unsigned int op)
617 unsigned int eax, ebx, ecx, edx;
619 cpuid(op, &eax, &ebx, &ecx, &edx);
624 static inline unsigned int cpuid_ebx(unsigned int op)
626 unsigned int eax, ebx, ecx, edx;
628 cpuid(op, &eax, &ebx, &ecx, &edx);
633 static inline unsigned int cpuid_ecx(unsigned int op)
635 unsigned int eax, ebx, ecx, edx;
637 cpuid(op, &eax, &ebx, &ecx, &edx);
642 static inline unsigned int cpuid_edx(unsigned int op)
644 unsigned int eax, ebx, ecx, edx;
646 cpuid(op, &eax, &ebx, &ecx, &edx);
651 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
652 static inline void rep_nop(void)
654 asm volatile("rep; nop" ::: "memory");
657 static inline void cpu_relax(void)
662 /* Stop speculative execution and prefetching of modified code. */
663 static inline void sync_core(void)
667 #if defined(CONFIG_M386) || defined(CONFIG_M486)
668 if (boot_cpu_data.x86 < 5)
669 /* There is no speculative execution.
670 * jmp is a barrier to prefetching. */
671 asm volatile("jmp 1f\n1:\n" ::: "memory");
674 /* cpuid is a barrier to speculative execution.
675 * Prefetched instructions are automatically
676 * invalidated when modified. */
677 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
678 : "ebx", "ecx", "edx", "memory");
681 static inline void __monitor(const void *eax, unsigned long ecx,
684 /* "monitor %eax, %ecx, %edx;" */
685 asm volatile(".byte 0x0f, 0x01, 0xc8;"
686 :: "a" (eax), "c" (ecx), "d"(edx));
689 static inline void __mwait(unsigned long eax, unsigned long ecx)
691 /* "mwait %eax, %ecx;" */
692 asm volatile(".byte 0x0f, 0x01, 0xc9;"
693 :: "a" (eax), "c" (ecx));
696 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
699 /* "mwait %eax, %ecx;" */
700 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
701 :: "a" (eax), "c" (ecx));
704 extern void select_idle_routine(const struct cpuinfo_x86 *c);
705 extern void init_amd_e400_c1e_mask(void);
707 extern unsigned long boot_option_idle_override;
708 extern bool amd_e400_c1e_detected;
710 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
711 IDLE_POLL, IDLE_FORCE_MWAIT};
713 extern void enable_sep_cpu(void);
714 extern int sysenter_setup(void);
716 extern void early_trap_init(void);
718 /* Defined in head.S */
719 extern struct desc_ptr early_gdt_descr;
721 extern void cpu_set_gdt(int);
722 extern void switch_to_new_gdt(int);
723 extern void load_percpu_segment(int);
724 extern void cpu_init(void);
726 static inline unsigned long get_debugctlmsr(void)
728 unsigned long debugctlmsr = 0;
730 #ifndef CONFIG_X86_DEBUGCTLMSR
731 if (boot_cpu_data.x86 < 6)
734 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
739 static inline void update_debugctlmsr(unsigned long debugctlmsr)
741 #ifndef CONFIG_X86_DEBUGCTLMSR
742 if (boot_cpu_data.x86 < 6)
745 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
749 * from system description table in BIOS. Mostly for MCA use, but
750 * others may find it useful:
752 extern unsigned int machine_id;
753 extern unsigned int machine_submodel_id;
754 extern unsigned int BIOS_revision;
756 /* Boot loader type from the setup header: */
757 extern int bootloader_type;
758 extern int bootloader_version;
760 extern char ignore_fpu_irq;
762 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
763 #define ARCH_HAS_PREFETCHW
764 #define ARCH_HAS_SPINLOCK_PREFETCH
767 # define BASE_PREFETCH ASM_NOP4
768 # define ARCH_HAS_PREFETCH
770 # define BASE_PREFETCH "prefetcht0 (%1)"
774 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
776 * It's not worth to care about 3dnow prefetches for the K6
777 * because they are microcoded there and very slow.
779 static inline void prefetch(const void *x)
781 alternative_input(BASE_PREFETCH,
788 * 3dnow prefetch to get an exclusive cache line.
789 * Useful for spinlocks to avoid one state transition in the
790 * cache coherency protocol:
792 static inline void prefetchw(const void *x)
794 alternative_input(BASE_PREFETCH,
800 static inline void spin_lock_prefetch(const void *x)
807 * User space process size: 3GB (default).
809 #define TASK_SIZE PAGE_OFFSET
810 #define TASK_SIZE_MAX TASK_SIZE
811 #define STACK_TOP TASK_SIZE
812 #define STACK_TOP_MAX STACK_TOP
814 #define INIT_THREAD { \
815 .sp0 = sizeof(init_stack) + (long)&init_stack, \
817 .sysenter_cs = __KERNEL_CS, \
818 .io_bitmap_ptr = NULL, \
822 * Note that the .io_bitmap member must be extra-big. This is because
823 * the CPU will access an additional byte beyond the end of the IO
824 * permission bitmap. The extra byte must be all 1 bits, and must
825 * be within the limit.
829 .sp0 = sizeof(init_stack) + (long)&init_stack, \
830 .ss0 = __KERNEL_DS, \
831 .ss1 = __KERNEL_CS, \
832 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
834 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
837 extern unsigned long thread_saved_pc(struct task_struct *tsk);
839 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
840 #define KSTK_TOP(info) \
842 unsigned long *__ptr = (unsigned long *)(info); \
843 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
847 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
848 * This is necessary to guarantee that the entire "struct pt_regs"
849 * is accessible even if the CPU haven't stored the SS/ESP registers
850 * on the stack (interrupt gate does not save these registers
851 * when switching to the same priv ring).
852 * Therefore beware: accessing the ss/esp fields of the
853 * "struct pt_regs" is possible, but they may contain the
854 * completely wrong values.
856 #define task_pt_regs(task) \
858 struct pt_regs *__regs__; \
859 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
865 * User space process size. 47bits minus one guard page.
867 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
869 /* This decides where the kernel will search for a free chunk of vm
870 * space during mmap's.
872 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
873 0xc0000000 : 0xFFFFe000)
875 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
876 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
877 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
878 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
880 #define STACK_TOP TASK_SIZE
881 #define STACK_TOP_MAX TASK_SIZE_MAX
883 #define INIT_THREAD { \
884 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
888 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
892 * Return saved PC of a blocked thread.
893 * What is this good for? it will be always the scheduler or ret_from_fork.
895 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
897 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
900 * User space RSP while inside the SYSCALL fast path
902 DECLARE_PER_CPU(unsigned long, old_rsp);
904 #endif /* CONFIG_X86_64 */
906 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
907 unsigned long new_sp);
910 * This decides where the kernel will search for a free chunk of vm
911 * space during mmap's.
913 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
915 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
916 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
918 /* Get/set a process' ability to use the timestamp counter instruction */
919 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
920 #define SET_TSC_CTL(val) set_tsc_mode((val))
922 extern int get_tsc_mode(unsigned long adr);
923 extern int set_tsc_mode(unsigned int val);
925 extern int amd_get_nb_id(int cpu);
931 static inline void get_aperfmperf(struct aperfmperf *am)
933 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
935 rdmsrl(MSR_IA32_APERF, am->aperf);
936 rdmsrl(MSR_IA32_MPERF, am->mperf);
939 #define APERFMPERF_SHIFT 10
942 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
943 struct aperfmperf *new)
945 u64 aperf = new->aperf - old->aperf;
946 u64 mperf = new->mperf - old->mperf;
947 unsigned long ratio = aperf;
949 mperf >>= APERFMPERF_SHIFT;
951 ratio = div64_u64(aperf, mperf);
957 * AMD errata checking
959 #ifdef CONFIG_CPU_SUP_AMD
960 extern const int amd_erratum_383[];
961 extern const int amd_erratum_400[];
962 extern bool cpu_has_amd_erratum(const int *);
964 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
965 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
966 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
967 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
968 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
969 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
970 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
973 #define cpu_has_amd_erratum(x) (false)
974 #endif /* CONFIG_CPU_SUP_AMD */
976 void cpu_idle_wait(void);
978 extern unsigned long arch_align_stack(unsigned long sp);
979 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
982 bool set_pm_idle_to_default(void);
984 void stop_this_cpu(void *dummy);
986 #endif /* _ASM_X86_PROCESSOR_H */