1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
26 #include <linux/personality.h>
27 #include <linux/cpumask.h>
28 #include <linux/cache.h>
29 #include <linux/threads.h>
30 #include <linux/math64.h>
31 #include <linux/init.h>
32 #include <xen/interface/physdev.h>
36 * Default implementation of macro that returns current
37 * instruction pointer ("program counter").
39 static inline void *current_text_addr(void)
43 asm volatile("mov $1f, %0; 1:":"=r" (pc));
48 #ifdef CONFIG_X86_VSMP
49 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
50 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
52 # define ARCH_MIN_TASKALIGN 16
53 # define ARCH_MIN_MMSTRUCT_ALIGN 0
57 * CPU type and hardware bug flags. Kept separately for each CPU.
58 * Members of this structure are referenced in head.S, so think twice
59 * before touching them. [mj]
63 __u8 x86; /* CPU family */
64 __u8 x86_vendor; /* CPU vendor */
68 char wp_works_ok; /* It doesn't on 386's */
70 /* Problems on some 486Dx4's and old 386's: */
79 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
84 /* CPUID returned core id bits: */
86 /* Max extended CPUID function supported: */
87 __u32 extended_cpuid_level;
88 /* Maximum supported CPUID level, -1=no CPUID: */
90 __u32 x86_capability[NCAPINTS];
91 char x86_vendor_id[16];
92 char x86_model_id[64];
93 /* in KB - valid for CPUS which support this call: */
95 int x86_cache_alignment; /* In bytes */
97 unsigned long loops_per_jiffy;
98 #if defined(CONFIG_SMP) && !defined(CONFIG_XEN)
99 /* cpus sharing the last level cache: */
100 cpumask_var_t llc_shared_map;
102 /* cpuid returned max cores value: */
106 u16 x86_clflush_size;
108 /* number of cores as seen by the OS: */
110 /* Physical processor id: */
114 /* Index into per_cpu list: */
117 unsigned int x86_hyper_vendor;
118 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
120 #define X86_VENDOR_INTEL 0
121 #define X86_VENDOR_CYRIX 1
122 #define X86_VENDOR_AMD 2
123 #define X86_VENDOR_UMC 3
124 #define X86_VENDOR_CENTAUR 5
125 #define X86_VENDOR_TRANSMETA 7
126 #define X86_VENDOR_NSC 8
127 #define X86_VENDOR_NUM 9
129 #define X86_VENDOR_UNKNOWN 0xff
131 #define X86_HYPER_VENDOR_NONE 0
132 #define X86_HYPER_VENDOR_VMWARE 1
133 #define X86_HYPER_VENDOR_XEN 'X'
136 * capabilities of CPUs
138 extern struct cpuinfo_x86 boot_cpu_data;
139 extern struct cpuinfo_x86 new_cpu_data;
141 extern __u32 cpu_caps_cleared[NCAPINTS];
142 extern __u32 cpu_caps_set[NCAPINTS];
145 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
146 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
147 #define current_cpu_data __get_cpu_var(cpu_info)
149 #define cpu_data(cpu) boot_cpu_data
150 #define current_cpu_data boot_cpu_data
153 extern const struct seq_operations cpuinfo_op;
155 static inline int hlt_works(int cpu)
158 return cpu_data(cpu).hlt_works_ok;
164 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
166 extern void cpu_detect(struct cpuinfo_x86 *c);
168 extern struct pt_regs *idle_regs(struct pt_regs *);
170 extern void early_cpu_init(void);
171 extern void identify_boot_cpu(void);
172 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
173 extern void print_cpu_info(struct cpuinfo_x86 *);
174 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
175 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
176 extern unsigned short num_cache_leaves;
178 extern void detect_extended_topology(struct cpuinfo_x86 *c);
179 extern void detect_ht(struct cpuinfo_x86 *c);
181 static inline void xen_cpuid(unsigned int *eax, unsigned int *ebx,
182 unsigned int *ecx, unsigned int *edx)
184 /* ecx is often an input as well as an output. */
185 asm volatile(XEN_CPUID
190 : "0" (*eax), "2" (*ecx));
193 static inline void load_cr3(pgd_t *pgdir)
195 write_cr3(__pa(pgdir));
198 #ifndef CONFIG_X86_NO_TSS
200 /* This is the TSS defined by the hardware. */
202 unsigned short back_link, __blh;
204 unsigned short ss0, __ss0h;
206 /* ss1 caches MSR_IA32_SYSENTER_CS: */
207 unsigned short ss1, __ss1h;
209 unsigned short ss2, __ss2h;
221 unsigned short es, __esh;
222 unsigned short cs, __csh;
223 unsigned short ss, __ssh;
224 unsigned short ds, __dsh;
225 unsigned short fs, __fsh;
226 unsigned short gs, __gsh;
227 unsigned short ldt, __ldth;
228 unsigned short trace;
229 unsigned short io_bitmap_base;
231 } __attribute__((packed));
232 extern struct tss_struct doublefault_tss;
246 } __attribute__((packed)) ____cacheline_aligned;
248 #endif /* CONFIG_X86_NO_TSS */
253 #define IO_BITMAP_BITS 65536
254 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
255 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
256 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
257 #define INVALID_IO_BITMAP_OFFSET 0x8000
259 #ifndef CONFIG_X86_NO_TSS
262 * The hardware state:
264 struct x86_hw_tss x86_tss;
267 * The extra 1 is there because the CPU will access an
268 * additional byte beyond the end of the IO permission
269 * bitmap. The extra byte must be all 1 bits, and must
270 * be within the limit.
272 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
275 * .. and then another 0x100 bytes for the emergency kernel stack:
277 unsigned long stack[64];
279 } ____cacheline_aligned;
281 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
284 * Save the original ist values for checking stack pointers during debugging
287 unsigned long ist[7];
289 #endif /* CONFIG_X86_NO_TSS */
291 #define MXCSR_DEFAULT 0x1f80
293 struct i387_fsave_struct {
294 u32 cwd; /* FPU Control Word */
295 u32 swd; /* FPU Status Word */
296 u32 twd; /* FPU Tag Word */
297 u32 fip; /* FPU IP Offset */
298 u32 fcs; /* FPU IP Selector */
299 u32 foo; /* FPU Operand Pointer Offset */
300 u32 fos; /* FPU Operand Pointer Selector */
302 /* 8*10 bytes for each FP-reg = 80 bytes: */
305 /* Software status information [not touched by FSAVE ]: */
309 struct i387_fxsave_struct {
310 u16 cwd; /* Control Word */
311 u16 swd; /* Status Word */
312 u16 twd; /* Tag Word */
313 u16 fop; /* Last Instruction Opcode */
316 u64 rip; /* Instruction Pointer */
317 u64 rdp; /* Data Pointer */
320 u32 fip; /* FPU IP Offset */
321 u32 fcs; /* FPU IP Selector */
322 u32 foo; /* FPU Operand Offset */
323 u32 fos; /* FPU Operand Selector */
326 u32 mxcsr; /* MXCSR Register State */
327 u32 mxcsr_mask; /* MXCSR Mask */
329 /* 8*16 bytes for each FP-reg = 128 bytes: */
332 /* 16*16 bytes for each XMM-reg = 256 bytes: */
342 } __attribute__((aligned(16)));
344 struct i387_soft_struct {
352 /* 8*10 bytes for each FP-reg = 80 bytes: */
360 struct math_emu_info *info;
365 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
369 struct xsave_hdr_struct {
373 } __attribute__((packed));
375 struct xsave_struct {
376 struct i387_fxsave_struct i387;
377 struct xsave_hdr_struct xsave_hdr;
378 struct ymmh_struct ymmh;
379 /* new processor state extensions will go here */
380 } __attribute__ ((packed, aligned (64)));
382 union thread_xstate {
383 struct i387_fsave_struct fsave;
384 struct i387_fxsave_struct fxsave;
385 struct i387_soft_struct soft;
386 struct xsave_struct xsave;
390 #ifndef CONFIG_X86_NO_TSS
391 DECLARE_PER_CPU(struct orig_ist, orig_ist);
394 union irq_stack_union {
395 char irq_stack[IRQ_STACK_SIZE];
397 * GCC hardcodes the stack canary as %gs:40. Since the
398 * irq_stack is the object at %gs:0, we reserve the bottom
399 * 48 bytes of the irq stack for the canary.
403 unsigned long stack_canary;
407 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
408 DECLARE_INIT_PER_CPU(irq_stack_union);
410 DECLARE_PER_CPU(char *, irq_stack_ptr);
411 DECLARE_PER_CPU(unsigned int, irq_count);
412 extern unsigned long kernel_eflags;
413 extern asmlinkage void ignore_sysret(void);
415 #ifdef CONFIG_CC_STACKPROTECTOR
417 * Make sure stack canary segment base is cached-aligned:
418 * "For Intel Atom processors, avoid non zero segment base address
419 * that is not aligned to cache line boundary at all cost."
420 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
422 struct stack_canary {
423 char __pad[20]; /* canary at %gs:20 */
424 unsigned long canary;
426 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
430 extern unsigned int xstate_size;
431 extern void free_thread_xstate(struct task_struct *);
432 extern struct kmem_cache *task_xstate_cachep;
436 struct thread_struct {
437 /* Cached TLS descriptors: */
438 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
442 unsigned long sysenter_cs;
446 unsigned short fsindex;
447 unsigned short gsindex;
456 /* Save middle states of ptrace breakpoints */
457 struct perf_event *ptrace_bps[HBP_NUM];
458 /* Debug status used for traps, single steps, etc... */
459 unsigned long debugreg6;
460 /* Keep track of the exact dr7 value set by the user */
461 unsigned long ptrace_dr7;
464 unsigned long trap_no;
465 unsigned long error_code;
466 /* floating point and extended processor state */
467 union thread_xstate *xstate;
469 /* Virtual 86 mode info */
470 struct vm86_struct __user *vm86_info;
471 unsigned long screen_bitmap;
472 unsigned long v86flags, v86mask, saved_sp0;
473 unsigned int saved_fs, saved_gs;
475 /* IO permissions: */
476 unsigned long *io_bitmap_ptr;
478 /* Max allowed port in the bitmap, in bytes: */
479 unsigned io_bitmap_max;
480 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
481 unsigned long debugctlmsr;
482 /* Debug Store context; see asm/ds.h */
483 struct ds_context *ds_ctx;
486 static inline unsigned long xen_get_debugreg(int regno)
488 return HYPERVISOR_get_debugreg(regno);
491 static inline void xen_set_debugreg(int regno, unsigned long value)
493 WARN_ON(HYPERVISOR_set_debugreg(regno, value));
497 * Set IOPL bits in EFLAGS from given mask
499 static inline void xen_set_iopl_mask(unsigned mask)
501 struct physdev_set_iopl set_iopl;
503 /* Force the change at ring 0. */
504 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
505 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl));
508 #ifndef CONFIG_X86_NO_TSS
510 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
512 tss->x86_tss.sp0 = thread->sp0;
514 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
515 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
516 tss->x86_tss.ss1 = thread->sysenter_cs;
517 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
522 #define xen_load_sp0(tss, thread) do { \
523 if (HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->sp0)) \
528 #define __cpuid xen_cpuid
529 #define paravirt_enabled() 0
532 * These special macros can be used to get or set a debugging register
534 #define get_debugreg(var, register) \
535 (var) = xen_get_debugreg(register)
536 #define set_debugreg(value, register) \
537 xen_set_debugreg(register, value)
539 #define load_sp0 xen_load_sp0
541 #define set_iopl_mask xen_set_iopl_mask
544 * Save the cr4 feature set we're using (ie
545 * Pentium 4MB enable and PPro Global page
546 * enable), so that any CPU's that boot up
547 * after us can get the correct flags.
549 extern unsigned long mmu_cr4_features;
551 static inline void set_in_cr4(unsigned long mask)
555 mmu_cr4_features |= mask;
561 static inline void clear_in_cr4(unsigned long mask)
565 mmu_cr4_features &= ~mask;
577 * create a kernel thread without removing it from tasklists
579 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
581 /* Free all resources held by a thread. */
582 extern void release_thread(struct task_struct *);
584 /* Prepare to copy thread state - unlazy all lazy state */
585 extern void prepare_to_copy(struct task_struct *tsk);
587 unsigned long get_wchan(struct task_struct *p);
590 * Generic CPUID function
591 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
592 * resulting in stale register contents being returned.
594 static inline void cpuid(unsigned int op,
595 unsigned int *eax, unsigned int *ebx,
596 unsigned int *ecx, unsigned int *edx)
600 __cpuid(eax, ebx, ecx, edx);
603 /* Some CPUID calls want 'count' to be placed in ecx */
604 static inline void cpuid_count(unsigned int op, int count,
605 unsigned int *eax, unsigned int *ebx,
606 unsigned int *ecx, unsigned int *edx)
610 __cpuid(eax, ebx, ecx, edx);
614 * CPUID functions returning a single datum
616 static inline unsigned int cpuid_eax(unsigned int op)
618 unsigned int eax, ebx, ecx, edx;
620 cpuid(op, &eax, &ebx, &ecx, &edx);
625 static inline unsigned int cpuid_ebx(unsigned int op)
627 unsigned int eax, ebx, ecx, edx;
629 cpuid(op, &eax, &ebx, &ecx, &edx);
634 static inline unsigned int cpuid_ecx(unsigned int op)
636 unsigned int eax, ebx, ecx, edx;
638 cpuid(op, &eax, &ebx, &ecx, &edx);
643 static inline unsigned int cpuid_edx(unsigned int op)
645 unsigned int eax, ebx, ecx, edx;
647 cpuid(op, &eax, &ebx, &ecx, &edx);
652 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
653 static inline void rep_nop(void)
655 asm volatile("rep; nop" ::: "memory");
658 static inline void cpu_relax(void)
663 /* Stop speculative execution and prefetching of modified code. */
664 static inline void sync_core(void)
668 #if defined(CONFIG_M386) || defined(CONFIG_M486)
669 if (boot_cpu_data.x86 < 5)
670 /* There is no speculative execution.
671 * jmp is a barrier to prefetching. */
672 asm volatile("jmp 1f\n1:\n" ::: "memory");
675 /* cpuid is a barrier to speculative execution.
676 * Prefetched instructions are automatically
677 * invalidated when modified. */
678 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
679 : "ebx", "ecx", "edx", "memory");
682 static inline void __monitor(const void *eax, unsigned long ecx,
685 /* "monitor %eax, %ecx, %edx;" */
686 asm volatile(".byte 0x0f, 0x01, 0xc8;"
687 :: "a" (eax), "c" (ecx), "d"(edx));
690 static inline void __mwait(unsigned long eax, unsigned long ecx)
692 /* "mwait %eax, %ecx;" */
693 asm volatile(".byte 0x0f, 0x01, 0xc9;"
694 :: "a" (eax), "c" (ecx));
697 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
700 /* "mwait %eax, %ecx;" */
701 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
702 :: "a" (eax), "c" (ecx));
705 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
707 extern void select_idle_routine(const struct cpuinfo_x86 *c);
708 extern void init_c1e_mask(void);
710 extern unsigned long boot_option_idle_override;
711 extern unsigned long idle_halt;
712 extern unsigned long idle_nomwait;
716 * on systems with caches, caches must be flashed as the absolute
717 * last instruction before going into a suspended halt. Otherwise,
718 * dirty data can linger in the cache and become stale on resume,
719 * leading to strange errors.
721 * perform a variety of operations to guarantee that the compiler
722 * will not reorder instructions. wbinvd itself is serializing
723 * so the processor will not reorder.
725 * Systems without cache can just go into halt.
727 static inline void wbinvd_halt(void)
730 /* check for clflush to determine if wbinvd is legal */
732 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
739 extern void enable_sep_cpu(void);
740 extern int sysenter_setup(void);
742 /* Defined in head.S */
743 extern struct desc_ptr early_gdt_descr;
745 extern void cpu_set_gdt(int);
746 extern void switch_to_new_gdt(int);
747 extern void load_percpu_segment(int);
748 extern void cpu_init(void);
750 static inline unsigned long get_debugctlmsr(void)
752 unsigned long debugctlmsr = 0;
754 #ifndef CONFIG_X86_DEBUGCTLMSR
755 if (boot_cpu_data.x86 < 6)
758 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
763 static inline unsigned long get_debugctlmsr_on_cpu(int cpu)
768 #ifndef CONFIG_X86_DEBUGCTLMSR
769 if (boot_cpu_data.x86 < 6)
772 rdmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &val1, &val2);
773 debugctlmsr = val1 | ((u64)val2 << 32);
778 static inline void update_debugctlmsr(unsigned long debugctlmsr)
780 #ifndef CONFIG_X86_DEBUGCTLMSR
781 if (boot_cpu_data.x86 < 6)
784 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
787 static inline void update_debugctlmsr_on_cpu(int cpu,
788 unsigned long debugctlmsr)
790 #ifndef CONFIG_X86_DEBUGCTLMSR
791 if (boot_cpu_data.x86 < 6)
794 wrmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,
795 (u32)((u64)debugctlmsr),
796 (u32)((u64)debugctlmsr >> 32));
800 * from system description table in BIOS. Mostly for MCA use, but
801 * others may find it useful:
803 extern unsigned int machine_id;
804 extern unsigned int machine_submodel_id;
805 extern unsigned int BIOS_revision;
807 /* Boot loader type from the setup header: */
808 extern int bootloader_type;
809 extern int bootloader_version;
811 extern char ignore_fpu_irq;
813 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
814 #define ARCH_HAS_PREFETCHW
815 #define ARCH_HAS_SPINLOCK_PREFETCH
818 # define BASE_PREFETCH ASM_NOP4
819 # define ARCH_HAS_PREFETCH
821 # define BASE_PREFETCH "prefetcht0 (%1)"
825 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
827 * It's not worth to care about 3dnow prefetches for the K6
828 * because they are microcoded there and very slow.
830 static inline void prefetch(const void *x)
832 alternative_input(BASE_PREFETCH,
839 * 3dnow prefetch to get an exclusive cache line.
840 * Useful for spinlocks to avoid one state transition in the
841 * cache coherency protocol:
843 static inline void prefetchw(const void *x)
845 alternative_input(BASE_PREFETCH,
851 static inline void spin_lock_prefetch(const void *x)
858 * User space process size: 3GB (default).
860 #define TASK_SIZE PAGE_OFFSET
861 #define TASK_SIZE_MAX TASK_SIZE
862 #define STACK_TOP TASK_SIZE
863 #define STACK_TOP_MAX STACK_TOP
865 #define INIT_THREAD { \
866 .sp0 = sizeof(init_stack) + (long)&init_stack, \
868 .sysenter_cs = __KERNEL_CS, \
869 .io_bitmap_ptr = NULL, \
873 * Note that the .io_bitmap member must be extra-big. This is because
874 * the CPU will access an additional byte beyond the end of the IO
875 * permission bitmap. The extra byte must be all 1 bits, and must
876 * be within the limit.
880 .sp0 = sizeof(init_stack) + (long)&init_stack, \
881 .ss0 = __KERNEL_DS, \
882 .ss1 = __KERNEL_CS, \
883 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
885 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
888 extern unsigned long thread_saved_pc(struct task_struct *tsk);
890 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
891 #define KSTK_TOP(info) \
893 unsigned long *__ptr = (unsigned long *)(info); \
894 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
898 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
899 * This is necessary to guarantee that the entire "struct pt_regs"
900 * is accessable even if the CPU haven't stored the SS/ESP registers
901 * on the stack (interrupt gate does not save these registers
902 * when switching to the same priv ring).
903 * Therefore beware: accessing the ss/esp fields of the
904 * "struct pt_regs" is possible, but they may contain the
905 * completely wrong values.
907 #define task_pt_regs(task) \
909 struct pt_regs *__regs__; \
910 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
916 * User space process size. 47bits minus one guard page.
918 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
920 /* This decides where the kernel will search for a free chunk of vm
921 * space during mmap's.
923 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
924 0xc0000000 : 0xFFFFe000)
926 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
927 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
928 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
929 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
931 #define STACK_TOP TASK_SIZE
932 #define STACK_TOP_MAX TASK_SIZE_MAX
934 #define INIT_THREAD { \
935 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
939 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
943 * Return saved PC of a blocked thread.
944 * What is this good for? it will be always the scheduler or ret_from_fork.
946 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
948 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
949 #endif /* CONFIG_X86_64 */
951 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
952 unsigned long new_sp);
955 * This decides where the kernel will search for a free chunk of vm
956 * space during mmap's.
958 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
960 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
961 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
963 /* Get/set a process' ability to use the timestamp counter instruction */
964 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
965 #define SET_TSC_CTL(val) set_tsc_mode((val))
967 extern int get_tsc_mode(unsigned long adr);
968 extern int set_tsc_mode(unsigned int val);
970 extern int amd_get_nb_id(int cpu);
976 static inline void get_aperfmperf(struct aperfmperf *am)
978 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
980 rdmsrl(MSR_IA32_APERF, am->aperf);
981 rdmsrl(MSR_IA32_MPERF, am->mperf);
984 #define APERFMPERF_SHIFT 10
987 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
988 struct aperfmperf *new)
990 u64 aperf = new->aperf - old->aperf;
991 u64 mperf = new->mperf - old->mperf;
992 unsigned long ratio = aperf;
994 mperf >>= APERFMPERF_SHIFT;
996 ratio = div64_u64(aperf, mperf);
1001 #endif /* _ASM_X86_PROCESSOR_H */