2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
48 #include "../suncore.h"
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60 static struct uart_driver serial8250_reg;
62 static int serial_index(struct uart_port *port)
64 return (serial8250_reg.minor - 64) + port->line;
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
79 #define DEBUG_INTR(fmt...) printk(fmt)
81 #define DEBUG_INTR(fmt...) do { } while (0)
84 #define PASS_LIMIT 512
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
94 #define is_real_interrupt(irq) ((irq) != 0)
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
103 #define arch_8250_sysrq_via_ctrl_o(a,b) 0
106 * HUB6 is always on. This will be removed once the header
107 * files have been cleaned.
109 #define CONFIG_HUB6 1
111 #include <asm/serial.h>
113 * SERIAL_PORT_DFNS tells us about built-in ports that have no
114 * standard enumeration mechanism. Platforms that can find all
115 * serial ports via mechanisms like ACPI or PCI need not supply it.
117 #ifndef SERIAL_PORT_DFNS
118 #define SERIAL_PORT_DFNS
121 static const struct old_serial_port old_serial_port[] = {
122 SERIAL_PORT_DFNS /* defined in asm/serial.h */
125 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
127 #ifdef CONFIG_SERIAL_8250_RSA
129 #define PORT_RSA_MAX 4
130 static unsigned long probe_rsa[PORT_RSA_MAX];
131 static unsigned int probe_rsa_count;
132 #endif /* CONFIG_SERIAL_8250_RSA */
135 struct hlist_node node;
137 spinlock_t lock; /* Protects list not the hash */
138 struct list_head *head;
141 #define NR_IRQ_HASH 32 /* Can be adjusted later */
142 static struct hlist_head irq_lists[NR_IRQ_HASH];
143 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
146 * Here we define the default xmit fifo size used for each type of UART.
148 static const struct serial8250_config uart_config[] = {
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
185 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
201 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
209 .name = "16C950/954",
212 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
213 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
214 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
220 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
228 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
229 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
236 .flags = UART_CAP_FIFO,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO | UART_NATSEMI,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
256 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
257 .flags = UART_CAP_FIFO,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
264 .flags = UART_CAP_FIFO,
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
271 .flags = UART_CAP_FIFO | UART_CAP_AFE,
277 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
278 .flags = UART_CAP_FIFO | UART_CAP_AFE,
284 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
286 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
292 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
293 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
297 #if defined(CONFIG_MIPS_ALCHEMY)
299 /* Au1x00 UART hardware has a weird register layout */
300 static const u8 au_io_in_map[] = {
310 static const u8 au_io_out_map[] = {
318 /* sane hardware needs no mapping */
319 static inline int map_8250_in_reg(struct uart_port *p, int offset)
321 if (p->iotype != UPIO_AU)
323 return au_io_in_map[offset];
326 static inline int map_8250_out_reg(struct uart_port *p, int offset)
328 if (p->iotype != UPIO_AU)
330 return au_io_out_map[offset];
333 #elif defined(CONFIG_SERIAL_8250_RM9K)
357 static inline int map_8250_in_reg(struct uart_port *p, int offset)
359 if (p->iotype != UPIO_RM9000)
361 return regmap_in[offset];
364 static inline int map_8250_out_reg(struct uart_port *p, int offset)
366 if (p->iotype != UPIO_RM9000)
368 return regmap_out[offset];
373 /* sane hardware needs no mapping */
374 #define map_8250_in_reg(up, offset) (offset)
375 #define map_8250_out_reg(up, offset) (offset)
379 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
381 offset = map_8250_in_reg(p, offset) << p->regshift;
382 outb(p->hub6 - 1 + offset, p->iobase);
383 return inb(p->iobase + 1);
386 static void hub6_serial_out(struct uart_port *p, int offset, int value)
388 offset = map_8250_out_reg(p, offset) << p->regshift;
389 outb(p->hub6 - 1 + offset, p->iobase);
390 outb(value, p->iobase + 1);
393 static unsigned int mem_serial_in(struct uart_port *p, int offset)
395 offset = map_8250_in_reg(p, offset) << p->regshift;
396 return readb(p->membase + offset);
399 static void mem_serial_out(struct uart_port *p, int offset, int value)
401 offset = map_8250_out_reg(p, offset) << p->regshift;
402 writeb(value, p->membase + offset);
405 static void mem32_serial_out(struct uart_port *p, int offset, int value)
407 offset = map_8250_out_reg(p, offset) << p->regshift;
408 writel(value, p->membase + offset);
411 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
413 offset = map_8250_in_reg(p, offset) << p->regshift;
414 return readl(p->membase + offset);
417 static unsigned int au_serial_in(struct uart_port *p, int offset)
419 offset = map_8250_in_reg(p, offset) << p->regshift;
420 return __raw_readl(p->membase + offset);
423 static void au_serial_out(struct uart_port *p, int offset, int value)
425 offset = map_8250_out_reg(p, offset) << p->regshift;
426 __raw_writel(value, p->membase + offset);
429 static unsigned int io_serial_in(struct uart_port *p, int offset)
431 offset = map_8250_in_reg(p, offset) << p->regshift;
432 return inb(p->iobase + offset);
435 static void io_serial_out(struct uart_port *p, int offset, int value)
437 offset = map_8250_out_reg(p, offset) << p->regshift;
438 outb(value, p->iobase + offset);
441 static int serial8250_default_handle_irq(struct uart_port *port);
443 static void set_io_from_upio(struct uart_port *p)
445 struct uart_8250_port *up =
446 container_of(p, struct uart_8250_port, port);
449 p->serial_in = hub6_serial_in;
450 p->serial_out = hub6_serial_out;
454 p->serial_in = mem_serial_in;
455 p->serial_out = mem_serial_out;
460 p->serial_in = mem32_serial_in;
461 p->serial_out = mem32_serial_out;
465 p->serial_in = au_serial_in;
466 p->serial_out = au_serial_out;
470 p->serial_in = io_serial_in;
471 p->serial_out = io_serial_out;
474 /* Remember loaded iotype */
475 up->cur_iotype = p->iotype;
476 p->handle_irq = serial8250_default_handle_irq;
480 serial_out_sync(struct uart_8250_port *up, int offset, int value)
482 struct uart_port *p = &up->port;
487 p->serial_out(p, offset, value);
488 p->serial_in(p, UART_LCR); /* safe, no side-effects */
491 p->serial_out(p, offset, value);
495 #define serial_in(up, offset) \
496 (up->port.serial_in(&(up)->port, (offset)))
497 #define serial_out(up, offset, value) \
498 (up->port.serial_out(&(up)->port, (offset), (value)))
500 * We used to support using pause I/O for certain machines. We
501 * haven't supported this for a while, but just in case it's badly
502 * needed for certain old 386 machines, I've left these #define's
505 #define serial_inp(up, offset) serial_in(up, offset)
506 #define serial_outp(up, offset, value) serial_out(up, offset, value)
508 /* Uart divisor latch read */
509 static inline int _serial_dl_read(struct uart_8250_port *up)
511 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
514 /* Uart divisor latch write */
515 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
517 serial_outp(up, UART_DLL, value & 0xff);
518 serial_outp(up, UART_DLM, value >> 8 & 0xff);
521 #if defined(CONFIG_MIPS_ALCHEMY)
522 /* Au1x00 haven't got a standard divisor latch */
523 static int serial_dl_read(struct uart_8250_port *up)
525 if (up->port.iotype == UPIO_AU)
526 return __raw_readl(up->port.membase + 0x28);
528 return _serial_dl_read(up);
531 static void serial_dl_write(struct uart_8250_port *up, int value)
533 if (up->port.iotype == UPIO_AU)
534 __raw_writel(value, up->port.membase + 0x28);
536 _serial_dl_write(up, value);
538 #elif defined(CONFIG_SERIAL_8250_RM9K)
539 static int serial_dl_read(struct uart_8250_port *up)
541 return (up->port.iotype == UPIO_RM9000) ?
542 (((__raw_readl(up->port.membase + 0x10) << 8) |
543 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
547 static void serial_dl_write(struct uart_8250_port *up, int value)
549 if (up->port.iotype == UPIO_RM9000) {
550 __raw_writel(value, up->port.membase + 0x08);
551 __raw_writel(value >> 8, up->port.membase + 0x10);
553 _serial_dl_write(up, value);
557 #define serial_dl_read(up) _serial_dl_read(up)
558 #define serial_dl_write(up, value) _serial_dl_write(up, value)
564 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
566 serial_out(up, UART_SCR, offset);
567 serial_out(up, UART_ICR, value);
570 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
574 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
575 serial_out(up, UART_SCR, offset);
576 value = serial_in(up, UART_ICR);
577 serial_icr_write(up, UART_ACR, up->acr);
585 static void serial8250_clear_fifos(struct uart_8250_port *p)
587 if (p->capabilities & UART_CAP_FIFO) {
588 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
589 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
590 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
591 serial_outp(p, UART_FCR, 0);
596 * IER sleep support. UARTs which have EFRs need the "extended
597 * capability" bit enabled. Note that on XR16C850s, we need to
598 * reset LCR to write to IER.
600 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
602 if (p->capabilities & UART_CAP_SLEEP) {
603 if (p->capabilities & UART_CAP_EFR) {
604 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
605 serial_outp(p, UART_EFR, UART_EFR_ECB);
606 serial_outp(p, UART_LCR, 0);
608 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
609 if (p->capabilities & UART_CAP_EFR) {
610 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
611 serial_outp(p, UART_EFR, 0);
612 serial_outp(p, UART_LCR, 0);
617 #ifdef CONFIG_SERIAL_8250_RSA
619 * Attempts to turn on the RSA FIFO. Returns zero on failure.
620 * We set the port uart clock rate if we succeed.
622 static int __enable_rsa(struct uart_8250_port *up)
627 mode = serial_inp(up, UART_RSA_MSR);
628 result = mode & UART_RSA_MSR_FIFO;
631 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
632 mode = serial_inp(up, UART_RSA_MSR);
633 result = mode & UART_RSA_MSR_FIFO;
637 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
642 static void enable_rsa(struct uart_8250_port *up)
644 if (up->port.type == PORT_RSA) {
645 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
646 spin_lock_irq(&up->port.lock);
648 spin_unlock_irq(&up->port.lock);
650 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
651 serial_outp(up, UART_RSA_FRR, 0);
656 * Attempts to turn off the RSA FIFO. Returns zero on failure.
657 * It is unknown why interrupts were disabled in here. However,
658 * the caller is expected to preserve this behaviour by grabbing
659 * the spinlock before calling this function.
661 static void disable_rsa(struct uart_8250_port *up)
666 if (up->port.type == PORT_RSA &&
667 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
668 spin_lock_irq(&up->port.lock);
670 mode = serial_inp(up, UART_RSA_MSR);
671 result = !(mode & UART_RSA_MSR_FIFO);
674 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
675 mode = serial_inp(up, UART_RSA_MSR);
676 result = !(mode & UART_RSA_MSR_FIFO);
680 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
681 spin_unlock_irq(&up->port.lock);
684 #endif /* CONFIG_SERIAL_8250_RSA */
687 * This is a quickie test to see how big the FIFO is.
688 * It doesn't work at all the time, more's the pity.
690 static int size_fifo(struct uart_8250_port *up)
692 unsigned char old_fcr, old_mcr, old_lcr;
693 unsigned short old_dl;
696 old_lcr = serial_inp(up, UART_LCR);
697 serial_outp(up, UART_LCR, 0);
698 old_fcr = serial_inp(up, UART_FCR);
699 old_mcr = serial_inp(up, UART_MCR);
700 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
701 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
702 serial_outp(up, UART_MCR, UART_MCR_LOOP);
703 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
704 old_dl = serial_dl_read(up);
705 serial_dl_write(up, 0x0001);
706 serial_outp(up, UART_LCR, 0x03);
707 for (count = 0; count < 256; count++)
708 serial_outp(up, UART_TX, count);
709 mdelay(20);/* FIXME - schedule_timeout */
710 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
711 (count < 256); count++)
712 serial_inp(up, UART_RX);
713 serial_outp(up, UART_FCR, old_fcr);
714 serial_outp(up, UART_MCR, old_mcr);
715 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
716 serial_dl_write(up, old_dl);
717 serial_outp(up, UART_LCR, old_lcr);
723 * Read UART ID using the divisor method - set DLL and DLM to zero
724 * and the revision will be in DLL and device type in DLM. We
725 * preserve the device state across this.
727 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
729 unsigned char old_dll, old_dlm, old_lcr;
732 old_lcr = serial_inp(p, UART_LCR);
733 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
735 old_dll = serial_inp(p, UART_DLL);
736 old_dlm = serial_inp(p, UART_DLM);
738 serial_outp(p, UART_DLL, 0);
739 serial_outp(p, UART_DLM, 0);
741 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
743 serial_outp(p, UART_DLL, old_dll);
744 serial_outp(p, UART_DLM, old_dlm);
745 serial_outp(p, UART_LCR, old_lcr);
751 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
752 * When this function is called we know it is at least a StarTech
753 * 16650 V2, but it might be one of several StarTech UARTs, or one of
754 * its clones. (We treat the broken original StarTech 16650 V1 as a
755 * 16550, and why not? Startech doesn't seem to even acknowledge its
758 * What evil have men's minds wrought...
760 static void autoconfig_has_efr(struct uart_8250_port *up)
762 unsigned int id1, id2, id3, rev;
765 * Everything with an EFR has SLEEP
767 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
770 * First we check to see if it's an Oxford Semiconductor UART.
772 * If we have to do this here because some non-National
773 * Semiconductor clone chips lock up if you try writing to the
774 * LSR register (which serial_icr_read does)
778 * Check for Oxford Semiconductor 16C950.
780 * EFR [4] must be set else this test fails.
782 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
783 * claims that it's needed for 952 dual UART's (which are not
784 * recommended for new designs).
787 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
788 serial_out(up, UART_EFR, UART_EFR_ECB);
789 serial_out(up, UART_LCR, 0x00);
790 id1 = serial_icr_read(up, UART_ID1);
791 id2 = serial_icr_read(up, UART_ID2);
792 id3 = serial_icr_read(up, UART_ID3);
793 rev = serial_icr_read(up, UART_REV);
795 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
797 if (id1 == 0x16 && id2 == 0xC9 &&
798 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
799 up->port.type = PORT_16C950;
802 * Enable work around for the Oxford Semiconductor 952 rev B
803 * chip which causes it to seriously miscalculate baud rates
806 if (id3 == 0x52 && rev == 0x01)
807 up->bugs |= UART_BUG_QUOT;
812 * We check for a XR16C850 by setting DLL and DLM to 0, and then
813 * reading back DLL and DLM. The chip type depends on the DLM
815 * 0x10 - XR16C850 and the DLL contains the chip revision.
819 id1 = autoconfig_read_divisor_id(up);
820 DEBUG_AUTOCONF("850id=%04x ", id1);
823 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
824 up->port.type = PORT_16850;
829 * It wasn't an XR16C850.
831 * We distinguish between the '654 and the '650 by counting
832 * how many bytes are in the FIFO. I'm using this for now,
833 * since that's the technique that was sent to me in the
834 * serial driver update, but I'm not convinced this works.
835 * I've had problems doing this in the past. -TYT
837 if (size_fifo(up) == 64)
838 up->port.type = PORT_16654;
840 up->port.type = PORT_16650V2;
844 * We detected a chip without a FIFO. Only two fall into
845 * this category - the original 8250 and the 16450. The
846 * 16450 has a scratch register (accessible with LCR=0)
848 static void autoconfig_8250(struct uart_8250_port *up)
850 unsigned char scratch, status1, status2;
852 up->port.type = PORT_8250;
854 scratch = serial_in(up, UART_SCR);
855 serial_outp(up, UART_SCR, 0xa5);
856 status1 = serial_in(up, UART_SCR);
857 serial_outp(up, UART_SCR, 0x5a);
858 status2 = serial_in(up, UART_SCR);
859 serial_outp(up, UART_SCR, scratch);
861 if (status1 == 0xa5 && status2 == 0x5a)
862 up->port.type = PORT_16450;
865 static int broken_efr(struct uart_8250_port *up)
868 * Exar ST16C2550 "A2" devices incorrectly detect as
869 * having an EFR, and report an ID of 0x0201. See
870 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
872 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
878 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
880 unsigned char status;
882 status = serial_in(up, 0x04); /* EXCR2 */
883 #define PRESL(x) ((x) & 0x30)
884 if (PRESL(status) == 0x10) {
885 /* already in high speed mode */
888 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
889 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
890 serial_outp(up, 0x04, status);
896 * We know that the chip has FIFOs. Does it have an EFR? The
897 * EFR is located in the same register position as the IIR and
898 * we know the top two bits of the IIR are currently set. The
899 * EFR should contain zero. Try to read the EFR.
901 static void autoconfig_16550a(struct uart_8250_port *up)
903 unsigned char status1, status2;
904 unsigned int iersave;
906 up->port.type = PORT_16550A;
907 up->capabilities |= UART_CAP_FIFO;
910 * Check for presence of the EFR when DLAB is set.
911 * Only ST16C650V1 UARTs pass this test.
913 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
914 if (serial_in(up, UART_EFR) == 0) {
915 serial_outp(up, UART_EFR, 0xA8);
916 if (serial_in(up, UART_EFR) != 0) {
917 DEBUG_AUTOCONF("EFRv1 ");
918 up->port.type = PORT_16650;
919 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
921 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
923 serial_outp(up, UART_EFR, 0);
928 * Maybe it requires 0xbf to be written to the LCR.
929 * (other ST16C650V2 UARTs, TI16C752A, etc)
931 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
932 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
933 DEBUG_AUTOCONF("EFRv2 ");
934 autoconfig_has_efr(up);
939 * Check for a National Semiconductor SuperIO chip.
940 * Attempt to switch to bank 2, read the value of the LOOP bit
941 * from EXCR1. Switch back to bank 0, change it in MCR. Then
942 * switch back to bank 2, read it from EXCR1 again and check
943 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
945 serial_outp(up, UART_LCR, 0);
946 status1 = serial_in(up, UART_MCR);
947 serial_outp(up, UART_LCR, 0xE0);
948 status2 = serial_in(up, 0x02); /* EXCR1 */
950 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
951 serial_outp(up, UART_LCR, 0);
952 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
953 serial_outp(up, UART_LCR, 0xE0);
954 status2 = serial_in(up, 0x02); /* EXCR1 */
955 serial_outp(up, UART_LCR, 0);
956 serial_outp(up, UART_MCR, status1);
958 if ((status2 ^ status1) & UART_MCR_LOOP) {
961 serial_outp(up, UART_LCR, 0xE0);
963 quot = serial_dl_read(up);
966 if (ns16550a_goto_highspeed(up))
967 serial_dl_write(up, quot);
969 serial_outp(up, UART_LCR, 0);
971 up->port.uartclk = 921600*16;
972 up->port.type = PORT_NS16550A;
973 up->capabilities |= UART_NATSEMI;
979 * No EFR. Try to detect a TI16750, which only sets bit 5 of
980 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
981 * Try setting it with and without DLAB set. Cheap clones
982 * set bit 5 without DLAB set.
984 serial_outp(up, UART_LCR, 0);
985 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
986 status1 = serial_in(up, UART_IIR) >> 5;
987 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
988 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
989 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
990 status2 = serial_in(up, UART_IIR) >> 5;
991 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
992 serial_outp(up, UART_LCR, 0);
994 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
996 if (status1 == 6 && status2 == 7) {
997 up->port.type = PORT_16750;
998 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1003 * Try writing and reading the UART_IER_UUE bit (b6).
1004 * If it works, this is probably one of the Xscale platform's
1006 * We're going to explicitly set the UUE bit to 0 before
1007 * trying to write and read a 1 just to make sure it's not
1008 * already a 1 and maybe locked there before we even start start.
1010 iersave = serial_in(up, UART_IER);
1011 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1012 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1014 * OK it's in a known zero state, try writing and reading
1015 * without disturbing the current state of the other bits.
1017 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1018 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1021 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1023 DEBUG_AUTOCONF("Xscale ");
1024 up->port.type = PORT_XSCALE;
1025 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1030 * If we got here we couldn't force the IER_UUE bit to 0.
1031 * Log it and continue.
1033 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1035 serial_outp(up, UART_IER, iersave);
1038 * Exar uarts have EFR in a weird location
1040 if (up->port.flags & UPF_EXAR_EFR) {
1041 up->port.type = PORT_XR17D15X;
1042 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1046 * We distinguish between 16550A and U6 16550A by counting
1047 * how many bytes are in the FIFO.
1049 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1050 up->port.type = PORT_U6_16550A;
1051 up->capabilities |= UART_CAP_AFE;
1056 * This routine is called by rs_init() to initialize a specific serial
1057 * port. It determines what type of UART chip this serial port is
1058 * using: 8250, 16450, 16550, 16550A. The important question is
1059 * whether or not this UART is a 16550A or not, since this will
1060 * determine whether or not we can use its FIFO features or not.
1062 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1064 unsigned char status1, scratch, scratch2, scratch3;
1065 unsigned char save_lcr, save_mcr;
1066 unsigned long flags;
1068 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1071 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1072 serial_index(&up->port), up->port.iobase, up->port.membase);
1075 * We really do need global IRQs disabled here - we're going to
1076 * be frobbing the chips IRQ enable register to see if it exists.
1078 spin_lock_irqsave(&up->port.lock, flags);
1080 up->capabilities = 0;
1083 if (!(up->port.flags & UPF_BUGGY_UART)) {
1085 * Do a simple existence test first; if we fail this,
1086 * there's no point trying anything else.
1088 * 0x80 is used as a nonsense port to prevent against
1089 * false positives due to ISA bus float. The
1090 * assumption is that 0x80 is a non-existent port;
1091 * which should be safe since include/asm/io.h also
1092 * makes this assumption.
1094 * Note: this is safe as long as MCR bit 4 is clear
1095 * and the device is in "PC" mode.
1097 scratch = serial_inp(up, UART_IER);
1098 serial_outp(up, UART_IER, 0);
1103 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1104 * 16C754B) allow only to modify them if an EFR bit is set.
1106 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1107 serial_outp(up, UART_IER, 0x0F);
1111 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1112 serial_outp(up, UART_IER, scratch);
1113 if (scratch2 != 0 || scratch3 != 0x0F) {
1115 * We failed; there's nothing here
1117 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1118 scratch2, scratch3);
1123 save_mcr = serial_in(up, UART_MCR);
1124 save_lcr = serial_in(up, UART_LCR);
1127 * Check to see if a UART is really there. Certain broken
1128 * internal modems based on the Rockwell chipset fail this
1129 * test, because they apparently don't implement the loopback
1130 * test mode. So this test is skipped on the COM 1 through
1131 * COM 4 ports. This *should* be safe, since no board
1132 * manufacturer would be stupid enough to design a board
1133 * that conflicts with COM 1-4 --- we hope!
1135 if (!(up->port.flags & UPF_SKIP_TEST)) {
1136 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1137 status1 = serial_inp(up, UART_MSR) & 0xF0;
1138 serial_outp(up, UART_MCR, save_mcr);
1139 if (status1 != 0x90) {
1140 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1147 * We're pretty sure there's a port here. Lets find out what
1148 * type of port it is. The IIR top two bits allows us to find
1149 * out if it's 8250 or 16450, 16550, 16550A or later. This
1150 * determines what we test for next.
1152 * We also initialise the EFR (if any) to zero for later. The
1153 * EFR occupies the same register location as the FCR and IIR.
1155 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1156 serial_outp(up, UART_EFR, 0);
1157 serial_outp(up, UART_LCR, 0);
1159 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1160 scratch = serial_in(up, UART_IIR) >> 6;
1162 DEBUG_AUTOCONF("iir=%d ", scratch);
1166 autoconfig_8250(up);
1169 up->port.type = PORT_UNKNOWN;
1172 up->port.type = PORT_16550;
1175 autoconfig_16550a(up);
1179 #ifdef CONFIG_SERIAL_8250_RSA
1181 * Only probe for RSA ports if we got the region.
1183 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1186 for (i = 0 ; i < probe_rsa_count; ++i) {
1187 if (probe_rsa[i] == up->port.iobase &&
1189 up->port.type = PORT_RSA;
1196 serial_outp(up, UART_LCR, save_lcr);
1198 if (up->capabilities != uart_config[up->port.type].flags) {
1200 "ttyS%d: detected caps %08x should be %08x\n",
1201 serial_index(&up->port), up->capabilities,
1202 uart_config[up->port.type].flags);
1205 up->port.fifosize = uart_config[up->port.type].fifo_size;
1206 up->capabilities = uart_config[up->port.type].flags;
1207 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1209 if (up->port.type == PORT_UNKNOWN)
1215 #ifdef CONFIG_SERIAL_8250_RSA
1216 if (up->port.type == PORT_RSA)
1217 serial_outp(up, UART_RSA_FRR, 0);
1219 serial_outp(up, UART_MCR, save_mcr);
1220 serial8250_clear_fifos(up);
1221 serial_in(up, UART_RX);
1222 if (up->capabilities & UART_CAP_UUE)
1223 serial_outp(up, UART_IER, UART_IER_UUE);
1225 serial_outp(up, UART_IER, 0);
1228 spin_unlock_irqrestore(&up->port.lock, flags);
1229 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1232 static void autoconfig_irq(struct uart_8250_port *up)
1234 unsigned char save_mcr, save_ier;
1235 unsigned char save_ICP = 0;
1236 unsigned int ICP = 0;
1240 if (up->port.flags & UPF_FOURPORT) {
1241 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1242 save_ICP = inb_p(ICP);
1247 /* forget possible initially masked and pending IRQ */
1248 probe_irq_off(probe_irq_on());
1249 save_mcr = serial_inp(up, UART_MCR);
1250 save_ier = serial_inp(up, UART_IER);
1251 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1253 irqs = probe_irq_on();
1254 serial_outp(up, UART_MCR, 0);
1256 if (up->port.flags & UPF_FOURPORT) {
1257 serial_outp(up, UART_MCR,
1258 UART_MCR_DTR | UART_MCR_RTS);
1260 serial_outp(up, UART_MCR,
1261 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1263 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1264 (void)serial_inp(up, UART_LSR);
1265 (void)serial_inp(up, UART_RX);
1266 (void)serial_inp(up, UART_IIR);
1267 (void)serial_inp(up, UART_MSR);
1268 serial_outp(up, UART_TX, 0xFF);
1270 irq = probe_irq_off(irqs);
1272 serial_outp(up, UART_MCR, save_mcr);
1273 serial_outp(up, UART_IER, save_ier);
1275 if (up->port.flags & UPF_FOURPORT)
1276 outb_p(save_ICP, ICP);
1278 up->port.irq = (irq > 0) ? irq : 0;
1281 static inline void __stop_tx(struct uart_8250_port *p)
1283 if (p->ier & UART_IER_THRI) {
1284 p->ier &= ~UART_IER_THRI;
1285 serial_out(p, UART_IER, p->ier);
1289 static void serial8250_stop_tx(struct uart_port *port)
1291 struct uart_8250_port *up =
1292 container_of(port, struct uart_8250_port, port);
1297 * We really want to stop the transmitter from sending.
1299 if (up->port.type == PORT_16C950) {
1300 up->acr |= UART_ACR_TXDIS;
1301 serial_icr_write(up, UART_ACR, up->acr);
1305 static void serial8250_start_tx(struct uart_port *port)
1307 struct uart_8250_port *up =
1308 container_of(port, struct uart_8250_port, port);
1310 if (!(up->ier & UART_IER_THRI)) {
1311 up->ier |= UART_IER_THRI;
1312 serial_out(up, UART_IER, up->ier);
1314 if (up->bugs & UART_BUG_TXEN) {
1316 lsr = serial_in(up, UART_LSR);
1317 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1318 if ((up->port.type == PORT_RM9000) ?
1319 (lsr & UART_LSR_THRE) :
1320 (lsr & UART_LSR_TEMT))
1321 serial8250_tx_chars(up);
1326 * Re-enable the transmitter if we disabled it.
1328 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1329 up->acr &= ~UART_ACR_TXDIS;
1330 serial_icr_write(up, UART_ACR, up->acr);
1334 static void serial8250_stop_rx(struct uart_port *port)
1336 struct uart_8250_port *up =
1337 container_of(port, struct uart_8250_port, port);
1339 up->ier &= ~UART_IER_RLSI;
1340 up->port.read_status_mask &= ~UART_LSR_DR;
1341 serial_out(up, UART_IER, up->ier);
1344 static void serial8250_enable_ms(struct uart_port *port)
1346 struct uart_8250_port *up =
1347 container_of(port, struct uart_8250_port, port);
1349 /* no MSR capabilities */
1350 if (up->bugs & UART_BUG_NOMSR)
1353 up->ier |= UART_IER_MSI;
1354 serial_out(up, UART_IER, up->ier);
1358 * Clear the Tegra rx fifo after a break
1360 * FIXME: This needs to become a port specific callback once we have a
1361 * framework for this
1363 static void clear_rx_fifo(struct uart_8250_port *up)
1365 unsigned int status, tmout = 10000;
1367 status = serial_in(up, UART_LSR);
1368 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1369 status = serial_in(up, UART_RX);
1379 * serial8250_rx_chars: processes according to the passed in LSR
1380 * value, and returns the remaining LSR bits not handled
1381 * by this Rx routine.
1384 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1386 struct tty_struct *tty = up->port.state->port.tty;
1388 int max_count = 256;
1392 if (likely(lsr & UART_LSR_DR))
1394 ch = serial_inp(up, UART_RX);
1395 if (arch_8250_sysrq_via_ctrl_o(ch, &up->port))
1400 * Intel 82571 has a Serial Over Lan device that will
1401 * set UART_LSR_BI without setting UART_LSR_DR when
1402 * it receives a break. To avoid reading from the
1403 * receive buffer without UART_LSR_DR bit set, we
1404 * just force the read character to be 0
1409 up->port.icount.rx++;
1411 lsr |= up->lsr_saved_flags;
1412 up->lsr_saved_flags = 0;
1414 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1416 * For statistics only
1418 if (lsr & UART_LSR_BI) {
1419 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1420 up->port.icount.brk++;
1422 * If tegra port then clear the rx fifo to
1423 * accept another break/character.
1425 if (up->port.type == PORT_TEGRA)
1429 * We do the SysRQ and SAK checking
1430 * here because otherwise the break
1431 * may get masked by ignore_status_mask
1432 * or read_status_mask.
1434 if (uart_handle_break(&up->port))
1436 } else if (lsr & UART_LSR_PE)
1437 up->port.icount.parity++;
1438 else if (lsr & UART_LSR_FE)
1439 up->port.icount.frame++;
1440 if (lsr & UART_LSR_OE)
1441 up->port.icount.overrun++;
1444 * Mask off conditions which should be ignored.
1446 lsr &= up->port.read_status_mask;
1448 if (lsr & UART_LSR_BI) {
1449 DEBUG_INTR("handling break....");
1451 } else if (lsr & UART_LSR_PE)
1453 else if (lsr & UART_LSR_FE)
1456 if (uart_handle_sysrq_char(&up->port, ch))
1459 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1462 lsr = serial_inp(up, UART_LSR);
1463 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1464 spin_unlock(&up->port.lock);
1465 tty_flip_buffer_push(tty);
1466 spin_lock(&up->port.lock);
1469 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1471 void serial8250_tx_chars(struct uart_8250_port *up)
1473 struct circ_buf *xmit = &up->port.state->xmit;
1476 if (up->port.x_char) {
1477 serial_outp(up, UART_TX, up->port.x_char);
1478 up->port.icount.tx++;
1479 up->port.x_char = 0;
1482 if (uart_tx_stopped(&up->port)) {
1483 serial8250_stop_tx(&up->port);
1486 if (uart_circ_empty(xmit)) {
1491 count = up->tx_loadsz;
1493 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1494 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1495 up->port.icount.tx++;
1496 if (uart_circ_empty(xmit))
1498 } while (--count > 0);
1500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1501 uart_write_wakeup(&up->port);
1503 DEBUG_INTR("THRE...");
1505 if (uart_circ_empty(xmit))
1508 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1510 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1512 unsigned int status = serial_in(up, UART_MSR);
1514 status |= up->msr_saved_flags;
1515 up->msr_saved_flags = 0;
1516 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1517 up->port.state != NULL) {
1518 if (status & UART_MSR_TERI)
1519 up->port.icount.rng++;
1520 if (status & UART_MSR_DDSR)
1521 up->port.icount.dsr++;
1522 if (status & UART_MSR_DDCD)
1523 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1524 if (status & UART_MSR_DCTS)
1525 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1527 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1532 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1535 * This handles the interrupt from one port.
1537 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1539 unsigned char status;
1540 unsigned long flags;
1541 struct uart_8250_port *up =
1542 container_of(port, struct uart_8250_port, port);
1544 if (iir & UART_IIR_NO_INT)
1547 spin_lock_irqsave(&up->port.lock, flags);
1549 status = serial_inp(up, UART_LSR);
1551 DEBUG_INTR("status = %x...", status);
1553 if (status & (UART_LSR_DR | UART_LSR_BI))
1554 status = serial8250_rx_chars(up, status);
1555 serial8250_modem_status(up);
1556 if (status & UART_LSR_THRE)
1557 serial8250_tx_chars(up);
1559 spin_unlock_irqrestore(&up->port.lock, flags);
1562 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1564 static int serial8250_default_handle_irq(struct uart_port *port)
1566 struct uart_8250_port *up =
1567 container_of(port, struct uart_8250_port, port);
1568 unsigned int iir = serial_in(up, UART_IIR);
1570 return serial8250_handle_irq(port, iir);
1574 * This is the serial driver's interrupt routine.
1576 * Arjan thinks the old way was overly complex, so it got simplified.
1577 * Alan disagrees, saying that need the complexity to handle the weird
1578 * nature of ISA shared interrupts. (This is a special exception.)
1580 * In order to handle ISA shared interrupts properly, we need to check
1581 * that all ports have been serviced, and therefore the ISA interrupt
1582 * line has been de-asserted.
1584 * This means we need to loop through all ports. checking that they
1585 * don't have an interrupt pending.
1587 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1589 struct irq_info *i = dev_id;
1590 struct list_head *l, *end = NULL;
1591 int pass_counter = 0, handled = 0;
1593 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1595 spin_lock(&i->lock);
1599 struct uart_8250_port *up;
1600 struct uart_port *port;
1603 up = list_entry(l, struct uart_8250_port, list);
1605 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1607 if (!skip && port->handle_irq(port)) {
1610 } else if (end == NULL)
1615 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1616 /* If we hit this, we're dead. */
1617 printk_ratelimited(KERN_ERR
1618 "serial8250: too much work for irq%d\n", irq);
1623 spin_unlock(&i->lock);
1625 DEBUG_INTR("end.\n");
1627 return IRQ_RETVAL(handled);
1631 * To support ISA shared interrupts, we need to have one interrupt
1632 * handler that ensures that the IRQ line has been deasserted
1633 * before returning. Failing to do this will result in the IRQ
1634 * line being stuck active, and, since ISA irqs are edge triggered,
1635 * no more IRQs will be seen.
1637 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1639 spin_lock_irq(&i->lock);
1641 if (!list_empty(i->head)) {
1642 if (i->head == &up->list)
1643 i->head = i->head->next;
1644 list_del(&up->list);
1646 BUG_ON(i->head != &up->list);
1649 spin_unlock_irq(&i->lock);
1650 /* List empty so throw away the hash node */
1651 if (i->head == NULL) {
1652 hlist_del(&i->node);
1657 static int serial_link_irq_chain(struct uart_8250_port *up)
1659 struct hlist_head *h;
1660 struct hlist_node *n;
1662 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1664 mutex_lock(&hash_mutex);
1666 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1668 hlist_for_each(n, h) {
1669 i = hlist_entry(n, struct irq_info, node);
1670 if (i->irq == up->port.irq)
1675 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1677 mutex_unlock(&hash_mutex);
1680 spin_lock_init(&i->lock);
1681 i->irq = up->port.irq;
1682 hlist_add_head(&i->node, h);
1684 mutex_unlock(&hash_mutex);
1686 spin_lock_irq(&i->lock);
1689 list_add(&up->list, i->head);
1690 spin_unlock_irq(&i->lock);
1694 INIT_LIST_HEAD(&up->list);
1695 i->head = &up->list;
1696 spin_unlock_irq(&i->lock);
1697 irq_flags |= up->port.irqflags;
1698 ret = request_irq(up->port.irq, serial8250_interrupt,
1699 irq_flags, "serial", i);
1701 serial_do_unlink(i, up);
1707 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1710 struct hlist_node *n;
1711 struct hlist_head *h;
1713 mutex_lock(&hash_mutex);
1715 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1717 hlist_for_each(n, h) {
1718 i = hlist_entry(n, struct irq_info, node);
1719 if (i->irq == up->port.irq)
1724 BUG_ON(i->head == NULL);
1726 if (list_empty(i->head))
1727 free_irq(up->port.irq, i);
1729 serial_do_unlink(i, up);
1730 mutex_unlock(&hash_mutex);
1734 * This function is used to handle ports that do not have an
1735 * interrupt. This doesn't work very well for 16450's, but gives
1736 * barely passable results for a 16550A. (Although at the expense
1737 * of much CPU overhead).
1739 static void serial8250_timeout(unsigned long data)
1741 struct uart_8250_port *up = (struct uart_8250_port *)data;
1743 up->port.handle_irq(&up->port);
1744 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1747 static void serial8250_backup_timeout(unsigned long data)
1749 struct uart_8250_port *up = (struct uart_8250_port *)data;
1750 unsigned int iir, ier = 0, lsr;
1751 unsigned long flags;
1753 spin_lock_irqsave(&up->port.lock, flags);
1756 * Must disable interrupts or else we risk racing with the interrupt
1759 if (is_real_interrupt(up->port.irq)) {
1760 ier = serial_in(up, UART_IER);
1761 serial_out(up, UART_IER, 0);
1764 iir = serial_in(up, UART_IIR);
1767 * This should be a safe test for anyone who doesn't trust the
1768 * IIR bits on their UART, but it's specifically designed for
1769 * the "Diva" UART used on the management processor on many HP
1770 * ia64 and parisc boxes.
1772 lsr = serial_in(up, UART_LSR);
1773 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1774 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1775 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1776 (lsr & UART_LSR_THRE)) {
1777 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1778 iir |= UART_IIR_THRI;
1781 if (!(iir & UART_IIR_NO_INT))
1782 serial8250_tx_chars(up);
1784 if (is_real_interrupt(up->port.irq))
1785 serial_out(up, UART_IER, ier);
1787 spin_unlock_irqrestore(&up->port.lock, flags);
1789 /* Standard timer interval plus 0.2s to keep the port running */
1790 mod_timer(&up->timer,
1791 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1794 static unsigned int serial8250_tx_empty(struct uart_port *port)
1796 struct uart_8250_port *up =
1797 container_of(port, struct uart_8250_port, port);
1798 unsigned long flags;
1801 spin_lock_irqsave(&up->port.lock, flags);
1802 lsr = serial_in(up, UART_LSR);
1803 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1804 spin_unlock_irqrestore(&up->port.lock, flags);
1806 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1809 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1811 struct uart_8250_port *up =
1812 container_of(port, struct uart_8250_port, port);
1813 unsigned int status;
1816 status = serial8250_modem_status(up);
1819 if (status & UART_MSR_DCD)
1821 if (status & UART_MSR_RI)
1823 if (status & UART_MSR_DSR)
1825 if (status & UART_MSR_CTS)
1830 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1832 struct uart_8250_port *up =
1833 container_of(port, struct uart_8250_port, port);
1834 unsigned char mcr = 0;
1836 if (mctrl & TIOCM_RTS)
1837 mcr |= UART_MCR_RTS;
1838 if (mctrl & TIOCM_DTR)
1839 mcr |= UART_MCR_DTR;
1840 if (mctrl & TIOCM_OUT1)
1841 mcr |= UART_MCR_OUT1;
1842 if (mctrl & TIOCM_OUT2)
1843 mcr |= UART_MCR_OUT2;
1844 if (mctrl & TIOCM_LOOP)
1845 mcr |= UART_MCR_LOOP;
1847 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1849 serial_out(up, UART_MCR, mcr);
1852 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1854 struct uart_8250_port *up =
1855 container_of(port, struct uart_8250_port, port);
1856 unsigned long flags;
1858 spin_lock_irqsave(&up->port.lock, flags);
1859 if (break_state == -1)
1860 up->lcr |= UART_LCR_SBC;
1862 up->lcr &= ~UART_LCR_SBC;
1863 serial_out(up, UART_LCR, up->lcr);
1864 spin_unlock_irqrestore(&up->port.lock, flags);
1868 * Wait for transmitter & holding register to empty
1870 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1872 unsigned int status, tmout = 10000;
1874 /* Wait up to 10ms for the character(s) to be sent. */
1876 status = serial_in(up, UART_LSR);
1878 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1880 if ((status & bits) == bits)
1887 /* Wait up to 1s for flow control if necessary */
1888 if (up->port.flags & UPF_CONS_FLOW) {
1890 for (tmout = 1000000; tmout; tmout--) {
1891 unsigned int msr = serial_in(up, UART_MSR);
1892 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1893 if (msr & UART_MSR_CTS)
1896 touch_nmi_watchdog();
1901 #ifdef CONFIG_CONSOLE_POLL
1903 * Console polling routines for writing and reading from the uart while
1904 * in an interrupt or debug context.
1907 static int serial8250_get_poll_char(struct uart_port *port)
1909 struct uart_8250_port *up =
1910 container_of(port, struct uart_8250_port, port);
1911 unsigned char lsr = serial_inp(up, UART_LSR);
1913 if (!(lsr & UART_LSR_DR))
1914 return NO_POLL_CHAR;
1916 return serial_inp(up, UART_RX);
1920 static void serial8250_put_poll_char(struct uart_port *port,
1924 struct uart_8250_port *up =
1925 container_of(port, struct uart_8250_port, port);
1928 * First save the IER then disable the interrupts
1930 ier = serial_in(up, UART_IER);
1931 if (up->capabilities & UART_CAP_UUE)
1932 serial_out(up, UART_IER, UART_IER_UUE);
1934 serial_out(up, UART_IER, 0);
1936 wait_for_xmitr(up, BOTH_EMPTY);
1938 * Send the character out.
1939 * If a LF, also do CR...
1941 serial_out(up, UART_TX, c);
1943 wait_for_xmitr(up, BOTH_EMPTY);
1944 serial_out(up, UART_TX, 13);
1948 * Finally, wait for transmitter to become empty
1949 * and restore the IER
1951 wait_for_xmitr(up, BOTH_EMPTY);
1952 serial_out(up, UART_IER, ier);
1955 #endif /* CONFIG_CONSOLE_POLL */
1957 static int serial8250_startup(struct uart_port *port)
1959 struct uart_8250_port *up =
1960 container_of(port, struct uart_8250_port, port);
1961 unsigned long flags;
1962 unsigned char lsr, iir;
1965 up->port.fifosize = uart_config[up->port.type].fifo_size;
1966 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1967 up->capabilities = uart_config[up->port.type].flags;
1970 if (up->port.iotype != up->cur_iotype)
1971 set_io_from_upio(port);
1973 if (up->port.type == PORT_16C950) {
1974 /* Wake up and initialize UART */
1976 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1977 serial_outp(up, UART_EFR, UART_EFR_ECB);
1978 serial_outp(up, UART_IER, 0);
1979 serial_outp(up, UART_LCR, 0);
1980 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1981 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1982 serial_outp(up, UART_EFR, UART_EFR_ECB);
1983 serial_outp(up, UART_LCR, 0);
1986 #ifdef CONFIG_SERIAL_8250_RSA
1988 * If this is an RSA port, see if we can kick it up to the
1989 * higher speed clock.
1995 * Clear the FIFO buffers and disable them.
1996 * (they will be reenabled in set_termios())
1998 serial8250_clear_fifos(up);
2001 * Clear the interrupt registers.
2003 (void) serial_inp(up, UART_LSR);
2004 (void) serial_inp(up, UART_RX);
2005 (void) serial_inp(up, UART_IIR);
2006 (void) serial_inp(up, UART_MSR);
2009 * At this point, there's no way the LSR could still be 0xff;
2010 * if it is, then bail out, because there's likely no UART
2013 if (!(up->port.flags & UPF_BUGGY_UART) &&
2014 (serial_inp(up, UART_LSR) == 0xff)) {
2015 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2016 serial_index(&up->port));
2021 * For a XR16C850, we need to set the trigger levels
2023 if (up->port.type == PORT_16850) {
2026 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2028 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2029 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2030 serial_outp(up, UART_TRG, UART_TRG_96);
2031 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2032 serial_outp(up, UART_TRG, UART_TRG_96);
2034 serial_outp(up, UART_LCR, 0);
2037 if (is_real_interrupt(up->port.irq)) {
2040 * Test for UARTs that do not reassert THRE when the
2041 * transmitter is idle and the interrupt has already
2042 * been cleared. Real 16550s should always reassert
2043 * this interrupt whenever the transmitter is idle and
2044 * the interrupt is enabled. Delays are necessary to
2045 * allow register changes to become visible.
2047 spin_lock_irqsave(&up->port.lock, flags);
2048 if (up->port.irqflags & IRQF_SHARED)
2049 disable_irq_nosync(up->port.irq);
2051 wait_for_xmitr(up, UART_LSR_THRE);
2052 serial_out_sync(up, UART_IER, UART_IER_THRI);
2053 udelay(1); /* allow THRE to set */
2054 iir1 = serial_in(up, UART_IIR);
2055 serial_out(up, UART_IER, 0);
2056 serial_out_sync(up, UART_IER, UART_IER_THRI);
2057 udelay(1); /* allow a working UART time to re-assert THRE */
2058 iir = serial_in(up, UART_IIR);
2059 serial_out(up, UART_IER, 0);
2061 if (up->port.irqflags & IRQF_SHARED)
2062 enable_irq(up->port.irq);
2063 spin_unlock_irqrestore(&up->port.lock, flags);
2066 * If the interrupt is not reasserted, setup a timer to
2067 * kick the UART on a regular basis.
2069 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2070 up->bugs |= UART_BUG_THRE;
2071 pr_debug("ttyS%d - using backup timer\n",
2072 serial_index(port));
2077 * The above check will only give an accurate result the first time
2078 * the port is opened so this value needs to be preserved.
2080 if (up->bugs & UART_BUG_THRE) {
2081 up->timer.function = serial8250_backup_timeout;
2082 up->timer.data = (unsigned long)up;
2083 mod_timer(&up->timer, jiffies +
2084 uart_poll_timeout(port) + HZ / 5);
2088 * If the "interrupt" for this port doesn't correspond with any
2089 * hardware interrupt, we use a timer-based system. The original
2090 * driver used to do this with IRQ0.
2092 if (!is_real_interrupt(up->port.irq)) {
2093 up->timer.data = (unsigned long)up;
2094 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2096 retval = serial_link_irq_chain(up);
2102 * Now, initialize the UART
2104 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2106 spin_lock_irqsave(&up->port.lock, flags);
2107 if (up->port.flags & UPF_FOURPORT) {
2108 if (!is_real_interrupt(up->port.irq))
2109 up->port.mctrl |= TIOCM_OUT1;
2112 * Most PC uarts need OUT2 raised to enable interrupts.
2114 if (is_real_interrupt(up->port.irq))
2115 up->port.mctrl |= TIOCM_OUT2;
2117 serial8250_set_mctrl(&up->port, up->port.mctrl);
2119 /* Serial over Lan (SoL) hack:
2120 Intel 8257x Gigabit ethernet chips have a
2121 16550 emulation, to be used for Serial Over Lan.
2122 Those chips take a longer time than a normal
2123 serial device to signalize that a transmission
2124 data was queued. Due to that, the above test generally
2125 fails. One solution would be to delay the reading of
2126 iir. However, this is not reliable, since the timeout
2127 is variable. So, let's just don't test if we receive
2128 TX irq. This way, we'll never enable UART_BUG_TXEN.
2130 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2131 goto dont_test_tx_en;
2134 * Do a quick test to see if we receive an
2135 * interrupt when we enable the TX irq.
2137 serial_outp(up, UART_IER, UART_IER_THRI);
2138 lsr = serial_in(up, UART_LSR);
2139 iir = serial_in(up, UART_IIR);
2140 serial_outp(up, UART_IER, 0);
2142 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2143 if (!(up->bugs & UART_BUG_TXEN)) {
2144 up->bugs |= UART_BUG_TXEN;
2145 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2146 serial_index(port));
2149 up->bugs &= ~UART_BUG_TXEN;
2153 spin_unlock_irqrestore(&up->port.lock, flags);
2156 * Clear the interrupt registers again for luck, and clear the
2157 * saved flags to avoid getting false values from polling
2158 * routines or the previous session.
2160 serial_inp(up, UART_LSR);
2161 serial_inp(up, UART_RX);
2162 serial_inp(up, UART_IIR);
2163 serial_inp(up, UART_MSR);
2164 up->lsr_saved_flags = 0;
2165 up->msr_saved_flags = 0;
2168 * Finally, enable interrupts. Note: Modem status interrupts
2169 * are set via set_termios(), which will be occurring imminently
2170 * anyway, so we don't enable them here.
2172 up->ier = UART_IER_RLSI | UART_IER_RDI;
2173 serial_outp(up, UART_IER, up->ier);
2175 if (up->port.flags & UPF_FOURPORT) {
2178 * Enable interrupts on the AST Fourport board
2180 icp = (up->port.iobase & 0xfe0) | 0x01f;
2188 static void serial8250_shutdown(struct uart_port *port)
2190 struct uart_8250_port *up =
2191 container_of(port, struct uart_8250_port, port);
2192 unsigned long flags;
2195 * Disable interrupts from this port
2198 serial_outp(up, UART_IER, 0);
2200 spin_lock_irqsave(&up->port.lock, flags);
2201 if (up->port.flags & UPF_FOURPORT) {
2202 /* reset interrupts on the AST Fourport board */
2203 inb((up->port.iobase & 0xfe0) | 0x1f);
2204 up->port.mctrl |= TIOCM_OUT1;
2206 up->port.mctrl &= ~TIOCM_OUT2;
2208 serial8250_set_mctrl(&up->port, up->port.mctrl);
2209 spin_unlock_irqrestore(&up->port.lock, flags);
2212 * Disable break condition and FIFOs
2214 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2215 serial8250_clear_fifos(up);
2217 #ifdef CONFIG_SERIAL_8250_RSA
2219 * Reset the RSA board back to 115kbps compat mode.
2225 * Read data port to reset things, and then unlink from
2228 (void) serial_in(up, UART_RX);
2230 del_timer_sync(&up->timer);
2231 up->timer.function = serial8250_timeout;
2232 if (is_real_interrupt(up->port.irq))
2233 serial_unlink_irq_chain(up);
2236 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2241 * Handle magic divisors for baud rates above baud_base on
2242 * SMSC SuperIO chips.
2244 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2245 baud == (port->uartclk/4))
2247 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2248 baud == (port->uartclk/8))
2251 quot = uart_get_divisor(port, baud);
2257 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2258 struct ktermios *old)
2260 struct uart_8250_port *up =
2261 container_of(port, struct uart_8250_port, port);
2262 unsigned char cval, fcr = 0;
2263 unsigned long flags;
2264 unsigned int baud, quot;
2266 switch (termios->c_cflag & CSIZE) {
2268 cval = UART_LCR_WLEN5;
2271 cval = UART_LCR_WLEN6;
2274 cval = UART_LCR_WLEN7;
2278 cval = UART_LCR_WLEN8;
2282 if (termios->c_cflag & CSTOPB)
2283 cval |= UART_LCR_STOP;
2284 if (termios->c_cflag & PARENB)
2285 cval |= UART_LCR_PARITY;
2286 if (!(termios->c_cflag & PARODD))
2287 cval |= UART_LCR_EPAR;
2289 if (termios->c_cflag & CMSPAR)
2290 cval |= UART_LCR_SPAR;
2294 * Ask the core to calculate the divisor for us.
2296 baud = uart_get_baud_rate(port, termios, old,
2297 port->uartclk / 16 / 0xffff,
2298 port->uartclk / 16);
2299 quot = serial8250_get_divisor(port, baud);
2302 * Oxford Semi 952 rev B workaround
2304 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2307 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2309 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2311 fcr = uart_config[up->port.type].fcr;
2315 * MCR-based auto flow control. When AFE is enabled, RTS will be
2316 * deasserted when the receive FIFO contains more characters than
2317 * the trigger, or the MCR RTS bit is cleared. In the case where
2318 * the remote UART is not using CTS auto flow control, we must
2319 * have sufficient FIFO entries for the latency of the remote
2320 * UART to respond. IOW, at least 32 bytes of FIFO.
2322 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2323 up->mcr &= ~UART_MCR_AFE;
2324 if (termios->c_cflag & CRTSCTS)
2325 up->mcr |= UART_MCR_AFE;
2329 * Ok, we're now changing the port state. Do it with
2330 * interrupts disabled.
2332 spin_lock_irqsave(&up->port.lock, flags);
2335 * Update the per-port timeout.
2337 uart_update_timeout(port, termios->c_cflag, baud);
2339 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2340 if (termios->c_iflag & INPCK)
2341 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2342 if (termios->c_iflag & (BRKINT | PARMRK))
2343 up->port.read_status_mask |= UART_LSR_BI;
2346 * Characteres to ignore
2348 up->port.ignore_status_mask = 0;
2349 if (termios->c_iflag & IGNPAR)
2350 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2351 if (termios->c_iflag & IGNBRK) {
2352 up->port.ignore_status_mask |= UART_LSR_BI;
2354 * If we're ignoring parity and break indicators,
2355 * ignore overruns too (for real raw support).
2357 if (termios->c_iflag & IGNPAR)
2358 up->port.ignore_status_mask |= UART_LSR_OE;
2362 * ignore all characters if CREAD is not set
2364 if ((termios->c_cflag & CREAD) == 0)
2365 up->port.ignore_status_mask |= UART_LSR_DR;
2368 * CTS flow control flag and modem status interrupts
2370 up->ier &= ~UART_IER_MSI;
2371 if (!(up->bugs & UART_BUG_NOMSR) &&
2372 UART_ENABLE_MS(&up->port, termios->c_cflag))
2373 up->ier |= UART_IER_MSI;
2374 if (up->capabilities & UART_CAP_UUE)
2375 up->ier |= UART_IER_UUE;
2376 if (up->capabilities & UART_CAP_RTOIE)
2377 up->ier |= UART_IER_RTOIE;
2379 serial_out(up, UART_IER, up->ier);
2381 if (up->capabilities & UART_CAP_EFR) {
2382 unsigned char efr = 0;
2384 * TI16C752/Startech hardware flow control. FIXME:
2385 * - TI16C752 requires control thresholds to be set.
2386 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2388 if (termios->c_cflag & CRTSCTS)
2389 efr |= UART_EFR_CTS;
2391 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2392 if (up->port.flags & UPF_EXAR_EFR)
2393 serial_outp(up, UART_XR_EFR, efr);
2395 serial_outp(up, UART_EFR, efr);
2398 #ifdef CONFIG_ARCH_OMAP
2399 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2400 if (cpu_is_omap1510() && is_omap_port(up)) {
2401 if (baud == 115200) {
2403 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2405 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2409 if (up->capabilities & UART_NATSEMI) {
2410 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2411 serial_outp(up, UART_LCR, 0xe0);
2413 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2416 serial_dl_write(up, quot);
2419 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2420 * is written without DLAB set, this mode will be disabled.
2422 if (up->port.type == PORT_16750)
2423 serial_outp(up, UART_FCR, fcr);
2425 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2426 up->lcr = cval; /* Save LCR */
2427 if (up->port.type != PORT_16750) {
2428 if (fcr & UART_FCR_ENABLE_FIFO) {
2429 /* emulated UARTs (Lucent Venus 167x) need two steps */
2430 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2432 serial_outp(up, UART_FCR, fcr); /* set fcr */
2434 serial8250_set_mctrl(&up->port, up->port.mctrl);
2435 spin_unlock_irqrestore(&up->port.lock, flags);
2436 /* Don't rewrite B0 */
2437 if (tty_termios_baud_rate(termios))
2438 tty_termios_encode_baud_rate(termios, baud, baud);
2440 EXPORT_SYMBOL(serial8250_do_set_termios);
2443 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2444 struct ktermios *old)
2446 if (port->set_termios)
2447 port->set_termios(port, termios, old);
2449 serial8250_do_set_termios(port, termios, old);
2453 serial8250_set_ldisc(struct uart_port *port, int new)
2456 port->flags |= UPF_HARDPPS_CD;
2457 serial8250_enable_ms(port);
2459 port->flags &= ~UPF_HARDPPS_CD;
2463 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2464 unsigned int oldstate)
2466 struct uart_8250_port *p =
2467 container_of(port, struct uart_8250_port, port);
2469 serial8250_set_sleep(p, state != 0);
2471 EXPORT_SYMBOL(serial8250_do_pm);
2474 serial8250_pm(struct uart_port *port, unsigned int state,
2475 unsigned int oldstate)
2478 port->pm(port, state, oldstate);
2480 serial8250_do_pm(port, state, oldstate);
2483 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2485 if (pt->port.iotype == UPIO_AU)
2487 #ifdef CONFIG_ARCH_OMAP
2488 if (is_omap_port(pt))
2489 return 0x16 << pt->port.regshift;
2491 return 8 << pt->port.regshift;
2495 * Resource handling.
2497 static int serial8250_request_std_resource(struct uart_8250_port *up)
2499 unsigned int size = serial8250_port_size(up);
2502 switch (up->port.iotype) {
2507 if (!up->port.mapbase)
2510 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2515 if (up->port.flags & UPF_IOREMAP) {
2516 up->port.membase = ioremap_nocache(up->port.mapbase,
2518 if (!up->port.membase) {
2519 release_mem_region(up->port.mapbase, size);
2527 if (!request_region(up->port.iobase, size, "serial"))
2534 static void serial8250_release_std_resource(struct uart_8250_port *up)
2536 unsigned int size = serial8250_port_size(up);
2538 switch (up->port.iotype) {
2543 if (!up->port.mapbase)
2546 if (up->port.flags & UPF_IOREMAP) {
2547 iounmap(up->port.membase);
2548 up->port.membase = NULL;
2551 release_mem_region(up->port.mapbase, size);
2556 release_region(up->port.iobase, size);
2561 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2563 unsigned long start = UART_RSA_BASE << up->port.regshift;
2564 unsigned int size = 8 << up->port.regshift;
2567 switch (up->port.iotype) {
2570 start += up->port.iobase;
2571 if (request_region(start, size, "serial-rsa"))
2581 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2583 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2584 unsigned int size = 8 << up->port.regshift;
2586 switch (up->port.iotype) {
2589 release_region(up->port.iobase + offset, size);
2594 static void serial8250_release_port(struct uart_port *port)
2596 struct uart_8250_port *up =
2597 container_of(port, struct uart_8250_port, port);
2599 serial8250_release_std_resource(up);
2600 if (up->port.type == PORT_RSA)
2601 serial8250_release_rsa_resource(up);
2604 static int serial8250_request_port(struct uart_port *port)
2606 struct uart_8250_port *up =
2607 container_of(port, struct uart_8250_port, port);
2610 ret = serial8250_request_std_resource(up);
2611 if (ret == 0 && up->port.type == PORT_RSA) {
2612 ret = serial8250_request_rsa_resource(up);
2614 serial8250_release_std_resource(up);
2620 static void serial8250_config_port(struct uart_port *port, int flags)
2622 struct uart_8250_port *up =
2623 container_of(port, struct uart_8250_port, port);
2624 int probeflags = PROBE_ANY;
2628 * Find the region that we can probe for. This in turn
2629 * tells us whether we can probe for the type of port.
2631 ret = serial8250_request_std_resource(up);
2635 ret = serial8250_request_rsa_resource(up);
2637 probeflags &= ~PROBE_RSA;
2639 if (up->port.iotype != up->cur_iotype)
2640 set_io_from_upio(port);
2642 if (flags & UART_CONFIG_TYPE)
2643 autoconfig(up, probeflags);
2645 /* if access method is AU, it is a 16550 with a quirk */
2646 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2647 up->bugs |= UART_BUG_NOMSR;
2649 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2652 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2653 serial8250_release_rsa_resource(up);
2654 if (up->port.type == PORT_UNKNOWN)
2655 serial8250_release_std_resource(up);
2659 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2661 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2662 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2663 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2664 ser->type == PORT_STARTECH)
2670 serial8250_type(struct uart_port *port)
2672 int type = port->type;
2674 if (type >= ARRAY_SIZE(uart_config))
2676 return uart_config[type].name;
2679 static struct uart_ops serial8250_pops = {
2680 .tx_empty = serial8250_tx_empty,
2681 .set_mctrl = serial8250_set_mctrl,
2682 .get_mctrl = serial8250_get_mctrl,
2683 .stop_tx = serial8250_stop_tx,
2684 .start_tx = serial8250_start_tx,
2685 .stop_rx = serial8250_stop_rx,
2686 .enable_ms = serial8250_enable_ms,
2687 .break_ctl = serial8250_break_ctl,
2688 .startup = serial8250_startup,
2689 .shutdown = serial8250_shutdown,
2690 .set_termios = serial8250_set_termios,
2691 .set_ldisc = serial8250_set_ldisc,
2692 .pm = serial8250_pm,
2693 .type = serial8250_type,
2694 .release_port = serial8250_release_port,
2695 .request_port = serial8250_request_port,
2696 .config_port = serial8250_config_port,
2697 .verify_port = serial8250_verify_port,
2698 #ifdef CONFIG_CONSOLE_POLL
2699 .poll_get_char = serial8250_get_poll_char,
2700 .poll_put_char = serial8250_put_poll_char,
2704 static struct uart_8250_port serial8250_ports[UART_NR];
2706 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2707 unsigned short *capabilities);
2709 void serial8250_set_isa_configurator(
2710 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2712 serial8250_isa_config = v;
2714 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2716 static void __init serial8250_isa_init_ports(void)
2718 struct uart_8250_port *up;
2719 static int first = 1;
2726 for (i = 0; i < nr_uarts; i++) {
2727 struct uart_8250_port *up = &serial8250_ports[i];
2730 spin_lock_init(&up->port.lock);
2732 init_timer(&up->timer);
2733 up->timer.function = serial8250_timeout;
2736 * ALPHA_KLUDGE_MCR needs to be killed.
2738 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2739 up->mcr_force = ALPHA_KLUDGE_MCR;
2741 up->port.ops = &serial8250_pops;
2745 irqflag = IRQF_SHARED;
2747 for (i = 0, up = serial8250_ports;
2748 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2750 up->port.iobase = old_serial_port[i].port;
2751 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2752 up->port.irqflags = old_serial_port[i].irqflags;
2753 up->port.uartclk = old_serial_port[i].baud_base * 16;
2754 up->port.flags = old_serial_port[i].flags;
2755 up->port.hub6 = old_serial_port[i].hub6;
2756 up->port.membase = old_serial_port[i].iomem_base;
2757 up->port.iotype = old_serial_port[i].io_type;
2758 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2759 set_io_from_upio(&up->port);
2760 up->port.irqflags |= irqflag;
2761 if (serial8250_isa_config != NULL)
2762 serial8250_isa_config(i, &up->port, &up->capabilities);
2768 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2770 up->port.type = type;
2771 up->port.fifosize = uart_config[type].fifo_size;
2772 up->capabilities = uart_config[type].flags;
2773 up->tx_loadsz = uart_config[type].tx_loadsz;
2777 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2781 for (i = 0; i < nr_uarts; i++) {
2782 struct uart_8250_port *up = &serial8250_ports[i];
2783 up->cur_iotype = 0xFF;
2786 serial8250_isa_init_ports();
2788 for (i = 0; i < nr_uarts; i++) {
2789 struct uart_8250_port *up = &serial8250_ports[i];
2793 if (up->port.flags & UPF_FIXED_TYPE)
2794 serial8250_init_fixed_type_port(up, up->port.type);
2796 uart_add_one_port(drv, &up->port);
2800 #ifdef CONFIG_SERIAL_8250_CONSOLE
2802 static void serial8250_console_putchar(struct uart_port *port, int ch)
2804 struct uart_8250_port *up =
2805 container_of(port, struct uart_8250_port, port);
2807 wait_for_xmitr(up, UART_LSR_THRE);
2808 serial_out(up, UART_TX, ch);
2812 * Print a string to the serial port trying not to disturb
2813 * any possible real use of the port...
2815 * The console_lock must be held when we get here.
2818 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2820 struct uart_8250_port *up = &serial8250_ports[co->index];
2821 unsigned long flags;
2825 touch_nmi_watchdog();
2827 local_irq_save(flags);
2828 if (up->port.sysrq) {
2829 /* serial8250_handle_irq() already took the lock */
2831 } else if (oops_in_progress) {
2832 locked = spin_trylock(&up->port.lock);
2834 spin_lock(&up->port.lock);
2837 * First save the IER then disable the interrupts
2839 ier = serial_in(up, UART_IER);
2841 if (up->capabilities & UART_CAP_UUE)
2842 serial_out(up, UART_IER, UART_IER_UUE);
2844 serial_out(up, UART_IER, 0);
2846 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2849 * Finally, wait for transmitter to become empty
2850 * and restore the IER
2852 wait_for_xmitr(up, BOTH_EMPTY);
2853 serial_out(up, UART_IER, ier);
2856 * The receive handling will happen properly because the
2857 * receive ready bit will still be set; it is not cleared
2858 * on read. However, modem control will not, we must
2859 * call it if we have saved something in the saved flags
2860 * while processing with interrupts off.
2862 if (up->msr_saved_flags)
2863 serial8250_modem_status(up);
2866 spin_unlock(&up->port.lock);
2867 local_irq_restore(flags);
2870 static int __init serial8250_console_setup(struct console *co, char *options)
2872 struct uart_port *port;
2879 * Check whether an invalid uart number has been specified, and
2880 * if so, search for the first available port that does have
2883 if (co->index >= nr_uarts)
2885 port = &serial8250_ports[co->index].port;
2886 if (!port->iobase && !port->membase)
2890 uart_parse_options(options, &baud, &parity, &bits, &flow);
2892 return uart_set_options(port, co, baud, parity, bits, flow);
2895 static int serial8250_console_early_setup(void)
2897 return serial8250_find_port_for_earlycon();
2900 static struct console serial8250_console = {
2902 .write = serial8250_console_write,
2903 .device = uart_console_device,
2904 .setup = serial8250_console_setup,
2905 .early_setup = serial8250_console_early_setup,
2906 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2908 .data = &serial8250_reg,
2911 static int __init serial8250_console_init(void)
2913 if (nr_uarts > UART_NR)
2916 serial8250_isa_init_ports();
2917 register_console(&serial8250_console);
2920 console_initcall(serial8250_console_init);
2922 int serial8250_find_port(struct uart_port *p)
2925 struct uart_port *port;
2927 for (line = 0; line < nr_uarts; line++) {
2928 port = &serial8250_ports[line].port;
2929 if (uart_match_port(p, port))
2935 #define SERIAL8250_CONSOLE &serial8250_console
2937 #define SERIAL8250_CONSOLE NULL
2940 static struct uart_driver serial8250_reg = {
2941 .owner = THIS_MODULE,
2942 .driver_name = "serial",
2946 .cons = SERIAL8250_CONSOLE,
2950 * early_serial_setup - early registration for 8250 ports
2952 * Setup an 8250 port structure prior to console initialisation. Use
2953 * after console initialisation will cause undefined behaviour.
2955 int __init early_serial_setup(struct uart_port *port)
2957 struct uart_port *p;
2959 if (port->line >= ARRAY_SIZE(serial8250_ports))
2962 serial8250_isa_init_ports();
2963 p = &serial8250_ports[port->line].port;
2964 p->iobase = port->iobase;
2965 p->membase = port->membase;
2967 p->irqflags = port->irqflags;
2968 p->uartclk = port->uartclk;
2969 p->fifosize = port->fifosize;
2970 p->regshift = port->regshift;
2971 p->iotype = port->iotype;
2972 p->flags = port->flags;
2973 p->mapbase = port->mapbase;
2974 p->private_data = port->private_data;
2975 p->type = port->type;
2976 p->line = port->line;
2978 set_io_from_upio(p);
2979 if (port->serial_in)
2980 p->serial_in = port->serial_in;
2981 if (port->serial_out)
2982 p->serial_out = port->serial_out;
2983 if (port->handle_irq)
2984 p->handle_irq = port->handle_irq;
2986 p->handle_irq = serial8250_default_handle_irq;
2992 * serial8250_suspend_port - suspend one serial port
2993 * @line: serial line number
2995 * Suspend one serial port.
2997 void serial8250_suspend_port(int line)
2999 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3003 * serial8250_resume_port - resume one serial port
3004 * @line: serial line number
3006 * Resume one serial port.
3008 void serial8250_resume_port(int line)
3010 struct uart_8250_port *up = &serial8250_ports[line];
3012 if (up->capabilities & UART_NATSEMI) {
3013 /* Ensure it's still in high speed mode */
3014 serial_outp(up, UART_LCR, 0xE0);
3016 ns16550a_goto_highspeed(up);
3018 serial_outp(up, UART_LCR, 0);
3019 up->port.uartclk = 921600*16;
3021 uart_resume_port(&serial8250_reg, &up->port);
3025 * Register a set of serial devices attached to a platform device. The
3026 * list is terminated with a zero flags entry, which means we expect
3027 * all entries to have at least UPF_BOOT_AUTOCONF set.
3029 static int __devinit serial8250_probe(struct platform_device *dev)
3031 struct plat_serial8250_port *p = dev->dev.platform_data;
3032 struct uart_port port;
3033 int ret, i, irqflag = 0;
3035 memset(&port, 0, sizeof(struct uart_port));
3038 irqflag = IRQF_SHARED;
3040 for (i = 0; p && p->flags != 0; p++, i++) {
3041 port.iobase = p->iobase;
3042 port.membase = p->membase;
3044 port.irqflags = p->irqflags;
3045 port.uartclk = p->uartclk;
3046 port.regshift = p->regshift;
3047 port.iotype = p->iotype;
3048 port.flags = p->flags;
3049 port.mapbase = p->mapbase;
3050 port.hub6 = p->hub6;
3051 port.private_data = p->private_data;
3052 port.type = p->type;
3053 port.serial_in = p->serial_in;
3054 port.serial_out = p->serial_out;
3055 port.handle_irq = p->handle_irq;
3056 port.set_termios = p->set_termios;
3058 port.dev = &dev->dev;
3059 port.irqflags |= irqflag;
3060 ret = serial8250_register_port(&port);
3062 dev_err(&dev->dev, "unable to register port at index %d "
3063 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3064 p->iobase, (unsigned long long)p->mapbase,
3072 * Remove serial ports registered against a platform device.
3074 static int __devexit serial8250_remove(struct platform_device *dev)
3078 for (i = 0; i < nr_uarts; i++) {
3079 struct uart_8250_port *up = &serial8250_ports[i];
3081 if (up->port.dev == &dev->dev)
3082 serial8250_unregister_port(i);
3087 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3091 for (i = 0; i < UART_NR; i++) {
3092 struct uart_8250_port *up = &serial8250_ports[i];
3094 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3095 uart_suspend_port(&serial8250_reg, &up->port);
3101 static int serial8250_resume(struct platform_device *dev)
3105 for (i = 0; i < UART_NR; i++) {
3106 struct uart_8250_port *up = &serial8250_ports[i];
3108 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3109 serial8250_resume_port(i);
3115 static struct platform_driver serial8250_isa_driver = {
3116 .probe = serial8250_probe,
3117 .remove = __devexit_p(serial8250_remove),
3118 .suspend = serial8250_suspend,
3119 .resume = serial8250_resume,
3121 .name = "serial8250",
3122 .owner = THIS_MODULE,
3127 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3128 * in the table in include/asm/serial.h
3130 static struct platform_device *serial8250_isa_devs;
3133 * serial8250_register_port and serial8250_unregister_port allows for
3134 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3135 * modems and PCI multiport cards.
3137 static DEFINE_MUTEX(serial_mutex);
3139 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3144 * First, find a port entry which matches.
3146 for (i = 0; i < nr_uarts; i++)
3147 if (uart_match_port(&serial8250_ports[i].port, port))
3148 return &serial8250_ports[i];
3151 * We didn't find a matching entry, so look for the first
3152 * free entry. We look for one which hasn't been previously
3153 * used (indicated by zero iobase).
3155 for (i = 0; i < nr_uarts; i++)
3156 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3157 serial8250_ports[i].port.iobase == 0)
3158 return &serial8250_ports[i];
3161 * That also failed. Last resort is to find any entry which
3162 * doesn't have a real port associated with it.
3164 for (i = 0; i < nr_uarts; i++)
3165 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3166 return &serial8250_ports[i];
3172 * serial8250_register_port - register a serial port
3173 * @port: serial port template
3175 * Configure the serial port specified by the request. If the
3176 * port exists and is in use, it is hung up and unregistered
3179 * The port is then probed and if necessary the IRQ is autodetected
3180 * If this fails an error is returned.
3182 * On success the port is ready to use and the line number is returned.
3184 int serial8250_register_port(struct uart_port *port)
3186 struct uart_8250_port *uart;
3189 if (port->uartclk == 0)
3192 mutex_lock(&serial_mutex);
3194 uart = serial8250_find_match_or_unused(port);
3196 uart_remove_one_port(&serial8250_reg, &uart->port);
3198 uart->port.iobase = port->iobase;
3199 uart->port.membase = port->membase;
3200 uart->port.irq = port->irq;
3201 uart->port.irqflags = port->irqflags;
3202 uart->port.uartclk = port->uartclk;
3203 uart->port.fifosize = port->fifosize;
3204 uart->port.regshift = port->regshift;
3205 uart->port.iotype = port->iotype;
3206 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3207 uart->port.mapbase = port->mapbase;
3208 uart->port.private_data = port->private_data;
3210 uart->port.dev = port->dev;
3212 if (port->flags & UPF_FIXED_TYPE)
3213 serial8250_init_fixed_type_port(uart, port->type);
3215 set_io_from_upio(&uart->port);
3216 /* Possibly override default I/O functions. */
3217 if (port->serial_in)
3218 uart->port.serial_in = port->serial_in;
3219 if (port->serial_out)
3220 uart->port.serial_out = port->serial_out;
3221 if (port->handle_irq)
3222 uart->port.handle_irq = port->handle_irq;
3223 /* Possibly override set_termios call */
3224 if (port->set_termios)
3225 uart->port.set_termios = port->set_termios;
3227 uart->port.pm = port->pm;
3229 if (serial8250_isa_config != NULL)
3230 serial8250_isa_config(0, &uart->port,
3231 &uart->capabilities);
3233 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3235 ret = uart->port.line;
3237 mutex_unlock(&serial_mutex);
3241 EXPORT_SYMBOL(serial8250_register_port);
3244 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3245 * @line: serial line number
3247 * Remove one serial port. This may not be called from interrupt
3248 * context. We hand the port back to the our control.
3250 void serial8250_unregister_port(int line)
3252 struct uart_8250_port *uart = &serial8250_ports[line];
3254 mutex_lock(&serial_mutex);
3255 uart_remove_one_port(&serial8250_reg, &uart->port);
3256 if (serial8250_isa_devs) {
3257 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3258 uart->port.type = PORT_UNKNOWN;
3259 uart->port.dev = &serial8250_isa_devs->dev;
3260 uart->capabilities = uart_config[uart->port.type].flags;
3261 uart_add_one_port(&serial8250_reg, &uart->port);
3263 uart->port.dev = NULL;
3265 mutex_unlock(&serial_mutex);
3267 EXPORT_SYMBOL(serial8250_unregister_port);
3269 static int __init serial8250_init(void)
3273 if (nr_uarts > UART_NR)
3276 printk(KERN_INFO "Serial: 8250/16550 driver, "
3277 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3278 share_irqs ? "en" : "dis");
3281 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3283 serial8250_reg.nr = UART_NR;
3284 ret = uart_register_driver(&serial8250_reg);
3289 serial8250_isa_devs = platform_device_alloc("serial8250",
3290 PLAT8250_DEV_LEGACY);
3291 if (!serial8250_isa_devs) {
3293 goto unreg_uart_drv;
3296 ret = platform_device_add(serial8250_isa_devs);
3300 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3302 ret = platform_driver_register(&serial8250_isa_driver);
3306 platform_device_del(serial8250_isa_devs);
3308 platform_device_put(serial8250_isa_devs);
3311 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3313 uart_unregister_driver(&serial8250_reg);
3319 static void __exit serial8250_exit(void)
3321 struct platform_device *isa_dev = serial8250_isa_devs;
3324 * This tells serial8250_unregister_port() not to re-register
3325 * the ports (thereby making serial8250_isa_driver permanently
3328 serial8250_isa_devs = NULL;
3330 platform_driver_unregister(&serial8250_isa_driver);
3331 platform_device_unregister(isa_dev);
3334 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3336 uart_unregister_driver(&serial8250_reg);
3340 module_init(serial8250_init);
3341 module_exit(serial8250_exit);
3343 EXPORT_SYMBOL(serial8250_suspend_port);
3344 EXPORT_SYMBOL(serial8250_resume_port);
3346 MODULE_LICENSE("GPL");
3347 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3349 module_param(share_irqs, uint, 0644);
3350 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3353 module_param(nr_uarts, uint, 0644);
3354 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3356 module_param(skip_txen_test, uint, 0644);
3357 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3359 #ifdef CONFIG_SERIAL_8250_RSA
3360 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3361 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3363 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);