2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
42 #include <linux/sunserialcore.h>
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59 static struct uart_driver serial8250_reg;
61 static int serial_index(struct uart_port *port)
63 return (serial8250_reg.minor - 64) + port->line;
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
78 #define DEBUG_INTR(fmt...) printk(fmt)
80 #define DEBUG_INTR(fmt...) do { } while (0)
83 #define PASS_LIMIT 512
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
95 #define arch_8250_sysrq_via_ctrl_o(a,b) 0
98 * HUB6 is always on. This will be removed once the header
99 * files have been cleaned.
101 #define CONFIG_HUB6 1
103 #include <asm/serial.h>
105 * SERIAL_PORT_DFNS tells us about built-in ports that have no
106 * standard enumeration mechanism. Platforms that can find all
107 * serial ports via mechanisms like ACPI or PCI need not supply it.
109 #ifndef SERIAL_PORT_DFNS
110 #define SERIAL_PORT_DFNS
113 static const struct old_serial_port old_serial_port[] = {
114 SERIAL_PORT_DFNS /* defined in asm/serial.h */
117 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
119 #ifdef CONFIG_SERIAL_8250_RSA
121 #define PORT_RSA_MAX 4
122 static unsigned long probe_rsa[PORT_RSA_MAX];
123 static unsigned int probe_rsa_count;
124 #endif /* CONFIG_SERIAL_8250_RSA */
127 struct hlist_node node;
129 spinlock_t lock; /* Protects list not the hash */
130 struct list_head *head;
133 #define NR_IRQ_HASH 32 /* Can be adjusted later */
134 static struct hlist_head irq_lists[NR_IRQ_HASH];
135 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
138 * Here we define the default xmit fifo size used for each type of UART.
140 static const struct serial8250_config uart_config[] = {
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
166 .flags = UART_CAP_FIFO,
177 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
183 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
185 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
193 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
201 .name = "16C950/954",
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
206 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
212 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
214 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
221 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
227 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
228 .flags = UART_CAP_FIFO,
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 .flags = UART_CAP_FIFO | UART_NATSEMI,
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
242 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
248 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
249 .flags = UART_CAP_FIFO,
255 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
256 .flags = UART_CAP_FIFO,
262 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
263 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
270 .flags = UART_CAP_FIFO | UART_CAP_AFE,
276 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
278 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
284 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
285 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
289 #if defined(CONFIG_MIPS_ALCHEMY)
291 /* Au1x00 UART hardware has a weird register layout */
292 static const u8 au_io_in_map[] = {
302 static const u8 au_io_out_map[] = {
310 /* sane hardware needs no mapping */
311 static inline int map_8250_in_reg(struct uart_port *p, int offset)
313 if (p->iotype != UPIO_AU)
315 return au_io_in_map[offset];
318 static inline int map_8250_out_reg(struct uart_port *p, int offset)
320 if (p->iotype != UPIO_AU)
322 return au_io_out_map[offset];
325 #elif defined(CONFIG_SERIAL_8250_RM9K)
349 static inline int map_8250_in_reg(struct uart_port *p, int offset)
351 if (p->iotype != UPIO_RM9000)
353 return regmap_in[offset];
356 static inline int map_8250_out_reg(struct uart_port *p, int offset)
358 if (p->iotype != UPIO_RM9000)
360 return regmap_out[offset];
365 /* sane hardware needs no mapping */
366 #define map_8250_in_reg(up, offset) (offset)
367 #define map_8250_out_reg(up, offset) (offset)
371 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
373 offset = map_8250_in_reg(p, offset) << p->regshift;
374 outb(p->hub6 - 1 + offset, p->iobase);
375 return inb(p->iobase + 1);
378 static void hub6_serial_out(struct uart_port *p, int offset, int value)
380 offset = map_8250_out_reg(p, offset) << p->regshift;
381 outb(p->hub6 - 1 + offset, p->iobase);
382 outb(value, p->iobase + 1);
385 static unsigned int mem_serial_in(struct uart_port *p, int offset)
387 offset = map_8250_in_reg(p, offset) << p->regshift;
388 return readb(p->membase + offset);
391 static void mem_serial_out(struct uart_port *p, int offset, int value)
393 offset = map_8250_out_reg(p, offset) << p->regshift;
394 writeb(value, p->membase + offset);
397 static void mem32_serial_out(struct uart_port *p, int offset, int value)
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 writel(value, p->membase + offset);
403 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
405 offset = map_8250_in_reg(p, offset) << p->regshift;
406 return readl(p->membase + offset);
409 static unsigned int au_serial_in(struct uart_port *p, int offset)
411 offset = map_8250_in_reg(p, offset) << p->regshift;
412 return __raw_readl(p->membase + offset);
415 static void au_serial_out(struct uart_port *p, int offset, int value)
417 offset = map_8250_out_reg(p, offset) << p->regshift;
418 __raw_writel(value, p->membase + offset);
421 static unsigned int io_serial_in(struct uart_port *p, int offset)
423 offset = map_8250_in_reg(p, offset) << p->regshift;
424 return inb(p->iobase + offset);
427 static void io_serial_out(struct uart_port *p, int offset, int value)
429 offset = map_8250_out_reg(p, offset) << p->regshift;
430 outb(value, p->iobase + offset);
433 static int serial8250_default_handle_irq(struct uart_port *port);
435 static void set_io_from_upio(struct uart_port *p)
437 struct uart_8250_port *up =
438 container_of(p, struct uart_8250_port, port);
441 p->serial_in = hub6_serial_in;
442 p->serial_out = hub6_serial_out;
446 p->serial_in = mem_serial_in;
447 p->serial_out = mem_serial_out;
452 p->serial_in = mem32_serial_in;
453 p->serial_out = mem32_serial_out;
457 p->serial_in = au_serial_in;
458 p->serial_out = au_serial_out;
462 p->serial_in = io_serial_in;
463 p->serial_out = io_serial_out;
466 /* Remember loaded iotype */
467 up->cur_iotype = p->iotype;
468 p->handle_irq = serial8250_default_handle_irq;
472 serial_port_out_sync(struct uart_port *p, int offset, int value)
478 p->serial_out(p, offset, value);
479 p->serial_in(p, UART_LCR); /* safe, no side-effects */
482 p->serial_out(p, offset, value);
486 /* Uart divisor latch read */
487 static inline int _serial_dl_read(struct uart_8250_port *up)
489 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
492 /* Uart divisor latch write */
493 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
495 serial_out(up, UART_DLL, value & 0xff);
496 serial_out(up, UART_DLM, value >> 8 & 0xff);
499 #if defined(CONFIG_MIPS_ALCHEMY)
500 /* Au1x00 haven't got a standard divisor latch */
501 static int serial_dl_read(struct uart_8250_port *up)
503 if (up->port.iotype == UPIO_AU)
504 return __raw_readl(up->port.membase + 0x28);
506 return _serial_dl_read(up);
509 static void serial_dl_write(struct uart_8250_port *up, int value)
511 if (up->port.iotype == UPIO_AU)
512 __raw_writel(value, up->port.membase + 0x28);
514 _serial_dl_write(up, value);
516 #elif defined(CONFIG_SERIAL_8250_RM9K)
517 static int serial_dl_read(struct uart_8250_port *up)
519 return (up->port.iotype == UPIO_RM9000) ?
520 (((__raw_readl(up->port.membase + 0x10) << 8) |
521 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
525 static void serial_dl_write(struct uart_8250_port *up, int value)
527 if (up->port.iotype == UPIO_RM9000) {
528 __raw_writel(value, up->port.membase + 0x08);
529 __raw_writel(value >> 8, up->port.membase + 0x10);
531 _serial_dl_write(up, value);
535 #define serial_dl_read(up) _serial_dl_read(up)
536 #define serial_dl_write(up, value) _serial_dl_write(up, value)
542 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
544 serial_out(up, UART_SCR, offset);
545 serial_out(up, UART_ICR, value);
548 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
552 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
553 serial_out(up, UART_SCR, offset);
554 value = serial_in(up, UART_ICR);
555 serial_icr_write(up, UART_ACR, up->acr);
563 static void serial8250_clear_fifos(struct uart_8250_port *p)
565 if (p->capabilities & UART_CAP_FIFO) {
566 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
567 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
568 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
569 serial_out(p, UART_FCR, 0);
574 * IER sleep support. UARTs which have EFRs need the "extended
575 * capability" bit enabled. Note that on XR16C850s, we need to
576 * reset LCR to write to IER.
578 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
580 if (p->capabilities & UART_CAP_SLEEP) {
581 if (p->capabilities & UART_CAP_EFR) {
582 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
583 serial_out(p, UART_EFR, UART_EFR_ECB);
584 serial_out(p, UART_LCR, 0);
586 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
587 if (p->capabilities & UART_CAP_EFR) {
588 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
589 serial_out(p, UART_EFR, 0);
590 serial_out(p, UART_LCR, 0);
595 #ifdef CONFIG_SERIAL_8250_RSA
597 * Attempts to turn on the RSA FIFO. Returns zero on failure.
598 * We set the port uart clock rate if we succeed.
600 static int __enable_rsa(struct uart_8250_port *up)
605 mode = serial_in(up, UART_RSA_MSR);
606 result = mode & UART_RSA_MSR_FIFO;
609 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
610 mode = serial_in(up, UART_RSA_MSR);
611 result = mode & UART_RSA_MSR_FIFO;
615 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
620 static void enable_rsa(struct uart_8250_port *up)
622 if (up->port.type == PORT_RSA) {
623 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
624 spin_lock_irq(&up->port.lock);
626 spin_unlock_irq(&up->port.lock);
628 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
629 serial_out(up, UART_RSA_FRR, 0);
634 * Attempts to turn off the RSA FIFO. Returns zero on failure.
635 * It is unknown why interrupts were disabled in here. However,
636 * the caller is expected to preserve this behaviour by grabbing
637 * the spinlock before calling this function.
639 static void disable_rsa(struct uart_8250_port *up)
644 if (up->port.type == PORT_RSA &&
645 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
646 spin_lock_irq(&up->port.lock);
648 mode = serial_in(up, UART_RSA_MSR);
649 result = !(mode & UART_RSA_MSR_FIFO);
652 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
653 mode = serial_in(up, UART_RSA_MSR);
654 result = !(mode & UART_RSA_MSR_FIFO);
658 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
659 spin_unlock_irq(&up->port.lock);
662 #endif /* CONFIG_SERIAL_8250_RSA */
665 * This is a quickie test to see how big the FIFO is.
666 * It doesn't work at all the time, more's the pity.
668 static int size_fifo(struct uart_8250_port *up)
670 unsigned char old_fcr, old_mcr, old_lcr;
671 unsigned short old_dl;
674 old_lcr = serial_in(up, UART_LCR);
675 serial_out(up, UART_LCR, 0);
676 old_fcr = serial_in(up, UART_FCR);
677 old_mcr = serial_in(up, UART_MCR);
678 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
679 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
680 serial_out(up, UART_MCR, UART_MCR_LOOP);
681 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
682 old_dl = serial_dl_read(up);
683 serial_dl_write(up, 0x0001);
684 serial_out(up, UART_LCR, 0x03);
685 for (count = 0; count < 256; count++)
686 serial_out(up, UART_TX, count);
687 mdelay(20);/* FIXME - schedule_timeout */
688 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
689 (count < 256); count++)
690 serial_in(up, UART_RX);
691 serial_out(up, UART_FCR, old_fcr);
692 serial_out(up, UART_MCR, old_mcr);
693 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
694 serial_dl_write(up, old_dl);
695 serial_out(up, UART_LCR, old_lcr);
701 * Read UART ID using the divisor method - set DLL and DLM to zero
702 * and the revision will be in DLL and device type in DLM. We
703 * preserve the device state across this.
705 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
707 unsigned char old_dll, old_dlm, old_lcr;
710 old_lcr = serial_in(p, UART_LCR);
711 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
713 old_dll = serial_in(p, UART_DLL);
714 old_dlm = serial_in(p, UART_DLM);
716 serial_out(p, UART_DLL, 0);
717 serial_out(p, UART_DLM, 0);
719 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
721 serial_out(p, UART_DLL, old_dll);
722 serial_out(p, UART_DLM, old_dlm);
723 serial_out(p, UART_LCR, old_lcr);
729 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
730 * When this function is called we know it is at least a StarTech
731 * 16650 V2, but it might be one of several StarTech UARTs, or one of
732 * its clones. (We treat the broken original StarTech 16650 V1 as a
733 * 16550, and why not? Startech doesn't seem to even acknowledge its
736 * What evil have men's minds wrought...
738 static void autoconfig_has_efr(struct uart_8250_port *up)
740 unsigned int id1, id2, id3, rev;
743 * Everything with an EFR has SLEEP
745 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
748 * First we check to see if it's an Oxford Semiconductor UART.
750 * If we have to do this here because some non-National
751 * Semiconductor clone chips lock up if you try writing to the
752 * LSR register (which serial_icr_read does)
756 * Check for Oxford Semiconductor 16C950.
758 * EFR [4] must be set else this test fails.
760 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
761 * claims that it's needed for 952 dual UART's (which are not
762 * recommended for new designs).
765 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
766 serial_out(up, UART_EFR, UART_EFR_ECB);
767 serial_out(up, UART_LCR, 0x00);
768 id1 = serial_icr_read(up, UART_ID1);
769 id2 = serial_icr_read(up, UART_ID2);
770 id3 = serial_icr_read(up, UART_ID3);
771 rev = serial_icr_read(up, UART_REV);
773 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
775 if (id1 == 0x16 && id2 == 0xC9 &&
776 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
777 up->port.type = PORT_16C950;
780 * Enable work around for the Oxford Semiconductor 952 rev B
781 * chip which causes it to seriously miscalculate baud rates
784 if (id3 == 0x52 && rev == 0x01)
785 up->bugs |= UART_BUG_QUOT;
790 * We check for a XR16C850 by setting DLL and DLM to 0, and then
791 * reading back DLL and DLM. The chip type depends on the DLM
793 * 0x10 - XR16C850 and the DLL contains the chip revision.
797 id1 = autoconfig_read_divisor_id(up);
798 DEBUG_AUTOCONF("850id=%04x ", id1);
801 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
802 up->port.type = PORT_16850;
807 * It wasn't an XR16C850.
809 * We distinguish between the '654 and the '650 by counting
810 * how many bytes are in the FIFO. I'm using this for now,
811 * since that's the technique that was sent to me in the
812 * serial driver update, but I'm not convinced this works.
813 * I've had problems doing this in the past. -TYT
815 if (size_fifo(up) == 64)
816 up->port.type = PORT_16654;
818 up->port.type = PORT_16650V2;
822 * We detected a chip without a FIFO. Only two fall into
823 * this category - the original 8250 and the 16450. The
824 * 16450 has a scratch register (accessible with LCR=0)
826 static void autoconfig_8250(struct uart_8250_port *up)
828 unsigned char scratch, status1, status2;
830 up->port.type = PORT_8250;
832 scratch = serial_in(up, UART_SCR);
833 serial_out(up, UART_SCR, 0xa5);
834 status1 = serial_in(up, UART_SCR);
835 serial_out(up, UART_SCR, 0x5a);
836 status2 = serial_in(up, UART_SCR);
837 serial_out(up, UART_SCR, scratch);
839 if (status1 == 0xa5 && status2 == 0x5a)
840 up->port.type = PORT_16450;
843 static int broken_efr(struct uart_8250_port *up)
846 * Exar ST16C2550 "A2" devices incorrectly detect as
847 * having an EFR, and report an ID of 0x0201. See
848 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
850 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
856 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
858 unsigned char status;
860 status = serial_in(up, 0x04); /* EXCR2 */
861 #define PRESL(x) ((x) & 0x30)
862 if (PRESL(status) == 0x10) {
863 /* already in high speed mode */
866 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
867 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
868 serial_out(up, 0x04, status);
874 * We know that the chip has FIFOs. Does it have an EFR? The
875 * EFR is located in the same register position as the IIR and
876 * we know the top two bits of the IIR are currently set. The
877 * EFR should contain zero. Try to read the EFR.
879 static void autoconfig_16550a(struct uart_8250_port *up)
881 unsigned char status1, status2;
882 unsigned int iersave;
884 up->port.type = PORT_16550A;
885 up->capabilities |= UART_CAP_FIFO;
888 * Check for presence of the EFR when DLAB is set.
889 * Only ST16C650V1 UARTs pass this test.
891 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
892 if (serial_in(up, UART_EFR) == 0) {
893 serial_out(up, UART_EFR, 0xA8);
894 if (serial_in(up, UART_EFR) != 0) {
895 DEBUG_AUTOCONF("EFRv1 ");
896 up->port.type = PORT_16650;
897 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
899 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
901 serial_out(up, UART_EFR, 0);
906 * Maybe it requires 0xbf to be written to the LCR.
907 * (other ST16C650V2 UARTs, TI16C752A, etc)
909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
910 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
911 DEBUG_AUTOCONF("EFRv2 ");
912 autoconfig_has_efr(up);
917 * Check for a National Semiconductor SuperIO chip.
918 * Attempt to switch to bank 2, read the value of the LOOP bit
919 * from EXCR1. Switch back to bank 0, change it in MCR. Then
920 * switch back to bank 2, read it from EXCR1 again and check
921 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
923 serial_out(up, UART_LCR, 0);
924 status1 = serial_in(up, UART_MCR);
925 serial_out(up, UART_LCR, 0xE0);
926 status2 = serial_in(up, 0x02); /* EXCR1 */
928 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
929 serial_out(up, UART_LCR, 0);
930 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
931 serial_out(up, UART_LCR, 0xE0);
932 status2 = serial_in(up, 0x02); /* EXCR1 */
933 serial_out(up, UART_LCR, 0);
934 serial_out(up, UART_MCR, status1);
936 if ((status2 ^ status1) & UART_MCR_LOOP) {
939 serial_out(up, UART_LCR, 0xE0);
941 quot = serial_dl_read(up);
944 if (ns16550a_goto_highspeed(up))
945 serial_dl_write(up, quot);
947 serial_out(up, UART_LCR, 0);
949 up->port.uartclk = 921600*16;
950 up->port.type = PORT_NS16550A;
951 up->capabilities |= UART_NATSEMI;
957 * No EFR. Try to detect a TI16750, which only sets bit 5 of
958 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
959 * Try setting it with and without DLAB set. Cheap clones
960 * set bit 5 without DLAB set.
962 serial_out(up, UART_LCR, 0);
963 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
964 status1 = serial_in(up, UART_IIR) >> 5;
965 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
966 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
967 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
968 status2 = serial_in(up, UART_IIR) >> 5;
969 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
970 serial_out(up, UART_LCR, 0);
972 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
974 if (status1 == 6 && status2 == 7) {
975 up->port.type = PORT_16750;
976 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
981 * Try writing and reading the UART_IER_UUE bit (b6).
982 * If it works, this is probably one of the Xscale platform's
984 * We're going to explicitly set the UUE bit to 0 before
985 * trying to write and read a 1 just to make sure it's not
986 * already a 1 and maybe locked there before we even start start.
988 iersave = serial_in(up, UART_IER);
989 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
990 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
992 * OK it's in a known zero state, try writing and reading
993 * without disturbing the current state of the other bits.
995 serial_out(up, UART_IER, iersave | UART_IER_UUE);
996 if (serial_in(up, UART_IER) & UART_IER_UUE) {
999 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1001 DEBUG_AUTOCONF("Xscale ");
1002 up->port.type = PORT_XSCALE;
1003 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1008 * If we got here we couldn't force the IER_UUE bit to 0.
1009 * Log it and continue.
1011 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1013 serial_out(up, UART_IER, iersave);
1016 * Exar uarts have EFR in a weird location
1018 if (up->port.flags & UPF_EXAR_EFR) {
1019 up->port.type = PORT_XR17D15X;
1020 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1024 * We distinguish between 16550A and U6 16550A by counting
1025 * how many bytes are in the FIFO.
1027 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1028 up->port.type = PORT_U6_16550A;
1029 up->capabilities |= UART_CAP_AFE;
1034 * This routine is called by rs_init() to initialize a specific serial
1035 * port. It determines what type of UART chip this serial port is
1036 * using: 8250, 16450, 16550, 16550A. The important question is
1037 * whether or not this UART is a 16550A or not, since this will
1038 * determine whether or not we can use its FIFO features or not.
1040 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1042 unsigned char status1, scratch, scratch2, scratch3;
1043 unsigned char save_lcr, save_mcr;
1044 struct uart_port *port = &up->port;
1045 unsigned long flags;
1047 if (!port->iobase && !port->mapbase && !port->membase)
1050 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1051 serial_index(port), port->iobase, port->membase);
1054 * We really do need global IRQs disabled here - we're going to
1055 * be frobbing the chips IRQ enable register to see if it exists.
1057 spin_lock_irqsave(&port->lock, flags);
1059 up->capabilities = 0;
1062 if (!(port->flags & UPF_BUGGY_UART)) {
1064 * Do a simple existence test first; if we fail this,
1065 * there's no point trying anything else.
1067 * 0x80 is used as a nonsense port to prevent against
1068 * false positives due to ISA bus float. The
1069 * assumption is that 0x80 is a non-existent port;
1070 * which should be safe since include/asm/io.h also
1071 * makes this assumption.
1073 * Note: this is safe as long as MCR bit 4 is clear
1074 * and the device is in "PC" mode.
1076 scratch = serial_in(up, UART_IER);
1077 serial_out(up, UART_IER, 0);
1082 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1083 * 16C754B) allow only to modify them if an EFR bit is set.
1085 scratch2 = serial_in(up, UART_IER) & 0x0f;
1086 serial_out(up, UART_IER, 0x0F);
1090 scratch3 = serial_in(up, UART_IER) & 0x0f;
1091 serial_out(up, UART_IER, scratch);
1092 if (scratch2 != 0 || scratch3 != 0x0F) {
1094 * We failed; there's nothing here
1096 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1097 scratch2, scratch3);
1102 save_mcr = serial_in(up, UART_MCR);
1103 save_lcr = serial_in(up, UART_LCR);
1106 * Check to see if a UART is really there. Certain broken
1107 * internal modems based on the Rockwell chipset fail this
1108 * test, because they apparently don't implement the loopback
1109 * test mode. So this test is skipped on the COM 1 through
1110 * COM 4 ports. This *should* be safe, since no board
1111 * manufacturer would be stupid enough to design a board
1112 * that conflicts with COM 1-4 --- we hope!
1114 if (!(port->flags & UPF_SKIP_TEST)) {
1115 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1116 status1 = serial_in(up, UART_MSR) & 0xF0;
1117 serial_out(up, UART_MCR, save_mcr);
1118 if (status1 != 0x90) {
1119 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1126 * We're pretty sure there's a port here. Lets find out what
1127 * type of port it is. The IIR top two bits allows us to find
1128 * out if it's 8250 or 16450, 16550, 16550A or later. This
1129 * determines what we test for next.
1131 * We also initialise the EFR (if any) to zero for later. The
1132 * EFR occupies the same register location as the FCR and IIR.
1134 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1135 serial_out(up, UART_EFR, 0);
1136 serial_out(up, UART_LCR, 0);
1138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1139 scratch = serial_in(up, UART_IIR) >> 6;
1141 DEBUG_AUTOCONF("iir=%d ", scratch);
1145 autoconfig_8250(up);
1148 port->type = PORT_UNKNOWN;
1151 port->type = PORT_16550;
1154 autoconfig_16550a(up);
1158 #ifdef CONFIG_SERIAL_8250_RSA
1160 * Only probe for RSA ports if we got the region.
1162 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1165 for (i = 0 ; i < probe_rsa_count; ++i) {
1166 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1167 port->type = PORT_RSA;
1174 serial_out(up, UART_LCR, save_lcr);
1176 if (up->capabilities != uart_config[port->type].flags) {
1178 "ttyS%d: detected caps %08x should be %08x\n",
1179 serial_index(port), up->capabilities,
1180 uart_config[port->type].flags);
1183 port->fifosize = uart_config[up->port.type].fifo_size;
1184 up->capabilities = uart_config[port->type].flags;
1185 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1187 if (port->type == PORT_UNKNOWN)
1193 #ifdef CONFIG_SERIAL_8250_RSA
1194 if (port->type == PORT_RSA)
1195 serial_out(up, UART_RSA_FRR, 0);
1197 serial_out(up, UART_MCR, save_mcr);
1198 serial8250_clear_fifos(up);
1199 serial_in(up, UART_RX);
1200 if (up->capabilities & UART_CAP_UUE)
1201 serial_out(up, UART_IER, UART_IER_UUE);
1203 serial_out(up, UART_IER, 0);
1206 spin_unlock_irqrestore(&port->lock, flags);
1207 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1210 static void autoconfig_irq(struct uart_8250_port *up)
1212 struct uart_port *port = &up->port;
1213 unsigned char save_mcr, save_ier;
1214 unsigned char save_ICP = 0;
1215 unsigned int ICP = 0;
1219 if (port->flags & UPF_FOURPORT) {
1220 ICP = (port->iobase & 0xfe0) | 0x1f;
1221 save_ICP = inb_p(ICP);
1226 /* forget possible initially masked and pending IRQ */
1227 probe_irq_off(probe_irq_on());
1228 save_mcr = serial_in(up, UART_MCR);
1229 save_ier = serial_in(up, UART_IER);
1230 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1232 irqs = probe_irq_on();
1233 serial_out(up, UART_MCR, 0);
1235 if (port->flags & UPF_FOURPORT) {
1236 serial_out(up, UART_MCR,
1237 UART_MCR_DTR | UART_MCR_RTS);
1239 serial_out(up, UART_MCR,
1240 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1242 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1243 serial_in(up, UART_LSR);
1244 serial_in(up, UART_RX);
1245 serial_in(up, UART_IIR);
1246 serial_in(up, UART_MSR);
1247 serial_out(up, UART_TX, 0xFF);
1249 irq = probe_irq_off(irqs);
1251 serial_out(up, UART_MCR, save_mcr);
1252 serial_out(up, UART_IER, save_ier);
1254 if (port->flags & UPF_FOURPORT)
1255 outb_p(save_ICP, ICP);
1257 port->irq = (irq > 0) ? irq : 0;
1260 static inline void __stop_tx(struct uart_8250_port *p)
1262 if (p->ier & UART_IER_THRI) {
1263 p->ier &= ~UART_IER_THRI;
1264 serial_out(p, UART_IER, p->ier);
1268 static void serial8250_stop_tx(struct uart_port *port)
1270 struct uart_8250_port *up =
1271 container_of(port, struct uart_8250_port, port);
1276 * We really want to stop the transmitter from sending.
1278 if (port->type == PORT_16C950) {
1279 up->acr |= UART_ACR_TXDIS;
1280 serial_icr_write(up, UART_ACR, up->acr);
1284 static void serial8250_start_tx(struct uart_port *port)
1286 struct uart_8250_port *up =
1287 container_of(port, struct uart_8250_port, port);
1289 if (!(up->ier & UART_IER_THRI)) {
1290 up->ier |= UART_IER_THRI;
1291 serial_port_out(port, UART_IER, up->ier);
1293 if (up->bugs & UART_BUG_TXEN) {
1295 lsr = serial_in(up, UART_LSR);
1296 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1297 if ((port->type == PORT_RM9000) ?
1298 (lsr & UART_LSR_THRE) :
1299 (lsr & UART_LSR_TEMT))
1300 serial8250_tx_chars(up);
1305 * Re-enable the transmitter if we disabled it.
1307 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1308 up->acr &= ~UART_ACR_TXDIS;
1309 serial_icr_write(up, UART_ACR, up->acr);
1313 static void serial8250_stop_rx(struct uart_port *port)
1315 struct uart_8250_port *up =
1316 container_of(port, struct uart_8250_port, port);
1318 up->ier &= ~UART_IER_RLSI;
1319 up->port.read_status_mask &= ~UART_LSR_DR;
1320 serial_port_out(port, UART_IER, up->ier);
1323 static void serial8250_enable_ms(struct uart_port *port)
1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1328 /* no MSR capabilities */
1329 if (up->bugs & UART_BUG_NOMSR)
1332 up->ier |= UART_IER_MSI;
1333 serial_port_out(port, UART_IER, up->ier);
1337 * Clear the Tegra rx fifo after a break
1339 * FIXME: This needs to become a port specific callback once we have a
1340 * framework for this
1342 static void clear_rx_fifo(struct uart_8250_port *up)
1344 unsigned int status, tmout = 10000;
1346 status = serial_in(up, UART_LSR);
1347 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1348 status = serial_in(up, UART_RX);
1358 * serial8250_rx_chars: processes according to the passed in LSR
1359 * value, and returns the remaining LSR bits not handled
1360 * by this Rx routine.
1363 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1365 struct uart_port *port = &up->port;
1366 struct tty_struct *tty = port->state->port.tty;
1368 int max_count = 256;
1372 if (likely(lsr & UART_LSR_DR))
1374 ch = serial_in(up, UART_RX);
1375 if (arch_8250_sysrq_via_ctrl_o(ch, &up->port))
1380 * Intel 82571 has a Serial Over Lan device that will
1381 * set UART_LSR_BI without setting UART_LSR_DR when
1382 * it receives a break. To avoid reading from the
1383 * receive buffer without UART_LSR_DR bit set, we
1384 * just force the read character to be 0
1391 lsr |= up->lsr_saved_flags;
1392 up->lsr_saved_flags = 0;
1394 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1396 * For statistics only
1398 if (lsr & UART_LSR_BI) {
1399 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1402 * If tegra port then clear the rx fifo to
1403 * accept another break/character.
1405 if (port->type == PORT_TEGRA)
1409 * We do the SysRQ and SAK checking
1410 * here because otherwise the break
1411 * may get masked by ignore_status_mask
1412 * or read_status_mask.
1414 if (uart_handle_break(port))
1416 } else if (lsr & UART_LSR_PE)
1417 port->icount.parity++;
1418 else if (lsr & UART_LSR_FE)
1419 port->icount.frame++;
1420 if (lsr & UART_LSR_OE)
1421 port->icount.overrun++;
1424 * Mask off conditions which should be ignored.
1426 lsr &= port->read_status_mask;
1428 if (lsr & UART_LSR_BI) {
1429 DEBUG_INTR("handling break....");
1431 } else if (lsr & UART_LSR_PE)
1433 else if (lsr & UART_LSR_FE)
1436 if (uart_handle_sysrq_char(port, ch))
1439 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1442 lsr = serial_in(up, UART_LSR);
1443 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1444 spin_unlock(&port->lock);
1445 tty_flip_buffer_push(tty);
1446 spin_lock(&port->lock);
1449 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1451 void serial8250_tx_chars(struct uart_8250_port *up)
1453 struct uart_port *port = &up->port;
1454 struct circ_buf *xmit = &port->state->xmit;
1458 serial_out(up, UART_TX, port->x_char);
1463 if (uart_tx_stopped(port)) {
1464 serial8250_stop_tx(port);
1467 if (uart_circ_empty(xmit)) {
1472 count = up->tx_loadsz;
1474 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1475 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1477 if (uart_circ_empty(xmit))
1479 } while (--count > 0);
1481 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1482 uart_write_wakeup(port);
1484 DEBUG_INTR("THRE...");
1486 if (uart_circ_empty(xmit))
1489 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1491 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1493 struct uart_port *port = &up->port;
1494 unsigned int status = serial_in(up, UART_MSR);
1496 status |= up->msr_saved_flags;
1497 up->msr_saved_flags = 0;
1498 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1499 port->state != NULL) {
1500 if (status & UART_MSR_TERI)
1502 if (status & UART_MSR_DDSR)
1504 if (status & UART_MSR_DDCD)
1505 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1506 if (status & UART_MSR_DCTS)
1507 uart_handle_cts_change(port, status & UART_MSR_CTS);
1509 wake_up_interruptible(&port->state->port.delta_msr_wait);
1514 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1517 * This handles the interrupt from one port.
1519 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1521 unsigned char status;
1522 unsigned long flags;
1523 struct uart_8250_port *up =
1524 container_of(port, struct uart_8250_port, port);
1526 if (iir & UART_IIR_NO_INT)
1529 spin_lock_irqsave(&port->lock, flags);
1531 status = serial_port_in(port, UART_LSR);
1533 DEBUG_INTR("status = %x...", status);
1535 if (status & (UART_LSR_DR | UART_LSR_BI))
1536 status = serial8250_rx_chars(up, status);
1537 serial8250_modem_status(up);
1538 if (status & UART_LSR_THRE)
1539 serial8250_tx_chars(up);
1541 spin_unlock_irqrestore(&port->lock, flags);
1544 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1546 static int serial8250_default_handle_irq(struct uart_port *port)
1548 unsigned int iir = serial_port_in(port, UART_IIR);
1550 return serial8250_handle_irq(port, iir);
1554 * This is the serial driver's interrupt routine.
1556 * Arjan thinks the old way was overly complex, so it got simplified.
1557 * Alan disagrees, saying that need the complexity to handle the weird
1558 * nature of ISA shared interrupts. (This is a special exception.)
1560 * In order to handle ISA shared interrupts properly, we need to check
1561 * that all ports have been serviced, and therefore the ISA interrupt
1562 * line has been de-asserted.
1564 * This means we need to loop through all ports. checking that they
1565 * don't have an interrupt pending.
1567 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1569 struct irq_info *i = dev_id;
1570 struct list_head *l, *end = NULL;
1571 int pass_counter = 0, handled = 0;
1573 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1575 spin_lock(&i->lock);
1579 struct uart_8250_port *up;
1580 struct uart_port *port;
1582 up = list_entry(l, struct uart_8250_port, list);
1585 if (port->handle_irq(port)) {
1588 } else if (end == NULL)
1593 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1594 /* If we hit this, we're dead. */
1595 printk_ratelimited(KERN_ERR
1596 "serial8250: too much work for irq%d\n", irq);
1601 spin_unlock(&i->lock);
1603 DEBUG_INTR("end.\n");
1605 return IRQ_RETVAL(handled);
1609 * To support ISA shared interrupts, we need to have one interrupt
1610 * handler that ensures that the IRQ line has been deasserted
1611 * before returning. Failing to do this will result in the IRQ
1612 * line being stuck active, and, since ISA irqs are edge triggered,
1613 * no more IRQs will be seen.
1615 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1617 spin_lock_irq(&i->lock);
1619 if (!list_empty(i->head)) {
1620 if (i->head == &up->list)
1621 i->head = i->head->next;
1622 list_del(&up->list);
1624 BUG_ON(i->head != &up->list);
1627 spin_unlock_irq(&i->lock);
1628 /* List empty so throw away the hash node */
1629 if (i->head == NULL) {
1630 hlist_del(&i->node);
1635 static int serial_link_irq_chain(struct uart_8250_port *up)
1637 struct hlist_head *h;
1638 struct hlist_node *n;
1640 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1642 mutex_lock(&hash_mutex);
1644 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1646 hlist_for_each(n, h) {
1647 i = hlist_entry(n, struct irq_info, node);
1648 if (i->irq == up->port.irq)
1653 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1655 mutex_unlock(&hash_mutex);
1658 spin_lock_init(&i->lock);
1659 i->irq = up->port.irq;
1660 hlist_add_head(&i->node, h);
1662 mutex_unlock(&hash_mutex);
1664 spin_lock_irq(&i->lock);
1667 list_add(&up->list, i->head);
1668 spin_unlock_irq(&i->lock);
1672 INIT_LIST_HEAD(&up->list);
1673 i->head = &up->list;
1674 spin_unlock_irq(&i->lock);
1675 irq_flags |= up->port.irqflags;
1676 ret = request_irq(up->port.irq, serial8250_interrupt,
1677 irq_flags, "serial", i);
1679 serial_do_unlink(i, up);
1685 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1688 struct hlist_node *n;
1689 struct hlist_head *h;
1691 mutex_lock(&hash_mutex);
1693 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1695 hlist_for_each(n, h) {
1696 i = hlist_entry(n, struct irq_info, node);
1697 if (i->irq == up->port.irq)
1702 BUG_ON(i->head == NULL);
1704 if (list_empty(i->head))
1705 free_irq(up->port.irq, i);
1707 serial_do_unlink(i, up);
1708 mutex_unlock(&hash_mutex);
1712 * This function is used to handle ports that do not have an
1713 * interrupt. This doesn't work very well for 16450's, but gives
1714 * barely passable results for a 16550A. (Although at the expense
1715 * of much CPU overhead).
1717 static void serial8250_timeout(unsigned long data)
1719 struct uart_8250_port *up = (struct uart_8250_port *)data;
1721 up->port.handle_irq(&up->port);
1722 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1725 static void serial8250_backup_timeout(unsigned long data)
1727 struct uart_8250_port *up = (struct uart_8250_port *)data;
1728 unsigned int iir, ier = 0, lsr;
1729 unsigned long flags;
1731 spin_lock_irqsave(&up->port.lock, flags);
1734 * Must disable interrupts or else we risk racing with the interrupt
1738 ier = serial_in(up, UART_IER);
1739 serial_out(up, UART_IER, 0);
1742 iir = serial_in(up, UART_IIR);
1745 * This should be a safe test for anyone who doesn't trust the
1746 * IIR bits on their UART, but it's specifically designed for
1747 * the "Diva" UART used on the management processor on many HP
1748 * ia64 and parisc boxes.
1750 lsr = serial_in(up, UART_LSR);
1751 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1752 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1753 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1754 (lsr & UART_LSR_THRE)) {
1755 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1756 iir |= UART_IIR_THRI;
1759 if (!(iir & UART_IIR_NO_INT))
1760 serial8250_tx_chars(up);
1763 serial_out(up, UART_IER, ier);
1765 spin_unlock_irqrestore(&up->port.lock, flags);
1767 /* Standard timer interval plus 0.2s to keep the port running */
1768 mod_timer(&up->timer,
1769 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1772 static unsigned int serial8250_tx_empty(struct uart_port *port)
1774 struct uart_8250_port *up =
1775 container_of(port, struct uart_8250_port, port);
1776 unsigned long flags;
1779 spin_lock_irqsave(&port->lock, flags);
1780 lsr = serial_port_in(port, UART_LSR);
1781 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1782 spin_unlock_irqrestore(&port->lock, flags);
1784 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1787 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1789 struct uart_8250_port *up =
1790 container_of(port, struct uart_8250_port, port);
1791 unsigned int status;
1794 status = serial8250_modem_status(up);
1797 if (status & UART_MSR_DCD)
1799 if (status & UART_MSR_RI)
1801 if (status & UART_MSR_DSR)
1803 if (status & UART_MSR_CTS)
1808 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1810 struct uart_8250_port *up =
1811 container_of(port, struct uart_8250_port, port);
1812 unsigned char mcr = 0;
1814 if (mctrl & TIOCM_RTS)
1815 mcr |= UART_MCR_RTS;
1816 if (mctrl & TIOCM_DTR)
1817 mcr |= UART_MCR_DTR;
1818 if (mctrl & TIOCM_OUT1)
1819 mcr |= UART_MCR_OUT1;
1820 if (mctrl & TIOCM_OUT2)
1821 mcr |= UART_MCR_OUT2;
1822 if (mctrl & TIOCM_LOOP)
1823 mcr |= UART_MCR_LOOP;
1825 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1827 serial_port_out(port, UART_MCR, mcr);
1830 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1832 struct uart_8250_port *up =
1833 container_of(port, struct uart_8250_port, port);
1834 unsigned long flags;
1836 spin_lock_irqsave(&port->lock, flags);
1837 if (break_state == -1)
1838 up->lcr |= UART_LCR_SBC;
1840 up->lcr &= ~UART_LCR_SBC;
1841 serial_port_out(port, UART_LCR, up->lcr);
1842 spin_unlock_irqrestore(&port->lock, flags);
1846 * Wait for transmitter & holding register to empty
1848 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1850 unsigned int status, tmout = 10000;
1852 /* Wait up to 10ms for the character(s) to be sent. */
1854 status = serial_in(up, UART_LSR);
1856 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1858 if ((status & bits) == bits)
1865 /* Wait up to 1s for flow control if necessary */
1866 if (up->port.flags & UPF_CONS_FLOW) {
1868 for (tmout = 1000000; tmout; tmout--) {
1869 unsigned int msr = serial_in(up, UART_MSR);
1870 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1871 if (msr & UART_MSR_CTS)
1874 touch_nmi_watchdog();
1879 #ifdef CONFIG_CONSOLE_POLL
1881 * Console polling routines for writing and reading from the uart while
1882 * in an interrupt or debug context.
1885 static int serial8250_get_poll_char(struct uart_port *port)
1887 unsigned char lsr = serial_port_in(port, UART_LSR);
1889 if (!(lsr & UART_LSR_DR))
1890 return NO_POLL_CHAR;
1892 return serial_port_in(port, UART_RX);
1896 static void serial8250_put_poll_char(struct uart_port *port,
1900 struct uart_8250_port *up =
1901 container_of(port, struct uart_8250_port, port);
1904 * First save the IER then disable the interrupts
1906 ier = serial_port_in(port, UART_IER);
1907 if (up->capabilities & UART_CAP_UUE)
1908 serial_port_out(port, UART_IER, UART_IER_UUE);
1910 serial_port_out(port, UART_IER, 0);
1912 wait_for_xmitr(up, BOTH_EMPTY);
1914 * Send the character out.
1915 * If a LF, also do CR...
1917 serial_port_out(port, UART_TX, c);
1919 wait_for_xmitr(up, BOTH_EMPTY);
1920 serial_port_out(port, UART_TX, 13);
1924 * Finally, wait for transmitter to become empty
1925 * and restore the IER
1927 wait_for_xmitr(up, BOTH_EMPTY);
1928 serial_port_out(port, UART_IER, ier);
1931 #endif /* CONFIG_CONSOLE_POLL */
1933 static int serial8250_startup(struct uart_port *port)
1935 struct uart_8250_port *up =
1936 container_of(port, struct uart_8250_port, port);
1937 unsigned long flags;
1938 unsigned char lsr, iir;
1941 port->fifosize = uart_config[up->port.type].fifo_size;
1942 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1943 up->capabilities = uart_config[up->port.type].flags;
1946 if (port->iotype != up->cur_iotype)
1947 set_io_from_upio(port);
1949 if (port->type == PORT_16C950) {
1950 /* Wake up and initialize UART */
1952 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1953 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1954 serial_port_out(port, UART_IER, 0);
1955 serial_port_out(port, UART_LCR, 0);
1956 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1957 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1958 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1959 serial_port_out(port, UART_LCR, 0);
1962 #ifdef CONFIG_SERIAL_8250_RSA
1964 * If this is an RSA port, see if we can kick it up to the
1965 * higher speed clock.
1971 * Clear the FIFO buffers and disable them.
1972 * (they will be reenabled in set_termios())
1974 serial8250_clear_fifos(up);
1977 * Clear the interrupt registers.
1979 serial_port_in(port, UART_LSR);
1980 serial_port_in(port, UART_RX);
1981 serial_port_in(port, UART_IIR);
1982 serial_port_in(port, UART_MSR);
1985 * At this point, there's no way the LSR could still be 0xff;
1986 * if it is, then bail out, because there's likely no UART
1989 if (!(port->flags & UPF_BUGGY_UART) &&
1990 (serial_port_in(port, UART_LSR) == 0xff)) {
1991 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1992 serial_index(port));
1997 * For a XR16C850, we need to set the trigger levels
1999 if (port->type == PORT_16850) {
2002 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2004 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2005 serial_port_out(port, UART_FCTR,
2006 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2007 serial_port_out(port, UART_TRG, UART_TRG_96);
2008 serial_port_out(port, UART_FCTR,
2009 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2010 serial_port_out(port, UART_TRG, UART_TRG_96);
2012 serial_port_out(port, UART_LCR, 0);
2018 * Test for UARTs that do not reassert THRE when the
2019 * transmitter is idle and the interrupt has already
2020 * been cleared. Real 16550s should always reassert
2021 * this interrupt whenever the transmitter is idle and
2022 * the interrupt is enabled. Delays are necessary to
2023 * allow register changes to become visible.
2025 spin_lock_irqsave(&port->lock, flags);
2026 if (up->port.irqflags & IRQF_SHARED)
2027 disable_irq_nosync(port->irq);
2029 wait_for_xmitr(up, UART_LSR_THRE);
2030 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2031 udelay(1); /* allow THRE to set */
2032 iir1 = serial_port_in(port, UART_IIR);
2033 serial_port_out(port, UART_IER, 0);
2034 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2035 udelay(1); /* allow a working UART time to re-assert THRE */
2036 iir = serial_port_in(port, UART_IIR);
2037 serial_port_out(port, UART_IER, 0);
2039 if (port->irqflags & IRQF_SHARED)
2040 enable_irq(port->irq);
2041 spin_unlock_irqrestore(&port->lock, flags);
2044 * If the interrupt is not reasserted, or we otherwise
2045 * don't trust the iir, setup a timer to kick the UART
2046 * on a regular basis.
2048 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2049 up->port.flags & UPF_BUG_THRE) {
2050 up->bugs |= UART_BUG_THRE;
2051 pr_debug("ttyS%d - using backup timer\n",
2052 serial_index(port));
2057 * The above check will only give an accurate result the first time
2058 * the port is opened so this value needs to be preserved.
2060 if (up->bugs & UART_BUG_THRE) {
2061 up->timer.function = serial8250_backup_timeout;
2062 up->timer.data = (unsigned long)up;
2063 mod_timer(&up->timer, jiffies +
2064 uart_poll_timeout(port) + HZ / 5);
2068 * If the "interrupt" for this port doesn't correspond with any
2069 * hardware interrupt, we use a timer-based system. The original
2070 * driver used to do this with IRQ0.
2073 up->timer.data = (unsigned long)up;
2074 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2076 retval = serial_link_irq_chain(up);
2082 * Now, initialize the UART
2084 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2086 spin_lock_irqsave(&port->lock, flags);
2087 if (up->port.flags & UPF_FOURPORT) {
2089 up->port.mctrl |= TIOCM_OUT1;
2092 * Most PC uarts need OUT2 raised to enable interrupts.
2095 up->port.mctrl |= TIOCM_OUT2;
2097 serial8250_set_mctrl(port, port->mctrl);
2099 /* Serial over Lan (SoL) hack:
2100 Intel 8257x Gigabit ethernet chips have a
2101 16550 emulation, to be used for Serial Over Lan.
2102 Those chips take a longer time than a normal
2103 serial device to signalize that a transmission
2104 data was queued. Due to that, the above test generally
2105 fails. One solution would be to delay the reading of
2106 iir. However, this is not reliable, since the timeout
2107 is variable. So, let's just don't test if we receive
2108 TX irq. This way, we'll never enable UART_BUG_TXEN.
2110 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2111 goto dont_test_tx_en;
2114 * Do a quick test to see if we receive an
2115 * interrupt when we enable the TX irq.
2117 serial_port_out(port, UART_IER, UART_IER_THRI);
2118 lsr = serial_port_in(port, UART_LSR);
2119 iir = serial_port_in(port, UART_IIR);
2120 serial_port_out(port, UART_IER, 0);
2122 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2123 if (!(up->bugs & UART_BUG_TXEN)) {
2124 up->bugs |= UART_BUG_TXEN;
2125 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2126 serial_index(port));
2129 up->bugs &= ~UART_BUG_TXEN;
2133 spin_unlock_irqrestore(&port->lock, flags);
2136 * Clear the interrupt registers again for luck, and clear the
2137 * saved flags to avoid getting false values from polling
2138 * routines or the previous session.
2140 serial_port_in(port, UART_LSR);
2141 serial_port_in(port, UART_RX);
2142 serial_port_in(port, UART_IIR);
2143 serial_port_in(port, UART_MSR);
2144 up->lsr_saved_flags = 0;
2145 up->msr_saved_flags = 0;
2148 * Finally, enable interrupts. Note: Modem status interrupts
2149 * are set via set_termios(), which will be occurring imminently
2150 * anyway, so we don't enable them here.
2152 up->ier = UART_IER_RLSI | UART_IER_RDI;
2153 serial_port_out(port, UART_IER, up->ier);
2155 if (port->flags & UPF_FOURPORT) {
2158 * Enable interrupts on the AST Fourport board
2160 icp = (port->iobase & 0xfe0) | 0x01f;
2168 static void serial8250_shutdown(struct uart_port *port)
2170 struct uart_8250_port *up =
2171 container_of(port, struct uart_8250_port, port);
2172 unsigned long flags;
2175 * Disable interrupts from this port
2178 serial_port_out(port, UART_IER, 0);
2180 spin_lock_irqsave(&port->lock, flags);
2181 if (port->flags & UPF_FOURPORT) {
2182 /* reset interrupts on the AST Fourport board */
2183 inb((port->iobase & 0xfe0) | 0x1f);
2184 port->mctrl |= TIOCM_OUT1;
2186 port->mctrl &= ~TIOCM_OUT2;
2188 serial8250_set_mctrl(port, port->mctrl);
2189 spin_unlock_irqrestore(&port->lock, flags);
2192 * Disable break condition and FIFOs
2194 serial_port_out(port, UART_LCR,
2195 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2196 serial8250_clear_fifos(up);
2198 #ifdef CONFIG_SERIAL_8250_RSA
2200 * Reset the RSA board back to 115kbps compat mode.
2206 * Read data port to reset things, and then unlink from
2209 serial_port_in(port, UART_RX);
2211 del_timer_sync(&up->timer);
2212 up->timer.function = serial8250_timeout;
2214 serial_unlink_irq_chain(up);
2217 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2222 * Handle magic divisors for baud rates above baud_base on
2223 * SMSC SuperIO chips.
2225 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2226 baud == (port->uartclk/4))
2228 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2229 baud == (port->uartclk/8))
2232 quot = uart_get_divisor(port, baud);
2238 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2239 struct ktermios *old)
2241 struct uart_8250_port *up =
2242 container_of(port, struct uart_8250_port, port);
2243 unsigned char cval, fcr = 0;
2244 unsigned long flags;
2245 unsigned int baud, quot;
2247 switch (termios->c_cflag & CSIZE) {
2249 cval = UART_LCR_WLEN5;
2252 cval = UART_LCR_WLEN6;
2255 cval = UART_LCR_WLEN7;
2259 cval = UART_LCR_WLEN8;
2263 if (termios->c_cflag & CSTOPB)
2264 cval |= UART_LCR_STOP;
2265 if (termios->c_cflag & PARENB)
2266 cval |= UART_LCR_PARITY;
2267 if (!(termios->c_cflag & PARODD))
2268 cval |= UART_LCR_EPAR;
2270 if (termios->c_cflag & CMSPAR)
2271 cval |= UART_LCR_SPAR;
2275 * Ask the core to calculate the divisor for us.
2277 baud = uart_get_baud_rate(port, termios, old,
2278 port->uartclk / 16 / 0xffff,
2279 port->uartclk / 16);
2280 quot = serial8250_get_divisor(port, baud);
2283 * Oxford Semi 952 rev B workaround
2285 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2288 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2290 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2292 fcr = uart_config[port->type].fcr;
2296 * MCR-based auto flow control. When AFE is enabled, RTS will be
2297 * deasserted when the receive FIFO contains more characters than
2298 * the trigger, or the MCR RTS bit is cleared. In the case where
2299 * the remote UART is not using CTS auto flow control, we must
2300 * have sufficient FIFO entries for the latency of the remote
2301 * UART to respond. IOW, at least 32 bytes of FIFO.
2303 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2304 up->mcr &= ~UART_MCR_AFE;
2305 if (termios->c_cflag & CRTSCTS)
2306 up->mcr |= UART_MCR_AFE;
2310 * Ok, we're now changing the port state. Do it with
2311 * interrupts disabled.
2313 spin_lock_irqsave(&port->lock, flags);
2316 * Update the per-port timeout.
2318 uart_update_timeout(port, termios->c_cflag, baud);
2320 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2321 if (termios->c_iflag & INPCK)
2322 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2323 if (termios->c_iflag & (BRKINT | PARMRK))
2324 port->read_status_mask |= UART_LSR_BI;
2327 * Characteres to ignore
2329 port->ignore_status_mask = 0;
2330 if (termios->c_iflag & IGNPAR)
2331 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2332 if (termios->c_iflag & IGNBRK) {
2333 port->ignore_status_mask |= UART_LSR_BI;
2335 * If we're ignoring parity and break indicators,
2336 * ignore overruns too (for real raw support).
2338 if (termios->c_iflag & IGNPAR)
2339 port->ignore_status_mask |= UART_LSR_OE;
2343 * ignore all characters if CREAD is not set
2345 if ((termios->c_cflag & CREAD) == 0)
2346 port->ignore_status_mask |= UART_LSR_DR;
2349 * CTS flow control flag and modem status interrupts
2351 up->ier &= ~UART_IER_MSI;
2352 if (!(up->bugs & UART_BUG_NOMSR) &&
2353 UART_ENABLE_MS(&up->port, termios->c_cflag))
2354 up->ier |= UART_IER_MSI;
2355 if (up->capabilities & UART_CAP_UUE)
2356 up->ier |= UART_IER_UUE;
2357 if (up->capabilities & UART_CAP_RTOIE)
2358 up->ier |= UART_IER_RTOIE;
2360 serial_port_out(port, UART_IER, up->ier);
2362 if (up->capabilities & UART_CAP_EFR) {
2363 unsigned char efr = 0;
2365 * TI16C752/Startech hardware flow control. FIXME:
2366 * - TI16C752 requires control thresholds to be set.
2367 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2369 if (termios->c_cflag & CRTSCTS)
2370 efr |= UART_EFR_CTS;
2372 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2373 if (port->flags & UPF_EXAR_EFR)
2374 serial_port_out(port, UART_XR_EFR, efr);
2376 serial_port_out(port, UART_EFR, efr);
2379 #ifdef CONFIG_ARCH_OMAP
2380 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2381 if (cpu_is_omap1510() && is_omap_port(up)) {
2382 if (baud == 115200) {
2384 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2386 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2391 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2392 * otherwise just set DLAB
2394 if (up->capabilities & UART_NATSEMI)
2395 serial_port_out(port, UART_LCR, 0xe0);
2397 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2399 serial_dl_write(up, quot);
2402 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2403 * is written without DLAB set, this mode will be disabled.
2405 if (port->type == PORT_16750)
2406 serial_port_out(port, UART_FCR, fcr);
2408 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2409 up->lcr = cval; /* Save LCR */
2410 if (port->type != PORT_16750) {
2411 /* emulated UARTs (Lucent Venus 167x) need two steps */
2412 if (fcr & UART_FCR_ENABLE_FIFO)
2413 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2414 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2416 serial8250_set_mctrl(port, port->mctrl);
2417 spin_unlock_irqrestore(&port->lock, flags);
2418 /* Don't rewrite B0 */
2419 if (tty_termios_baud_rate(termios))
2420 tty_termios_encode_baud_rate(termios, baud, baud);
2422 EXPORT_SYMBOL(serial8250_do_set_termios);
2425 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2426 struct ktermios *old)
2428 if (port->set_termios)
2429 port->set_termios(port, termios, old);
2431 serial8250_do_set_termios(port, termios, old);
2435 serial8250_set_ldisc(struct uart_port *port, int new)
2438 port->flags |= UPF_HARDPPS_CD;
2439 serial8250_enable_ms(port);
2441 port->flags &= ~UPF_HARDPPS_CD;
2445 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2446 unsigned int oldstate)
2448 struct uart_8250_port *p =
2449 container_of(port, struct uart_8250_port, port);
2451 serial8250_set_sleep(p, state != 0);
2453 EXPORT_SYMBOL(serial8250_do_pm);
2456 serial8250_pm(struct uart_port *port, unsigned int state,
2457 unsigned int oldstate)
2460 port->pm(port, state, oldstate);
2462 serial8250_do_pm(port, state, oldstate);
2465 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2467 if (pt->port.iotype == UPIO_AU)
2469 #ifdef CONFIG_ARCH_OMAP
2470 if (is_omap_port(pt))
2471 return 0x16 << pt->port.regshift;
2473 return 8 << pt->port.regshift;
2477 * Resource handling.
2479 static int serial8250_request_std_resource(struct uart_8250_port *up)
2481 unsigned int size = serial8250_port_size(up);
2482 struct uart_port *port = &up->port;
2485 switch (port->iotype) {
2493 if (!request_mem_region(port->mapbase, size, "serial")) {
2498 if (port->flags & UPF_IOREMAP) {
2499 port->membase = ioremap_nocache(port->mapbase, size);
2500 if (!port->membase) {
2501 release_mem_region(port->mapbase, size);
2509 if (!request_region(port->iobase, size, "serial"))
2516 static void serial8250_release_std_resource(struct uart_8250_port *up)
2518 unsigned int size = serial8250_port_size(up);
2519 struct uart_port *port = &up->port;
2521 switch (port->iotype) {
2529 if (port->flags & UPF_IOREMAP) {
2530 iounmap(port->membase);
2531 port->membase = NULL;
2534 release_mem_region(port->mapbase, size);
2539 release_region(port->iobase, size);
2544 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2546 unsigned long start = UART_RSA_BASE << up->port.regshift;
2547 unsigned int size = 8 << up->port.regshift;
2548 struct uart_port *port = &up->port;
2551 switch (port->iotype) {
2554 start += port->iobase;
2555 if (request_region(start, size, "serial-rsa"))
2565 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2567 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2568 unsigned int size = 8 << up->port.regshift;
2569 struct uart_port *port = &up->port;
2571 switch (port->iotype) {
2574 release_region(port->iobase + offset, size);
2579 static void serial8250_release_port(struct uart_port *port)
2581 struct uart_8250_port *up =
2582 container_of(port, struct uart_8250_port, port);
2584 serial8250_release_std_resource(up);
2585 if (port->type == PORT_RSA)
2586 serial8250_release_rsa_resource(up);
2589 static int serial8250_request_port(struct uart_port *port)
2591 struct uart_8250_port *up =
2592 container_of(port, struct uart_8250_port, port);
2595 ret = serial8250_request_std_resource(up);
2596 if (ret == 0 && port->type == PORT_RSA) {
2597 ret = serial8250_request_rsa_resource(up);
2599 serial8250_release_std_resource(up);
2605 static void serial8250_config_port(struct uart_port *port, int flags)
2607 struct uart_8250_port *up =
2608 container_of(port, struct uart_8250_port, port);
2609 int probeflags = PROBE_ANY;
2613 * Find the region that we can probe for. This in turn
2614 * tells us whether we can probe for the type of port.
2616 ret = serial8250_request_std_resource(up);
2620 ret = serial8250_request_rsa_resource(up);
2622 probeflags &= ~PROBE_RSA;
2624 if (port->iotype != up->cur_iotype)
2625 set_io_from_upio(port);
2627 if (flags & UART_CONFIG_TYPE)
2628 autoconfig(up, probeflags);
2630 /* if access method is AU, it is a 16550 with a quirk */
2631 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2632 up->bugs |= UART_BUG_NOMSR;
2634 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2637 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2638 serial8250_release_rsa_resource(up);
2639 if (port->type == PORT_UNKNOWN)
2640 serial8250_release_std_resource(up);
2644 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2646 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2647 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2648 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2649 ser->type == PORT_STARTECH)
2655 serial8250_type(struct uart_port *port)
2657 int type = port->type;
2659 if (type >= ARRAY_SIZE(uart_config))
2661 return uart_config[type].name;
2664 static struct uart_ops serial8250_pops = {
2665 .tx_empty = serial8250_tx_empty,
2666 .set_mctrl = serial8250_set_mctrl,
2667 .get_mctrl = serial8250_get_mctrl,
2668 .stop_tx = serial8250_stop_tx,
2669 .start_tx = serial8250_start_tx,
2670 .stop_rx = serial8250_stop_rx,
2671 .enable_ms = serial8250_enable_ms,
2672 .break_ctl = serial8250_break_ctl,
2673 .startup = serial8250_startup,
2674 .shutdown = serial8250_shutdown,
2675 .set_termios = serial8250_set_termios,
2676 .set_ldisc = serial8250_set_ldisc,
2677 .pm = serial8250_pm,
2678 .type = serial8250_type,
2679 .release_port = serial8250_release_port,
2680 .request_port = serial8250_request_port,
2681 .config_port = serial8250_config_port,
2682 .verify_port = serial8250_verify_port,
2683 #ifdef CONFIG_CONSOLE_POLL
2684 .poll_get_char = serial8250_get_poll_char,
2685 .poll_put_char = serial8250_put_poll_char,
2689 static struct uart_8250_port serial8250_ports[UART_NR];
2691 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2692 unsigned short *capabilities);
2694 void serial8250_set_isa_configurator(
2695 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2697 serial8250_isa_config = v;
2699 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2701 static void __init serial8250_isa_init_ports(void)
2703 struct uart_8250_port *up;
2704 static int first = 1;
2711 for (i = 0; i < nr_uarts; i++) {
2712 struct uart_8250_port *up = &serial8250_ports[i];
2713 struct uart_port *port = &up->port;
2716 spin_lock_init(&port->lock);
2718 init_timer(&up->timer);
2719 up->timer.function = serial8250_timeout;
2722 * ALPHA_KLUDGE_MCR needs to be killed.
2724 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2725 up->mcr_force = ALPHA_KLUDGE_MCR;
2727 port->ops = &serial8250_pops;
2731 irqflag = IRQF_SHARED;
2733 for (i = 0, up = serial8250_ports;
2734 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2736 struct uart_port *port = &up->port;
2738 port->iobase = old_serial_port[i].port;
2739 port->irq = irq_canonicalize(old_serial_port[i].irq);
2740 port->irqflags = old_serial_port[i].irqflags;
2741 port->uartclk = old_serial_port[i].baud_base * 16;
2742 port->flags = old_serial_port[i].flags;
2743 port->hub6 = old_serial_port[i].hub6;
2744 port->membase = old_serial_port[i].iomem_base;
2745 port->iotype = old_serial_port[i].io_type;
2746 port->regshift = old_serial_port[i].iomem_reg_shift;
2747 set_io_from_upio(port);
2748 port->irqflags |= irqflag;
2749 if (serial8250_isa_config != NULL)
2750 serial8250_isa_config(i, &up->port, &up->capabilities);
2756 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2758 up->port.type = type;
2759 up->port.fifosize = uart_config[type].fifo_size;
2760 up->capabilities = uart_config[type].flags;
2761 up->tx_loadsz = uart_config[type].tx_loadsz;
2765 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2769 for (i = 0; i < nr_uarts; i++) {
2770 struct uart_8250_port *up = &serial8250_ports[i];
2771 up->cur_iotype = 0xFF;
2774 serial8250_isa_init_ports();
2776 for (i = 0; i < nr_uarts; i++) {
2777 struct uart_8250_port *up = &serial8250_ports[i];
2781 if (up->port.flags & UPF_FIXED_TYPE)
2782 serial8250_init_fixed_type_port(up, up->port.type);
2784 uart_add_one_port(drv, &up->port);
2788 #ifdef CONFIG_SERIAL_8250_CONSOLE
2790 static void serial8250_console_putchar(struct uart_port *port, int ch)
2792 struct uart_8250_port *up =
2793 container_of(port, struct uart_8250_port, port);
2795 wait_for_xmitr(up, UART_LSR_THRE);
2796 serial_port_out(port, UART_TX, ch);
2800 * Print a string to the serial port trying not to disturb
2801 * any possible real use of the port...
2803 * The console_lock must be held when we get here.
2806 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2808 struct uart_8250_port *up = &serial8250_ports[co->index];
2809 struct uart_port *port = &up->port;
2810 unsigned long flags;
2814 touch_nmi_watchdog();
2816 local_irq_save(flags);
2818 /* serial8250_handle_irq() already took the lock */
2820 } else if (oops_in_progress) {
2821 locked = spin_trylock(&port->lock);
2823 spin_lock(&port->lock);
2826 * First save the IER then disable the interrupts
2828 ier = serial_port_in(port, UART_IER);
2830 if (up->capabilities & UART_CAP_UUE)
2831 serial_port_out(port, UART_IER, UART_IER_UUE);
2833 serial_port_out(port, UART_IER, 0);
2835 uart_console_write(port, s, count, serial8250_console_putchar);
2838 * Finally, wait for transmitter to become empty
2839 * and restore the IER
2841 wait_for_xmitr(up, BOTH_EMPTY);
2842 serial_port_out(port, UART_IER, ier);
2845 * The receive handling will happen properly because the
2846 * receive ready bit will still be set; it is not cleared
2847 * on read. However, modem control will not, we must
2848 * call it if we have saved something in the saved flags
2849 * while processing with interrupts off.
2851 if (up->msr_saved_flags)
2852 serial8250_modem_status(up);
2855 spin_unlock(&port->lock);
2856 local_irq_restore(flags);
2859 static int __init serial8250_console_setup(struct console *co, char *options)
2861 struct uart_port *port;
2868 * Check whether an invalid uart number has been specified, and
2869 * if so, search for the first available port that does have
2872 if (co->index >= nr_uarts)
2874 port = &serial8250_ports[co->index].port;
2875 if (!port->iobase && !port->membase)
2879 uart_parse_options(options, &baud, &parity, &bits, &flow);
2881 return uart_set_options(port, co, baud, parity, bits, flow);
2884 static int serial8250_console_early_setup(void)
2886 return serial8250_find_port_for_earlycon();
2889 static struct console serial8250_console = {
2891 .write = serial8250_console_write,
2892 .device = uart_console_device,
2893 .setup = serial8250_console_setup,
2894 .early_setup = serial8250_console_early_setup,
2895 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2897 .data = &serial8250_reg,
2900 static int __init serial8250_console_init(void)
2902 if (nr_uarts > UART_NR)
2905 serial8250_isa_init_ports();
2906 register_console(&serial8250_console);
2909 console_initcall(serial8250_console_init);
2911 int serial8250_find_port(struct uart_port *p)
2914 struct uart_port *port;
2916 for (line = 0; line < nr_uarts; line++) {
2917 port = &serial8250_ports[line].port;
2918 if (uart_match_port(p, port))
2924 #define SERIAL8250_CONSOLE &serial8250_console
2926 #define SERIAL8250_CONSOLE NULL
2929 static struct uart_driver serial8250_reg = {
2930 .owner = THIS_MODULE,
2931 .driver_name = "serial",
2935 .cons = SERIAL8250_CONSOLE,
2939 * early_serial_setup - early registration for 8250 ports
2941 * Setup an 8250 port structure prior to console initialisation. Use
2942 * after console initialisation will cause undefined behaviour.
2944 int __init early_serial_setup(struct uart_port *port)
2946 struct uart_port *p;
2948 if (port->line >= ARRAY_SIZE(serial8250_ports))
2951 serial8250_isa_init_ports();
2952 p = &serial8250_ports[port->line].port;
2953 p->iobase = port->iobase;
2954 p->membase = port->membase;
2956 p->irqflags = port->irqflags;
2957 p->uartclk = port->uartclk;
2958 p->fifosize = port->fifosize;
2959 p->regshift = port->regshift;
2960 p->iotype = port->iotype;
2961 p->flags = port->flags;
2962 p->mapbase = port->mapbase;
2963 p->private_data = port->private_data;
2964 p->type = port->type;
2965 p->line = port->line;
2967 set_io_from_upio(p);
2968 if (port->serial_in)
2969 p->serial_in = port->serial_in;
2970 if (port->serial_out)
2971 p->serial_out = port->serial_out;
2972 if (port->handle_irq)
2973 p->handle_irq = port->handle_irq;
2975 p->handle_irq = serial8250_default_handle_irq;
2981 * serial8250_suspend_port - suspend one serial port
2982 * @line: serial line number
2984 * Suspend one serial port.
2986 void serial8250_suspend_port(int line)
2988 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2992 * serial8250_resume_port - resume one serial port
2993 * @line: serial line number
2995 * Resume one serial port.
2997 void serial8250_resume_port(int line)
2999 struct uart_8250_port *up = &serial8250_ports[line];
3000 struct uart_port *port = &up->port;
3002 if (up->capabilities & UART_NATSEMI) {
3003 /* Ensure it's still in high speed mode */
3004 serial_port_out(port, UART_LCR, 0xE0);
3006 ns16550a_goto_highspeed(up);
3008 serial_port_out(port, UART_LCR, 0);
3009 port->uartclk = 921600*16;
3011 uart_resume_port(&serial8250_reg, port);
3015 * Register a set of serial devices attached to a platform device. The
3016 * list is terminated with a zero flags entry, which means we expect
3017 * all entries to have at least UPF_BOOT_AUTOCONF set.
3019 static int __devinit serial8250_probe(struct platform_device *dev)
3021 struct plat_serial8250_port *p = dev->dev.platform_data;
3022 struct uart_port port;
3023 int ret, i, irqflag = 0;
3025 memset(&port, 0, sizeof(struct uart_port));
3028 irqflag = IRQF_SHARED;
3030 for (i = 0; p && p->flags != 0; p++, i++) {
3031 port.iobase = p->iobase;
3032 port.membase = p->membase;
3034 port.irqflags = p->irqflags;
3035 port.uartclk = p->uartclk;
3036 port.regshift = p->regshift;
3037 port.iotype = p->iotype;
3038 port.flags = p->flags;
3039 port.mapbase = p->mapbase;
3040 port.hub6 = p->hub6;
3041 port.private_data = p->private_data;
3042 port.type = p->type;
3043 port.serial_in = p->serial_in;
3044 port.serial_out = p->serial_out;
3045 port.handle_irq = p->handle_irq;
3046 port.set_termios = p->set_termios;
3048 port.dev = &dev->dev;
3049 port.irqflags |= irqflag;
3050 ret = serial8250_register_port(&port);
3052 dev_err(&dev->dev, "unable to register port at index %d "
3053 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3054 p->iobase, (unsigned long long)p->mapbase,
3062 * Remove serial ports registered against a platform device.
3064 static int __devexit serial8250_remove(struct platform_device *dev)
3068 for (i = 0; i < nr_uarts; i++) {
3069 struct uart_8250_port *up = &serial8250_ports[i];
3071 if (up->port.dev == &dev->dev)
3072 serial8250_unregister_port(i);
3077 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3081 for (i = 0; i < UART_NR; i++) {
3082 struct uart_8250_port *up = &serial8250_ports[i];
3084 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3085 uart_suspend_port(&serial8250_reg, &up->port);
3091 static int serial8250_resume(struct platform_device *dev)
3095 for (i = 0; i < UART_NR; i++) {
3096 struct uart_8250_port *up = &serial8250_ports[i];
3098 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3099 serial8250_resume_port(i);
3105 static struct platform_driver serial8250_isa_driver = {
3106 .probe = serial8250_probe,
3107 .remove = __devexit_p(serial8250_remove),
3108 .suspend = serial8250_suspend,
3109 .resume = serial8250_resume,
3111 .name = "serial8250",
3112 .owner = THIS_MODULE,
3117 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3118 * in the table in include/asm/serial.h
3120 static struct platform_device *serial8250_isa_devs;
3123 * serial8250_register_port and serial8250_unregister_port allows for
3124 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3125 * modems and PCI multiport cards.
3127 static DEFINE_MUTEX(serial_mutex);
3129 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3134 * First, find a port entry which matches.
3136 for (i = 0; i < nr_uarts; i++)
3137 if (uart_match_port(&serial8250_ports[i].port, port))
3138 return &serial8250_ports[i];
3141 * We didn't find a matching entry, so look for the first
3142 * free entry. We look for one which hasn't been previously
3143 * used (indicated by zero iobase).
3145 for (i = 0; i < nr_uarts; i++)
3146 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3147 serial8250_ports[i].port.iobase == 0)
3148 return &serial8250_ports[i];
3151 * That also failed. Last resort is to find any entry which
3152 * doesn't have a real port associated with it.
3154 for (i = 0; i < nr_uarts; i++)
3155 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3156 return &serial8250_ports[i];
3162 * serial8250_register_port - register a serial port
3163 * @port: serial port template
3165 * Configure the serial port specified by the request. If the
3166 * port exists and is in use, it is hung up and unregistered
3169 * The port is then probed and if necessary the IRQ is autodetected
3170 * If this fails an error is returned.
3172 * On success the port is ready to use and the line number is returned.
3174 int serial8250_register_port(struct uart_port *port)
3176 struct uart_8250_port *uart;
3179 if (port->uartclk == 0)
3182 mutex_lock(&serial_mutex);
3184 uart = serial8250_find_match_or_unused(port);
3186 uart_remove_one_port(&serial8250_reg, &uart->port);
3188 uart->port.iobase = port->iobase;
3189 uart->port.membase = port->membase;
3190 uart->port.irq = port->irq;
3191 uart->port.irqflags = port->irqflags;
3192 uart->port.uartclk = port->uartclk;
3193 uart->port.fifosize = port->fifosize;
3194 uart->port.regshift = port->regshift;
3195 uart->port.iotype = port->iotype;
3196 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3197 uart->port.mapbase = port->mapbase;
3198 uart->port.private_data = port->private_data;
3200 uart->port.dev = port->dev;
3202 if (port->flags & UPF_FIXED_TYPE)
3203 serial8250_init_fixed_type_port(uart, port->type);
3205 set_io_from_upio(&uart->port);
3206 /* Possibly override default I/O functions. */
3207 if (port->serial_in)
3208 uart->port.serial_in = port->serial_in;
3209 if (port->serial_out)
3210 uart->port.serial_out = port->serial_out;
3211 if (port->handle_irq)
3212 uart->port.handle_irq = port->handle_irq;
3213 /* Possibly override set_termios call */
3214 if (port->set_termios)
3215 uart->port.set_termios = port->set_termios;
3217 uart->port.pm = port->pm;
3219 if (serial8250_isa_config != NULL)
3220 serial8250_isa_config(0, &uart->port,
3221 &uart->capabilities);
3223 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3225 ret = uart->port.line;
3227 mutex_unlock(&serial_mutex);
3231 EXPORT_SYMBOL(serial8250_register_port);
3234 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3235 * @line: serial line number
3237 * Remove one serial port. This may not be called from interrupt
3238 * context. We hand the port back to the our control.
3240 void serial8250_unregister_port(int line)
3242 struct uart_8250_port *uart = &serial8250_ports[line];
3244 mutex_lock(&serial_mutex);
3245 uart_remove_one_port(&serial8250_reg, &uart->port);
3246 if (serial8250_isa_devs) {
3247 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3248 uart->port.type = PORT_UNKNOWN;
3249 uart->port.dev = &serial8250_isa_devs->dev;
3250 uart->capabilities = uart_config[uart->port.type].flags;
3251 uart_add_one_port(&serial8250_reg, &uart->port);
3253 uart->port.dev = NULL;
3255 mutex_unlock(&serial_mutex);
3257 EXPORT_SYMBOL(serial8250_unregister_port);
3259 static int __init serial8250_init(void)
3263 if (nr_uarts > UART_NR)
3266 printk(KERN_INFO "Serial: 8250/16550 driver, "
3267 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3268 share_irqs ? "en" : "dis");
3271 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3273 serial8250_reg.nr = UART_NR;
3274 ret = uart_register_driver(&serial8250_reg);
3279 serial8250_isa_devs = platform_device_alloc("serial8250",
3280 PLAT8250_DEV_LEGACY);
3281 if (!serial8250_isa_devs) {
3283 goto unreg_uart_drv;
3286 ret = platform_device_add(serial8250_isa_devs);
3290 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3292 ret = platform_driver_register(&serial8250_isa_driver);
3296 platform_device_del(serial8250_isa_devs);
3298 platform_device_put(serial8250_isa_devs);
3301 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3303 uart_unregister_driver(&serial8250_reg);
3309 static void __exit serial8250_exit(void)
3311 struct platform_device *isa_dev = serial8250_isa_devs;
3314 * This tells serial8250_unregister_port() not to re-register
3315 * the ports (thereby making serial8250_isa_driver permanently
3318 serial8250_isa_devs = NULL;
3320 platform_driver_unregister(&serial8250_isa_driver);
3321 platform_device_unregister(isa_dev);
3324 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3326 uart_unregister_driver(&serial8250_reg);
3330 module_init(serial8250_init);
3331 module_exit(serial8250_exit);
3333 EXPORT_SYMBOL(serial8250_suspend_port);
3334 EXPORT_SYMBOL(serial8250_resume_port);
3336 MODULE_LICENSE("GPL");
3337 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3339 module_param(share_irqs, uint, 0644);
3340 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3343 module_param(nr_uarts, uint, 0644);
3344 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3346 module_param(skip_txen_test, uint, 0644);
3347 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3349 #ifdef CONFIG_SERIAL_8250_RSA
3350 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3351 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3353 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);