2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 static DEFINE_MUTEX(mce_read_mutex);
51 #define rcu_dereference_check_mce(p) \
52 rcu_dereference_check((p), \
53 rcu_read_lock_sched_held() || \
54 lockdep_is_held(&mce_read_mutex))
56 #define CREATE_TRACE_POINTS
57 #include <trace/events/mce.h>
59 int mce_disabled __read_mostly;
61 #define MISC_MCELOG_MINOR 227
63 #define SPINUNIT 100 /* 100ns */
67 DEFINE_PER_CPU(unsigned, mce_exception_count);
71 * 0: always panic on uncorrected errors, log corrected errors
72 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
73 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
74 * 3: never panic or SIGBUS, log all errors (for testing only)
76 static int tolerant __read_mostly = 1;
77 static int banks __read_mostly;
78 static int rip_msr __read_mostly;
79 static int mce_bootlog __read_mostly = -1;
80 static int monarch_timeout __read_mostly = -1;
81 static int mce_panic_timeout __read_mostly;
82 static int mce_dont_log_ce __read_mostly;
83 int mce_cmci_disabled __read_mostly;
84 int mce_ignore_ce __read_mostly;
85 int mce_ser __read_mostly;
87 struct mce_bank *mce_banks __read_mostly;
89 /* User mode helper program triggered by machine check event */
90 static unsigned long mce_need_notify;
91 static char mce_helper[128];
92 static char *mce_helper_argv[2] = { mce_helper, NULL };
94 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
97 void (*mce_cpu_specific_poll)(struct mce *);
98 EXPORT_SYMBOL_GPL(mce_cpu_specific_poll);
101 * CPU/chipset specific EDAC code can register a notifier call here to print
102 * MCE errors in a human-readable form.
104 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
105 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
107 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
110 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
111 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
116 static struct notifier_block mce_dec_nb = {
117 .notifier_call = default_decode_mce,
121 /* MCA banks polled by the period polling timer for corrected events */
122 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
123 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
126 static DEFINE_PER_CPU(struct work_struct, mce_work);
128 /* Do initial initialization of a struct mce */
129 void mce_setup(struct mce *m)
131 memset(m, 0, sizeof(struct mce));
132 m->cpu = m->extcpu = smp_processor_id();
134 /* We hope get_seconds stays lockless */
135 m->time = get_seconds();
136 m->cpuvendor = boot_cpu_data.x86_vendor;
137 m->cpuid = cpuid_eax(1);
139 m->socketid = cpu_data(m->extcpu).phys_proc_id;
141 m->apicid = cpu_data(m->extcpu).initial_apicid;
142 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
145 DEFINE_PER_CPU(struct mce, injectm);
146 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
149 * Lockless MCE logging infrastructure.
150 * This avoids deadlocks on printk locks without having to break locks. Also
151 * separate MCEs from kernel messages to avoid bogus bug reports.
154 static struct mce_log mcelog = {
155 .signature = MCE_LOG_SIGNATURE,
157 .recordlen = sizeof(struct mce),
160 void mce_log(struct mce *mce)
162 unsigned next, entry;
164 /* Emit the trace record: */
165 trace_mce_record(mce);
170 entry = rcu_dereference_check_mce(mcelog.next);
173 * When the buffer fills up discard new entries.
174 * Assume that the earlier errors are the more
177 if (entry >= MCE_LOG_LEN) {
178 set_bit(MCE_OVERFLOW,
179 (unsigned long *)&mcelog.flags);
182 /* Old left over entry. Skip: */
183 if (mcelog.entry[entry].finished) {
191 if (cmpxchg(&mcelog.next, entry, next) == entry)
194 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
196 mcelog.entry[entry].finished = 1;
200 set_bit(0, &mce_need_notify);
203 static void print_mce(struct mce *m)
205 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
206 m->extcpu, m->mcgstatus, m->bank, m->status);
209 pr_emerg("RIP%s %02x:<%016Lx> ",
210 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
213 if (m->cs == __KERNEL_CS)
214 print_symbol("{%s}", m->ip);
218 pr_emerg("TSC %llx ", m->tsc);
220 pr_cont("ADDR %llx ", m->addr);
222 pr_cont("MISC %llx ", m->misc);
225 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
226 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
229 * Print out human-readable details about the MCE error,
230 * (if the CPU has an implementation for that)
232 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
235 static void print_mce_head(void)
237 pr_emerg("\nHARDWARE ERROR\n");
240 static void print_mce_tail(void)
242 pr_emerg("This is not a software problem!\n");
245 #define PANIC_TIMEOUT 5 /* 5 seconds */
247 static atomic_t mce_paniced;
249 static int fake_panic;
250 static atomic_t mce_fake_paniced;
252 /* Panic in progress. Enable interrupts and wait for final IPI */
253 static void wait_for_panic(void)
255 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
259 while (timeout-- > 0)
261 if (panic_timeout == 0)
262 panic_timeout = mce_panic_timeout;
263 panic("Panicing machine check CPU died");
266 static void mce_panic(char *msg, struct mce *final, char *exp)
272 * Make sure only one CPU runs in machine check panic
274 if (atomic_inc_return(&mce_paniced) > 1)
281 /* Don't log too much for fake panic */
282 if (atomic_inc_return(&mce_fake_paniced) > 1)
286 /* First print corrected ones that are still unlogged */
287 for (i = 0; i < MCE_LOG_LEN; i++) {
288 struct mce *m = &mcelog.entry[i];
289 if (!(m->status & MCI_STATUS_VAL))
291 if (!(m->status & MCI_STATUS_UC))
294 /* Now print uncorrected but with the final one last */
295 for (i = 0; i < MCE_LOG_LEN; i++) {
296 struct mce *m = &mcelog.entry[i];
297 if (!(m->status & MCI_STATUS_VAL))
299 if (!(m->status & MCI_STATUS_UC))
301 if (!final || memcmp(m, final, sizeof(struct mce)))
307 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
310 printk(KERN_EMERG "Machine check: %s\n", exp);
312 if (panic_timeout == 0)
313 panic_timeout = mce_panic_timeout;
316 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
319 /* Support code for software error injection */
321 static int msr_to_offset(u32 msr)
323 unsigned bank = __get_cpu_var(injectm.bank);
326 return offsetof(struct mce, ip);
327 if (msr == MSR_IA32_MCx_STATUS(bank))
328 return offsetof(struct mce, status);
329 if (msr == MSR_IA32_MCx_ADDR(bank))
330 return offsetof(struct mce, addr);
331 if (msr == MSR_IA32_MCx_MISC(bank))
332 return offsetof(struct mce, misc);
333 if (msr == MSR_IA32_MCG_STATUS)
334 return offsetof(struct mce, mcgstatus);
338 /* MSR access wrappers used for error injection */
339 static u64 mce_rdmsrl(u32 msr)
343 if (__get_cpu_var(injectm).finished) {
344 int offset = msr_to_offset(msr);
348 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
351 if (rdmsrl_safe(msr, &v)) {
352 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
354 * Return zero in case the access faulted. This should
355 * not happen normally but can happen if the CPU does
356 * something weird, or if the code is buggy.
364 static void mce_wrmsrl(u32 msr, u64 v)
366 if (__get_cpu_var(injectm).finished) {
367 int offset = msr_to_offset(msr);
370 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
376 static int under_injection(void)
378 return __get_cpu_var(injectm).finished;
382 * Simple lockless ring to communicate PFNs from the exception handler with the
383 * process context work function. This is vastly simplified because there's
384 * only a single reader and a single writer.
386 #define MCE_RING_SIZE 16 /* we use one entry less */
389 unsigned short start;
391 unsigned long ring[MCE_RING_SIZE];
393 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
395 /* Runs with CPU affinity in workqueue */
396 static int mce_ring_empty(void)
398 struct mce_ring *r = &__get_cpu_var(mce_ring);
400 return r->start == r->end;
403 static int mce_ring_get(unsigned long *pfn)
410 r = &__get_cpu_var(mce_ring);
411 if (r->start == r->end)
413 *pfn = r->ring[r->start];
414 r->start = (r->start + 1) % MCE_RING_SIZE;
421 /* Always runs in MCE context with preempt off */
422 static int mce_ring_add(unsigned long pfn)
424 struct mce_ring *r = &__get_cpu_var(mce_ring);
427 next = (r->end + 1) % MCE_RING_SIZE;
428 if (next == r->start)
430 r->ring[r->end] = pfn;
436 int mce_available(struct cpuinfo_x86 *c)
440 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
443 static void mce_schedule_work(void)
445 if (!mce_ring_empty()) {
446 struct work_struct *work = &__get_cpu_var(mce_work);
447 if (!work_pending(work))
453 * Get the address of the instruction at the time of the machine check
456 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
459 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
467 m->ip = mce_rdmsrl(rip_msr);
470 #ifdef CONFIG_X86_LOCAL_APIC
472 * Called after interrupts have been reenabled again
473 * when a MCE happened during an interrupts off region
476 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
487 static void mce_report_event(struct pt_regs *regs)
489 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
492 * Triggering the work queue here is just an insurance
493 * policy in case the syscall exit notify handler
494 * doesn't run soon enough or ends up running on the
495 * wrong CPU (can happen when audit sleeps)
501 #ifdef CONFIG_X86_LOCAL_APIC
503 * Without APIC do not notify. The event will be picked
510 * When interrupts are disabled we cannot use
511 * kernel services safely. Trigger an self interrupt
512 * through the APIC to instead do the notification
513 * after interrupts are reenabled again.
515 apic->send_IPI_self(MCE_SELF_VECTOR);
518 * Wait for idle afterwards again so that we don't leave the
519 * APIC in a non idle state because the normal APIC writes
522 apic_wait_icr_idle();
526 DEFINE_PER_CPU(unsigned, mce_poll_count);
529 * Poll for corrected events or events that happened before reset.
530 * Those are just logged through /dev/mcelog.
532 * This is executed in standard interrupt context.
534 * Note: spec recommends to panic for fatal unsignalled
535 * errors here. However this would be quite problematic --
536 * we would need to reimplement the Monarch handling and
537 * it would mess up the exclusion between exception handler
538 * and poll hander -- * so we skip this for now.
539 * These cases should not happen anyways, or only when the CPU
540 * is already totally * confused. In this case it's likely it will
541 * not fully execute the machine check handler either.
543 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
548 __get_cpu_var(mce_poll_count)++;
552 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
553 for (i = 0; i < banks; i++) {
554 if (!mce_banks[i].ctl || !test_bit(i, *b))
563 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
564 if (!(m.status & MCI_STATUS_VAL))
568 * Uncorrected or signalled events are handled by the exception
569 * handler when it is enabled, so don't process those here.
571 * TBD do the same check for MCI_STATUS_EN here?
573 if (!(flags & MCP_UC) &&
574 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
577 if (m.status & MCI_STATUS_MISCV)
578 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
579 if (m.status & MCI_STATUS_ADDRV)
580 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
582 if (!(flags & MCP_TIMESTAMP))
585 if (mce_cpu_specific_poll && !under_injection() && !mce_dont_log_ce)
586 mce_cpu_specific_poll(&m);
589 * Don't get the IP here because it's unlikely to
590 * have anything to do with the actual error location.
592 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
594 add_taint(TAINT_MACHINE_CHECK);
598 * Clear state for this bank.
600 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
604 * Don't clear MCG_STATUS here because it's only defined for
610 EXPORT_SYMBOL_GPL(machine_check_poll);
613 * Do a quick check if any of the events requires a panic.
614 * This decides if we keep the events around or clear them.
616 static int mce_no_way_out(struct mce *m, char **msg)
620 for (i = 0; i < banks; i++) {
621 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
622 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
629 * Variable to establish order between CPUs while scanning.
630 * Each CPU spins initially until executing is equal its number.
632 static atomic_t mce_executing;
635 * Defines order of CPUs on entry. First CPU becomes Monarch.
637 static atomic_t mce_callin;
640 * Check if a timeout waiting for other CPUs happened.
642 static int mce_timed_out(u64 *t)
645 * The others already did panic for some reason.
646 * Bail out like in a timeout.
647 * rmb() to tell the compiler that system_state
648 * might have been modified by someone else.
651 if (atomic_read(&mce_paniced))
653 if (!monarch_timeout)
655 if ((s64)*t < SPINUNIT) {
656 /* CHECKME: Make panic default for 1 too? */
658 mce_panic("Timeout synchronizing machine check over CPUs",
665 touch_nmi_watchdog();
670 * The Monarch's reign. The Monarch is the CPU who entered
671 * the machine check handler first. It waits for the others to
672 * raise the exception too and then grades them. When any
673 * error is fatal panic. Only then let the others continue.
675 * The other CPUs entering the MCE handler will be controlled by the
676 * Monarch. They are called Subjects.
678 * This way we prevent any potential data corruption in a unrecoverable case
679 * and also makes sure always all CPU's errors are examined.
681 * Also this detects the case of a machine check event coming from outer
682 * space (not detected by any CPUs) In this case some external agent wants
683 * us to shut down, so panic too.
685 * The other CPUs might still decide to panic if the handler happens
686 * in a unrecoverable place, but in this case the system is in a semi-stable
687 * state and won't corrupt anything by itself. It's ok to let the others
688 * continue for a bit first.
690 * All the spin loops have timeouts; when a timeout happens a CPU
691 * typically elects itself to be Monarch.
693 static void mce_reign(void)
696 struct mce *m = NULL;
697 int global_worst = 0;
702 * This CPU is the Monarch and the other CPUs have run
703 * through their handlers.
704 * Grade the severity of the errors of all the CPUs.
706 for_each_possible_cpu(cpu) {
707 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
709 if (severity > global_worst) {
711 global_worst = severity;
712 m = &per_cpu(mces_seen, cpu);
717 * Cannot recover? Panic here then.
718 * This dumps all the mces in the log buffer and stops the
721 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
722 mce_panic("Fatal Machine check", m, msg);
725 * For UC somewhere we let the CPU who detects it handle it.
726 * Also must let continue the others, otherwise the handling
727 * CPU could deadlock on a lock.
731 * No machine check event found. Must be some external
732 * source or one CPU is hung. Panic.
734 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
735 mce_panic("Machine check from unknown source", NULL, NULL);
738 * Now clear all the mces_seen so that they don't reappear on
741 for_each_possible_cpu(cpu)
742 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
745 static atomic_t global_nwo;
748 * Start of Monarch synchronization. This waits until all CPUs have
749 * entered the exception handler and then determines if any of them
750 * saw a fatal event that requires panic. Then it executes them
751 * in the entry order.
752 * TBD double check parallel CPU hotunplug
754 static int mce_start(int *no_way_out)
757 int cpus = num_online_cpus();
758 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
763 atomic_add(*no_way_out, &global_nwo);
765 * global_nwo should be updated before mce_callin
768 order = atomic_inc_return(&mce_callin);
773 while (atomic_read(&mce_callin) != cpus) {
774 if (mce_timed_out(&timeout)) {
775 atomic_set(&global_nwo, 0);
782 * mce_callin should be read before global_nwo
788 * Monarch: Starts executing now, the others wait.
790 atomic_set(&mce_executing, 1);
793 * Subject: Now start the scanning loop one by one in
794 * the original callin order.
795 * This way when there are any shared banks it will be
796 * only seen by one CPU before cleared, avoiding duplicates.
798 while (atomic_read(&mce_executing) < order) {
799 if (mce_timed_out(&timeout)) {
800 atomic_set(&global_nwo, 0);
808 * Cache the global no_way_out state.
810 *no_way_out = atomic_read(&global_nwo);
816 * Synchronize between CPUs after main scanning loop.
817 * This invokes the bulk of the Monarch processing.
819 static int mce_end(int order)
822 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
830 * Allow others to run.
832 atomic_inc(&mce_executing);
835 /* CHECKME: Can this race with a parallel hotplug? */
836 int cpus = num_online_cpus();
839 * Monarch: Wait for everyone to go through their scanning
842 while (atomic_read(&mce_executing) <= cpus) {
843 if (mce_timed_out(&timeout))
853 * Subject: Wait for Monarch to finish.
855 while (atomic_read(&mce_executing) != 0) {
856 if (mce_timed_out(&timeout))
862 * Don't reset anything. That's done by the Monarch.
868 * Reset all global state.
871 atomic_set(&global_nwo, 0);
872 atomic_set(&mce_callin, 0);
876 * Let others run again.
878 atomic_set(&mce_executing, 0);
883 * Check if the address reported by the CPU is in a format we can parse.
884 * It would be possible to add code for most other cases, but all would
885 * be somewhat complicated (e.g. segment offset would require an instruction
886 * parser). So only support physical addresses upto page granuality for now.
888 static int mce_usable_address(struct mce *m)
890 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
892 if ((m->misc & 0x3f) > PAGE_SHIFT)
894 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
899 static void mce_clear_state(unsigned long *toclear)
903 for (i = 0; i < banks; i++) {
904 if (test_bit(i, toclear))
905 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
910 * The actual machine check handler. This only handles real
911 * exceptions when something got corrupted coming in through int 18.
913 * This is executed in NMI context not subject to normal locking rules. This
914 * implies that most kernel services cannot be safely used. Don't even
915 * think about putting a printk in there!
917 * On Intel systems this is entered on all CPUs in parallel through
918 * MCE broadcast. However some CPUs might be broken beyond repair,
919 * so be always careful when synchronizing with others.
921 void do_machine_check(struct pt_regs *regs, long error_code)
923 struct mce m, *final;
928 * Establish sequential order between the CPUs entering the machine
933 * If no_way_out gets set, there is no safe way to recover from this
934 * MCE. If tolerant is cranked up, we'll try anyway.
938 * If kill_it gets set, there might be a way to recover from this
942 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
943 char *msg = "Unknown";
945 atomic_inc(&mce_entry);
947 __get_cpu_var(mce_exception_count)++;
949 if (notify_die(DIE_NMI, "machine check", regs, error_code,
950 18, SIGKILL) == NOTIFY_STOP)
957 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
958 final = &__get_cpu_var(mces_seen);
961 no_way_out = mce_no_way_out(&m, &msg);
966 * When no restart IP must always kill or panic.
968 if (!(m.mcgstatus & MCG_STATUS_RIPV))
972 * Go through all the banks in exclusion of the other CPUs.
973 * This way we don't report duplicated events on shared banks
974 * because the first one to see it will clear it.
976 order = mce_start(&no_way_out);
977 for (i = 0; i < banks; i++) {
978 __clear_bit(i, toclear);
979 if (!mce_banks[i].ctl)
986 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
987 if ((m.status & MCI_STATUS_VAL) == 0)
991 * Non uncorrected or non signaled errors are handled by
992 * machine_check_poll. Leave them alone, unless this panics.
994 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
999 * Set taint even when machine check was not enabled.
1001 add_taint(TAINT_MACHINE_CHECK);
1003 severity = mce_severity(&m, tolerant, NULL);
1006 * When machine check was for corrected handler don't touch,
1007 * unless we're panicing.
1009 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1011 __set_bit(i, toclear);
1012 if (severity == MCE_NO_SEVERITY) {
1014 * Machine check event was not enabled. Clear, but
1021 * Kill on action required.
1023 if (severity == MCE_AR_SEVERITY)
1026 if (m.status & MCI_STATUS_MISCV)
1027 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1028 if (m.status & MCI_STATUS_ADDRV)
1029 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1032 * Action optional error. Queue address for later processing.
1033 * When the ring overflows we just ignore the AO error.
1034 * RED-PEN add some logging mechanism when
1035 * usable_address or mce_add_ring fails.
1036 * RED-PEN don't ignore overflow for tolerant == 0
1038 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1039 mce_ring_add(m.addr >> PAGE_SHIFT);
1041 mce_get_rip(&m, regs);
1044 if (severity > worst) {
1051 mce_clear_state(toclear);
1054 * Do most of the synchronization with other CPUs.
1055 * When there's any problem use only local no_way_out state.
1057 if (mce_end(order) < 0)
1058 no_way_out = worst >= MCE_PANIC_SEVERITY;
1061 * If we have decided that we just CAN'T continue, and the user
1062 * has not set tolerant to an insane level, give up and die.
1064 * This is mainly used in the case when the system doesn't
1065 * support MCE broadcasting or it has been disabled.
1067 if (no_way_out && tolerant < 3)
1068 mce_panic("Fatal machine check on current CPU", final, msg);
1071 * If the error seems to be unrecoverable, something should be
1072 * done. Try to kill as little as possible. If we can kill just
1073 * one task, do that. If the user has set the tolerance very
1074 * high, don't try to do anything at all.
1077 if (kill_it && tolerant < 3)
1078 force_sig(SIGBUS, current);
1080 /* notify userspace ASAP */
1081 set_thread_flag(TIF_MCE_NOTIFY);
1084 mce_report_event(regs);
1085 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1087 atomic_dec(&mce_entry);
1090 EXPORT_SYMBOL_GPL(do_machine_check);
1092 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1093 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1095 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1099 * Called after mce notification in process context. This code
1100 * is allowed to sleep. Call the high level VM handler to process
1101 * any corrupted pages.
1102 * Assume that the work queue code only calls this one at a time
1104 * Note we don't disable preemption, so this code might run on the wrong
1105 * CPU. In this case the event is picked up by the scheduled work queue.
1106 * This is merely a fast path to expedite processing in some common
1109 void mce_notify_process(void)
1113 while (mce_ring_get(&pfn))
1114 memory_failure(pfn, MCE_VECTOR);
1117 static void mce_process_work(struct work_struct *dummy)
1119 mce_notify_process();
1122 #ifdef CONFIG_X86_MCE_INTEL
1124 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1125 * @cpu: The CPU on which the event occurred.
1126 * @status: Event status information
1128 * This function should be called by the thermal interrupt after the
1129 * event has been processed and the decision was made to log the event
1132 * The status parameter will be saved to the 'status' field of 'struct mce'
1133 * and historically has been the register value of the
1134 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1136 void mce_log_therm_throt_event(__u64 status)
1141 m.bank = MCE_THERMAL_BANK;
1145 #endif /* CONFIG_X86_MCE_INTEL */
1148 * Periodic polling timer for "silent" machine check errors. If the
1149 * poller finds an MCE, poll 2x faster. When the poller finds no more
1150 * errors, poll 2x slower (up to check_interval seconds).
1152 static int check_interval = 5 * 60; /* 5 minutes */
1154 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1155 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1157 static void mce_start_timer(unsigned long data)
1159 struct timer_list *t = &per_cpu(mce_timer, data);
1162 WARN_ON(smp_processor_id() != data);
1164 if (mce_available(¤t_cpu_data)) {
1165 machine_check_poll(MCP_TIMESTAMP,
1166 &__get_cpu_var(mce_poll_banks));
1170 * Alert userspace if needed. If we logged an MCE, reduce the
1171 * polling interval, otherwise increase the polling interval.
1173 n = &__get_cpu_var(mce_next_interval);
1174 if (mce_notify_irq())
1175 *n = max(*n/2, HZ/100);
1177 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1179 t->expires = jiffies + *n;
1180 add_timer_on(t, smp_processor_id());
1183 static void mce_do_trigger(struct work_struct *work)
1185 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1188 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1191 * Notify the user(s) about new machine check events.
1192 * Can be called from interrupt context, but not from machine check/NMI
1195 int mce_notify_irq(void)
1197 /* Not more than two messages every minute */
1198 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1200 clear_thread_flag(TIF_MCE_NOTIFY);
1202 if (test_and_clear_bit(0, &mce_need_notify)) {
1203 wake_up_interruptible(&mce_wait);
1206 * There is no risk of missing notifications because
1207 * work_pending is always cleared before the function is
1210 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1211 schedule_work(&mce_trigger_work);
1213 if (__ratelimit(&ratelimit))
1214 printk(KERN_INFO "Machine check events logged\n");
1220 EXPORT_SYMBOL_GPL(mce_notify_irq);
1222 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1226 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1229 for (i = 0; i < banks; i++) {
1230 struct mce_bank *b = &mce_banks[i];
1239 * Initialize Machine Checks for a CPU.
1241 static int __cpuinit __mcheck_cpu_cap_init(void)
1246 rdmsrl(MSR_IA32_MCG_CAP, cap);
1248 b = cap & MCG_BANKCNT_MASK;
1250 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1252 if (b > MAX_NR_BANKS) {
1254 "MCE: Using only %u machine check banks out of %u\n",
1259 /* Don't support asymmetric configurations today */
1260 WARN_ON(banks != 0 && b != banks);
1263 int err = __mcheck_cpu_mce_banks_init();
1269 /* Use accurate RIP reporting if available. */
1270 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1271 rip_msr = MSR_IA32_MCG_EIP;
1273 if (cap & MCG_SER_P)
1279 static void __mcheck_cpu_init_generic(void)
1281 mce_banks_t all_banks;
1286 * Log the machine checks left over from the previous reset.
1288 bitmap_fill(all_banks, MAX_NR_BANKS);
1289 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1291 set_in_cr4(X86_CR4_MCE);
1293 rdmsrl(MSR_IA32_MCG_CAP, cap);
1294 if (cap & MCG_CTL_P)
1295 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1297 for (i = 0; i < banks; i++) {
1298 struct mce_bank *b = &mce_banks[i];
1302 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1303 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1307 /* Add per CPU specific workarounds here */
1308 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1310 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1311 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1315 /* This should be disabled by the BIOS, but isn't always */
1316 if (c->x86_vendor == X86_VENDOR_AMD) {
1317 if (c->x86 == 15 && banks > 4) {
1319 * disable GART TBL walk error reporting, which
1320 * trips off incorrectly with the IOMMU & 3ware
1323 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1325 if (c->x86 <= 17 && mce_bootlog < 0) {
1327 * Lots of broken BIOS around that don't clear them
1328 * by default and leave crap in there. Don't log:
1333 * Various K7s with broken bank 0 around. Always disable
1336 if (c->x86 == 6 && banks > 0)
1337 mce_banks[0].ctl = 0;
1340 if (c->x86_vendor == X86_VENDOR_INTEL) {
1342 * SDM documents that on family 6 bank 0 should not be written
1343 * because it aliases to another special BIOS controlled
1345 * But it's not aliased anymore on model 0x1a+
1346 * Don't ignore bank 0 completely because there could be a
1347 * valid event later, merely don't write CTL0.
1350 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1351 mce_banks[0].init = 0;
1354 * All newer Intel systems support MCE broadcasting. Enable
1355 * synchronization with a one second timeout.
1357 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1358 monarch_timeout < 0)
1359 monarch_timeout = USEC_PER_SEC;
1362 * There are also broken BIOSes on some Pentium M and
1365 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1368 if (monarch_timeout < 0)
1369 monarch_timeout = 0;
1370 if (mce_bootlog != 0)
1371 mce_panic_timeout = 30;
1376 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1380 switch (c->x86_vendor) {
1381 case X86_VENDOR_INTEL:
1382 intel_p5_mcheck_init(c);
1384 case X86_VENDOR_CENTAUR:
1385 winchip_mcheck_init(c);
1390 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1392 switch (c->x86_vendor) {
1393 case X86_VENDOR_INTEL:
1394 mce_intel_feature_init(c);
1396 case X86_VENDOR_AMD:
1397 mce_amd_feature_init(c);
1404 static void __mcheck_cpu_init_timer(void)
1406 struct timer_list *t = &__get_cpu_var(mce_timer);
1407 int *n = &__get_cpu_var(mce_next_interval);
1409 setup_timer(t, mce_start_timer, smp_processor_id());
1414 *n = check_interval * HZ;
1417 t->expires = round_jiffies(jiffies + *n);
1418 add_timer_on(t, smp_processor_id());
1421 /* Handle unconfigured int18 (should never happen) */
1422 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1424 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1425 smp_processor_id());
1428 /* Call the installed machine check handler for this CPU setup. */
1429 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1430 unexpected_machine_check;
1433 * Called for each booted CPU to set up machine checks.
1434 * Must be called with preempt off:
1436 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1441 __mcheck_cpu_ancient_init(c);
1443 if (!mce_available(c))
1446 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1451 machine_check_vector = do_machine_check;
1453 __mcheck_cpu_init_generic();
1454 __mcheck_cpu_init_vendor(c);
1455 __mcheck_cpu_init_timer();
1456 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1461 * Character device to read and clear the MCE log.
1464 static DEFINE_SPINLOCK(mce_state_lock);
1465 static int open_count; /* #times opened */
1466 static int open_exclu; /* already open exclusive? */
1468 static int mce_open(struct inode *inode, struct file *file)
1470 spin_lock(&mce_state_lock);
1472 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1473 spin_unlock(&mce_state_lock);
1478 if (file->f_flags & O_EXCL)
1482 spin_unlock(&mce_state_lock);
1484 return nonseekable_open(inode, file);
1487 static int mce_release(struct inode *inode, struct file *file)
1489 spin_lock(&mce_state_lock);
1494 spin_unlock(&mce_state_lock);
1499 static void collect_tscs(void *data)
1501 unsigned long *cpu_tsc = (unsigned long *)data;
1503 rdtscll(cpu_tsc[smp_processor_id()]);
1506 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1509 char __user *buf = ubuf;
1510 unsigned long *cpu_tsc;
1511 unsigned prev, next;
1514 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1518 mutex_lock(&mce_read_mutex);
1519 next = rcu_dereference_check_mce(mcelog.next);
1521 /* Only supports full reads right now */
1522 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1523 mutex_unlock(&mce_read_mutex);
1532 for (i = prev; i < next; i++) {
1533 unsigned long start = jiffies;
1535 while (!mcelog.entry[i].finished) {
1536 if (time_after_eq(jiffies, start + 2)) {
1537 memset(mcelog.entry + i, 0,
1538 sizeof(struct mce));
1544 err |= copy_to_user(buf, mcelog.entry + i,
1545 sizeof(struct mce));
1546 buf += sizeof(struct mce);
1551 memset(mcelog.entry + prev, 0,
1552 (next - prev) * sizeof(struct mce));
1554 next = cmpxchg(&mcelog.next, prev, 0);
1555 } while (next != prev);
1557 synchronize_sched();
1560 * Collect entries that were still getting written before the
1563 on_each_cpu(collect_tscs, cpu_tsc, 1);
1565 for (i = next; i < MCE_LOG_LEN; i++) {
1566 if (mcelog.entry[i].finished &&
1567 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1568 err |= copy_to_user(buf, mcelog.entry+i,
1569 sizeof(struct mce));
1571 buf += sizeof(struct mce);
1572 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1575 mutex_unlock(&mce_read_mutex);
1578 return err ? -EFAULT : buf - ubuf;
1581 static unsigned int mce_poll(struct file *file, poll_table *wait)
1583 poll_wait(file, &mce_wait, wait);
1584 if (rcu_dereference_check_mce(mcelog.next))
1585 return POLLIN | POLLRDNORM;
1589 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1591 int __user *p = (int __user *)arg;
1593 if (!capable(CAP_SYS_ADMIN))
1597 case MCE_GET_RECORD_LEN:
1598 return put_user(sizeof(struct mce), p);
1599 case MCE_GET_LOG_LEN:
1600 return put_user(MCE_LOG_LEN, p);
1601 case MCE_GETCLEAR_FLAGS: {
1605 flags = mcelog.flags;
1606 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1608 return put_user(flags, p);
1615 /* Modified in mce-inject.c, so not static or const */
1616 struct file_operations mce_chrdev_ops = {
1618 .release = mce_release,
1621 .unlocked_ioctl = mce_ioctl,
1623 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1625 static struct miscdevice mce_log_device = {
1632 * mce=off Disables machine check
1633 * mce=no_cmci Disables CMCI
1634 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1635 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1636 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1637 * monarchtimeout is how long to wait for other CPUs on machine
1638 * check, or 0 to not wait
1639 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1640 * mce=nobootlog Don't log MCEs from before booting.
1642 static int __init mcheck_enable(char *str)
1650 if (!strcmp(str, "off"))
1652 else if (!strcmp(str, "no_cmci"))
1653 mce_cmci_disabled = 1;
1654 else if (!strcmp(str, "dont_log_ce"))
1655 mce_dont_log_ce = 1;
1656 else if (!strcmp(str, "ignore_ce"))
1658 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1659 mce_bootlog = (str[0] == 'b');
1660 else if (isdigit(str[0])) {
1661 get_option(&str, &tolerant);
1664 get_option(&str, &monarch_timeout);
1667 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1673 __setup("mce", mcheck_enable);
1675 int __init mcheck_init(void)
1677 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1679 mcheck_intel_therm_init();
1689 * Disable machine checks on suspend and shutdown. We can't really handle
1692 static int mce_disable_error_reporting(void)
1696 for (i = 0; i < banks; i++) {
1697 struct mce_bank *b = &mce_banks[i];
1700 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1705 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1707 return mce_disable_error_reporting();
1710 static int mce_shutdown(struct sys_device *dev)
1712 return mce_disable_error_reporting();
1716 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1717 * Only one CPU is active at this time, the others get re-added later using
1720 static int mce_resume(struct sys_device *dev)
1722 __mcheck_cpu_init_generic();
1723 __mcheck_cpu_init_vendor(¤t_cpu_data);
1728 static void mce_cpu_restart(void *data)
1730 del_timer_sync(&__get_cpu_var(mce_timer));
1731 if (!mce_available(¤t_cpu_data))
1733 __mcheck_cpu_init_generic();
1734 __mcheck_cpu_init_timer();
1737 /* Reinit MCEs after user configuration changes */
1738 static void mce_restart(void)
1740 on_each_cpu(mce_cpu_restart, NULL, 1);
1743 /* Toggle features for corrected errors */
1744 static void mce_disable_ce(void *all)
1746 if (!mce_available(¤t_cpu_data))
1749 del_timer_sync(&__get_cpu_var(mce_timer));
1753 static void mce_enable_ce(void *all)
1755 if (!mce_available(¤t_cpu_data))
1760 __mcheck_cpu_init_timer();
1763 static struct sysdev_class mce_sysclass = {
1764 .suspend = mce_suspend,
1765 .shutdown = mce_shutdown,
1766 .resume = mce_resume,
1767 .name = "machinecheck",
1770 DEFINE_PER_CPU(struct sys_device, mce_dev);
1773 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1775 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1777 return container_of(attr, struct mce_bank, attr);
1780 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1783 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1786 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1787 const char *buf, size_t size)
1791 if (strict_strtoull(buf, 0, &new) < 0)
1794 attr_to_bank(attr)->ctl = new;
1801 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1803 strcpy(buf, mce_helper);
1805 return strlen(mce_helper) + 1;
1808 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1809 const char *buf, size_t siz)
1813 strncpy(mce_helper, buf, sizeof(mce_helper));
1814 mce_helper[sizeof(mce_helper)-1] = 0;
1815 p = strchr(mce_helper, '\n');
1820 return strlen(mce_helper) + !!p;
1823 static ssize_t set_ignore_ce(struct sys_device *s,
1824 struct sysdev_attribute *attr,
1825 const char *buf, size_t size)
1829 if (strict_strtoull(buf, 0, &new) < 0)
1832 if (mce_ignore_ce ^ !!new) {
1834 /* disable ce features */
1835 on_each_cpu(mce_disable_ce, (void *)1, 1);
1838 /* enable ce features */
1840 on_each_cpu(mce_enable_ce, (void *)1, 1);
1846 static ssize_t set_cmci_disabled(struct sys_device *s,
1847 struct sysdev_attribute *attr,
1848 const char *buf, size_t size)
1852 if (strict_strtoull(buf, 0, &new) < 0)
1855 if (mce_cmci_disabled ^ !!new) {
1858 on_each_cpu(mce_disable_ce, NULL, 1);
1859 mce_cmci_disabled = 1;
1862 mce_cmci_disabled = 0;
1863 on_each_cpu(mce_enable_ce, NULL, 1);
1869 static ssize_t store_int_with_restart(struct sys_device *s,
1870 struct sysdev_attribute *attr,
1871 const char *buf, size_t size)
1873 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1878 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1879 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1880 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1881 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1883 static struct sysdev_ext_attribute attr_check_interval = {
1884 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1885 store_int_with_restart),
1889 static struct sysdev_ext_attribute attr_ignore_ce = {
1890 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1894 static struct sysdev_ext_attribute attr_cmci_disabled = {
1895 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1899 static struct sysdev_attribute *mce_attrs[] = {
1900 &attr_tolerant.attr,
1901 &attr_check_interval.attr,
1903 &attr_monarch_timeout.attr,
1904 &attr_dont_log_ce.attr,
1905 &attr_ignore_ce.attr,
1906 &attr_cmci_disabled.attr,
1910 static cpumask_var_t mce_dev_initialized;
1912 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1913 static __cpuinit int mce_create_device(unsigned int cpu)
1918 if (!mce_available(&boot_cpu_data))
1921 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1922 per_cpu(mce_dev, cpu).id = cpu;
1923 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1925 err = sysdev_register(&per_cpu(mce_dev, cpu));
1929 for (i = 0; mce_attrs[i]; i++) {
1930 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1934 for (j = 0; j < banks; j++) {
1935 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1936 &mce_banks[j].attr);
1940 cpumask_set_cpu(cpu, mce_dev_initialized);
1945 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1948 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1950 sysdev_unregister(&per_cpu(mce_dev, cpu));
1955 static __cpuinit void mce_remove_device(unsigned int cpu)
1959 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1962 for (i = 0; mce_attrs[i]; i++)
1963 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1965 for (i = 0; i < banks; i++)
1966 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1968 sysdev_unregister(&per_cpu(mce_dev, cpu));
1969 cpumask_clear_cpu(cpu, mce_dev_initialized);
1972 /* Make sure there are no machine checks on offlined CPUs. */
1973 static void __cpuinit mce_disable_cpu(void *h)
1975 unsigned long action = *(unsigned long *)h;
1978 if (!mce_available(¤t_cpu_data))
1981 if (!(action & CPU_TASKS_FROZEN))
1983 for (i = 0; i < banks; i++) {
1984 struct mce_bank *b = &mce_banks[i];
1987 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1991 static void __cpuinit mce_reenable_cpu(void *h)
1993 unsigned long action = *(unsigned long *)h;
1996 if (!mce_available(¤t_cpu_data))
1999 if (!(action & CPU_TASKS_FROZEN))
2001 for (i = 0; i < banks; i++) {
2002 struct mce_bank *b = &mce_banks[i];
2005 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2009 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2010 static int __cpuinit
2011 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2013 unsigned int cpu = (unsigned long)hcpu;
2014 struct timer_list *t = &per_cpu(mce_timer, cpu);
2018 case CPU_ONLINE_FROZEN:
2019 mce_create_device(cpu);
2020 if (threshold_cpu_callback)
2021 threshold_cpu_callback(action, cpu);
2024 case CPU_DEAD_FROZEN:
2025 if (threshold_cpu_callback)
2026 threshold_cpu_callback(action, cpu);
2027 mce_remove_device(cpu);
2029 case CPU_DOWN_PREPARE:
2030 case CPU_DOWN_PREPARE_FROZEN:
2032 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2034 case CPU_DOWN_FAILED:
2035 case CPU_DOWN_FAILED_FROZEN:
2036 if (!mce_ignore_ce && check_interval) {
2037 t->expires = round_jiffies(jiffies +
2038 __get_cpu_var(mce_next_interval));
2039 add_timer_on(t, cpu);
2041 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2044 /* intentionally ignoring frozen here */
2045 cmci_rediscover(cpu);
2051 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2052 .notifier_call = mce_cpu_callback,
2055 static __init void mce_init_banks(void)
2059 for (i = 0; i < banks; i++) {
2060 struct mce_bank *b = &mce_banks[i];
2061 struct sysdev_attribute *a = &b->attr;
2063 sysfs_attr_init(&a->attr);
2064 a->attr.name = b->attrname;
2065 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2067 a->attr.mode = 0644;
2068 a->show = show_bank;
2069 a->store = set_bank;
2073 static __init int mcheck_init_device(void)
2078 if (!mce_available(&boot_cpu_data))
2081 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2085 err = sysdev_class_register(&mce_sysclass);
2089 for_each_online_cpu(i) {
2090 err = mce_create_device(i);
2095 register_hotcpu_notifier(&mce_cpu_notifier);
2096 misc_register(&mce_log_device);
2101 device_initcall(mcheck_init_device);
2104 * Old style boot options parsing. Only for compatibility.
2106 static int __init mcheck_disable(char *str)
2111 __setup("nomce", mcheck_disable);
2113 #ifdef CONFIG_DEBUG_FS
2114 struct dentry *mce_get_debugfs_dir(void)
2116 static struct dentry *dmce;
2119 dmce = debugfs_create_dir("mce", NULL);
2124 static void mce_reset(void)
2127 atomic_set(&mce_fake_paniced, 0);
2128 atomic_set(&mce_executing, 0);
2129 atomic_set(&mce_callin, 0);
2130 atomic_set(&global_nwo, 0);
2133 static int fake_panic_get(void *data, u64 *val)
2139 static int fake_panic_set(void *data, u64 val)
2146 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2147 fake_panic_set, "%llu\n");
2149 static int __init mcheck_debugfs_init(void)
2151 struct dentry *dmce, *ffake_panic;
2153 dmce = mce_get_debugfs_dir();
2156 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2163 late_initcall(mcheck_debugfs_init);