2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/device.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
98 /* MCA banks polled by the period polling timer for corrected events */
99 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
100 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
103 static DEFINE_PER_CPU(struct work_struct, mce_work);
106 * CPU/chipset specific EDAC code can register a notifier call here to print
107 * MCE errors in a human-readable form.
109 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
111 /* Do initial initialization of a struct mce */
112 void mce_setup(struct mce *m)
114 memset(m, 0, sizeof(struct mce));
115 m->cpu = m->extcpu = smp_processor_id();
117 /* We hope get_seconds stays lockless */
118 m->time = get_seconds();
119 m->cpuvendor = boot_cpu_data.x86_vendor;
120 m->cpuid = cpuid_eax(1);
122 m->socketid = cpu_data(m->extcpu).phys_proc_id;
123 m->apicid = cpu_data(m->extcpu).initial_apicid;
125 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
128 DEFINE_PER_CPU(struct mce, injectm);
129 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
132 * Lockless MCE logging infrastructure.
133 * This avoids deadlocks on printk locks without having to break locks. Also
134 * separate MCEs from kernel messages to avoid bogus bug reports.
137 static struct mce_log mcelog = {
138 .signature = MCE_LOG_SIGNATURE,
140 .recordlen = sizeof(struct mce),
143 void mce_log(struct mce *mce)
145 unsigned next, entry;
148 /* Emit the trace record: */
149 trace_mce_record(mce);
151 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
152 if (ret == NOTIFY_STOP)
158 entry = rcu_dereference_check_mce(mcelog.next);
162 * When the buffer fills up discard new entries.
163 * Assume that the earlier errors are the more
166 if (entry >= MCE_LOG_LEN) {
167 set_bit(MCE_OVERFLOW,
168 (unsigned long *)&mcelog.flags);
171 /* Old left over entry. Skip: */
172 if (mcelog.entry[entry].finished) {
180 if (cmpxchg(&mcelog.next, entry, next) == entry)
183 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
185 mcelog.entry[entry].finished = 1;
189 set_bit(0, &mce_need_notify);
192 static void drain_mcelog_buffer(void)
194 unsigned int next, i, prev = 0;
196 next = ACCESS_ONCE(mcelog.next);
201 /* drain what was logged during boot */
202 for (i = prev; i < next; i++) {
203 unsigned long start = jiffies;
204 unsigned retries = 1;
206 m = &mcelog.entry[i];
208 while (!m->finished) {
209 if (time_after_eq(jiffies, start + 2*retries))
214 if (!m->finished && retries >= 4) {
215 pr_err("MCE: skipping error being logged currently!\n");
220 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
223 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
225 next = cmpxchg(&mcelog.next, prev, 0);
226 } while (next != prev);
230 void mce_register_decode_chain(struct notifier_block *nb)
232 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
233 drain_mcelog_buffer();
235 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
237 void mce_unregister_decode_chain(struct notifier_block *nb)
239 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
241 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
243 static void print_mce(struct mce *m)
247 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
248 m->extcpu, m->mcgstatus, m->bank, m->status);
251 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
252 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
255 if (m->cs == __KERNEL_CS)
256 print_symbol("{%s}", m->ip);
260 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
262 pr_cont("ADDR %llx ", m->addr);
264 pr_cont("MISC %llx ", m->misc);
268 * Note this output is parsed by external tools and old fields
269 * should not be changed.
272 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
273 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
274 cpu_data(m->extcpu).microcode);
276 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
277 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
281 * Print out human-readable details about the MCE error,
282 * (if the CPU has an implementation for that)
284 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
285 if (ret == NOTIFY_STOP)
288 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
291 #define PANIC_TIMEOUT 5 /* 5 seconds */
293 static atomic_t mce_paniced;
295 static int fake_panic;
296 static atomic_t mce_fake_paniced;
298 /* Panic in progress. Enable interrupts and wait for final IPI */
299 static void wait_for_panic(void)
301 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
305 while (timeout-- > 0)
307 if (panic_timeout == 0)
308 panic_timeout = mce_panic_timeout;
309 panic("Panicing machine check CPU died");
312 static void mce_panic(char *msg, struct mce *final, char *exp)
318 * Make sure only one CPU runs in machine check panic
320 if (atomic_inc_return(&mce_paniced) > 1)
327 /* Don't log too much for fake panic */
328 if (atomic_inc_return(&mce_fake_paniced) > 1)
331 /* First print corrected ones that are still unlogged */
332 for (i = 0; i < MCE_LOG_LEN; i++) {
333 struct mce *m = &mcelog.entry[i];
334 if (!(m->status & MCI_STATUS_VAL))
336 if (!(m->status & MCI_STATUS_UC)) {
339 apei_err = apei_write_mce(m);
342 /* Now print uncorrected but with the final one last */
343 for (i = 0; i < MCE_LOG_LEN; i++) {
344 struct mce *m = &mcelog.entry[i];
345 if (!(m->status & MCI_STATUS_VAL))
347 if (!(m->status & MCI_STATUS_UC))
349 if (!final || memcmp(m, final, sizeof(struct mce))) {
352 apei_err = apei_write_mce(m);
358 apei_err = apei_write_mce(final);
361 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
363 pr_emerg(HW_ERR "Machine check: %s\n", exp);
365 if (panic_timeout == 0)
366 panic_timeout = mce_panic_timeout;
369 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
372 /* Support code for software error injection */
374 static int msr_to_offset(u32 msr)
376 unsigned bank = __this_cpu_read(injectm.bank);
379 return offsetof(struct mce, ip);
380 if (msr == MSR_IA32_MCx_STATUS(bank))
381 return offsetof(struct mce, status);
382 if (msr == MSR_IA32_MCx_ADDR(bank))
383 return offsetof(struct mce, addr);
384 if (msr == MSR_IA32_MCx_MISC(bank))
385 return offsetof(struct mce, misc);
386 if (msr == MSR_IA32_MCG_STATUS)
387 return offsetof(struct mce, mcgstatus);
391 /* MSR access wrappers used for error injection */
392 static u64 mce_rdmsrl(u32 msr)
396 if (__this_cpu_read(injectm.finished)) {
397 int offset = msr_to_offset(msr);
401 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
404 if (rdmsrl_safe(msr, &v)) {
405 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
407 * Return zero in case the access faulted. This should
408 * not happen normally but can happen if the CPU does
409 * something weird, or if the code is buggy.
417 static void mce_wrmsrl(u32 msr, u64 v)
419 if (__this_cpu_read(injectm.finished)) {
420 int offset = msr_to_offset(msr);
423 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
430 * Collect all global (w.r.t. this processor) status about this machine
431 * check into our "mce" struct so that we can use it later to assess
432 * the severity of the problem as we read per-bank specific details.
434 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
438 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
441 * Get the address of the instruction at the time of
442 * the machine check error.
444 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
448 /* Use accurate RIP reporting if available. */
450 m->ip = mce_rdmsrl(rip_msr);
455 * Simple lockless ring to communicate PFNs from the exception handler with the
456 * process context work function. This is vastly simplified because there's
457 * only a single reader and a single writer.
459 #define MCE_RING_SIZE 16 /* we use one entry less */
462 unsigned short start;
464 unsigned long ring[MCE_RING_SIZE];
466 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
468 /* Runs with CPU affinity in workqueue */
469 static int mce_ring_empty(void)
471 struct mce_ring *r = &__get_cpu_var(mce_ring);
473 return r->start == r->end;
476 static int mce_ring_get(unsigned long *pfn)
483 r = &__get_cpu_var(mce_ring);
484 if (r->start == r->end)
486 *pfn = r->ring[r->start];
487 r->start = (r->start + 1) % MCE_RING_SIZE;
494 /* Always runs in MCE context with preempt off */
495 static int mce_ring_add(unsigned long pfn)
497 struct mce_ring *r = &__get_cpu_var(mce_ring);
500 next = (r->end + 1) % MCE_RING_SIZE;
501 if (next == r->start)
503 r->ring[r->end] = pfn;
509 int mce_available(struct cpuinfo_x86 *c)
513 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
516 static void mce_schedule_work(void)
518 if (!mce_ring_empty()) {
519 struct work_struct *work = &__get_cpu_var(mce_work);
520 if (!work_pending(work))
525 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
527 static void mce_irq_work_cb(struct irq_work *entry)
533 static void mce_report_event(struct pt_regs *regs)
535 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
538 * Triggering the work queue here is just an insurance
539 * policy in case the syscall exit notify handler
540 * doesn't run soon enough or ends up running on the
541 * wrong CPU (can happen when audit sleeps)
547 irq_work_queue(&__get_cpu_var(mce_irq_work));
551 * Read ADDR and MISC registers.
553 static void mce_read_aux(struct mce *m, int i)
555 if (m->status & MCI_STATUS_MISCV)
556 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
557 if (m->status & MCI_STATUS_ADDRV) {
558 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
561 * Mask the reported address by the reported granularity.
563 if (mce_ser && (m->status & MCI_STATUS_MISCV)) {
564 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
571 DEFINE_PER_CPU(unsigned, mce_poll_count);
574 * Poll for corrected events or events that happened before reset.
575 * Those are just logged through /dev/mcelog.
577 * This is executed in standard interrupt context.
579 * Note: spec recommends to panic for fatal unsignalled
580 * errors here. However this would be quite problematic --
581 * we would need to reimplement the Monarch handling and
582 * it would mess up the exclusion between exception handler
583 * and poll hander -- * so we skip this for now.
584 * These cases should not happen anyways, or only when the CPU
585 * is already totally * confused. In this case it's likely it will
586 * not fully execute the machine check handler either.
588 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
593 percpu_inc(mce_poll_count);
595 mce_gather_info(&m, NULL);
597 for (i = 0; i < banks; i++) {
598 if (!mce_banks[i].ctl || !test_bit(i, *b))
607 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
608 if (!(m.status & MCI_STATUS_VAL))
612 * Uncorrected or signalled events are handled by the exception
613 * handler when it is enabled, so don't process those here.
615 * TBD do the same check for MCI_STATUS_EN here?
617 if (!(flags & MCP_UC) &&
618 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
623 if (!(flags & MCP_TIMESTAMP))
626 * Don't get the IP here because it's unlikely to
627 * have anything to do with the actual error location.
629 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
633 * Clear state for this bank.
635 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
639 * Don't clear MCG_STATUS here because it's only defined for
645 EXPORT_SYMBOL_GPL(machine_check_poll);
648 * Do a quick check if any of the events requires a panic.
649 * This decides if we keep the events around or clear them.
651 static int mce_no_way_out(struct mce *m, char **msg)
655 for (i = 0; i < banks; i++) {
656 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
657 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
664 * Variable to establish order between CPUs while scanning.
665 * Each CPU spins initially until executing is equal its number.
667 static atomic_t mce_executing;
670 * Defines order of CPUs on entry. First CPU becomes Monarch.
672 static atomic_t mce_callin;
675 * Check if a timeout waiting for other CPUs happened.
677 static int mce_timed_out(u64 *t)
680 * The others already did panic for some reason.
681 * Bail out like in a timeout.
682 * rmb() to tell the compiler that system_state
683 * might have been modified by someone else.
686 if (atomic_read(&mce_paniced))
688 if (!monarch_timeout)
690 if ((s64)*t < SPINUNIT) {
691 /* CHECKME: Make panic default for 1 too? */
693 mce_panic("Timeout synchronizing machine check over CPUs",
700 touch_nmi_watchdog();
705 * The Monarch's reign. The Monarch is the CPU who entered
706 * the machine check handler first. It waits for the others to
707 * raise the exception too and then grades them. When any
708 * error is fatal panic. Only then let the others continue.
710 * The other CPUs entering the MCE handler will be controlled by the
711 * Monarch. They are called Subjects.
713 * This way we prevent any potential data corruption in a unrecoverable case
714 * and also makes sure always all CPU's errors are examined.
716 * Also this detects the case of a machine check event coming from outer
717 * space (not detected by any CPUs) In this case some external agent wants
718 * us to shut down, so panic too.
720 * The other CPUs might still decide to panic if the handler happens
721 * in a unrecoverable place, but in this case the system is in a semi-stable
722 * state and won't corrupt anything by itself. It's ok to let the others
723 * continue for a bit first.
725 * All the spin loops have timeouts; when a timeout happens a CPU
726 * typically elects itself to be Monarch.
728 static void mce_reign(void)
731 struct mce *m = NULL;
732 int global_worst = 0;
737 * This CPU is the Monarch and the other CPUs have run
738 * through their handlers.
739 * Grade the severity of the errors of all the CPUs.
741 for_each_possible_cpu(cpu) {
742 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
744 if (severity > global_worst) {
746 global_worst = severity;
747 m = &per_cpu(mces_seen, cpu);
752 * Cannot recover? Panic here then.
753 * This dumps all the mces in the log buffer and stops the
756 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
757 mce_panic("Fatal Machine check", m, msg);
760 * For UC somewhere we let the CPU who detects it handle it.
761 * Also must let continue the others, otherwise the handling
762 * CPU could deadlock on a lock.
766 * No machine check event found. Must be some external
767 * source or one CPU is hung. Panic.
769 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
770 mce_panic("Machine check from unknown source", NULL, NULL);
773 * Now clear all the mces_seen so that they don't reappear on
776 for_each_possible_cpu(cpu)
777 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
780 static atomic_t global_nwo;
783 * Start of Monarch synchronization. This waits until all CPUs have
784 * entered the exception handler and then determines if any of them
785 * saw a fatal event that requires panic. Then it executes them
786 * in the entry order.
787 * TBD double check parallel CPU hotunplug
789 static int mce_start(int *no_way_out)
792 int cpus = num_online_cpus();
793 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
798 atomic_add(*no_way_out, &global_nwo);
800 * global_nwo should be updated before mce_callin
803 order = atomic_inc_return(&mce_callin);
808 while (atomic_read(&mce_callin) != cpus) {
809 if (mce_timed_out(&timeout)) {
810 atomic_set(&global_nwo, 0);
817 * mce_callin should be read before global_nwo
823 * Monarch: Starts executing now, the others wait.
825 atomic_set(&mce_executing, 1);
828 * Subject: Now start the scanning loop one by one in
829 * the original callin order.
830 * This way when there are any shared banks it will be
831 * only seen by one CPU before cleared, avoiding duplicates.
833 while (atomic_read(&mce_executing) < order) {
834 if (mce_timed_out(&timeout)) {
835 atomic_set(&global_nwo, 0);
843 * Cache the global no_way_out state.
845 *no_way_out = atomic_read(&global_nwo);
851 * Synchronize between CPUs after main scanning loop.
852 * This invokes the bulk of the Monarch processing.
854 static int mce_end(int order)
857 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
865 * Allow others to run.
867 atomic_inc(&mce_executing);
870 /* CHECKME: Can this race with a parallel hotplug? */
871 int cpus = num_online_cpus();
874 * Monarch: Wait for everyone to go through their scanning
877 while (atomic_read(&mce_executing) <= cpus) {
878 if (mce_timed_out(&timeout))
888 * Subject: Wait for Monarch to finish.
890 while (atomic_read(&mce_executing) != 0) {
891 if (mce_timed_out(&timeout))
897 * Don't reset anything. That's done by the Monarch.
903 * Reset all global state.
906 atomic_set(&global_nwo, 0);
907 atomic_set(&mce_callin, 0);
911 * Let others run again.
913 atomic_set(&mce_executing, 0);
918 * Check if the address reported by the CPU is in a format we can parse.
919 * It would be possible to add code for most other cases, but all would
920 * be somewhat complicated (e.g. segment offset would require an instruction
921 * parser). So only support physical addresses up to page granuality for now.
923 static int mce_usable_address(struct mce *m)
925 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
927 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
929 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
934 static void mce_clear_state(unsigned long *toclear)
938 for (i = 0; i < banks; i++) {
939 if (test_bit(i, toclear))
940 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
945 * Need to save faulting physical address associated with a process
946 * in the machine check handler some place where we can grab it back
947 * later in mce_notify_process()
949 #define MCE_INFO_MAX 16
953 struct task_struct *t;
955 } mce_info[MCE_INFO_MAX];
957 static void mce_save_info(__u64 addr)
961 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) {
962 if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
969 mce_panic("Too many concurrent recoverable errors", NULL, NULL);
972 static struct mce_info *mce_find_info(void)
976 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++)
977 if (atomic_read(&mi->inuse) && mi->t == current)
982 static void mce_clear_info(struct mce_info *mi)
984 atomic_set(&mi->inuse, 0);
988 * The actual machine check handler. This only handles real
989 * exceptions when something got corrupted coming in through int 18.
991 * This is executed in NMI context not subject to normal locking rules. This
992 * implies that most kernel services cannot be safely used. Don't even
993 * think about putting a printk in there!
995 * On Intel systems this is entered on all CPUs in parallel through
996 * MCE broadcast. However some CPUs might be broken beyond repair,
997 * so be always careful when synchronizing with others.
999 void do_machine_check(struct pt_regs *regs, long error_code)
1001 struct mce m, *final;
1006 * Establish sequential order between the CPUs entering the machine
1011 * If no_way_out gets set, there is no safe way to recover from this
1012 * MCE. If tolerant is cranked up, we'll try anyway.
1016 * If kill_it gets set, there might be a way to recover from this
1020 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1021 char *msg = "Unknown";
1023 atomic_inc(&mce_entry);
1025 percpu_inc(mce_exception_count);
1030 mce_gather_info(&m, regs);
1032 final = &__get_cpu_var(mces_seen);
1035 no_way_out = mce_no_way_out(&m, &msg);
1040 * When no restart IP might need to kill or panic.
1041 * Assume the worst for now, but if we find the
1042 * severity is MCE_AR_SEVERITY we have other options.
1044 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1048 * Go through all the banks in exclusion of the other CPUs.
1049 * This way we don't report duplicated events on shared banks
1050 * because the first one to see it will clear it.
1052 order = mce_start(&no_way_out);
1053 for (i = 0; i < banks; i++) {
1054 __clear_bit(i, toclear);
1055 if (!mce_banks[i].ctl)
1062 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1063 if ((m.status & MCI_STATUS_VAL) == 0)
1067 * Non uncorrected or non signaled errors are handled by
1068 * machine_check_poll. Leave them alone, unless this panics.
1070 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1075 * Set taint even when machine check was not enabled.
1077 add_taint(TAINT_MACHINE_CHECK);
1079 severity = mce_severity(&m, tolerant, NULL);
1082 * When machine check was for corrected handler don't touch,
1083 * unless we're panicing.
1085 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1087 __set_bit(i, toclear);
1088 if (severity == MCE_NO_SEVERITY) {
1090 * Machine check event was not enabled. Clear, but
1096 mce_read_aux(&m, i);
1099 * Action optional error. Queue address for later processing.
1100 * When the ring overflows we just ignore the AO error.
1101 * RED-PEN add some logging mechanism when
1102 * usable_address or mce_add_ring fails.
1103 * RED-PEN don't ignore overflow for tolerant == 0
1105 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1106 mce_ring_add(m.addr >> PAGE_SHIFT);
1110 if (severity > worst) {
1116 /* mce_clear_state will clear *final, save locally for use later */
1120 mce_clear_state(toclear);
1123 * Do most of the synchronization with other CPUs.
1124 * When there's any problem use only local no_way_out state.
1126 if (mce_end(order) < 0)
1127 no_way_out = worst >= MCE_PANIC_SEVERITY;
1130 * At insane "tolerant" levels we take no action. Otherwise
1131 * we only die if we have no other choice. For less serious
1132 * issues we try to recover, or limit damage to the current
1137 mce_panic("Fatal machine check on current CPU", &m, msg);
1138 if (worst == MCE_AR_SEVERITY) {
1139 /* schedule action before return to userland */
1140 mce_save_info(m.addr);
1141 set_thread_flag(TIF_MCE_NOTIFY);
1142 } else if (kill_it) {
1143 force_sig(SIGBUS, current);
1148 mce_report_event(regs);
1149 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1151 atomic_dec(&mce_entry);
1154 EXPORT_SYMBOL_GPL(do_machine_check);
1156 #ifndef CONFIG_MEMORY_FAILURE
1157 int memory_failure(unsigned long pfn, int vector, int flags)
1159 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1160 BUG_ON(flags & MF_ACTION_REQUIRED);
1161 printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n"
1162 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn);
1169 * Called in process context that interrupted by MCE and marked with
1170 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1171 * This code is allowed to sleep.
1172 * Attempt possible recovery such as calling the high level VM handler to
1173 * process any corrupted pages, and kill/signal current process if required.
1174 * Action required errors are handled here.
1176 void mce_notify_process(void)
1179 struct mce_info *mi = mce_find_info();
1182 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
1183 pfn = mi->paddr >> PAGE_SHIFT;
1185 clear_thread_flag(TIF_MCE_NOTIFY);
1187 pr_err("Uncorrected hardware memory error in user-access at %llx",
1189 if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0) {
1190 pr_err("Memory error not recovered");
1191 force_sig(SIGBUS, current);
1197 * Action optional processing happens here (picking up
1198 * from the list of faulting pages that do_machine_check()
1199 * placed into the "ring").
1201 static void mce_process_work(struct work_struct *dummy)
1205 while (mce_ring_get(&pfn))
1206 memory_failure(pfn, MCE_VECTOR, 0);
1209 #ifdef CONFIG_X86_MCE_INTEL
1211 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1212 * @cpu: The CPU on which the event occurred.
1213 * @status: Event status information
1215 * This function should be called by the thermal interrupt after the
1216 * event has been processed and the decision was made to log the event
1219 * The status parameter will be saved to the 'status' field of 'struct mce'
1220 * and historically has been the register value of the
1221 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1223 void mce_log_therm_throt_event(__u64 status)
1228 m.bank = MCE_THERMAL_BANK;
1232 #endif /* CONFIG_X86_MCE_INTEL */
1235 * Periodic polling timer for "silent" machine check errors. If the
1236 * poller finds an MCE, poll 2x faster. When the poller finds no more
1237 * errors, poll 2x slower (up to check_interval seconds).
1239 * We will disable polling in DOM0 since all CMCI/Polling
1240 * mechanism will be done in XEN for Intel CPUs
1242 #if defined (CONFIG_X86_XEN_MCE)
1243 static int check_interval = 0; /* disable polling */
1245 static int check_interval = 5 * 60; /* 5 minutes */
1248 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1249 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1251 static void mce_start_timer(unsigned long data)
1253 struct timer_list *t = &per_cpu(mce_timer, data);
1256 WARN_ON(smp_processor_id() != data);
1258 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1259 machine_check_poll(MCP_TIMESTAMP,
1260 &__get_cpu_var(mce_poll_banks));
1264 * Alert userspace if needed. If we logged an MCE, reduce the
1265 * polling interval, otherwise increase the polling interval.
1267 n = &__get_cpu_var(mce_next_interval);
1268 if (mce_notify_irq())
1269 *n = max(*n/2, HZ/100);
1271 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1273 t->expires = jiffies + *n;
1274 add_timer_on(t, smp_processor_id());
1277 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1278 static void mce_timer_delete_all(void)
1282 for_each_online_cpu(cpu)
1283 del_timer_sync(&per_cpu(mce_timer, cpu));
1286 static void mce_do_trigger(struct work_struct *work)
1288 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1291 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1294 * Notify the user(s) about new machine check events.
1295 * Can be called from interrupt context, but not from machine check/NMI
1298 int mce_notify_irq(void)
1300 /* Not more than two messages every minute */
1301 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1303 if (test_and_clear_bit(0, &mce_need_notify)) {
1304 /* wake processes polling /dev/mcelog */
1305 wake_up_interruptible(&mce_chrdev_wait);
1308 * There is no risk of missing notifications because
1309 * work_pending is always cleared before the function is
1312 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1313 schedule_work(&mce_trigger_work);
1315 if (__ratelimit(&ratelimit))
1316 pr_info(HW_ERR "Machine check events logged\n");
1322 EXPORT_SYMBOL_GPL(mce_notify_irq);
1324 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1328 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1331 for (i = 0; i < banks; i++) {
1332 struct mce_bank *b = &mce_banks[i];
1341 * Initialize Machine Checks for a CPU.
1343 static int __cpuinit __mcheck_cpu_cap_init(void)
1348 rdmsrl(MSR_IA32_MCG_CAP, cap);
1350 b = cap & MCG_BANKCNT_MASK;
1352 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1354 if (b > MAX_NR_BANKS) {
1356 "MCE: Using only %u machine check banks out of %u\n",
1361 /* Don't support asymmetric configurations today */
1362 WARN_ON(banks != 0 && b != banks);
1365 int err = __mcheck_cpu_mce_banks_init();
1371 /* Use accurate RIP reporting if available. */
1372 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1373 rip_msr = MSR_IA32_MCG_EIP;
1375 if (cap & MCG_SER_P)
1381 static void __mcheck_cpu_init_generic(void)
1383 mce_banks_t all_banks;
1388 * Log the machine checks left over from the previous reset.
1390 bitmap_fill(all_banks, MAX_NR_BANKS);
1391 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1393 set_in_cr4(X86_CR4_MCE);
1395 rdmsrl(MSR_IA32_MCG_CAP, cap);
1396 if (cap & MCG_CTL_P)
1397 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1399 for (i = 0; i < banks; i++) {
1400 struct mce_bank *b = &mce_banks[i];
1404 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1405 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1409 /* Add per CPU specific workarounds here */
1410 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1412 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1413 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1417 /* This should be disabled by the BIOS, but isn't always */
1418 if (c->x86_vendor == X86_VENDOR_AMD) {
1420 if (c->x86 == 15 && banks > 4) {
1422 * disable GART TBL walk error reporting, which
1423 * trips off incorrectly with the IOMMU & 3ware
1426 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1429 if (c->x86 <= 17 && mce_bootlog < 0) {
1431 * Lots of broken BIOS around that don't clear them
1432 * by default and leave crap in there. Don't log:
1437 * Various K7s with broken bank 0 around. Always disable
1440 if (c->x86 == 6 && banks > 0)
1441 mce_banks[0].ctl = 0;
1444 if (c->x86_vendor == X86_VENDOR_INTEL) {
1446 * SDM documents that on family 6 bank 0 should not be written
1447 * because it aliases to another special BIOS controlled
1449 * But it's not aliased anymore on model 0x1a+
1450 * Don't ignore bank 0 completely because there could be a
1451 * valid event later, merely don't write CTL0.
1454 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1455 mce_banks[0].init = 0;
1458 * All newer Intel systems support MCE broadcasting. Enable
1459 * synchronization with a one second timeout.
1461 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1462 monarch_timeout < 0)
1463 monarch_timeout = USEC_PER_SEC;
1466 * There are also broken BIOSes on some Pentium M and
1469 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1472 if (monarch_timeout < 0)
1473 monarch_timeout = 0;
1474 if (mce_bootlog != 0)
1475 mce_panic_timeout = 30;
1480 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1485 switch (c->x86_vendor) {
1486 case X86_VENDOR_INTEL:
1487 intel_p5_mcheck_init(c);
1490 case X86_VENDOR_CENTAUR:
1491 winchip_mcheck_init(c);
1499 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1501 #ifndef CONFIG_X86_64_XEN
1502 switch (c->x86_vendor) {
1503 case X86_VENDOR_INTEL:
1504 mce_intel_feature_init(c);
1506 case X86_VENDOR_AMD:
1507 mce_amd_feature_init(c);
1515 static void __mcheck_cpu_init_timer(void)
1517 struct timer_list *t = &__get_cpu_var(mce_timer);
1518 int *n = &__get_cpu_var(mce_next_interval);
1520 setup_timer(t, mce_start_timer, smp_processor_id());
1525 *n = check_interval * HZ;
1528 t->expires = round_jiffies(jiffies + *n);
1529 add_timer_on(t, smp_processor_id());
1532 /* Handle unconfigured int18 (should never happen) */
1533 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1535 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1536 smp_processor_id());
1539 /* Call the installed machine check handler for this CPU setup. */
1540 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1541 unexpected_machine_check;
1544 * Called for each booted CPU to set up machine checks.
1545 * Must be called with preempt off:
1547 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1552 if (__mcheck_cpu_ancient_init(c))
1555 if (!mce_available(c))
1558 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1563 machine_check_vector = do_machine_check;
1565 __mcheck_cpu_init_generic();
1566 __mcheck_cpu_init_vendor(c);
1567 __mcheck_cpu_init_timer();
1568 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1569 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1573 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1576 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1577 static int mce_chrdev_open_count; /* #times opened */
1578 static int mce_chrdev_open_exclu; /* already open exclusive? */
1580 static int mce_chrdev_open(struct inode *inode, struct file *file)
1582 spin_lock(&mce_chrdev_state_lock);
1584 if (mce_chrdev_open_exclu ||
1585 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1586 spin_unlock(&mce_chrdev_state_lock);
1591 if (file->f_flags & O_EXCL)
1592 mce_chrdev_open_exclu = 1;
1593 mce_chrdev_open_count++;
1595 spin_unlock(&mce_chrdev_state_lock);
1597 return nonseekable_open(inode, file);
1600 static int mce_chrdev_release(struct inode *inode, struct file *file)
1602 spin_lock(&mce_chrdev_state_lock);
1604 mce_chrdev_open_count--;
1605 mce_chrdev_open_exclu = 0;
1607 spin_unlock(&mce_chrdev_state_lock);
1612 static void collect_tscs(void *data)
1614 unsigned long *cpu_tsc = (unsigned long *)data;
1616 rdtscll(cpu_tsc[smp_processor_id()]);
1619 static int mce_apei_read_done;
1621 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1622 static int __mce_read_apei(char __user **ubuf, size_t usize)
1628 if (usize < sizeof(struct mce))
1631 rc = apei_read_mce(&m, &record_id);
1632 /* Error or no more MCE record */
1634 mce_apei_read_done = 1;
1636 * When ERST is disabled, mce_chrdev_read() should return
1637 * "no record" instead of "no device."
1644 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1647 * In fact, we should have cleared the record after that has
1648 * been flushed to the disk or sent to network in
1649 * /sbin/mcelog, but we have no interface to support that now,
1650 * so just clear it to avoid duplication.
1652 rc = apei_clear_mce(record_id);
1654 mce_apei_read_done = 1;
1657 *ubuf += sizeof(struct mce);
1662 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1663 size_t usize, loff_t *off)
1665 char __user *buf = ubuf;
1666 unsigned long *cpu_tsc;
1667 unsigned prev, next;
1670 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1674 mutex_lock(&mce_chrdev_read_mutex);
1676 if (!mce_apei_read_done) {
1677 err = __mce_read_apei(&buf, usize);
1678 if (err || buf != ubuf)
1682 next = rcu_dereference_check_mce(mcelog.next);
1684 /* Only supports full reads right now */
1686 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1692 for (i = prev; i < next; i++) {
1693 unsigned long start = jiffies;
1694 struct mce *m = &mcelog.entry[i];
1696 while (!m->finished) {
1697 if (time_after_eq(jiffies, start + 2)) {
1698 memset(m, 0, sizeof(*m));
1704 err |= copy_to_user(buf, m, sizeof(*m));
1710 memset(mcelog.entry + prev, 0,
1711 (next - prev) * sizeof(struct mce));
1713 next = cmpxchg(&mcelog.next, prev, 0);
1714 } while (next != prev);
1716 synchronize_sched();
1719 * Collect entries that were still getting written before the
1722 on_each_cpu(collect_tscs, cpu_tsc, 1);
1724 for (i = next; i < MCE_LOG_LEN; i++) {
1725 struct mce *m = &mcelog.entry[i];
1727 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1728 err |= copy_to_user(buf, m, sizeof(*m));
1731 memset(m, 0, sizeof(*m));
1739 mutex_unlock(&mce_chrdev_read_mutex);
1742 return err ? err : buf - ubuf;
1745 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1747 poll_wait(file, &mce_chrdev_wait, wait);
1748 if (rcu_access_index(mcelog.next))
1749 return POLLIN | POLLRDNORM;
1750 if (!mce_apei_read_done && apei_check_mce())
1751 return POLLIN | POLLRDNORM;
1755 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1758 int __user *p = (int __user *)arg;
1760 if (!capable(CAP_SYS_ADMIN))
1764 case MCE_GET_RECORD_LEN:
1765 return put_user(sizeof(struct mce), p);
1766 case MCE_GET_LOG_LEN:
1767 return put_user(MCE_LOG_LEN, p);
1768 case MCE_GETCLEAR_FLAGS: {
1772 flags = mcelog.flags;
1773 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1775 return put_user(flags, p);
1782 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1783 size_t usize, loff_t *off);
1785 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1786 const char __user *ubuf,
1787 size_t usize, loff_t *off))
1791 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1793 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1794 size_t usize, loff_t *off)
1797 return mce_write(filp, ubuf, usize, off);
1802 static const struct file_operations mce_chrdev_ops = {
1803 .open = mce_chrdev_open,
1804 .release = mce_chrdev_release,
1805 .read = mce_chrdev_read,
1806 .write = mce_chrdev_write,
1807 .poll = mce_chrdev_poll,
1808 .unlocked_ioctl = mce_chrdev_ioctl,
1809 .llseek = no_llseek,
1812 static struct miscdevice mce_chrdev_device = {
1819 * mce=off Disables machine check
1820 * mce=no_cmci Disables CMCI
1821 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1822 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1823 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1824 * monarchtimeout is how long to wait for other CPUs on machine
1825 * check, or 0 to not wait
1826 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1827 * mce=nobootlog Don't log MCEs from before booting.
1829 static int __init mcheck_enable(char *str)
1837 if (!strcmp(str, "off"))
1839 else if (!strcmp(str, "no_cmci"))
1840 mce_cmci_disabled = 1;
1841 else if (!strcmp(str, "dont_log_ce"))
1842 mce_dont_log_ce = 1;
1843 else if (!strcmp(str, "ignore_ce"))
1845 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1846 mce_bootlog = (str[0] == 'b');
1847 else if (isdigit(str[0])) {
1848 get_option(&str, &tolerant);
1851 get_option(&str, &monarch_timeout);
1854 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1860 __setup("mce", mcheck_enable);
1862 int __init mcheck_init(void)
1864 mcheck_intel_therm_init();
1870 * mce_syscore: PM support
1874 * Disable machine checks on suspend and shutdown. We can't really handle
1877 static int mce_disable_error_reporting(void)
1881 for (i = 0; i < banks; i++) {
1882 struct mce_bank *b = &mce_banks[i];
1885 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1890 static int mce_syscore_suspend(void)
1892 return mce_disable_error_reporting();
1895 static void mce_syscore_shutdown(void)
1897 mce_disable_error_reporting();
1901 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1902 * Only one CPU is active at this time, the others get re-added later using
1905 static void mce_syscore_resume(void)
1907 __mcheck_cpu_init_generic();
1908 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1911 static struct syscore_ops mce_syscore_ops = {
1912 .suspend = mce_syscore_suspend,
1913 .shutdown = mce_syscore_shutdown,
1914 .resume = mce_syscore_resume,
1918 * mce_device: Sysfs support
1921 static void mce_cpu_restart(void *data)
1923 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1925 __mcheck_cpu_init_generic();
1926 __mcheck_cpu_init_timer();
1929 /* Reinit MCEs after user configuration changes */
1930 static void mce_restart(void)
1932 mce_timer_delete_all();
1933 on_each_cpu(mce_cpu_restart, NULL, 1);
1936 /* Toggle features for corrected errors */
1937 static void mce_disable_cmci(void *data)
1939 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1944 static void mce_enable_ce(void *all)
1946 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1951 __mcheck_cpu_init_timer();
1954 static struct bus_type mce_subsys = {
1955 .name = "machinecheck",
1956 .dev_name = "machinecheck",
1959 DEFINE_PER_CPU(struct device *, mce_device);
1962 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1964 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
1966 return container_of(attr, struct mce_bank, attr);
1969 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
1972 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1975 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
1976 const char *buf, size_t size)
1980 if (strict_strtoull(buf, 0, &new) < 0)
1983 attr_to_bank(attr)->ctl = new;
1990 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
1992 strcpy(buf, mce_helper);
1994 return strlen(mce_helper) + 1;
1997 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
1998 const char *buf, size_t siz)
2002 strncpy(mce_helper, buf, sizeof(mce_helper));
2003 mce_helper[sizeof(mce_helper)-1] = 0;
2004 p = strchr(mce_helper, '\n');
2009 return strlen(mce_helper) + !!p;
2012 static ssize_t set_ignore_ce(struct device *s,
2013 struct device_attribute *attr,
2014 const char *buf, size_t size)
2018 if (strict_strtoull(buf, 0, &new) < 0)
2021 if (mce_ignore_ce ^ !!new) {
2023 /* disable ce features */
2024 mce_timer_delete_all();
2025 on_each_cpu(mce_disable_cmci, NULL, 1);
2028 /* enable ce features */
2030 on_each_cpu(mce_enable_ce, (void *)1, 1);
2036 static ssize_t set_cmci_disabled(struct device *s,
2037 struct device_attribute *attr,
2038 const char *buf, size_t size)
2042 if (strict_strtoull(buf, 0, &new) < 0)
2045 if (mce_cmci_disabled ^ !!new) {
2048 on_each_cpu(mce_disable_cmci, NULL, 1);
2049 mce_cmci_disabled = 1;
2052 mce_cmci_disabled = 0;
2053 on_each_cpu(mce_enable_ce, NULL, 1);
2059 static ssize_t store_int_with_restart(struct device *s,
2060 struct device_attribute *attr,
2061 const char *buf, size_t size)
2063 ssize_t ret = device_store_int(s, attr, buf, size);
2068 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2069 static DEVICE_INT_ATTR(tolerant, 0644, tolerant);
2070 static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
2071 static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
2073 static struct dev_ext_attribute dev_attr_check_interval = {
2074 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2078 static struct dev_ext_attribute dev_attr_ignore_ce = {
2079 __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce),
2083 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2084 __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled),
2088 static struct device_attribute *mce_device_attrs[] = {
2089 &dev_attr_tolerant.attr,
2090 &dev_attr_check_interval.attr,
2092 &dev_attr_monarch_timeout.attr,
2093 &dev_attr_dont_log_ce.attr,
2094 &dev_attr_ignore_ce.attr,
2095 &dev_attr_cmci_disabled.attr,
2099 static cpumask_var_t mce_device_initialized;
2101 static void mce_device_release(struct device *dev)
2106 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2107 static __cpuinit int mce_device_create(unsigned int cpu)
2113 if (!mce_available(&boot_cpu_data))
2116 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2120 dev->bus = &mce_subsys;
2121 dev->release = &mce_device_release;
2123 err = device_register(dev);
2127 for (i = 0; mce_device_attrs[i]; i++) {
2128 err = device_create_file(dev, mce_device_attrs[i]);
2132 for (j = 0; j < banks; j++) {
2133 err = device_create_file(dev, &mce_banks[j].attr);
2137 cpumask_set_cpu(cpu, mce_device_initialized);
2138 per_cpu(mce_device, cpu) = dev;
2143 device_remove_file(dev, &mce_banks[j].attr);
2146 device_remove_file(dev, mce_device_attrs[i]);
2148 device_unregister(dev);
2153 static __cpuinit void mce_device_remove(unsigned int cpu)
2155 struct device *dev = per_cpu(mce_device, cpu);
2158 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2161 for (i = 0; mce_device_attrs[i]; i++)
2162 device_remove_file(dev, mce_device_attrs[i]);
2164 for (i = 0; i < banks; i++)
2165 device_remove_file(dev, &mce_banks[i].attr);
2167 device_unregister(dev);
2168 cpumask_clear_cpu(cpu, mce_device_initialized);
2169 per_cpu(mce_device, cpu) = NULL;
2172 /* Make sure there are no machine checks on offlined CPUs. */
2173 static void __cpuinit mce_disable_cpu(void *h)
2175 unsigned long action = *(unsigned long *)h;
2178 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2181 if (!(action & CPU_TASKS_FROZEN))
2183 for (i = 0; i < banks; i++) {
2184 struct mce_bank *b = &mce_banks[i];
2187 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2191 static void __cpuinit mce_reenable_cpu(void *h)
2193 unsigned long action = *(unsigned long *)h;
2196 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2199 if (!(action & CPU_TASKS_FROZEN))
2201 for (i = 0; i < banks; i++) {
2202 struct mce_bank *b = &mce_banks[i];
2205 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2209 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2210 static int __cpuinit
2211 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2213 unsigned int cpu = (unsigned long)hcpu;
2214 struct timer_list *t = &per_cpu(mce_timer, cpu);
2218 case CPU_ONLINE_FROZEN:
2219 mce_device_create(cpu);
2220 if (threshold_cpu_callback)
2221 threshold_cpu_callback(action, cpu);
2224 case CPU_DEAD_FROZEN:
2225 if (threshold_cpu_callback)
2226 threshold_cpu_callback(action, cpu);
2227 mce_device_remove(cpu);
2229 case CPU_DOWN_PREPARE:
2230 case CPU_DOWN_PREPARE_FROZEN:
2232 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2234 case CPU_DOWN_FAILED:
2235 case CPU_DOWN_FAILED_FROZEN:
2236 if (!mce_ignore_ce && check_interval) {
2237 t->expires = round_jiffies(jiffies +
2238 __get_cpu_var(mce_next_interval));
2239 add_timer_on(t, cpu);
2241 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2244 /* intentionally ignoring frozen here */
2245 cmci_rediscover(cpu);
2251 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2252 .notifier_call = mce_cpu_callback,
2255 static __init void mce_init_banks(void)
2259 for (i = 0; i < banks; i++) {
2260 struct mce_bank *b = &mce_banks[i];
2261 struct device_attribute *a = &b->attr;
2263 sysfs_attr_init(&a->attr);
2264 a->attr.name = b->attrname;
2265 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2267 a->attr.mode = 0644;
2268 a->show = show_bank;
2269 a->store = set_bank;
2273 static __init int mcheck_init_device(void)
2278 if (!mce_available(&boot_cpu_data))
2281 zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL);
2285 err = subsys_system_register(&mce_subsys, NULL);
2289 for_each_online_cpu(i) {
2290 err = mce_device_create(i);
2295 register_syscore_ops(&mce_syscore_ops);
2296 register_hotcpu_notifier(&mce_cpu_notifier);
2298 /* register character device /dev/mcelog */
2299 misc_register(&mce_chrdev_device);
2301 #ifdef CONFIG_X86_XEN_MCE
2302 if (is_initial_xendomain()) {
2303 /* Register vIRQ handler for MCE LOG processing */
2304 extern int bind_virq_for_mce(void);
2306 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2307 bind_virq_for_mce();
2313 device_initcall(mcheck_init_device);
2316 * Old style boot options parsing. Only for compatibility.
2318 static int __init mcheck_disable(char *str)
2323 __setup("nomce", mcheck_disable);
2325 #ifdef CONFIG_DEBUG_FS
2326 struct dentry *mce_get_debugfs_dir(void)
2328 static struct dentry *dmce;
2331 dmce = debugfs_create_dir("mce", NULL);
2336 static void mce_reset(void)
2339 atomic_set(&mce_fake_paniced, 0);
2340 atomic_set(&mce_executing, 0);
2341 atomic_set(&mce_callin, 0);
2342 atomic_set(&global_nwo, 0);
2345 static int fake_panic_get(void *data, u64 *val)
2351 static int fake_panic_set(void *data, u64 val)
2358 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2359 fake_panic_set, "%llu\n");
2361 static int __init mcheck_debugfs_init(void)
2363 struct dentry *dmce, *ffake_panic;
2365 dmce = mce_get_debugfs_dir();
2368 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2375 late_initcall(mcheck_debugfs_init);