2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
41 #include <asm/processor.h>
42 #include <asm/hw_irq.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
99 void (*mce_cpu_specific_poll)(struct mce *);
100 EXPORT_SYMBOL_GPL(mce_cpu_specific_poll);
103 * CPU/chipset specific EDAC code can register a notifier call here to print
104 * MCE errors in a human-readable form.
106 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
107 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
109 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
112 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
113 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
118 static struct notifier_block mce_dec_nb = {
119 .notifier_call = default_decode_mce,
123 /* MCA banks polled by the period polling timer for corrected events */
124 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
125 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
128 static DEFINE_PER_CPU(struct work_struct, mce_work);
130 /* Do initial initialization of a struct mce */
131 void mce_setup(struct mce *m)
133 memset(m, 0, sizeof(struct mce));
134 m->cpu = m->extcpu = smp_processor_id();
136 /* We hope get_seconds stays lockless */
137 m->time = get_seconds();
138 m->cpuvendor = boot_cpu_data.x86_vendor;
139 m->cpuid = cpuid_eax(1);
141 m->socketid = cpu_data(m->extcpu).phys_proc_id;
143 m->apicid = cpu_data(m->extcpu).initial_apicid;
144 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
147 DEFINE_PER_CPU(struct mce, injectm);
148 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
151 * Lockless MCE logging infrastructure.
152 * This avoids deadlocks on printk locks without having to break locks. Also
153 * separate MCEs from kernel messages to avoid bogus bug reports.
156 static struct mce_log mcelog = {
157 .signature = MCE_LOG_SIGNATURE,
159 .recordlen = sizeof(struct mce),
162 void mce_log(struct mce *mce)
164 unsigned next, entry;
166 /* Emit the trace record: */
167 trace_mce_record(mce);
172 entry = rcu_dereference_check_mce(mcelog.next);
175 * If edac_mce is enabled, it will check the error type
176 * and will process it, if it is a known error.
177 * Otherwise, the error will be sent through mcelog
180 if (edac_mce_parse(mce))
184 * When the buffer fills up discard new entries.
185 * Assume that the earlier errors are the more
188 if (entry >= MCE_LOG_LEN) {
189 set_bit(MCE_OVERFLOW,
190 (unsigned long *)&mcelog.flags);
193 /* Old left over entry. Skip: */
194 if (mcelog.entry[entry].finished) {
202 if (cmpxchg(&mcelog.next, entry, next) == entry)
205 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
207 mcelog.entry[entry].finished = 1;
211 set_bit(0, &mce_need_notify);
214 static void print_mce(struct mce *m)
216 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
217 m->extcpu, m->mcgstatus, m->bank, m->status);
220 pr_emerg("RIP%s %02x:<%016Lx> ",
221 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
224 if (m->cs == __KERNEL_CS)
225 print_symbol("{%s}", m->ip);
229 pr_emerg("TSC %llx ", m->tsc);
231 pr_cont("ADDR %llx ", m->addr);
233 pr_cont("MISC %llx ", m->misc);
236 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
237 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
240 * Print out human-readable details about the MCE error,
241 * (if the CPU has an implementation for that)
243 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
246 static void print_mce_head(void)
248 pr_emerg("\nHARDWARE ERROR\n");
251 static void print_mce_tail(void)
253 pr_emerg("This is not a software problem!\n");
256 #define PANIC_TIMEOUT 5 /* 5 seconds */
258 static atomic_t mce_paniced;
260 static int fake_panic;
261 static atomic_t mce_fake_paniced;
263 /* Panic in progress. Enable interrupts and wait for final IPI */
264 static void wait_for_panic(void)
266 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
270 while (timeout-- > 0)
272 if (panic_timeout == 0)
273 panic_timeout = mce_panic_timeout;
274 panic("Panicing machine check CPU died");
277 static void mce_panic(char *msg, struct mce *final, char *exp)
283 * Make sure only one CPU runs in machine check panic
285 if (atomic_inc_return(&mce_paniced) > 1)
292 /* Don't log too much for fake panic */
293 if (atomic_inc_return(&mce_fake_paniced) > 1)
297 /* First print corrected ones that are still unlogged */
298 for (i = 0; i < MCE_LOG_LEN; i++) {
299 struct mce *m = &mcelog.entry[i];
300 if (!(m->status & MCI_STATUS_VAL))
302 if (!(m->status & MCI_STATUS_UC)) {
305 apei_err = apei_write_mce(m);
308 /* Now print uncorrected but with the final one last */
309 for (i = 0; i < MCE_LOG_LEN; i++) {
310 struct mce *m = &mcelog.entry[i];
311 if (!(m->status & MCI_STATUS_VAL))
313 if (!(m->status & MCI_STATUS_UC))
315 if (!final || memcmp(m, final, sizeof(struct mce))) {
318 apei_err = apei_write_mce(m);
324 apei_err = apei_write_mce(final);
327 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
330 printk(KERN_EMERG "Machine check: %s\n", exp);
332 if (panic_timeout == 0)
333 panic_timeout = mce_panic_timeout;
336 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
339 /* Support code for software error injection */
341 static int msr_to_offset(u32 msr)
343 unsigned bank = __get_cpu_var(injectm.bank);
346 return offsetof(struct mce, ip);
347 if (msr == MSR_IA32_MCx_STATUS(bank))
348 return offsetof(struct mce, status);
349 if (msr == MSR_IA32_MCx_ADDR(bank))
350 return offsetof(struct mce, addr);
351 if (msr == MSR_IA32_MCx_MISC(bank))
352 return offsetof(struct mce, misc);
353 if (msr == MSR_IA32_MCG_STATUS)
354 return offsetof(struct mce, mcgstatus);
358 /* MSR access wrappers used for error injection */
359 static u64 mce_rdmsrl(u32 msr)
363 if (__get_cpu_var(injectm).finished) {
364 int offset = msr_to_offset(msr);
368 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
371 if (rdmsrl_safe(msr, &v)) {
372 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
374 * Return zero in case the access faulted. This should
375 * not happen normally but can happen if the CPU does
376 * something weird, or if the code is buggy.
384 static void mce_wrmsrl(u32 msr, u64 v)
386 if (__get_cpu_var(injectm).finished) {
387 int offset = msr_to_offset(msr);
390 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
396 static int under_injection(void)
398 return __get_cpu_var(injectm).finished;
402 * Simple lockless ring to communicate PFNs from the exception handler with the
403 * process context work function. This is vastly simplified because there's
404 * only a single reader and a single writer.
406 #define MCE_RING_SIZE 16 /* we use one entry less */
409 unsigned short start;
411 unsigned long ring[MCE_RING_SIZE];
413 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
415 /* Runs with CPU affinity in workqueue */
416 static int mce_ring_empty(void)
418 struct mce_ring *r = &__get_cpu_var(mce_ring);
420 return r->start == r->end;
423 static int mce_ring_get(unsigned long *pfn)
430 r = &__get_cpu_var(mce_ring);
431 if (r->start == r->end)
433 *pfn = r->ring[r->start];
434 r->start = (r->start + 1) % MCE_RING_SIZE;
441 /* Always runs in MCE context with preempt off */
442 static int mce_ring_add(unsigned long pfn)
444 struct mce_ring *r = &__get_cpu_var(mce_ring);
447 next = (r->end + 1) % MCE_RING_SIZE;
448 if (next == r->start)
450 r->ring[r->end] = pfn;
456 int mce_available(struct cpuinfo_x86 *c)
460 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
463 static void mce_schedule_work(void)
465 if (!mce_ring_empty()) {
466 struct work_struct *work = &__get_cpu_var(mce_work);
467 if (!work_pending(work))
473 * Get the address of the instruction at the time of the machine check
476 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
479 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
487 m->ip = mce_rdmsrl(rip_msr);
490 #ifdef CONFIG_X86_LOCAL_APIC
492 * Called after interrupts have been reenabled again
493 * when a MCE happened during an interrupts off region
496 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
509 static void mce_report_event(struct pt_regs *regs)
511 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
514 * Triggering the work queue here is just an insurance
515 * policy in case the syscall exit notify handler
516 * doesn't run soon enough or ends up running on the
517 * wrong CPU (can happen when audit sleeps)
523 #if defined(CONFIG_X86_LOCAL_APIC) && !defined(CONFIG_XEN)
525 * Without APIC do not notify. The event will be picked
532 * When interrupts are disabled we cannot use
533 * kernel services safely. Trigger an self interrupt
534 * through the APIC to instead do the notification
535 * after interrupts are reenabled again.
537 apic->send_IPI_self(MCE_SELF_VECTOR);
540 * Wait for idle afterwards again so that we don't leave the
541 * APIC in a non idle state because the normal APIC writes
544 apic_wait_icr_idle();
548 DEFINE_PER_CPU(unsigned, mce_poll_count);
551 * Poll for corrected events or events that happened before reset.
552 * Those are just logged through /dev/mcelog.
554 * This is executed in standard interrupt context.
556 * Note: spec recommends to panic for fatal unsignalled
557 * errors here. However this would be quite problematic --
558 * we would need to reimplement the Monarch handling and
559 * it would mess up the exclusion between exception handler
560 * and poll hander -- * so we skip this for now.
561 * These cases should not happen anyways, or only when the CPU
562 * is already totally * confused. In this case it's likely it will
563 * not fully execute the machine check handler either.
565 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
570 percpu_inc(mce_poll_count);
574 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
575 for (i = 0; i < banks; i++) {
576 if (!mce_banks[i].ctl || !test_bit(i, *b))
585 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
586 if (!(m.status & MCI_STATUS_VAL))
590 * Uncorrected or signalled events are handled by the exception
591 * handler when it is enabled, so don't process those here.
593 * TBD do the same check for MCI_STATUS_EN here?
595 if (!(flags & MCP_UC) &&
596 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
599 if (m.status & MCI_STATUS_MISCV)
600 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
601 if (m.status & MCI_STATUS_ADDRV)
602 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
604 if (!(flags & MCP_TIMESTAMP))
607 if (mce_cpu_specific_poll && !under_injection() && !mce_dont_log_ce)
608 mce_cpu_specific_poll(&m);
611 * Don't get the IP here because it's unlikely to
612 * have anything to do with the actual error location.
614 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
616 add_taint(TAINT_MACHINE_CHECK);
620 * Clear state for this bank.
622 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
626 * Don't clear MCG_STATUS here because it's only defined for
632 EXPORT_SYMBOL_GPL(machine_check_poll);
635 * Do a quick check if any of the events requires a panic.
636 * This decides if we keep the events around or clear them.
638 static int mce_no_way_out(struct mce *m, char **msg)
642 for (i = 0; i < banks; i++) {
643 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
644 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
651 * Variable to establish order between CPUs while scanning.
652 * Each CPU spins initially until executing is equal its number.
654 static atomic_t mce_executing;
657 * Defines order of CPUs on entry. First CPU becomes Monarch.
659 static atomic_t mce_callin;
662 * Check if a timeout waiting for other CPUs happened.
664 static int mce_timed_out(u64 *t)
667 * The others already did panic for some reason.
668 * Bail out like in a timeout.
669 * rmb() to tell the compiler that system_state
670 * might have been modified by someone else.
673 if (atomic_read(&mce_paniced))
675 if (!monarch_timeout)
677 if ((s64)*t < SPINUNIT) {
678 /* CHECKME: Make panic default for 1 too? */
680 mce_panic("Timeout synchronizing machine check over CPUs",
687 touch_nmi_watchdog();
692 * The Monarch's reign. The Monarch is the CPU who entered
693 * the machine check handler first. It waits for the others to
694 * raise the exception too and then grades them. When any
695 * error is fatal panic. Only then let the others continue.
697 * The other CPUs entering the MCE handler will be controlled by the
698 * Monarch. They are called Subjects.
700 * This way we prevent any potential data corruption in a unrecoverable case
701 * and also makes sure always all CPU's errors are examined.
703 * Also this detects the case of a machine check event coming from outer
704 * space (not detected by any CPUs) In this case some external agent wants
705 * us to shut down, so panic too.
707 * The other CPUs might still decide to panic if the handler happens
708 * in a unrecoverable place, but in this case the system is in a semi-stable
709 * state and won't corrupt anything by itself. It's ok to let the others
710 * continue for a bit first.
712 * All the spin loops have timeouts; when a timeout happens a CPU
713 * typically elects itself to be Monarch.
715 static void mce_reign(void)
718 struct mce *m = NULL;
719 int global_worst = 0;
724 * This CPU is the Monarch and the other CPUs have run
725 * through their handlers.
726 * Grade the severity of the errors of all the CPUs.
728 for_each_possible_cpu(cpu) {
729 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
731 if (severity > global_worst) {
733 global_worst = severity;
734 m = &per_cpu(mces_seen, cpu);
739 * Cannot recover? Panic here then.
740 * This dumps all the mces in the log buffer and stops the
743 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
744 mce_panic("Fatal Machine check", m, msg);
747 * For UC somewhere we let the CPU who detects it handle it.
748 * Also must let continue the others, otherwise the handling
749 * CPU could deadlock on a lock.
753 * No machine check event found. Must be some external
754 * source or one CPU is hung. Panic.
756 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
757 mce_panic("Machine check from unknown source", NULL, NULL);
760 * Now clear all the mces_seen so that they don't reappear on
763 for_each_possible_cpu(cpu)
764 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
767 static atomic_t global_nwo;
770 * Start of Monarch synchronization. This waits until all CPUs have
771 * entered the exception handler and then determines if any of them
772 * saw a fatal event that requires panic. Then it executes them
773 * in the entry order.
774 * TBD double check parallel CPU hotunplug
776 static int mce_start(int *no_way_out)
779 int cpus = num_online_cpus();
780 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
785 atomic_add(*no_way_out, &global_nwo);
787 * global_nwo should be updated before mce_callin
790 order = atomic_inc_return(&mce_callin);
795 while (atomic_read(&mce_callin) != cpus) {
796 if (mce_timed_out(&timeout)) {
797 atomic_set(&global_nwo, 0);
804 * mce_callin should be read before global_nwo
810 * Monarch: Starts executing now, the others wait.
812 atomic_set(&mce_executing, 1);
815 * Subject: Now start the scanning loop one by one in
816 * the original callin order.
817 * This way when there are any shared banks it will be
818 * only seen by one CPU before cleared, avoiding duplicates.
820 while (atomic_read(&mce_executing) < order) {
821 if (mce_timed_out(&timeout)) {
822 atomic_set(&global_nwo, 0);
830 * Cache the global no_way_out state.
832 *no_way_out = atomic_read(&global_nwo);
838 * Synchronize between CPUs after main scanning loop.
839 * This invokes the bulk of the Monarch processing.
841 static int mce_end(int order)
844 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
852 * Allow others to run.
854 atomic_inc(&mce_executing);
857 /* CHECKME: Can this race with a parallel hotplug? */
858 int cpus = num_online_cpus();
861 * Monarch: Wait for everyone to go through their scanning
864 while (atomic_read(&mce_executing) <= cpus) {
865 if (mce_timed_out(&timeout))
875 * Subject: Wait for Monarch to finish.
877 while (atomic_read(&mce_executing) != 0) {
878 if (mce_timed_out(&timeout))
884 * Don't reset anything. That's done by the Monarch.
890 * Reset all global state.
893 atomic_set(&global_nwo, 0);
894 atomic_set(&mce_callin, 0);
898 * Let others run again.
900 atomic_set(&mce_executing, 0);
905 * Check if the address reported by the CPU is in a format we can parse.
906 * It would be possible to add code for most other cases, but all would
907 * be somewhat complicated (e.g. segment offset would require an instruction
908 * parser). So only support physical addresses upto page granuality for now.
910 static int mce_usable_address(struct mce *m)
912 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
914 if ((m->misc & 0x3f) > PAGE_SHIFT)
916 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
921 static void mce_clear_state(unsigned long *toclear)
925 for (i = 0; i < banks; i++) {
926 if (test_bit(i, toclear))
927 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
932 * The actual machine check handler. This only handles real
933 * exceptions when something got corrupted coming in through int 18.
935 * This is executed in NMI context not subject to normal locking rules. This
936 * implies that most kernel services cannot be safely used. Don't even
937 * think about putting a printk in there!
939 * On Intel systems this is entered on all CPUs in parallel through
940 * MCE broadcast. However some CPUs might be broken beyond repair,
941 * so be always careful when synchronizing with others.
943 void do_machine_check(struct pt_regs *regs, long error_code)
945 struct mce m, *final;
950 * Establish sequential order between the CPUs entering the machine
955 * If no_way_out gets set, there is no safe way to recover from this
956 * MCE. If tolerant is cranked up, we'll try anyway.
960 * If kill_it gets set, there might be a way to recover from this
964 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
965 char *msg = "Unknown";
967 atomic_inc(&mce_entry);
969 percpu_inc(mce_exception_count);
971 if (notify_die(DIE_NMI, "machine check", regs, error_code,
972 18, SIGKILL) == NOTIFY_STOP)
979 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
980 final = &__get_cpu_var(mces_seen);
983 no_way_out = mce_no_way_out(&m, &msg);
988 * When no restart IP must always kill or panic.
990 if (!(m.mcgstatus & MCG_STATUS_RIPV))
994 * Go through all the banks in exclusion of the other CPUs.
995 * This way we don't report duplicated events on shared banks
996 * because the first one to see it will clear it.
998 order = mce_start(&no_way_out);
999 for (i = 0; i < banks; i++) {
1000 __clear_bit(i, toclear);
1001 if (!mce_banks[i].ctl)
1008 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1009 if ((m.status & MCI_STATUS_VAL) == 0)
1013 * Non uncorrected or non signaled errors are handled by
1014 * machine_check_poll. Leave them alone, unless this panics.
1016 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1021 * Set taint even when machine check was not enabled.
1023 add_taint(TAINT_MACHINE_CHECK);
1025 severity = mce_severity(&m, tolerant, NULL);
1028 * When machine check was for corrected handler don't touch,
1029 * unless we're panicing.
1031 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1033 __set_bit(i, toclear);
1034 if (severity == MCE_NO_SEVERITY) {
1036 * Machine check event was not enabled. Clear, but
1043 * Kill on action required.
1045 if (severity == MCE_AR_SEVERITY)
1048 if (m.status & MCI_STATUS_MISCV)
1049 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1050 if (m.status & MCI_STATUS_ADDRV)
1051 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1054 * Action optional error. Queue address for later processing.
1055 * When the ring overflows we just ignore the AO error.
1056 * RED-PEN add some logging mechanism when
1057 * usable_address or mce_add_ring fails.
1058 * RED-PEN don't ignore overflow for tolerant == 0
1060 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1061 mce_ring_add(m.addr >> PAGE_SHIFT);
1063 mce_get_rip(&m, regs);
1066 if (severity > worst) {
1073 mce_clear_state(toclear);
1076 * Do most of the synchronization with other CPUs.
1077 * When there's any problem use only local no_way_out state.
1079 if (mce_end(order) < 0)
1080 no_way_out = worst >= MCE_PANIC_SEVERITY;
1083 * If we have decided that we just CAN'T continue, and the user
1084 * has not set tolerant to an insane level, give up and die.
1086 * This is mainly used in the case when the system doesn't
1087 * support MCE broadcasting or it has been disabled.
1089 if (no_way_out && tolerant < 3)
1090 mce_panic("Fatal machine check on current CPU", final, msg);
1093 * If the error seems to be unrecoverable, something should be
1094 * done. Try to kill as little as possible. If we can kill just
1095 * one task, do that. If the user has set the tolerance very
1096 * high, don't try to do anything at all.
1099 if (kill_it && tolerant < 3)
1100 force_sig(SIGBUS, current);
1102 /* notify userspace ASAP */
1103 set_thread_flag(TIF_MCE_NOTIFY);
1106 mce_report_event(regs);
1107 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1109 atomic_dec(&mce_entry);
1112 EXPORT_SYMBOL_GPL(do_machine_check);
1114 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1115 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1117 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1121 * Called after mce notification in process context. This code
1122 * is allowed to sleep. Call the high level VM handler to process
1123 * any corrupted pages.
1124 * Assume that the work queue code only calls this one at a time
1126 * Note we don't disable preemption, so this code might run on the wrong
1127 * CPU. In this case the event is picked up by the scheduled work queue.
1128 * This is merely a fast path to expedite processing in some common
1131 void mce_notify_process(void)
1135 while (mce_ring_get(&pfn))
1136 memory_failure(pfn, MCE_VECTOR);
1139 static void mce_process_work(struct work_struct *dummy)
1141 mce_notify_process();
1144 #ifdef CONFIG_X86_MCE_INTEL
1146 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1147 * @cpu: The CPU on which the event occurred.
1148 * @status: Event status information
1150 * This function should be called by the thermal interrupt after the
1151 * event has been processed and the decision was made to log the event
1154 * The status parameter will be saved to the 'status' field of 'struct mce'
1155 * and historically has been the register value of the
1156 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1158 void mce_log_therm_throt_event(__u64 status)
1163 m.bank = MCE_THERMAL_BANK;
1167 #endif /* CONFIG_X86_MCE_INTEL */
1170 * Periodic polling timer for "silent" machine check errors. If the
1171 * poller finds an MCE, poll 2x faster. When the poller finds no more
1172 * errors, poll 2x slower (up to check_interval seconds).
1174 * We will disable polling in DOM0 since all CMCI/Polling
1175 * mechanism will be done in XEN for Intel CPUs
1177 #if defined (CONFIG_X86_XEN_MCE)
1178 static int check_interval = 0; /* disable polling */
1180 static int check_interval = 5 * 60; /* 5 minutes */
1183 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1184 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1186 static void mce_start_timer(unsigned long data)
1188 struct timer_list *t = &per_cpu(mce_timer, data);
1191 WARN_ON(smp_processor_id() != data);
1193 if (mce_available(¤t_cpu_data)) {
1194 machine_check_poll(MCP_TIMESTAMP,
1195 &__get_cpu_var(mce_poll_banks));
1199 * Alert userspace if needed. If we logged an MCE, reduce the
1200 * polling interval, otherwise increase the polling interval.
1202 n = &__get_cpu_var(mce_next_interval);
1203 if (mce_notify_irq())
1204 *n = max(*n/2, HZ/100);
1206 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1208 t->expires = jiffies + *n;
1209 add_timer_on(t, smp_processor_id());
1212 static void mce_do_trigger(struct work_struct *work)
1214 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1217 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1220 * Notify the user(s) about new machine check events.
1221 * Can be called from interrupt context, but not from machine check/NMI
1224 int mce_notify_irq(void)
1226 /* Not more than two messages every minute */
1227 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1229 clear_thread_flag(TIF_MCE_NOTIFY);
1231 if (test_and_clear_bit(0, &mce_need_notify)) {
1232 wake_up_interruptible(&mce_wait);
1235 * There is no risk of missing notifications because
1236 * work_pending is always cleared before the function is
1239 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1240 schedule_work(&mce_trigger_work);
1242 if (__ratelimit(&ratelimit))
1243 printk(KERN_INFO "Machine check events logged\n");
1249 EXPORT_SYMBOL_GPL(mce_notify_irq);
1251 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1255 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1258 for (i = 0; i < banks; i++) {
1259 struct mce_bank *b = &mce_banks[i];
1268 * Initialize Machine Checks for a CPU.
1270 static int __cpuinit __mcheck_cpu_cap_init(void)
1275 rdmsrl(MSR_IA32_MCG_CAP, cap);
1277 b = cap & MCG_BANKCNT_MASK;
1279 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1281 if (b > MAX_NR_BANKS) {
1283 "MCE: Using only %u machine check banks out of %u\n",
1288 /* Don't support asymmetric configurations today */
1289 WARN_ON(banks != 0 && b != banks);
1292 int err = __mcheck_cpu_mce_banks_init();
1298 /* Use accurate RIP reporting if available. */
1299 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1300 rip_msr = MSR_IA32_MCG_EIP;
1302 if (cap & MCG_SER_P)
1308 static void __mcheck_cpu_init_generic(void)
1310 mce_banks_t all_banks;
1315 * Log the machine checks left over from the previous reset.
1317 bitmap_fill(all_banks, MAX_NR_BANKS);
1318 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1320 set_in_cr4(X86_CR4_MCE);
1322 rdmsrl(MSR_IA32_MCG_CAP, cap);
1323 if (cap & MCG_CTL_P)
1324 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1326 for (i = 0; i < banks; i++) {
1327 struct mce_bank *b = &mce_banks[i];
1331 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1332 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1336 /* Add per CPU specific workarounds here */
1337 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1339 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1340 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1344 /* This should be disabled by the BIOS, but isn't always */
1345 if (c->x86_vendor == X86_VENDOR_AMD) {
1347 if (c->x86 == 15 && banks > 4) {
1349 * disable GART TBL walk error reporting, which
1350 * trips off incorrectly with the IOMMU & 3ware
1353 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1356 if (c->x86 <= 17 && mce_bootlog < 0) {
1358 * Lots of broken BIOS around that don't clear them
1359 * by default and leave crap in there. Don't log:
1364 * Various K7s with broken bank 0 around. Always disable
1367 if (c->x86 == 6 && banks > 0)
1368 mce_banks[0].ctl = 0;
1371 if (c->x86_vendor == X86_VENDOR_INTEL) {
1373 * SDM documents that on family 6 bank 0 should not be written
1374 * because it aliases to another special BIOS controlled
1376 * But it's not aliased anymore on model 0x1a+
1377 * Don't ignore bank 0 completely because there could be a
1378 * valid event later, merely don't write CTL0.
1381 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1382 mce_banks[0].init = 0;
1385 * All newer Intel systems support MCE broadcasting. Enable
1386 * synchronization with a one second timeout.
1388 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1389 monarch_timeout < 0)
1390 monarch_timeout = USEC_PER_SEC;
1393 * There are also broken BIOSes on some Pentium M and
1396 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1399 if (monarch_timeout < 0)
1400 monarch_timeout = 0;
1401 if (mce_bootlog != 0)
1402 mce_panic_timeout = 30;
1407 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1411 switch (c->x86_vendor) {
1412 case X86_VENDOR_INTEL:
1413 intel_p5_mcheck_init(c);
1415 case X86_VENDOR_CENTAUR:
1416 winchip_mcheck_init(c);
1421 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1423 #ifndef CONFIG_X86_64_XEN
1424 switch (c->x86_vendor) {
1425 case X86_VENDOR_INTEL:
1426 mce_intel_feature_init(c);
1428 case X86_VENDOR_AMD:
1429 mce_amd_feature_init(c);
1437 static void __mcheck_cpu_init_timer(void)
1439 struct timer_list *t = &__get_cpu_var(mce_timer);
1440 int *n = &__get_cpu_var(mce_next_interval);
1442 setup_timer(t, mce_start_timer, smp_processor_id());
1447 *n = check_interval * HZ;
1450 t->expires = round_jiffies(jiffies + *n);
1451 add_timer_on(t, smp_processor_id());
1454 /* Handle unconfigured int18 (should never happen) */
1455 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1457 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1458 smp_processor_id());
1461 /* Call the installed machine check handler for this CPU setup. */
1462 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1463 unexpected_machine_check;
1466 * Called for each booted CPU to set up machine checks.
1467 * Must be called with preempt off:
1469 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1474 __mcheck_cpu_ancient_init(c);
1476 if (!mce_available(c))
1479 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1484 machine_check_vector = do_machine_check;
1486 __mcheck_cpu_init_generic();
1487 __mcheck_cpu_init_vendor(c);
1488 __mcheck_cpu_init_timer();
1489 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1494 * Character device to read and clear the MCE log.
1497 static DEFINE_SPINLOCK(mce_state_lock);
1498 static int open_count; /* #times opened */
1499 static int open_exclu; /* already open exclusive? */
1501 static int mce_open(struct inode *inode, struct file *file)
1503 spin_lock(&mce_state_lock);
1505 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1506 spin_unlock(&mce_state_lock);
1511 if (file->f_flags & O_EXCL)
1515 spin_unlock(&mce_state_lock);
1517 return nonseekable_open(inode, file);
1520 static int mce_release(struct inode *inode, struct file *file)
1522 spin_lock(&mce_state_lock);
1527 spin_unlock(&mce_state_lock);
1532 static void collect_tscs(void *data)
1534 unsigned long *cpu_tsc = (unsigned long *)data;
1536 rdtscll(cpu_tsc[smp_processor_id()]);
1539 static int mce_apei_read_done;
1541 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1542 static int __mce_read_apei(char __user **ubuf, size_t usize)
1548 if (usize < sizeof(struct mce))
1551 rc = apei_read_mce(&m, &record_id);
1552 /* Error or no more MCE record */
1554 mce_apei_read_done = 1;
1558 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1561 * In fact, we should have cleared the record after that has
1562 * been flushed to the disk or sent to network in
1563 * /sbin/mcelog, but we have no interface to support that now,
1564 * so just clear it to avoid duplication.
1566 rc = apei_clear_mce(record_id);
1568 mce_apei_read_done = 1;
1571 *ubuf += sizeof(struct mce);
1576 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1579 char __user *buf = ubuf;
1580 unsigned long *cpu_tsc;
1581 unsigned prev, next;
1584 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1588 mutex_lock(&mce_read_mutex);
1590 if (!mce_apei_read_done) {
1591 err = __mce_read_apei(&buf, usize);
1592 if (err || buf != ubuf)
1596 next = rcu_dereference_check_mce(mcelog.next);
1598 /* Only supports full reads right now */
1600 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1606 for (i = prev; i < next; i++) {
1607 unsigned long start = jiffies;
1609 while (!mcelog.entry[i].finished) {
1610 if (time_after_eq(jiffies, start + 2)) {
1611 memset(mcelog.entry + i, 0,
1612 sizeof(struct mce));
1618 err |= copy_to_user(buf, mcelog.entry + i,
1619 sizeof(struct mce));
1620 buf += sizeof(struct mce);
1625 memset(mcelog.entry + prev, 0,
1626 (next - prev) * sizeof(struct mce));
1628 next = cmpxchg(&mcelog.next, prev, 0);
1629 } while (next != prev);
1631 synchronize_sched();
1634 * Collect entries that were still getting written before the
1637 on_each_cpu(collect_tscs, cpu_tsc, 1);
1639 for (i = next; i < MCE_LOG_LEN; i++) {
1640 if (mcelog.entry[i].finished &&
1641 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1642 err |= copy_to_user(buf, mcelog.entry+i,
1643 sizeof(struct mce));
1645 buf += sizeof(struct mce);
1646 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1654 mutex_unlock(&mce_read_mutex);
1657 return err ? err : buf - ubuf;
1660 static unsigned int mce_poll(struct file *file, poll_table *wait)
1662 poll_wait(file, &mce_wait, wait);
1663 if (rcu_dereference_check_mce(mcelog.next))
1664 return POLLIN | POLLRDNORM;
1665 if (!mce_apei_read_done && apei_check_mce())
1666 return POLLIN | POLLRDNORM;
1670 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1672 int __user *p = (int __user *)arg;
1674 if (!capable(CAP_SYS_ADMIN))
1678 case MCE_GET_RECORD_LEN:
1679 return put_user(sizeof(struct mce), p);
1680 case MCE_GET_LOG_LEN:
1681 return put_user(MCE_LOG_LEN, p);
1682 case MCE_GETCLEAR_FLAGS: {
1686 flags = mcelog.flags;
1687 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1689 return put_user(flags, p);
1696 /* Modified in mce-inject.c, so not static or const */
1697 struct file_operations mce_chrdev_ops = {
1699 .release = mce_release,
1702 .unlocked_ioctl = mce_ioctl,
1704 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1706 static struct miscdevice mce_log_device = {
1713 * mce=off Disables machine check
1714 * mce=no_cmci Disables CMCI
1715 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1716 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1717 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1718 * monarchtimeout is how long to wait for other CPUs on machine
1719 * check, or 0 to not wait
1720 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1721 * mce=nobootlog Don't log MCEs from before booting.
1723 static int __init mcheck_enable(char *str)
1731 if (!strcmp(str, "off"))
1733 else if (!strcmp(str, "no_cmci"))
1734 mce_cmci_disabled = 1;
1735 else if (!strcmp(str, "dont_log_ce"))
1736 mce_dont_log_ce = 1;
1737 else if (!strcmp(str, "ignore_ce"))
1739 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1740 mce_bootlog = (str[0] == 'b');
1741 else if (isdigit(str[0])) {
1742 get_option(&str, &tolerant);
1745 get_option(&str, &monarch_timeout);
1748 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1754 __setup("mce", mcheck_enable);
1756 int __init mcheck_init(void)
1758 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1760 mcheck_intel_therm_init();
1770 * Disable machine checks on suspend and shutdown. We can't really handle
1773 static int mce_disable_error_reporting(void)
1777 for (i = 0; i < banks; i++) {
1778 struct mce_bank *b = &mce_banks[i];
1781 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1786 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1788 return mce_disable_error_reporting();
1791 static int mce_shutdown(struct sys_device *dev)
1793 return mce_disable_error_reporting();
1797 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1798 * Only one CPU is active at this time, the others get re-added later using
1801 static int mce_resume(struct sys_device *dev)
1803 __mcheck_cpu_init_generic();
1804 __mcheck_cpu_init_vendor(¤t_cpu_data);
1809 static void mce_cpu_restart(void *data)
1811 del_timer_sync(&__get_cpu_var(mce_timer));
1812 if (!mce_available(¤t_cpu_data))
1814 __mcheck_cpu_init_generic();
1815 __mcheck_cpu_init_timer();
1818 /* Reinit MCEs after user configuration changes */
1819 static void mce_restart(void)
1821 on_each_cpu(mce_cpu_restart, NULL, 1);
1824 /* Toggle features for corrected errors */
1825 static void mce_disable_ce(void *all)
1827 if (!mce_available(¤t_cpu_data))
1830 del_timer_sync(&__get_cpu_var(mce_timer));
1834 static void mce_enable_ce(void *all)
1836 if (!mce_available(¤t_cpu_data))
1841 __mcheck_cpu_init_timer();
1844 static struct sysdev_class mce_sysclass = {
1845 .suspend = mce_suspend,
1846 .shutdown = mce_shutdown,
1847 .resume = mce_resume,
1848 .name = "machinecheck",
1851 DEFINE_PER_CPU(struct sys_device, mce_dev);
1854 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1856 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1858 return container_of(attr, struct mce_bank, attr);
1861 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1864 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1867 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1868 const char *buf, size_t size)
1872 if (strict_strtoull(buf, 0, &new) < 0)
1875 attr_to_bank(attr)->ctl = new;
1882 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1884 strcpy(buf, mce_helper);
1886 return strlen(mce_helper) + 1;
1889 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1890 const char *buf, size_t siz)
1894 strncpy(mce_helper, buf, sizeof(mce_helper));
1895 mce_helper[sizeof(mce_helper)-1] = 0;
1896 p = strchr(mce_helper, '\n');
1901 return strlen(mce_helper) + !!p;
1904 static ssize_t set_ignore_ce(struct sys_device *s,
1905 struct sysdev_attribute *attr,
1906 const char *buf, size_t size)
1910 if (strict_strtoull(buf, 0, &new) < 0)
1913 if (mce_ignore_ce ^ !!new) {
1915 /* disable ce features */
1916 on_each_cpu(mce_disable_ce, (void *)1, 1);
1919 /* enable ce features */
1921 on_each_cpu(mce_enable_ce, (void *)1, 1);
1927 static ssize_t set_cmci_disabled(struct sys_device *s,
1928 struct sysdev_attribute *attr,
1929 const char *buf, size_t size)
1933 if (strict_strtoull(buf, 0, &new) < 0)
1936 if (mce_cmci_disabled ^ !!new) {
1939 on_each_cpu(mce_disable_ce, NULL, 1);
1940 mce_cmci_disabled = 1;
1943 mce_cmci_disabled = 0;
1944 on_each_cpu(mce_enable_ce, NULL, 1);
1950 static ssize_t store_int_with_restart(struct sys_device *s,
1951 struct sysdev_attribute *attr,
1952 const char *buf, size_t size)
1954 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1959 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1960 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1961 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1962 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1964 static struct sysdev_ext_attribute attr_check_interval = {
1965 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1966 store_int_with_restart),
1970 static struct sysdev_ext_attribute attr_ignore_ce = {
1971 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1975 static struct sysdev_ext_attribute attr_cmci_disabled = {
1976 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1980 static struct sysdev_attribute *mce_attrs[] = {
1981 &attr_tolerant.attr,
1982 &attr_check_interval.attr,
1984 &attr_monarch_timeout.attr,
1985 &attr_dont_log_ce.attr,
1986 &attr_ignore_ce.attr,
1987 &attr_cmci_disabled.attr,
1991 static cpumask_var_t mce_dev_initialized;
1993 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1994 static __cpuinit int mce_create_device(unsigned int cpu)
1999 if (!mce_available(&boot_cpu_data))
2002 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
2003 per_cpu(mce_dev, cpu).id = cpu;
2004 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
2006 err = sysdev_register(&per_cpu(mce_dev, cpu));
2010 for (i = 0; mce_attrs[i]; i++) {
2011 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2015 for (j = 0; j < banks; j++) {
2016 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
2017 &mce_banks[j].attr);
2021 cpumask_set_cpu(cpu, mce_dev_initialized);
2026 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
2029 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2031 sysdev_unregister(&per_cpu(mce_dev, cpu));
2036 static __cpuinit void mce_remove_device(unsigned int cpu)
2040 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2043 for (i = 0; mce_attrs[i]; i++)
2044 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2046 for (i = 0; i < banks; i++)
2047 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2049 sysdev_unregister(&per_cpu(mce_dev, cpu));
2050 cpumask_clear_cpu(cpu, mce_dev_initialized);
2053 /* Make sure there are no machine checks on offlined CPUs. */
2054 static void __cpuinit mce_disable_cpu(void *h)
2056 unsigned long action = *(unsigned long *)h;
2059 if (!mce_available(¤t_cpu_data))
2062 if (!(action & CPU_TASKS_FROZEN))
2064 for (i = 0; i < banks; i++) {
2065 struct mce_bank *b = &mce_banks[i];
2068 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2072 static void __cpuinit mce_reenable_cpu(void *h)
2074 unsigned long action = *(unsigned long *)h;
2077 if (!mce_available(¤t_cpu_data))
2080 if (!(action & CPU_TASKS_FROZEN))
2082 for (i = 0; i < banks; i++) {
2083 struct mce_bank *b = &mce_banks[i];
2086 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2090 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2091 static int __cpuinit
2092 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2094 unsigned int cpu = (unsigned long)hcpu;
2095 struct timer_list *t = &per_cpu(mce_timer, cpu);
2099 case CPU_ONLINE_FROZEN:
2100 mce_create_device(cpu);
2101 if (threshold_cpu_callback)
2102 threshold_cpu_callback(action, cpu);
2105 case CPU_DEAD_FROZEN:
2106 if (threshold_cpu_callback)
2107 threshold_cpu_callback(action, cpu);
2108 mce_remove_device(cpu);
2110 case CPU_DOWN_PREPARE:
2111 case CPU_DOWN_PREPARE_FROZEN:
2113 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2115 case CPU_DOWN_FAILED:
2116 case CPU_DOWN_FAILED_FROZEN:
2117 if (!mce_ignore_ce && check_interval) {
2118 t->expires = round_jiffies(jiffies +
2119 __get_cpu_var(mce_next_interval));
2120 add_timer_on(t, cpu);
2122 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2125 /* intentionally ignoring frozen here */
2126 cmci_rediscover(cpu);
2132 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2133 .notifier_call = mce_cpu_callback,
2136 static __init void mce_init_banks(void)
2140 for (i = 0; i < banks; i++) {
2141 struct mce_bank *b = &mce_banks[i];
2142 struct sysdev_attribute *a = &b->attr;
2144 sysfs_attr_init(&a->attr);
2145 a->attr.name = b->attrname;
2146 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2148 a->attr.mode = 0644;
2149 a->show = show_bank;
2150 a->store = set_bank;
2154 static __init int mcheck_init_device(void)
2159 if (!mce_available(&boot_cpu_data))
2162 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2166 err = sysdev_class_register(&mce_sysclass);
2170 for_each_online_cpu(i) {
2171 err = mce_create_device(i);
2176 register_hotcpu_notifier(&mce_cpu_notifier);
2177 misc_register(&mce_log_device);
2179 #ifdef CONFIG_X86_XEN_MCE
2180 if (is_initial_xendomain()) {
2181 /* Register vIRQ handler for MCE LOG processing */
2182 extern int bind_virq_for_mce(void);
2184 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2185 bind_virq_for_mce();
2192 device_initcall(mcheck_init_device);
2195 * Old style boot options parsing. Only for compatibility.
2197 static int __init mcheck_disable(char *str)
2202 __setup("nomce", mcheck_disable);
2204 #ifdef CONFIG_DEBUG_FS
2205 struct dentry *mce_get_debugfs_dir(void)
2207 static struct dentry *dmce;
2210 dmce = debugfs_create_dir("mce", NULL);
2215 static void mce_reset(void)
2218 atomic_set(&mce_fake_paniced, 0);
2219 atomic_set(&mce_executing, 0);
2220 atomic_set(&mce_callin, 0);
2221 atomic_set(&global_nwo, 0);
2224 static int fake_panic_get(void *data, u64 *val)
2230 static int fake_panic_set(void *data, u64 val)
2237 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2238 fake_panic_set, "%llu\n");
2240 static int __init mcheck_debugfs_init(void)
2242 struct dentry *dmce, *ffake_panic;
2244 dmce = mce_get_debugfs_dir();
2247 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2254 late_initcall(mcheck_debugfs_init);