2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
105 /* MCA banks polled by the period polling timer for corrected events */
106 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce *m)
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
123 m->socketid = cpu_data(m->extcpu).phys_proc_id;
125 m->apicid = cpu_data(m->extcpu).initial_apicid;
126 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
129 DEFINE_PER_CPU(struct mce, injectm);
130 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
133 * Lockless MCE logging infrastructure.
134 * This avoids deadlocks on printk locks without having to break locks. Also
135 * separate MCEs from kernel messages to avoid bogus bug reports.
138 static struct mce_log mcelog = {
139 .signature = MCE_LOG_SIGNATURE,
141 .recordlen = sizeof(struct mce),
144 void mce_log(struct mce *mce)
146 unsigned next, entry;
149 /* Emit the trace record: */
150 trace_mce_record(mce);
152 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
153 if (ret == NOTIFY_STOP)
159 entry = rcu_dereference_check_mce(mcelog.next);
163 * When the buffer fills up discard new entries.
164 * Assume that the earlier errors are the more
167 if (entry >= MCE_LOG_LEN) {
168 set_bit(MCE_OVERFLOW,
169 (unsigned long *)&mcelog.flags);
172 /* Old left over entry. Skip: */
173 if (mcelog.entry[entry].finished) {
181 if (cmpxchg(&mcelog.next, entry, next) == entry)
184 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
186 mcelog.entry[entry].finished = 1;
190 set_bit(0, &mce_need_notify);
193 static void print_mce(struct mce *m)
197 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
198 m->extcpu, m->mcgstatus, m->bank, m->status);
201 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
202 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
205 if (m->cs == __KERNEL_CS)
206 print_symbol("{%s}", m->ip);
210 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
212 pr_cont("ADDR %llx ", m->addr);
214 pr_cont("MISC %llx ", m->misc);
218 * Note this output is parsed by external tools and old fields
219 * should not be changed.
221 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
222 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
223 cpu_data(m->extcpu).microcode);
226 * Print out human-readable details about the MCE error,
227 * (if the CPU has an implementation for that)
229 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
230 if (ret == NOTIFY_STOP)
233 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
236 #define PANIC_TIMEOUT 5 /* 5 seconds */
238 static atomic_t mce_paniced;
240 static int fake_panic;
241 static atomic_t mce_fake_paniced;
243 /* Panic in progress. Enable interrupts and wait for final IPI */
244 static void wait_for_panic(void)
246 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
250 while (timeout-- > 0)
252 if (panic_timeout == 0)
253 panic_timeout = mce_panic_timeout;
254 panic("Panicing machine check CPU died");
257 static void mce_panic(char *msg, struct mce *final, char *exp)
263 * Make sure only one CPU runs in machine check panic
265 if (atomic_inc_return(&mce_paniced) > 1)
272 /* Don't log too much for fake panic */
273 if (atomic_inc_return(&mce_fake_paniced) > 1)
276 /* First print corrected ones that are still unlogged */
277 for (i = 0; i < MCE_LOG_LEN; i++) {
278 struct mce *m = &mcelog.entry[i];
279 if (!(m->status & MCI_STATUS_VAL))
281 if (!(m->status & MCI_STATUS_UC)) {
284 apei_err = apei_write_mce(m);
287 /* Now print uncorrected but with the final one last */
288 for (i = 0; i < MCE_LOG_LEN; i++) {
289 struct mce *m = &mcelog.entry[i];
290 if (!(m->status & MCI_STATUS_VAL))
292 if (!(m->status & MCI_STATUS_UC))
294 if (!final || memcmp(m, final, sizeof(struct mce))) {
297 apei_err = apei_write_mce(m);
303 apei_err = apei_write_mce(final);
306 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
308 pr_emerg(HW_ERR "Machine check: %s\n", exp);
310 if (panic_timeout == 0)
311 panic_timeout = mce_panic_timeout;
314 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
317 /* Support code for software error injection */
319 static int msr_to_offset(u32 msr)
321 unsigned bank = __this_cpu_read(injectm.bank);
324 return offsetof(struct mce, ip);
325 if (msr == MSR_IA32_MCx_STATUS(bank))
326 return offsetof(struct mce, status);
327 if (msr == MSR_IA32_MCx_ADDR(bank))
328 return offsetof(struct mce, addr);
329 if (msr == MSR_IA32_MCx_MISC(bank))
330 return offsetof(struct mce, misc);
331 if (msr == MSR_IA32_MCG_STATUS)
332 return offsetof(struct mce, mcgstatus);
336 /* MSR access wrappers used for error injection */
337 static u64 mce_rdmsrl(u32 msr)
341 if (__this_cpu_read(injectm.finished)) {
342 int offset = msr_to_offset(msr);
346 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
349 if (rdmsrl_safe(msr, &v)) {
350 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
352 * Return zero in case the access faulted. This should
353 * not happen normally but can happen if the CPU does
354 * something weird, or if the code is buggy.
362 static void mce_wrmsrl(u32 msr, u64 v)
364 if (__this_cpu_read(injectm.finished)) {
365 int offset = msr_to_offset(msr);
368 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
375 * Collect all global (w.r.t. this processor) status about this machine
376 * check into our "mce" struct so that we can use it later to assess
377 * the severity of the problem as we read per-bank specific details.
379 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
383 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
386 * Get the address of the instruction at the time of
387 * the machine check error.
389 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
393 /* Use accurate RIP reporting if available. */
395 m->ip = mce_rdmsrl(rip_msr);
400 * Simple lockless ring to communicate PFNs from the exception handler with the
401 * process context work function. This is vastly simplified because there's
402 * only a single reader and a single writer.
404 #define MCE_RING_SIZE 16 /* we use one entry less */
407 unsigned short start;
409 unsigned long ring[MCE_RING_SIZE];
411 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
413 /* Runs with CPU affinity in workqueue */
414 static int mce_ring_empty(void)
416 struct mce_ring *r = &__get_cpu_var(mce_ring);
418 return r->start == r->end;
421 static int mce_ring_get(unsigned long *pfn)
428 r = &__get_cpu_var(mce_ring);
429 if (r->start == r->end)
431 *pfn = r->ring[r->start];
432 r->start = (r->start + 1) % MCE_RING_SIZE;
439 /* Always runs in MCE context with preempt off */
440 static int mce_ring_add(unsigned long pfn)
442 struct mce_ring *r = &__get_cpu_var(mce_ring);
445 next = (r->end + 1) % MCE_RING_SIZE;
446 if (next == r->start)
448 r->ring[r->end] = pfn;
454 int mce_available(struct cpuinfo_x86 *c)
458 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
461 static void mce_schedule_work(void)
463 if (!mce_ring_empty()) {
464 struct work_struct *work = &__get_cpu_var(mce_work);
465 if (!work_pending(work))
470 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
472 static void mce_irq_work_cb(struct irq_work *entry)
478 static void mce_report_event(struct pt_regs *regs)
480 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
483 * Triggering the work queue here is just an insurance
484 * policy in case the syscall exit notify handler
485 * doesn't run soon enough or ends up running on the
486 * wrong CPU (can happen when audit sleeps)
492 irq_work_queue(&__get_cpu_var(mce_irq_work));
496 * Read ADDR and MISC registers.
498 static void mce_read_aux(struct mce *m, int i)
500 if (m->status & MCI_STATUS_MISCV)
501 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
502 if (m->status & MCI_STATUS_ADDRV) {
503 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
506 * Mask the reported address by the reported granularity.
508 if (mce_ser && (m->status & MCI_STATUS_MISCV)) {
509 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
516 DEFINE_PER_CPU(unsigned, mce_poll_count);
519 * Poll for corrected events or events that happened before reset.
520 * Those are just logged through /dev/mcelog.
522 * This is executed in standard interrupt context.
524 * Note: spec recommends to panic for fatal unsignalled
525 * errors here. However this would be quite problematic --
526 * we would need to reimplement the Monarch handling and
527 * it would mess up the exclusion between exception handler
528 * and poll hander -- * so we skip this for now.
529 * These cases should not happen anyways, or only when the CPU
530 * is already totally * confused. In this case it's likely it will
531 * not fully execute the machine check handler either.
533 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
538 percpu_inc(mce_poll_count);
540 mce_gather_info(&m, NULL);
542 for (i = 0; i < banks; i++) {
543 if (!mce_banks[i].ctl || !test_bit(i, *b))
552 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
553 if (!(m.status & MCI_STATUS_VAL))
557 * Uncorrected or signalled events are handled by the exception
558 * handler when it is enabled, so don't process those here.
560 * TBD do the same check for MCI_STATUS_EN here?
562 if (!(flags & MCP_UC) &&
563 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
568 if (!(flags & MCP_TIMESTAMP))
571 * Don't get the IP here because it's unlikely to
572 * have anything to do with the actual error location.
574 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
578 * Clear state for this bank.
580 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
584 * Don't clear MCG_STATUS here because it's only defined for
590 EXPORT_SYMBOL_GPL(machine_check_poll);
593 * Do a quick check if any of the events requires a panic.
594 * This decides if we keep the events around or clear them.
596 static int mce_no_way_out(struct mce *m, char **msg)
600 for (i = 0; i < banks; i++) {
601 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
602 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
609 * Variable to establish order between CPUs while scanning.
610 * Each CPU spins initially until executing is equal its number.
612 static atomic_t mce_executing;
615 * Defines order of CPUs on entry. First CPU becomes Monarch.
617 static atomic_t mce_callin;
620 * Check if a timeout waiting for other CPUs happened.
622 static int mce_timed_out(u64 *t)
625 * The others already did panic for some reason.
626 * Bail out like in a timeout.
627 * rmb() to tell the compiler that system_state
628 * might have been modified by someone else.
631 if (atomic_read(&mce_paniced))
633 if (!monarch_timeout)
635 if ((s64)*t < SPINUNIT) {
636 /* CHECKME: Make panic default for 1 too? */
638 mce_panic("Timeout synchronizing machine check over CPUs",
645 touch_nmi_watchdog();
650 * The Monarch's reign. The Monarch is the CPU who entered
651 * the machine check handler first. It waits for the others to
652 * raise the exception too and then grades them. When any
653 * error is fatal panic. Only then let the others continue.
655 * The other CPUs entering the MCE handler will be controlled by the
656 * Monarch. They are called Subjects.
658 * This way we prevent any potential data corruption in a unrecoverable case
659 * and also makes sure always all CPU's errors are examined.
661 * Also this detects the case of a machine check event coming from outer
662 * space (not detected by any CPUs) In this case some external agent wants
663 * us to shut down, so panic too.
665 * The other CPUs might still decide to panic if the handler happens
666 * in a unrecoverable place, but in this case the system is in a semi-stable
667 * state and won't corrupt anything by itself. It's ok to let the others
668 * continue for a bit first.
670 * All the spin loops have timeouts; when a timeout happens a CPU
671 * typically elects itself to be Monarch.
673 static void mce_reign(void)
676 struct mce *m = NULL;
677 int global_worst = 0;
682 * This CPU is the Monarch and the other CPUs have run
683 * through their handlers.
684 * Grade the severity of the errors of all the CPUs.
686 for_each_possible_cpu(cpu) {
687 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
689 if (severity > global_worst) {
691 global_worst = severity;
692 m = &per_cpu(mces_seen, cpu);
697 * Cannot recover? Panic here then.
698 * This dumps all the mces in the log buffer and stops the
701 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
702 mce_panic("Fatal Machine check", m, msg);
705 * For UC somewhere we let the CPU who detects it handle it.
706 * Also must let continue the others, otherwise the handling
707 * CPU could deadlock on a lock.
711 * No machine check event found. Must be some external
712 * source or one CPU is hung. Panic.
714 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
715 mce_panic("Machine check from unknown source", NULL, NULL);
718 * Now clear all the mces_seen so that they don't reappear on
721 for_each_possible_cpu(cpu)
722 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
725 static atomic_t global_nwo;
728 * Start of Monarch synchronization. This waits until all CPUs have
729 * entered the exception handler and then determines if any of them
730 * saw a fatal event that requires panic. Then it executes them
731 * in the entry order.
732 * TBD double check parallel CPU hotunplug
734 static int mce_start(int *no_way_out)
737 int cpus = num_online_cpus();
738 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
743 atomic_add(*no_way_out, &global_nwo);
745 * global_nwo should be updated before mce_callin
748 order = atomic_inc_return(&mce_callin);
753 while (atomic_read(&mce_callin) != cpus) {
754 if (mce_timed_out(&timeout)) {
755 atomic_set(&global_nwo, 0);
762 * mce_callin should be read before global_nwo
768 * Monarch: Starts executing now, the others wait.
770 atomic_set(&mce_executing, 1);
773 * Subject: Now start the scanning loop one by one in
774 * the original callin order.
775 * This way when there are any shared banks it will be
776 * only seen by one CPU before cleared, avoiding duplicates.
778 while (atomic_read(&mce_executing) < order) {
779 if (mce_timed_out(&timeout)) {
780 atomic_set(&global_nwo, 0);
788 * Cache the global no_way_out state.
790 *no_way_out = atomic_read(&global_nwo);
796 * Synchronize between CPUs after main scanning loop.
797 * This invokes the bulk of the Monarch processing.
799 static int mce_end(int order)
802 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
810 * Allow others to run.
812 atomic_inc(&mce_executing);
815 /* CHECKME: Can this race with a parallel hotplug? */
816 int cpus = num_online_cpus();
819 * Monarch: Wait for everyone to go through their scanning
822 while (atomic_read(&mce_executing) <= cpus) {
823 if (mce_timed_out(&timeout))
833 * Subject: Wait for Monarch to finish.
835 while (atomic_read(&mce_executing) != 0) {
836 if (mce_timed_out(&timeout))
842 * Don't reset anything. That's done by the Monarch.
848 * Reset all global state.
851 atomic_set(&global_nwo, 0);
852 atomic_set(&mce_callin, 0);
856 * Let others run again.
858 atomic_set(&mce_executing, 0);
863 * Check if the address reported by the CPU is in a format we can parse.
864 * It would be possible to add code for most other cases, but all would
865 * be somewhat complicated (e.g. segment offset would require an instruction
866 * parser). So only support physical addresses up to page granuality for now.
868 static int mce_usable_address(struct mce *m)
870 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
872 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
874 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
879 static void mce_clear_state(unsigned long *toclear)
883 for (i = 0; i < banks; i++) {
884 if (test_bit(i, toclear))
885 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
890 * Need to save faulting physical address associated with a process
891 * in the machine check handler some place where we can grab it back
892 * later in mce_notify_process()
894 #define MCE_INFO_MAX 16
898 struct task_struct *t;
900 } mce_info[MCE_INFO_MAX];
902 static void mce_save_info(__u64 addr)
906 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) {
907 if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
914 mce_panic("Too many concurrent recoverable errors", NULL, NULL);
917 static struct mce_info *mce_find_info(void)
921 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++)
922 if (atomic_read(&mi->inuse) && mi->t == current)
927 static void mce_clear_info(struct mce_info *mi)
929 atomic_set(&mi->inuse, 0);
933 * The actual machine check handler. This only handles real
934 * exceptions when something got corrupted coming in through int 18.
936 * This is executed in NMI context not subject to normal locking rules. This
937 * implies that most kernel services cannot be safely used. Don't even
938 * think about putting a printk in there!
940 * On Intel systems this is entered on all CPUs in parallel through
941 * MCE broadcast. However some CPUs might be broken beyond repair,
942 * so be always careful when synchronizing with others.
944 void do_machine_check(struct pt_regs *regs, long error_code)
946 struct mce m, *final;
951 * Establish sequential order between the CPUs entering the machine
956 * If no_way_out gets set, there is no safe way to recover from this
957 * MCE. If tolerant is cranked up, we'll try anyway.
961 * If kill_it gets set, there might be a way to recover from this
965 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
966 char *msg = "Unknown";
968 atomic_inc(&mce_entry);
970 percpu_inc(mce_exception_count);
975 mce_gather_info(&m, regs);
977 final = &__get_cpu_var(mces_seen);
980 no_way_out = mce_no_way_out(&m, &msg);
985 * When no restart IP might need to kill or panic.
986 * Assume the worst for now, but if we find the
987 * severity is MCE_AR_SEVERITY we have other options.
989 if (!(m.mcgstatus & MCG_STATUS_RIPV))
993 * Go through all the banks in exclusion of the other CPUs.
994 * This way we don't report duplicated events on shared banks
995 * because the first one to see it will clear it.
997 order = mce_start(&no_way_out);
998 for (i = 0; i < banks; i++) {
999 __clear_bit(i, toclear);
1000 if (!mce_banks[i].ctl)
1007 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1008 if ((m.status & MCI_STATUS_VAL) == 0)
1012 * Non uncorrected or non signaled errors are handled by
1013 * machine_check_poll. Leave them alone, unless this panics.
1015 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1020 * Set taint even when machine check was not enabled.
1022 add_taint(TAINT_MACHINE_CHECK);
1024 severity = mce_severity(&m, tolerant, NULL);
1027 * When machine check was for corrected handler don't touch,
1028 * unless we're panicing.
1030 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1032 __set_bit(i, toclear);
1033 if (severity == MCE_NO_SEVERITY) {
1035 * Machine check event was not enabled. Clear, but
1041 mce_read_aux(&m, i);
1044 * Action optional error. Queue address for later processing.
1045 * When the ring overflows we just ignore the AO error.
1046 * RED-PEN add some logging mechanism when
1047 * usable_address or mce_add_ring fails.
1048 * RED-PEN don't ignore overflow for tolerant == 0
1050 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1051 mce_ring_add(m.addr >> PAGE_SHIFT);
1055 if (severity > worst) {
1061 /* mce_clear_state will clear *final, save locally for use later */
1065 mce_clear_state(toclear);
1068 * Do most of the synchronization with other CPUs.
1069 * When there's any problem use only local no_way_out state.
1071 if (mce_end(order) < 0)
1072 no_way_out = worst >= MCE_PANIC_SEVERITY;
1075 * At insane "tolerant" levels we take no action. Otherwise
1076 * we only die if we have no other choice. For less serious
1077 * issues we try to recover, or limit damage to the current
1082 mce_panic("Fatal machine check on current CPU", &m, msg);
1083 if (worst == MCE_AR_SEVERITY) {
1084 /* schedule action before return to userland */
1085 mce_save_info(m.addr);
1086 set_thread_flag(TIF_MCE_NOTIFY);
1087 } else if (kill_it) {
1088 force_sig(SIGBUS, current);
1093 mce_report_event(regs);
1094 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1096 atomic_dec(&mce_entry);
1099 EXPORT_SYMBOL_GPL(do_machine_check);
1101 #ifndef CONFIG_MEMORY_FAILURE
1102 int memory_failure(unsigned long pfn, int vector, int flags)
1104 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1105 BUG_ON(flags & MF_ACTION_REQUIRED);
1106 printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n"
1107 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn);
1114 * Called in process context that interrupted by MCE and marked with
1115 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1116 * This code is allowed to sleep.
1117 * Attempt possible recovery such as calling the high level VM handler to
1118 * process any corrupted pages, and kill/signal current process if required.
1119 * Action required errors are handled here.
1121 void mce_notify_process(void)
1124 struct mce_info *mi = mce_find_info();
1127 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
1128 pfn = mi->paddr >> PAGE_SHIFT;
1130 clear_thread_flag(TIF_MCE_NOTIFY);
1132 pr_err("Uncorrected hardware memory error in user-access at %llx",
1134 if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0) {
1135 pr_err("Memory error not recovered");
1136 force_sig(SIGBUS, current);
1142 * Action optional processing happens here (picking up
1143 * from the list of faulting pages that do_machine_check()
1144 * placed into the "ring").
1146 static void mce_process_work(struct work_struct *dummy)
1150 while (mce_ring_get(&pfn))
1151 memory_failure(pfn, MCE_VECTOR, 0);
1154 #ifdef CONFIG_X86_MCE_INTEL
1156 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1157 * @cpu: The CPU on which the event occurred.
1158 * @status: Event status information
1160 * This function should be called by the thermal interrupt after the
1161 * event has been processed and the decision was made to log the event
1164 * The status parameter will be saved to the 'status' field of 'struct mce'
1165 * and historically has been the register value of the
1166 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1168 void mce_log_therm_throt_event(__u64 status)
1173 m.bank = MCE_THERMAL_BANK;
1177 #endif /* CONFIG_X86_MCE_INTEL */
1180 * Periodic polling timer for "silent" machine check errors. If the
1181 * poller finds an MCE, poll 2x faster. When the poller finds no more
1182 * errors, poll 2x slower (up to check_interval seconds).
1184 static int check_interval = 5 * 60; /* 5 minutes */
1186 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1187 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1189 static void mce_start_timer(unsigned long data)
1191 struct timer_list *t = &per_cpu(mce_timer, data);
1194 WARN_ON(smp_processor_id() != data);
1196 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1197 machine_check_poll(MCP_TIMESTAMP,
1198 &__get_cpu_var(mce_poll_banks));
1202 * Alert userspace if needed. If we logged an MCE, reduce the
1203 * polling interval, otherwise increase the polling interval.
1205 n = &__get_cpu_var(mce_next_interval);
1206 if (mce_notify_irq())
1207 *n = max(*n/2, HZ/100);
1209 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1211 t->expires = jiffies + *n;
1212 add_timer_on(t, smp_processor_id());
1215 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1216 static void mce_timer_delete_all(void)
1220 for_each_online_cpu(cpu)
1221 del_timer_sync(&per_cpu(mce_timer, cpu));
1224 static void mce_do_trigger(struct work_struct *work)
1226 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1229 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1232 * Notify the user(s) about new machine check events.
1233 * Can be called from interrupt context, but not from machine check/NMI
1236 int mce_notify_irq(void)
1238 /* Not more than two messages every minute */
1239 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1241 if (test_and_clear_bit(0, &mce_need_notify)) {
1242 /* wake processes polling /dev/mcelog */
1243 wake_up_interruptible(&mce_chrdev_wait);
1246 * There is no risk of missing notifications because
1247 * work_pending is always cleared before the function is
1250 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1251 schedule_work(&mce_trigger_work);
1253 if (__ratelimit(&ratelimit))
1254 pr_info(HW_ERR "Machine check events logged\n");
1260 EXPORT_SYMBOL_GPL(mce_notify_irq);
1262 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1266 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1269 for (i = 0; i < banks; i++) {
1270 struct mce_bank *b = &mce_banks[i];
1279 * Initialize Machine Checks for a CPU.
1281 static int __cpuinit __mcheck_cpu_cap_init(void)
1286 rdmsrl(MSR_IA32_MCG_CAP, cap);
1288 b = cap & MCG_BANKCNT_MASK;
1290 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1292 if (b > MAX_NR_BANKS) {
1294 "MCE: Using only %u machine check banks out of %u\n",
1299 /* Don't support asymmetric configurations today */
1300 WARN_ON(banks != 0 && b != banks);
1303 int err = __mcheck_cpu_mce_banks_init();
1309 /* Use accurate RIP reporting if available. */
1310 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1311 rip_msr = MSR_IA32_MCG_EIP;
1313 if (cap & MCG_SER_P)
1319 static void __mcheck_cpu_init_generic(void)
1321 mce_banks_t all_banks;
1326 * Log the machine checks left over from the previous reset.
1328 bitmap_fill(all_banks, MAX_NR_BANKS);
1329 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1331 set_in_cr4(X86_CR4_MCE);
1333 rdmsrl(MSR_IA32_MCG_CAP, cap);
1334 if (cap & MCG_CTL_P)
1335 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1337 for (i = 0; i < banks; i++) {
1338 struct mce_bank *b = &mce_banks[i];
1342 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1343 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1347 /* Add per CPU specific workarounds here */
1348 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1350 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1351 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1355 /* This should be disabled by the BIOS, but isn't always */
1356 if (c->x86_vendor == X86_VENDOR_AMD) {
1357 if (c->x86 == 15 && banks > 4) {
1359 * disable GART TBL walk error reporting, which
1360 * trips off incorrectly with the IOMMU & 3ware
1363 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1365 if (c->x86 <= 17 && mce_bootlog < 0) {
1367 * Lots of broken BIOS around that don't clear them
1368 * by default and leave crap in there. Don't log:
1373 * Various K7s with broken bank 0 around. Always disable
1376 if (c->x86 == 6 && banks > 0)
1377 mce_banks[0].ctl = 0;
1380 if (c->x86_vendor == X86_VENDOR_INTEL) {
1382 * SDM documents that on family 6 bank 0 should not be written
1383 * because it aliases to another special BIOS controlled
1385 * But it's not aliased anymore on model 0x1a+
1386 * Don't ignore bank 0 completely because there could be a
1387 * valid event later, merely don't write CTL0.
1390 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1391 mce_banks[0].init = 0;
1394 * All newer Intel systems support MCE broadcasting. Enable
1395 * synchronization with a one second timeout.
1397 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1398 monarch_timeout < 0)
1399 monarch_timeout = USEC_PER_SEC;
1402 * There are also broken BIOSes on some Pentium M and
1405 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1408 if (monarch_timeout < 0)
1409 monarch_timeout = 0;
1410 if (mce_bootlog != 0)
1411 mce_panic_timeout = 30;
1416 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1421 switch (c->x86_vendor) {
1422 case X86_VENDOR_INTEL:
1423 intel_p5_mcheck_init(c);
1426 case X86_VENDOR_CENTAUR:
1427 winchip_mcheck_init(c);
1435 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1437 switch (c->x86_vendor) {
1438 case X86_VENDOR_INTEL:
1439 mce_intel_feature_init(c);
1441 case X86_VENDOR_AMD:
1442 mce_amd_feature_init(c);
1449 static void __mcheck_cpu_init_timer(void)
1451 struct timer_list *t = &__get_cpu_var(mce_timer);
1452 int *n = &__get_cpu_var(mce_next_interval);
1454 setup_timer(t, mce_start_timer, smp_processor_id());
1459 *n = check_interval * HZ;
1462 t->expires = round_jiffies(jiffies + *n);
1463 add_timer_on(t, smp_processor_id());
1466 /* Handle unconfigured int18 (should never happen) */
1467 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1469 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1470 smp_processor_id());
1473 /* Call the installed machine check handler for this CPU setup. */
1474 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1475 unexpected_machine_check;
1478 * Called for each booted CPU to set up machine checks.
1479 * Must be called with preempt off:
1481 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1486 if (__mcheck_cpu_ancient_init(c))
1489 if (!mce_available(c))
1492 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1497 machine_check_vector = do_machine_check;
1499 __mcheck_cpu_init_generic();
1500 __mcheck_cpu_init_vendor(c);
1501 __mcheck_cpu_init_timer();
1502 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1503 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1507 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1510 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1511 static int mce_chrdev_open_count; /* #times opened */
1512 static int mce_chrdev_open_exclu; /* already open exclusive? */
1514 static int mce_chrdev_open(struct inode *inode, struct file *file)
1516 spin_lock(&mce_chrdev_state_lock);
1518 if (mce_chrdev_open_exclu ||
1519 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1520 spin_unlock(&mce_chrdev_state_lock);
1525 if (file->f_flags & O_EXCL)
1526 mce_chrdev_open_exclu = 1;
1527 mce_chrdev_open_count++;
1529 spin_unlock(&mce_chrdev_state_lock);
1531 return nonseekable_open(inode, file);
1534 static int mce_chrdev_release(struct inode *inode, struct file *file)
1536 spin_lock(&mce_chrdev_state_lock);
1538 mce_chrdev_open_count--;
1539 mce_chrdev_open_exclu = 0;
1541 spin_unlock(&mce_chrdev_state_lock);
1546 static void collect_tscs(void *data)
1548 unsigned long *cpu_tsc = (unsigned long *)data;
1550 rdtscll(cpu_tsc[smp_processor_id()]);
1553 static int mce_apei_read_done;
1555 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1556 static int __mce_read_apei(char __user **ubuf, size_t usize)
1562 if (usize < sizeof(struct mce))
1565 rc = apei_read_mce(&m, &record_id);
1566 /* Error or no more MCE record */
1568 mce_apei_read_done = 1;
1572 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1575 * In fact, we should have cleared the record after that has
1576 * been flushed to the disk or sent to network in
1577 * /sbin/mcelog, but we have no interface to support that now,
1578 * so just clear it to avoid duplication.
1580 rc = apei_clear_mce(record_id);
1582 mce_apei_read_done = 1;
1585 *ubuf += sizeof(struct mce);
1590 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1591 size_t usize, loff_t *off)
1593 char __user *buf = ubuf;
1594 unsigned long *cpu_tsc;
1595 unsigned prev, next;
1598 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1602 mutex_lock(&mce_chrdev_read_mutex);
1604 if (!mce_apei_read_done) {
1605 err = __mce_read_apei(&buf, usize);
1606 if (err || buf != ubuf)
1610 next = rcu_dereference_check_mce(mcelog.next);
1612 /* Only supports full reads right now */
1614 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1620 for (i = prev; i < next; i++) {
1621 unsigned long start = jiffies;
1622 struct mce *m = &mcelog.entry[i];
1624 while (!m->finished) {
1625 if (time_after_eq(jiffies, start + 2)) {
1626 memset(m, 0, sizeof(*m));
1632 err |= copy_to_user(buf, m, sizeof(*m));
1638 memset(mcelog.entry + prev, 0,
1639 (next - prev) * sizeof(struct mce));
1641 next = cmpxchg(&mcelog.next, prev, 0);
1642 } while (next != prev);
1644 synchronize_sched();
1647 * Collect entries that were still getting written before the
1650 on_each_cpu(collect_tscs, cpu_tsc, 1);
1652 for (i = next; i < MCE_LOG_LEN; i++) {
1653 struct mce *m = &mcelog.entry[i];
1655 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1656 err |= copy_to_user(buf, m, sizeof(*m));
1659 memset(m, 0, sizeof(*m));
1667 mutex_unlock(&mce_chrdev_read_mutex);
1670 return err ? err : buf - ubuf;
1673 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1675 poll_wait(file, &mce_chrdev_wait, wait);
1676 if (rcu_access_index(mcelog.next))
1677 return POLLIN | POLLRDNORM;
1678 if (!mce_apei_read_done && apei_check_mce())
1679 return POLLIN | POLLRDNORM;
1683 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1686 int __user *p = (int __user *)arg;
1688 if (!capable(CAP_SYS_ADMIN))
1692 case MCE_GET_RECORD_LEN:
1693 return put_user(sizeof(struct mce), p);
1694 case MCE_GET_LOG_LEN:
1695 return put_user(MCE_LOG_LEN, p);
1696 case MCE_GETCLEAR_FLAGS: {
1700 flags = mcelog.flags;
1701 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1703 return put_user(flags, p);
1710 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1711 size_t usize, loff_t *off);
1713 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1714 const char __user *ubuf,
1715 size_t usize, loff_t *off))
1719 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1721 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1722 size_t usize, loff_t *off)
1725 return mce_write(filp, ubuf, usize, off);
1730 static const struct file_operations mce_chrdev_ops = {
1731 .open = mce_chrdev_open,
1732 .release = mce_chrdev_release,
1733 .read = mce_chrdev_read,
1734 .write = mce_chrdev_write,
1735 .poll = mce_chrdev_poll,
1736 .unlocked_ioctl = mce_chrdev_ioctl,
1737 .llseek = no_llseek,
1740 static struct miscdevice mce_chrdev_device = {
1747 * mce=off Disables machine check
1748 * mce=no_cmci Disables CMCI
1749 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1750 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1751 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1752 * monarchtimeout is how long to wait for other CPUs on machine
1753 * check, or 0 to not wait
1754 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1755 * mce=nobootlog Don't log MCEs from before booting.
1757 static int __init mcheck_enable(char *str)
1765 if (!strcmp(str, "off"))
1767 else if (!strcmp(str, "no_cmci"))
1768 mce_cmci_disabled = 1;
1769 else if (!strcmp(str, "dont_log_ce"))
1770 mce_dont_log_ce = 1;
1771 else if (!strcmp(str, "ignore_ce"))
1773 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1774 mce_bootlog = (str[0] == 'b');
1775 else if (isdigit(str[0])) {
1776 get_option(&str, &tolerant);
1779 get_option(&str, &monarch_timeout);
1782 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1788 __setup("mce", mcheck_enable);
1790 int __init mcheck_init(void)
1792 mcheck_intel_therm_init();
1798 * mce_syscore: PM support
1802 * Disable machine checks on suspend and shutdown. We can't really handle
1805 static int mce_disable_error_reporting(void)
1809 for (i = 0; i < banks; i++) {
1810 struct mce_bank *b = &mce_banks[i];
1813 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1818 static int mce_syscore_suspend(void)
1820 return mce_disable_error_reporting();
1823 static void mce_syscore_shutdown(void)
1825 mce_disable_error_reporting();
1829 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1830 * Only one CPU is active at this time, the others get re-added later using
1833 static void mce_syscore_resume(void)
1835 __mcheck_cpu_init_generic();
1836 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1839 static struct syscore_ops mce_syscore_ops = {
1840 .suspend = mce_syscore_suspend,
1841 .shutdown = mce_syscore_shutdown,
1842 .resume = mce_syscore_resume,
1846 * mce_sysdev: Sysfs support
1849 static void mce_cpu_restart(void *data)
1851 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1853 __mcheck_cpu_init_generic();
1854 __mcheck_cpu_init_timer();
1857 /* Reinit MCEs after user configuration changes */
1858 static void mce_restart(void)
1860 mce_timer_delete_all();
1861 on_each_cpu(mce_cpu_restart, NULL, 1);
1864 /* Toggle features for corrected errors */
1865 static void mce_disable_cmci(void *data)
1867 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1872 static void mce_enable_ce(void *all)
1874 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1879 __mcheck_cpu_init_timer();
1882 static struct sysdev_class mce_sysdev_class = {
1883 .name = "machinecheck",
1886 DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1889 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1891 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1893 return container_of(attr, struct mce_bank, attr);
1896 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1899 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1902 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1903 const char *buf, size_t size)
1907 if (strict_strtoull(buf, 0, &new) < 0)
1910 attr_to_bank(attr)->ctl = new;
1917 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1919 strcpy(buf, mce_helper);
1921 return strlen(mce_helper) + 1;
1924 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1925 const char *buf, size_t siz)
1929 strncpy(mce_helper, buf, sizeof(mce_helper));
1930 mce_helper[sizeof(mce_helper)-1] = 0;
1931 p = strchr(mce_helper, '\n');
1936 return strlen(mce_helper) + !!p;
1939 static ssize_t set_ignore_ce(struct sys_device *s,
1940 struct sysdev_attribute *attr,
1941 const char *buf, size_t size)
1945 if (strict_strtoull(buf, 0, &new) < 0)
1948 if (mce_ignore_ce ^ !!new) {
1950 /* disable ce features */
1951 mce_timer_delete_all();
1952 on_each_cpu(mce_disable_cmci, NULL, 1);
1955 /* enable ce features */
1957 on_each_cpu(mce_enable_ce, (void *)1, 1);
1963 static ssize_t set_cmci_disabled(struct sys_device *s,
1964 struct sysdev_attribute *attr,
1965 const char *buf, size_t size)
1969 if (strict_strtoull(buf, 0, &new) < 0)
1972 if (mce_cmci_disabled ^ !!new) {
1975 on_each_cpu(mce_disable_cmci, NULL, 1);
1976 mce_cmci_disabled = 1;
1979 mce_cmci_disabled = 0;
1980 on_each_cpu(mce_enable_ce, NULL, 1);
1986 static ssize_t store_int_with_restart(struct sys_device *s,
1987 struct sysdev_attribute *attr,
1988 const char *buf, size_t size)
1990 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1995 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1996 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1997 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1998 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
2000 static struct sysdev_ext_attribute attr_check_interval = {
2001 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
2002 store_int_with_restart),
2006 static struct sysdev_ext_attribute attr_ignore_ce = {
2007 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
2011 static struct sysdev_ext_attribute attr_cmci_disabled = {
2012 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
2016 static struct sysdev_attribute *mce_sysdev_attrs[] = {
2017 &attr_tolerant.attr,
2018 &attr_check_interval.attr,
2020 &attr_monarch_timeout.attr,
2021 &attr_dont_log_ce.attr,
2022 &attr_ignore_ce.attr,
2023 &attr_cmci_disabled.attr,
2027 static cpumask_var_t mce_sysdev_initialized;
2029 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
2030 static __cpuinit int mce_sysdev_create(unsigned int cpu)
2032 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
2036 if (!mce_available(&boot_cpu_data))
2039 memset(&sysdev->kobj, 0, sizeof(struct kobject));
2041 sysdev->cls = &mce_sysdev_class;
2043 err = sysdev_register(sysdev);
2047 for (i = 0; mce_sysdev_attrs[i]; i++) {
2048 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
2052 for (j = 0; j < banks; j++) {
2053 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
2057 cpumask_set_cpu(cpu, mce_sysdev_initialized);
2062 sysdev_remove_file(sysdev, &mce_banks[j].attr);
2065 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2067 sysdev_unregister(sysdev);
2072 static __cpuinit void mce_sysdev_remove(unsigned int cpu)
2074 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
2077 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
2080 for (i = 0; mce_sysdev_attrs[i]; i++)
2081 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2083 for (i = 0; i < banks; i++)
2084 sysdev_remove_file(sysdev, &mce_banks[i].attr);
2086 sysdev_unregister(sysdev);
2087 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
2090 /* Make sure there are no machine checks on offlined CPUs. */
2091 static void __cpuinit mce_disable_cpu(void *h)
2093 unsigned long action = *(unsigned long *)h;
2096 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2099 if (!(action & CPU_TASKS_FROZEN))
2101 for (i = 0; i < banks; i++) {
2102 struct mce_bank *b = &mce_banks[i];
2105 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2109 static void __cpuinit mce_reenable_cpu(void *h)
2111 unsigned long action = *(unsigned long *)h;
2114 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2117 if (!(action & CPU_TASKS_FROZEN))
2119 for (i = 0; i < banks; i++) {
2120 struct mce_bank *b = &mce_banks[i];
2123 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2127 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2128 static int __cpuinit
2129 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2131 unsigned int cpu = (unsigned long)hcpu;
2132 struct timer_list *t = &per_cpu(mce_timer, cpu);
2136 case CPU_ONLINE_FROZEN:
2137 mce_sysdev_create(cpu);
2138 if (threshold_cpu_callback)
2139 threshold_cpu_callback(action, cpu);
2142 case CPU_DEAD_FROZEN:
2143 if (threshold_cpu_callback)
2144 threshold_cpu_callback(action, cpu);
2145 mce_sysdev_remove(cpu);
2147 case CPU_DOWN_PREPARE:
2148 case CPU_DOWN_PREPARE_FROZEN:
2150 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2152 case CPU_DOWN_FAILED:
2153 case CPU_DOWN_FAILED_FROZEN:
2154 if (!mce_ignore_ce && check_interval) {
2155 t->expires = round_jiffies(jiffies +
2156 __get_cpu_var(mce_next_interval));
2157 add_timer_on(t, cpu);
2159 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2162 /* intentionally ignoring frozen here */
2163 cmci_rediscover(cpu);
2169 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2170 .notifier_call = mce_cpu_callback,
2173 static __init void mce_init_banks(void)
2177 for (i = 0; i < banks; i++) {
2178 struct mce_bank *b = &mce_banks[i];
2179 struct sysdev_attribute *a = &b->attr;
2181 sysfs_attr_init(&a->attr);
2182 a->attr.name = b->attrname;
2183 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2185 a->attr.mode = 0644;
2186 a->show = show_bank;
2187 a->store = set_bank;
2191 static __init int mcheck_init_device(void)
2196 if (!mce_available(&boot_cpu_data))
2199 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2203 err = sysdev_class_register(&mce_sysdev_class);
2207 for_each_online_cpu(i) {
2208 err = mce_sysdev_create(i);
2213 register_syscore_ops(&mce_syscore_ops);
2214 register_hotcpu_notifier(&mce_cpu_notifier);
2216 /* register character device /dev/mcelog */
2217 misc_register(&mce_chrdev_device);
2221 device_initcall(mcheck_init_device);
2224 * Old style boot options parsing. Only for compatibility.
2226 static int __init mcheck_disable(char *str)
2231 __setup("nomce", mcheck_disable);
2233 #ifdef CONFIG_DEBUG_FS
2234 struct dentry *mce_get_debugfs_dir(void)
2236 static struct dentry *dmce;
2239 dmce = debugfs_create_dir("mce", NULL);
2244 static void mce_reset(void)
2247 atomic_set(&mce_fake_paniced, 0);
2248 atomic_set(&mce_executing, 0);
2249 atomic_set(&mce_callin, 0);
2250 atomic_set(&global_nwo, 0);
2253 static int fake_panic_get(void *data, u64 *val)
2259 static int fake_panic_set(void *data, u64 val)
2266 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2267 fake_panic_set, "%llu\n");
2269 static int __init mcheck_debugfs_init(void)
2271 struct dentry *dmce, *ffake_panic;
2273 dmce = mce_get_debugfs_dir();
2276 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2283 late_initcall(mcheck_debugfs_init);