2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
41 #include <asm/processor.h>
42 #include <asm/hw_irq.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
101 * CPU/chipset specific EDAC code can register a notifier call here to print
102 * MCE errors in a human-readable form.
104 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
105 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
107 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
110 pr_emerg(HW_ERR "No human readable MCE decoding support on this CPU type.\n");
111 pr_emerg(HW_ERR "Run the message through 'mcelog --ascii' to decode.\n");
116 static struct notifier_block mce_dec_nb = {
117 .notifier_call = default_decode_mce,
121 /* MCA banks polled by the period polling timer for corrected events */
122 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
123 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
126 static DEFINE_PER_CPU(struct work_struct, mce_work);
128 /* Do initial initialization of a struct mce */
129 void mce_setup(struct mce *m)
131 memset(m, 0, sizeof(struct mce));
132 m->cpu = m->extcpu = smp_processor_id();
134 /* We hope get_seconds stays lockless */
135 m->time = get_seconds();
136 m->cpuvendor = boot_cpu_data.x86_vendor;
137 m->cpuid = cpuid_eax(1);
140 m->socketid = cpu_data(m->extcpu).phys_proc_id;
142 m->apicid = cpu_data(m->extcpu).initial_apicid;
144 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
147 DEFINE_PER_CPU(struct mce, injectm);
148 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
151 * Lockless MCE logging infrastructure.
152 * This avoids deadlocks on printk locks without having to break locks. Also
153 * separate MCEs from kernel messages to avoid bogus bug reports.
156 static struct mce_log mcelog = {
157 .signature = MCE_LOG_SIGNATURE,
159 .recordlen = sizeof(struct mce),
162 void mce_log(struct mce *mce)
164 unsigned next, entry;
166 /* Emit the trace record: */
167 trace_mce_record(mce);
172 entry = rcu_dereference_check_mce(mcelog.next);
175 * If edac_mce is enabled, it will check the error type
176 * and will process it, if it is a known error.
177 * Otherwise, the error will be sent through mcelog
180 if (edac_mce_parse(mce))
184 * When the buffer fills up discard new entries.
185 * Assume that the earlier errors are the more
188 if (entry >= MCE_LOG_LEN) {
189 set_bit(MCE_OVERFLOW,
190 (unsigned long *)&mcelog.flags);
193 /* Old left over entry. Skip: */
194 if (mcelog.entry[entry].finished) {
202 if (cmpxchg(&mcelog.next, entry, next) == entry)
205 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
207 mcelog.entry[entry].finished = 1;
211 set_bit(0, &mce_need_notify);
214 static void print_mce(struct mce *m)
216 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
217 m->extcpu, m->mcgstatus, m->bank, m->status);
220 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
221 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
224 if (m->cs == __KERNEL_CS)
225 print_symbol("{%s}", m->ip);
229 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
231 pr_cont("ADDR %llx ", m->addr);
233 pr_cont("MISC %llx ", m->misc);
236 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
237 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
240 * Print out human-readable details about the MCE error,
241 * (if the CPU has an implementation for that)
243 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
246 #define PANIC_TIMEOUT 5 /* 5 seconds */
248 static atomic_t mce_paniced;
250 static int fake_panic;
251 static atomic_t mce_fake_paniced;
253 /* Panic in progress. Enable interrupts and wait for final IPI */
254 static void wait_for_panic(void)
256 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
260 while (timeout-- > 0)
262 if (panic_timeout == 0)
263 panic_timeout = mce_panic_timeout;
264 panic("Panicing machine check CPU died");
267 static void mce_panic(char *msg, struct mce *final, char *exp)
273 * Make sure only one CPU runs in machine check panic
275 if (atomic_inc_return(&mce_paniced) > 1)
282 /* Don't log too much for fake panic */
283 if (atomic_inc_return(&mce_fake_paniced) > 1)
286 /* First print corrected ones that are still unlogged */
287 for (i = 0; i < MCE_LOG_LEN; i++) {
288 struct mce *m = &mcelog.entry[i];
289 if (!(m->status & MCI_STATUS_VAL))
291 if (!(m->status & MCI_STATUS_UC)) {
294 apei_err = apei_write_mce(m);
297 /* Now print uncorrected but with the final one last */
298 for (i = 0; i < MCE_LOG_LEN; i++) {
299 struct mce *m = &mcelog.entry[i];
300 if (!(m->status & MCI_STATUS_VAL))
302 if (!(m->status & MCI_STATUS_UC))
304 if (!final || memcmp(m, final, sizeof(struct mce))) {
307 apei_err = apei_write_mce(m);
313 apei_err = apei_write_mce(final);
316 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
318 pr_emerg(HW_ERR "Machine check: %s\n", exp);
320 if (panic_timeout == 0)
321 panic_timeout = mce_panic_timeout;
324 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
327 /* Support code for software error injection */
329 static int msr_to_offset(u32 msr)
331 unsigned bank = __this_cpu_read(injectm.bank);
334 return offsetof(struct mce, ip);
335 if (msr == MSR_IA32_MCx_STATUS(bank))
336 return offsetof(struct mce, status);
337 if (msr == MSR_IA32_MCx_ADDR(bank))
338 return offsetof(struct mce, addr);
339 if (msr == MSR_IA32_MCx_MISC(bank))
340 return offsetof(struct mce, misc);
341 if (msr == MSR_IA32_MCG_STATUS)
342 return offsetof(struct mce, mcgstatus);
346 /* MSR access wrappers used for error injection */
347 static u64 mce_rdmsrl(u32 msr)
351 if (__this_cpu_read(injectm.finished)) {
352 int offset = msr_to_offset(msr);
356 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
359 if (rdmsrl_safe(msr, &v)) {
360 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
362 * Return zero in case the access faulted. This should
363 * not happen normally but can happen if the CPU does
364 * something weird, or if the code is buggy.
372 static void mce_wrmsrl(u32 msr, u64 v)
374 if (__this_cpu_read(injectm.finished)) {
375 int offset = msr_to_offset(msr);
378 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
385 * Simple lockless ring to communicate PFNs from the exception handler with the
386 * process context work function. This is vastly simplified because there's
387 * only a single reader and a single writer.
389 #define MCE_RING_SIZE 16 /* we use one entry less */
392 unsigned short start;
394 unsigned long ring[MCE_RING_SIZE];
396 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
398 /* Runs with CPU affinity in workqueue */
399 static int mce_ring_empty(void)
401 struct mce_ring *r = &__get_cpu_var(mce_ring);
403 return r->start == r->end;
406 static int mce_ring_get(unsigned long *pfn)
413 r = &__get_cpu_var(mce_ring);
414 if (r->start == r->end)
416 *pfn = r->ring[r->start];
417 r->start = (r->start + 1) % MCE_RING_SIZE;
424 /* Always runs in MCE context with preempt off */
425 static int mce_ring_add(unsigned long pfn)
427 struct mce_ring *r = &__get_cpu_var(mce_ring);
430 next = (r->end + 1) % MCE_RING_SIZE;
431 if (next == r->start)
433 r->ring[r->end] = pfn;
439 int mce_available(struct cpuinfo_x86 *c)
443 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
446 static void mce_schedule_work(void)
448 if (!mce_ring_empty()) {
449 struct work_struct *work = &__get_cpu_var(mce_work);
450 if (!work_pending(work))
456 * Get the address of the instruction at the time of the machine check
459 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
462 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
470 m->ip = mce_rdmsrl(rip_msr);
473 #ifdef CONFIG_X86_LOCAL_APIC
475 * Called after interrupts have been reenabled again
476 * when a MCE happened during an interrupts off region
479 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
492 static void mce_report_event(struct pt_regs *regs)
494 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
497 * Triggering the work queue here is just an insurance
498 * policy in case the syscall exit notify handler
499 * doesn't run soon enough or ends up running on the
500 * wrong CPU (can happen when audit sleeps)
506 #if defined(CONFIG_X86_LOCAL_APIC) && !defined(CONFIG_XEN)
508 * Without APIC do not notify. The event will be picked
515 * When interrupts are disabled we cannot use
516 * kernel services safely. Trigger an self interrupt
517 * through the APIC to instead do the notification
518 * after interrupts are reenabled again.
520 apic->send_IPI_self(MCE_SELF_VECTOR);
523 * Wait for idle afterwards again so that we don't leave the
524 * APIC in a non idle state because the normal APIC writes
527 apic_wait_icr_idle();
531 DEFINE_PER_CPU(unsigned, mce_poll_count);
534 * Poll for corrected events or events that happened before reset.
535 * Those are just logged through /dev/mcelog.
537 * This is executed in standard interrupt context.
539 * Note: spec recommends to panic for fatal unsignalled
540 * errors here. However this would be quite problematic --
541 * we would need to reimplement the Monarch handling and
542 * it would mess up the exclusion between exception handler
543 * and poll hander -- * so we skip this for now.
544 * These cases should not happen anyways, or only when the CPU
545 * is already totally * confused. In this case it's likely it will
546 * not fully execute the machine check handler either.
548 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
553 percpu_inc(mce_poll_count);
557 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
558 for (i = 0; i < banks; i++) {
559 if (!mce_banks[i].ctl || !test_bit(i, *b))
568 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
569 if (!(m.status & MCI_STATUS_VAL))
573 * Uncorrected or signalled events are handled by the exception
574 * handler when it is enabled, so don't process those here.
576 * TBD do the same check for MCI_STATUS_EN here?
578 if (!(flags & MCP_UC) &&
579 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
582 if (m.status & MCI_STATUS_MISCV)
583 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
584 if (m.status & MCI_STATUS_ADDRV)
585 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
587 if (!(flags & MCP_TIMESTAMP))
590 * Don't get the IP here because it's unlikely to
591 * have anything to do with the actual error location.
593 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
595 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
596 add_taint(TAINT_MACHINE_CHECK);
600 * Clear state for this bank.
602 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
606 * Don't clear MCG_STATUS here because it's only defined for
612 EXPORT_SYMBOL_GPL(machine_check_poll);
615 * Do a quick check if any of the events requires a panic.
616 * This decides if we keep the events around or clear them.
618 static int mce_no_way_out(struct mce *m, char **msg)
622 for (i = 0; i < banks; i++) {
623 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
624 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
631 * Variable to establish order between CPUs while scanning.
632 * Each CPU spins initially until executing is equal its number.
634 static atomic_t mce_executing;
637 * Defines order of CPUs on entry. First CPU becomes Monarch.
639 static atomic_t mce_callin;
642 * Check if a timeout waiting for other CPUs happened.
644 static int mce_timed_out(u64 *t)
647 * The others already did panic for some reason.
648 * Bail out like in a timeout.
649 * rmb() to tell the compiler that system_state
650 * might have been modified by someone else.
653 if (atomic_read(&mce_paniced))
655 if (!monarch_timeout)
657 if ((s64)*t < SPINUNIT) {
658 /* CHECKME: Make panic default for 1 too? */
660 mce_panic("Timeout synchronizing machine check over CPUs",
667 touch_nmi_watchdog();
672 * The Monarch's reign. The Monarch is the CPU who entered
673 * the machine check handler first. It waits for the others to
674 * raise the exception too and then grades them. When any
675 * error is fatal panic. Only then let the others continue.
677 * The other CPUs entering the MCE handler will be controlled by the
678 * Monarch. They are called Subjects.
680 * This way we prevent any potential data corruption in a unrecoverable case
681 * and also makes sure always all CPU's errors are examined.
683 * Also this detects the case of a machine check event coming from outer
684 * space (not detected by any CPUs) In this case some external agent wants
685 * us to shut down, so panic too.
687 * The other CPUs might still decide to panic if the handler happens
688 * in a unrecoverable place, but in this case the system is in a semi-stable
689 * state and won't corrupt anything by itself. It's ok to let the others
690 * continue for a bit first.
692 * All the spin loops have timeouts; when a timeout happens a CPU
693 * typically elects itself to be Monarch.
695 static void mce_reign(void)
698 struct mce *m = NULL;
699 int global_worst = 0;
704 * This CPU is the Monarch and the other CPUs have run
705 * through their handlers.
706 * Grade the severity of the errors of all the CPUs.
708 for_each_possible_cpu(cpu) {
709 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
711 if (severity > global_worst) {
713 global_worst = severity;
714 m = &per_cpu(mces_seen, cpu);
719 * Cannot recover? Panic here then.
720 * This dumps all the mces in the log buffer and stops the
723 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
724 mce_panic("Fatal Machine check", m, msg);
727 * For UC somewhere we let the CPU who detects it handle it.
728 * Also must let continue the others, otherwise the handling
729 * CPU could deadlock on a lock.
733 * No machine check event found. Must be some external
734 * source or one CPU is hung. Panic.
736 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
737 mce_panic("Machine check from unknown source", NULL, NULL);
740 * Now clear all the mces_seen so that they don't reappear on
743 for_each_possible_cpu(cpu)
744 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
747 static atomic_t global_nwo;
750 * Start of Monarch synchronization. This waits until all CPUs have
751 * entered the exception handler and then determines if any of them
752 * saw a fatal event that requires panic. Then it executes them
753 * in the entry order.
754 * TBD double check parallel CPU hotunplug
756 static int mce_start(int *no_way_out)
759 int cpus = num_online_cpus();
760 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
765 atomic_add(*no_way_out, &global_nwo);
767 * global_nwo should be updated before mce_callin
770 order = atomic_inc_return(&mce_callin);
775 while (atomic_read(&mce_callin) != cpus) {
776 if (mce_timed_out(&timeout)) {
777 atomic_set(&global_nwo, 0);
784 * mce_callin should be read before global_nwo
790 * Monarch: Starts executing now, the others wait.
792 atomic_set(&mce_executing, 1);
795 * Subject: Now start the scanning loop one by one in
796 * the original callin order.
797 * This way when there are any shared banks it will be
798 * only seen by one CPU before cleared, avoiding duplicates.
800 while (atomic_read(&mce_executing) < order) {
801 if (mce_timed_out(&timeout)) {
802 atomic_set(&global_nwo, 0);
810 * Cache the global no_way_out state.
812 *no_way_out = atomic_read(&global_nwo);
818 * Synchronize between CPUs after main scanning loop.
819 * This invokes the bulk of the Monarch processing.
821 static int mce_end(int order)
824 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
832 * Allow others to run.
834 atomic_inc(&mce_executing);
837 /* CHECKME: Can this race with a parallel hotplug? */
838 int cpus = num_online_cpus();
841 * Monarch: Wait for everyone to go through their scanning
844 while (atomic_read(&mce_executing) <= cpus) {
845 if (mce_timed_out(&timeout))
855 * Subject: Wait for Monarch to finish.
857 while (atomic_read(&mce_executing) != 0) {
858 if (mce_timed_out(&timeout))
864 * Don't reset anything. That's done by the Monarch.
870 * Reset all global state.
873 atomic_set(&global_nwo, 0);
874 atomic_set(&mce_callin, 0);
878 * Let others run again.
880 atomic_set(&mce_executing, 0);
885 * Check if the address reported by the CPU is in a format we can parse.
886 * It would be possible to add code for most other cases, but all would
887 * be somewhat complicated (e.g. segment offset would require an instruction
888 * parser). So only support physical addresses upto page granuality for now.
890 static int mce_usable_address(struct mce *m)
892 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
894 if ((m->misc & 0x3f) > PAGE_SHIFT)
896 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
901 static void mce_clear_state(unsigned long *toclear)
905 for (i = 0; i < banks; i++) {
906 if (test_bit(i, toclear))
907 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
912 * The actual machine check handler. This only handles real
913 * exceptions when something got corrupted coming in through int 18.
915 * This is executed in NMI context not subject to normal locking rules. This
916 * implies that most kernel services cannot be safely used. Don't even
917 * think about putting a printk in there!
919 * On Intel systems this is entered on all CPUs in parallel through
920 * MCE broadcast. However some CPUs might be broken beyond repair,
921 * so be always careful when synchronizing with others.
923 void do_machine_check(struct pt_regs *regs, long error_code)
925 struct mce m, *final;
930 * Establish sequential order between the CPUs entering the machine
935 * If no_way_out gets set, there is no safe way to recover from this
936 * MCE. If tolerant is cranked up, we'll try anyway.
940 * If kill_it gets set, there might be a way to recover from this
944 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
945 char *msg = "Unknown";
947 atomic_inc(&mce_entry);
949 percpu_inc(mce_exception_count);
951 if (notify_die(DIE_NMI, "machine check", regs, error_code,
952 18, SIGKILL) == NOTIFY_STOP)
959 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
960 final = &__get_cpu_var(mces_seen);
963 no_way_out = mce_no_way_out(&m, &msg);
968 * When no restart IP must always kill or panic.
970 if (!(m.mcgstatus & MCG_STATUS_RIPV))
974 * Go through all the banks in exclusion of the other CPUs.
975 * This way we don't report duplicated events on shared banks
976 * because the first one to see it will clear it.
978 order = mce_start(&no_way_out);
979 for (i = 0; i < banks; i++) {
980 __clear_bit(i, toclear);
981 if (!mce_banks[i].ctl)
988 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
989 if ((m.status & MCI_STATUS_VAL) == 0)
993 * Non uncorrected or non signaled errors are handled by
994 * machine_check_poll. Leave them alone, unless this panics.
996 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1001 * Set taint even when machine check was not enabled.
1003 add_taint(TAINT_MACHINE_CHECK);
1005 severity = mce_severity(&m, tolerant, NULL);
1008 * When machine check was for corrected handler don't touch,
1009 * unless we're panicing.
1011 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1013 __set_bit(i, toclear);
1014 if (severity == MCE_NO_SEVERITY) {
1016 * Machine check event was not enabled. Clear, but
1023 * Kill on action required.
1025 if (severity == MCE_AR_SEVERITY)
1028 if (m.status & MCI_STATUS_MISCV)
1029 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1030 if (m.status & MCI_STATUS_ADDRV)
1031 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1034 * Action optional error. Queue address for later processing.
1035 * When the ring overflows we just ignore the AO error.
1036 * RED-PEN add some logging mechanism when
1037 * usable_address or mce_add_ring fails.
1038 * RED-PEN don't ignore overflow for tolerant == 0
1040 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1041 mce_ring_add(m.addr >> PAGE_SHIFT);
1043 mce_get_rip(&m, regs);
1046 if (severity > worst) {
1053 mce_clear_state(toclear);
1056 * Do most of the synchronization with other CPUs.
1057 * When there's any problem use only local no_way_out state.
1059 if (mce_end(order) < 0)
1060 no_way_out = worst >= MCE_PANIC_SEVERITY;
1063 * If we have decided that we just CAN'T continue, and the user
1064 * has not set tolerant to an insane level, give up and die.
1066 * This is mainly used in the case when the system doesn't
1067 * support MCE broadcasting or it has been disabled.
1069 if (no_way_out && tolerant < 3)
1070 mce_panic("Fatal machine check on current CPU", final, msg);
1073 * If the error seems to be unrecoverable, something should be
1074 * done. Try to kill as little as possible. If we can kill just
1075 * one task, do that. If the user has set the tolerance very
1076 * high, don't try to do anything at all.
1079 if (kill_it && tolerant < 3)
1080 force_sig(SIGBUS, current);
1082 /* notify userspace ASAP */
1083 set_thread_flag(TIF_MCE_NOTIFY);
1086 mce_report_event(regs);
1087 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1089 atomic_dec(&mce_entry);
1092 EXPORT_SYMBOL_GPL(do_machine_check);
1094 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1095 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1097 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1101 * Called after mce notification in process context. This code
1102 * is allowed to sleep. Call the high level VM handler to process
1103 * any corrupted pages.
1104 * Assume that the work queue code only calls this one at a time
1106 * Note we don't disable preemption, so this code might run on the wrong
1107 * CPU. In this case the event is picked up by the scheduled work queue.
1108 * This is merely a fast path to expedite processing in some common
1111 void mce_notify_process(void)
1115 while (mce_ring_get(&pfn))
1116 memory_failure(pfn, MCE_VECTOR);
1119 static void mce_process_work(struct work_struct *dummy)
1121 mce_notify_process();
1124 #ifdef CONFIG_X86_MCE_INTEL
1126 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1127 * @cpu: The CPU on which the event occurred.
1128 * @status: Event status information
1130 * This function should be called by the thermal interrupt after the
1131 * event has been processed and the decision was made to log the event
1134 * The status parameter will be saved to the 'status' field of 'struct mce'
1135 * and historically has been the register value of the
1136 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1138 void mce_log_therm_throt_event(__u64 status)
1143 m.bank = MCE_THERMAL_BANK;
1147 #endif /* CONFIG_X86_MCE_INTEL */
1150 * Periodic polling timer for "silent" machine check errors. If the
1151 * poller finds an MCE, poll 2x faster. When the poller finds no more
1152 * errors, poll 2x slower (up to check_interval seconds).
1154 * We will disable polling in DOM0 since all CMCI/Polling
1155 * mechanism will be done in XEN for Intel CPUs
1157 #if defined (CONFIG_X86_XEN_MCE)
1158 static int check_interval = 0; /* disable polling */
1160 static int check_interval = 5 * 60; /* 5 minutes */
1163 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1164 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1166 static void mce_start_timer(unsigned long data)
1168 struct timer_list *t = &per_cpu(mce_timer, data);
1171 WARN_ON(smp_processor_id() != data);
1173 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1174 machine_check_poll(MCP_TIMESTAMP,
1175 &__get_cpu_var(mce_poll_banks));
1179 * Alert userspace if needed. If we logged an MCE, reduce the
1180 * polling interval, otherwise increase the polling interval.
1182 n = &__get_cpu_var(mce_next_interval);
1183 if (mce_notify_irq())
1184 *n = max(*n/2, HZ/100);
1186 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1188 t->expires = jiffies + *n;
1189 add_timer_on(t, smp_processor_id());
1192 static void mce_do_trigger(struct work_struct *work)
1194 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1197 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1200 * Notify the user(s) about new machine check events.
1201 * Can be called from interrupt context, but not from machine check/NMI
1204 int mce_notify_irq(void)
1206 /* Not more than two messages every minute */
1207 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1209 clear_thread_flag(TIF_MCE_NOTIFY);
1211 if (test_and_clear_bit(0, &mce_need_notify)) {
1212 wake_up_interruptible(&mce_wait);
1215 * There is no risk of missing notifications because
1216 * work_pending is always cleared before the function is
1219 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1220 schedule_work(&mce_trigger_work);
1222 if (__ratelimit(&ratelimit))
1223 pr_info(HW_ERR "Machine check events logged\n");
1229 EXPORT_SYMBOL_GPL(mce_notify_irq);
1231 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1235 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1238 for (i = 0; i < banks; i++) {
1239 struct mce_bank *b = &mce_banks[i];
1248 * Initialize Machine Checks for a CPU.
1250 static int __cpuinit __mcheck_cpu_cap_init(void)
1255 rdmsrl(MSR_IA32_MCG_CAP, cap);
1257 b = cap & MCG_BANKCNT_MASK;
1259 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1261 if (b > MAX_NR_BANKS) {
1263 "MCE: Using only %u machine check banks out of %u\n",
1268 /* Don't support asymmetric configurations today */
1269 WARN_ON(banks != 0 && b != banks);
1272 int err = __mcheck_cpu_mce_banks_init();
1278 /* Use accurate RIP reporting if available. */
1279 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1280 rip_msr = MSR_IA32_MCG_EIP;
1282 if (cap & MCG_SER_P)
1288 static void __mcheck_cpu_init_generic(void)
1290 mce_banks_t all_banks;
1295 * Log the machine checks left over from the previous reset.
1297 bitmap_fill(all_banks, MAX_NR_BANKS);
1298 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1300 set_in_cr4(X86_CR4_MCE);
1302 rdmsrl(MSR_IA32_MCG_CAP, cap);
1303 if (cap & MCG_CTL_P)
1304 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1306 for (i = 0; i < banks; i++) {
1307 struct mce_bank *b = &mce_banks[i];
1311 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1312 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1316 /* Add per CPU specific workarounds here */
1317 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1319 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1320 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1324 /* This should be disabled by the BIOS, but isn't always */
1325 if (c->x86_vendor == X86_VENDOR_AMD) {
1327 if (c->x86 == 15 && banks > 4) {
1329 * disable GART TBL walk error reporting, which
1330 * trips off incorrectly with the IOMMU & 3ware
1333 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1336 if (c->x86 <= 17 && mce_bootlog < 0) {
1338 * Lots of broken BIOS around that don't clear them
1339 * by default and leave crap in there. Don't log:
1344 * Various K7s with broken bank 0 around. Always disable
1347 if (c->x86 == 6 && banks > 0)
1348 mce_banks[0].ctl = 0;
1351 if (c->x86_vendor == X86_VENDOR_INTEL) {
1353 * SDM documents that on family 6 bank 0 should not be written
1354 * because it aliases to another special BIOS controlled
1356 * But it's not aliased anymore on model 0x1a+
1357 * Don't ignore bank 0 completely because there could be a
1358 * valid event later, merely don't write CTL0.
1361 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1362 mce_banks[0].init = 0;
1365 * All newer Intel systems support MCE broadcasting. Enable
1366 * synchronization with a one second timeout.
1368 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1369 monarch_timeout < 0)
1370 monarch_timeout = USEC_PER_SEC;
1373 * There are also broken BIOSes on some Pentium M and
1376 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1379 if (monarch_timeout < 0)
1380 monarch_timeout = 0;
1381 if (mce_bootlog != 0)
1382 mce_panic_timeout = 30;
1387 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1391 switch (c->x86_vendor) {
1392 case X86_VENDOR_INTEL:
1393 intel_p5_mcheck_init(c);
1395 case X86_VENDOR_CENTAUR:
1396 winchip_mcheck_init(c);
1401 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1403 #ifndef CONFIG_X86_64_XEN
1404 switch (c->x86_vendor) {
1405 case X86_VENDOR_INTEL:
1406 mce_intel_feature_init(c);
1408 case X86_VENDOR_AMD:
1409 mce_amd_feature_init(c);
1417 static void __mcheck_cpu_init_timer(void)
1419 struct timer_list *t = &__get_cpu_var(mce_timer);
1420 int *n = &__get_cpu_var(mce_next_interval);
1422 setup_timer(t, mce_start_timer, smp_processor_id());
1427 *n = check_interval * HZ;
1430 t->expires = round_jiffies(jiffies + *n);
1431 add_timer_on(t, smp_processor_id());
1434 /* Handle unconfigured int18 (should never happen) */
1435 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1437 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1438 smp_processor_id());
1441 /* Call the installed machine check handler for this CPU setup. */
1442 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1443 unexpected_machine_check;
1446 * Called for each booted CPU to set up machine checks.
1447 * Must be called with preempt off:
1449 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1454 __mcheck_cpu_ancient_init(c);
1456 if (!mce_available(c))
1459 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1464 machine_check_vector = do_machine_check;
1466 __mcheck_cpu_init_generic();
1467 __mcheck_cpu_init_vendor(c);
1468 __mcheck_cpu_init_timer();
1469 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1474 * Character device to read and clear the MCE log.
1477 static DEFINE_SPINLOCK(mce_state_lock);
1478 static int open_count; /* #times opened */
1479 static int open_exclu; /* already open exclusive? */
1481 static int mce_open(struct inode *inode, struct file *file)
1483 spin_lock(&mce_state_lock);
1485 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1486 spin_unlock(&mce_state_lock);
1491 if (file->f_flags & O_EXCL)
1495 spin_unlock(&mce_state_lock);
1497 return nonseekable_open(inode, file);
1500 static int mce_release(struct inode *inode, struct file *file)
1502 spin_lock(&mce_state_lock);
1507 spin_unlock(&mce_state_lock);
1512 static void collect_tscs(void *data)
1514 unsigned long *cpu_tsc = (unsigned long *)data;
1516 rdtscll(cpu_tsc[smp_processor_id()]);
1519 static int mce_apei_read_done;
1521 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1522 static int __mce_read_apei(char __user **ubuf, size_t usize)
1528 if (usize < sizeof(struct mce))
1531 rc = apei_read_mce(&m, &record_id);
1532 /* Error or no more MCE record */
1534 mce_apei_read_done = 1;
1538 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1541 * In fact, we should have cleared the record after that has
1542 * been flushed to the disk or sent to network in
1543 * /sbin/mcelog, but we have no interface to support that now,
1544 * so just clear it to avoid duplication.
1546 rc = apei_clear_mce(record_id);
1548 mce_apei_read_done = 1;
1551 *ubuf += sizeof(struct mce);
1556 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1559 char __user *buf = ubuf;
1560 unsigned long *cpu_tsc;
1561 unsigned prev, next;
1564 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1568 mutex_lock(&mce_read_mutex);
1570 if (!mce_apei_read_done) {
1571 err = __mce_read_apei(&buf, usize);
1572 if (err || buf != ubuf)
1576 next = rcu_dereference_check_mce(mcelog.next);
1578 /* Only supports full reads right now */
1580 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1586 for (i = prev; i < next; i++) {
1587 unsigned long start = jiffies;
1589 while (!mcelog.entry[i].finished) {
1590 if (time_after_eq(jiffies, start + 2)) {
1591 memset(mcelog.entry + i, 0,
1592 sizeof(struct mce));
1598 err |= copy_to_user(buf, mcelog.entry + i,
1599 sizeof(struct mce));
1600 buf += sizeof(struct mce);
1605 memset(mcelog.entry + prev, 0,
1606 (next - prev) * sizeof(struct mce));
1608 next = cmpxchg(&mcelog.next, prev, 0);
1609 } while (next != prev);
1611 synchronize_sched();
1614 * Collect entries that were still getting written before the
1617 on_each_cpu(collect_tscs, cpu_tsc, 1);
1619 for (i = next; i < MCE_LOG_LEN; i++) {
1620 if (mcelog.entry[i].finished &&
1621 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1622 err |= copy_to_user(buf, mcelog.entry+i,
1623 sizeof(struct mce));
1625 buf += sizeof(struct mce);
1626 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1634 mutex_unlock(&mce_read_mutex);
1637 return err ? err : buf - ubuf;
1640 static unsigned int mce_poll(struct file *file, poll_table *wait)
1642 poll_wait(file, &mce_wait, wait);
1643 if (rcu_dereference_check_mce(mcelog.next))
1644 return POLLIN | POLLRDNORM;
1645 if (!mce_apei_read_done && apei_check_mce())
1646 return POLLIN | POLLRDNORM;
1650 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1652 int __user *p = (int __user *)arg;
1654 if (!capable(CAP_SYS_ADMIN))
1658 case MCE_GET_RECORD_LEN:
1659 return put_user(sizeof(struct mce), p);
1660 case MCE_GET_LOG_LEN:
1661 return put_user(MCE_LOG_LEN, p);
1662 case MCE_GETCLEAR_FLAGS: {
1666 flags = mcelog.flags;
1667 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1669 return put_user(flags, p);
1676 /* Modified in mce-inject.c, so not static or const */
1677 struct file_operations mce_chrdev_ops = {
1679 .release = mce_release,
1682 .unlocked_ioctl = mce_ioctl,
1683 .llseek = no_llseek,
1685 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1687 static struct miscdevice mce_log_device = {
1694 * mce=off Disables machine check
1695 * mce=no_cmci Disables CMCI
1696 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1697 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1698 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1699 * monarchtimeout is how long to wait for other CPUs on machine
1700 * check, or 0 to not wait
1701 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1702 * mce=nobootlog Don't log MCEs from before booting.
1704 static int __init mcheck_enable(char *str)
1712 if (!strcmp(str, "off"))
1714 else if (!strcmp(str, "no_cmci"))
1715 mce_cmci_disabled = 1;
1716 else if (!strcmp(str, "dont_log_ce"))
1717 mce_dont_log_ce = 1;
1718 else if (!strcmp(str, "ignore_ce"))
1720 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1721 mce_bootlog = (str[0] == 'b');
1722 else if (isdigit(str[0])) {
1723 get_option(&str, &tolerant);
1726 get_option(&str, &monarch_timeout);
1729 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1735 __setup("mce", mcheck_enable);
1737 int __init mcheck_init(void)
1739 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1741 mcheck_intel_therm_init();
1751 * Disable machine checks on suspend and shutdown. We can't really handle
1754 static int mce_disable_error_reporting(void)
1758 for (i = 0; i < banks; i++) {
1759 struct mce_bank *b = &mce_banks[i];
1762 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1767 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1769 return mce_disable_error_reporting();
1772 static int mce_shutdown(struct sys_device *dev)
1774 return mce_disable_error_reporting();
1778 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1779 * Only one CPU is active at this time, the others get re-added later using
1782 static int mce_resume(struct sys_device *dev)
1784 __mcheck_cpu_init_generic();
1785 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1790 static void mce_cpu_restart(void *data)
1792 del_timer_sync(&__get_cpu_var(mce_timer));
1793 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1795 __mcheck_cpu_init_generic();
1796 __mcheck_cpu_init_timer();
1799 /* Reinit MCEs after user configuration changes */
1800 static void mce_restart(void)
1802 on_each_cpu(mce_cpu_restart, NULL, 1);
1805 /* Toggle features for corrected errors */
1806 static void mce_disable_ce(void *all)
1808 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1811 del_timer_sync(&__get_cpu_var(mce_timer));
1815 static void mce_enable_ce(void *all)
1817 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1822 __mcheck_cpu_init_timer();
1825 static struct sysdev_class mce_sysclass = {
1826 .suspend = mce_suspend,
1827 .shutdown = mce_shutdown,
1828 .resume = mce_resume,
1829 .name = "machinecheck",
1832 DEFINE_PER_CPU(struct sys_device, mce_dev);
1835 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1837 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1839 return container_of(attr, struct mce_bank, attr);
1842 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1845 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1848 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1849 const char *buf, size_t size)
1853 if (strict_strtoull(buf, 0, &new) < 0)
1856 attr_to_bank(attr)->ctl = new;
1863 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1865 strcpy(buf, mce_helper);
1867 return strlen(mce_helper) + 1;
1870 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1871 const char *buf, size_t siz)
1875 strncpy(mce_helper, buf, sizeof(mce_helper));
1876 mce_helper[sizeof(mce_helper)-1] = 0;
1877 p = strchr(mce_helper, '\n');
1882 return strlen(mce_helper) + !!p;
1885 static ssize_t set_ignore_ce(struct sys_device *s,
1886 struct sysdev_attribute *attr,
1887 const char *buf, size_t size)
1891 if (strict_strtoull(buf, 0, &new) < 0)
1894 if (mce_ignore_ce ^ !!new) {
1896 /* disable ce features */
1897 on_each_cpu(mce_disable_ce, (void *)1, 1);
1900 /* enable ce features */
1902 on_each_cpu(mce_enable_ce, (void *)1, 1);
1908 static ssize_t set_cmci_disabled(struct sys_device *s,
1909 struct sysdev_attribute *attr,
1910 const char *buf, size_t size)
1914 if (strict_strtoull(buf, 0, &new) < 0)
1917 if (mce_cmci_disabled ^ !!new) {
1920 on_each_cpu(mce_disable_ce, NULL, 1);
1921 mce_cmci_disabled = 1;
1924 mce_cmci_disabled = 0;
1925 on_each_cpu(mce_enable_ce, NULL, 1);
1931 static ssize_t store_int_with_restart(struct sys_device *s,
1932 struct sysdev_attribute *attr,
1933 const char *buf, size_t size)
1935 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1940 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1941 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1942 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1943 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1945 static struct sysdev_ext_attribute attr_check_interval = {
1946 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1947 store_int_with_restart),
1951 static struct sysdev_ext_attribute attr_ignore_ce = {
1952 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1956 static struct sysdev_ext_attribute attr_cmci_disabled = {
1957 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1961 static struct sysdev_attribute *mce_attrs[] = {
1962 &attr_tolerant.attr,
1963 &attr_check_interval.attr,
1965 &attr_monarch_timeout.attr,
1966 &attr_dont_log_ce.attr,
1967 &attr_ignore_ce.attr,
1968 &attr_cmci_disabled.attr,
1972 static cpumask_var_t mce_dev_initialized;
1974 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1975 static __cpuinit int mce_create_device(unsigned int cpu)
1980 if (!mce_available(&boot_cpu_data))
1983 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1984 per_cpu(mce_dev, cpu).id = cpu;
1985 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1987 err = sysdev_register(&per_cpu(mce_dev, cpu));
1991 for (i = 0; mce_attrs[i]; i++) {
1992 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1996 for (j = 0; j < banks; j++) {
1997 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1998 &mce_banks[j].attr);
2002 cpumask_set_cpu(cpu, mce_dev_initialized);
2007 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
2010 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2012 sysdev_unregister(&per_cpu(mce_dev, cpu));
2017 static __cpuinit void mce_remove_device(unsigned int cpu)
2021 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2024 for (i = 0; mce_attrs[i]; i++)
2025 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2027 for (i = 0; i < banks; i++)
2028 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2030 sysdev_unregister(&per_cpu(mce_dev, cpu));
2031 cpumask_clear_cpu(cpu, mce_dev_initialized);
2034 /* Make sure there are no machine checks on offlined CPUs. */
2035 static void __cpuinit mce_disable_cpu(void *h)
2037 unsigned long action = *(unsigned long *)h;
2040 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2043 if (!(action & CPU_TASKS_FROZEN))
2045 for (i = 0; i < banks; i++) {
2046 struct mce_bank *b = &mce_banks[i];
2049 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2053 static void __cpuinit mce_reenable_cpu(void *h)
2055 unsigned long action = *(unsigned long *)h;
2058 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2061 if (!(action & CPU_TASKS_FROZEN))
2063 for (i = 0; i < banks; i++) {
2064 struct mce_bank *b = &mce_banks[i];
2067 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2071 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2072 static int __cpuinit
2073 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2075 unsigned int cpu = (unsigned long)hcpu;
2076 struct timer_list *t = &per_cpu(mce_timer, cpu);
2080 case CPU_ONLINE_FROZEN:
2081 mce_create_device(cpu);
2082 if (threshold_cpu_callback)
2083 threshold_cpu_callback(action, cpu);
2086 case CPU_DEAD_FROZEN:
2087 if (threshold_cpu_callback)
2088 threshold_cpu_callback(action, cpu);
2089 mce_remove_device(cpu);
2091 case CPU_DOWN_PREPARE:
2092 case CPU_DOWN_PREPARE_FROZEN:
2094 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2096 case CPU_DOWN_FAILED:
2097 case CPU_DOWN_FAILED_FROZEN:
2098 if (!mce_ignore_ce && check_interval) {
2099 t->expires = round_jiffies(jiffies +
2100 __get_cpu_var(mce_next_interval));
2101 add_timer_on(t, cpu);
2103 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2106 /* intentionally ignoring frozen here */
2107 cmci_rediscover(cpu);
2113 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2114 .notifier_call = mce_cpu_callback,
2117 static __init void mce_init_banks(void)
2121 for (i = 0; i < banks; i++) {
2122 struct mce_bank *b = &mce_banks[i];
2123 struct sysdev_attribute *a = &b->attr;
2125 sysfs_attr_init(&a->attr);
2126 a->attr.name = b->attrname;
2127 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2129 a->attr.mode = 0644;
2130 a->show = show_bank;
2131 a->store = set_bank;
2135 static __init int mcheck_init_device(void)
2140 if (!mce_available(&boot_cpu_data))
2143 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2147 err = sysdev_class_register(&mce_sysclass);
2151 for_each_online_cpu(i) {
2152 err = mce_create_device(i);
2157 register_hotcpu_notifier(&mce_cpu_notifier);
2158 misc_register(&mce_log_device);
2160 #ifdef CONFIG_X86_XEN_MCE
2161 if (is_initial_xendomain()) {
2162 /* Register vIRQ handler for MCE LOG processing */
2163 extern int bind_virq_for_mce(void);
2165 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2166 bind_virq_for_mce();
2173 device_initcall(mcheck_init_device);
2176 * Old style boot options parsing. Only for compatibility.
2178 static int __init mcheck_disable(char *str)
2183 __setup("nomce", mcheck_disable);
2185 #ifdef CONFIG_DEBUG_FS
2186 struct dentry *mce_get_debugfs_dir(void)
2188 static struct dentry *dmce;
2191 dmce = debugfs_create_dir("mce", NULL);
2196 static void mce_reset(void)
2199 atomic_set(&mce_fake_paniced, 0);
2200 atomic_set(&mce_executing, 0);
2201 atomic_set(&mce_callin, 0);
2202 atomic_set(&global_nwo, 0);
2205 static int fake_panic_get(void *data, u64 *val)
2211 static int fake_panic_set(void *data, u64 val)
2218 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2219 fake_panic_set, "%llu\n");
2221 static int __init mcheck_debugfs_init(void)
2223 struct dentry *dmce, *ffake_panic;
2225 dmce = mce_get_debugfs_dir();
2228 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2235 late_initcall(mcheck_debugfs_init);