2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
40 #include <linux/irq_work.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
105 /* MCA banks polled by the period polling timer for corrected events */
106 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce *m)
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
123 m->socketid = cpu_data(m->extcpu).phys_proc_id;
125 m->apicid = cpu_data(m->extcpu).initial_apicid;
126 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
129 DEFINE_PER_CPU(struct mce, injectm);
130 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
133 * Lockless MCE logging infrastructure.
134 * This avoids deadlocks on printk locks without having to break locks. Also
135 * separate MCEs from kernel messages to avoid bogus bug reports.
138 static struct mce_log mcelog = {
139 .signature = MCE_LOG_SIGNATURE,
141 .recordlen = sizeof(struct mce),
144 void mce_log(struct mce *mce)
146 unsigned next, entry;
148 /* Emit the trace record: */
149 trace_mce_record(mce);
154 entry = rcu_dereference_check_mce(mcelog.next);
157 * If edac_mce is enabled, it will check the error type
158 * and will process it, if it is a known error.
159 * Otherwise, the error will be sent through mcelog
162 if (edac_mce_parse(mce))
166 * When the buffer fills up discard new entries.
167 * Assume that the earlier errors are the more
170 if (entry >= MCE_LOG_LEN) {
171 set_bit(MCE_OVERFLOW,
172 (unsigned long *)&mcelog.flags);
175 /* Old left over entry. Skip: */
176 if (mcelog.entry[entry].finished) {
184 if (cmpxchg(&mcelog.next, entry, next) == entry)
187 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
189 mcelog.entry[entry].finished = 1;
193 set_bit(0, &mce_need_notify);
196 static void print_mce(struct mce *m)
200 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
201 m->extcpu, m->mcgstatus, m->bank, m->status);
204 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
205 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
208 if (m->cs == __KERNEL_CS)
209 print_symbol("{%s}", m->ip);
213 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
215 pr_cont("ADDR %llx ", m->addr);
217 pr_cont("MISC %llx ", m->misc);
220 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
221 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
224 * Print out human-readable details about the MCE error,
225 * (if the CPU has an implementation for that)
227 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
228 if (ret == NOTIFY_STOP)
231 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
234 #define PANIC_TIMEOUT 5 /* 5 seconds */
236 static atomic_t mce_paniced;
238 static int fake_panic;
239 static atomic_t mce_fake_paniced;
241 /* Panic in progress. Enable interrupts and wait for final IPI */
242 static void wait_for_panic(void)
244 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
248 while (timeout-- > 0)
250 if (panic_timeout == 0)
251 panic_timeout = mce_panic_timeout;
252 panic("Panicing machine check CPU died");
255 static void mce_panic(char *msg, struct mce *final, char *exp)
261 * Make sure only one CPU runs in machine check panic
263 if (atomic_inc_return(&mce_paniced) > 1)
270 /* Don't log too much for fake panic */
271 if (atomic_inc_return(&mce_fake_paniced) > 1)
274 /* First print corrected ones that are still unlogged */
275 for (i = 0; i < MCE_LOG_LEN; i++) {
276 struct mce *m = &mcelog.entry[i];
277 if (!(m->status & MCI_STATUS_VAL))
279 if (!(m->status & MCI_STATUS_UC)) {
282 apei_err = apei_write_mce(m);
285 /* Now print uncorrected but with the final one last */
286 for (i = 0; i < MCE_LOG_LEN; i++) {
287 struct mce *m = &mcelog.entry[i];
288 if (!(m->status & MCI_STATUS_VAL))
290 if (!(m->status & MCI_STATUS_UC))
292 if (!final || memcmp(m, final, sizeof(struct mce))) {
295 apei_err = apei_write_mce(m);
301 apei_err = apei_write_mce(final);
304 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
306 pr_emerg(HW_ERR "Machine check: %s\n", exp);
308 if (panic_timeout == 0)
309 panic_timeout = mce_panic_timeout;
312 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
315 /* Support code for software error injection */
317 static int msr_to_offset(u32 msr)
319 unsigned bank = __this_cpu_read(injectm.bank);
322 return offsetof(struct mce, ip);
323 if (msr == MSR_IA32_MCx_STATUS(bank))
324 return offsetof(struct mce, status);
325 if (msr == MSR_IA32_MCx_ADDR(bank))
326 return offsetof(struct mce, addr);
327 if (msr == MSR_IA32_MCx_MISC(bank))
328 return offsetof(struct mce, misc);
329 if (msr == MSR_IA32_MCG_STATUS)
330 return offsetof(struct mce, mcgstatus);
334 /* MSR access wrappers used for error injection */
335 static u64 mce_rdmsrl(u32 msr)
339 if (__this_cpu_read(injectm.finished)) {
340 int offset = msr_to_offset(msr);
344 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
347 if (rdmsrl_safe(msr, &v)) {
348 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
350 * Return zero in case the access faulted. This should
351 * not happen normally but can happen if the CPU does
352 * something weird, or if the code is buggy.
360 static void mce_wrmsrl(u32 msr, u64 v)
362 if (__this_cpu_read(injectm.finished)) {
363 int offset = msr_to_offset(msr);
366 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
373 * Collect all global (w.r.t. this processor) status about this machine
374 * check into our "mce" struct so that we can use it later to assess
375 * the severity of the problem as we read per-bank specific details.
377 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
381 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
384 * Get the address of the instruction at the time of
385 * the machine check error.
387 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
391 /* Use accurate RIP reporting if available. */
393 m->ip = mce_rdmsrl(rip_msr);
398 * Simple lockless ring to communicate PFNs from the exception handler with the
399 * process context work function. This is vastly simplified because there's
400 * only a single reader and a single writer.
402 #define MCE_RING_SIZE 16 /* we use one entry less */
405 unsigned short start;
407 unsigned long ring[MCE_RING_SIZE];
409 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
411 /* Runs with CPU affinity in workqueue */
412 static int mce_ring_empty(void)
414 struct mce_ring *r = &__get_cpu_var(mce_ring);
416 return r->start == r->end;
419 static int mce_ring_get(unsigned long *pfn)
426 r = &__get_cpu_var(mce_ring);
427 if (r->start == r->end)
429 *pfn = r->ring[r->start];
430 r->start = (r->start + 1) % MCE_RING_SIZE;
437 /* Always runs in MCE context with preempt off */
438 static int mce_ring_add(unsigned long pfn)
440 struct mce_ring *r = &__get_cpu_var(mce_ring);
443 next = (r->end + 1) % MCE_RING_SIZE;
444 if (next == r->start)
446 r->ring[r->end] = pfn;
452 int mce_available(struct cpuinfo_x86 *c)
456 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
459 static void mce_schedule_work(void)
461 if (!mce_ring_empty()) {
462 struct work_struct *work = &__get_cpu_var(mce_work);
463 if (!work_pending(work))
468 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
470 static void mce_irq_work_cb(struct irq_work *entry)
476 static void mce_report_event(struct pt_regs *regs)
478 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
481 * Triggering the work queue here is just an insurance
482 * policy in case the syscall exit notify handler
483 * doesn't run soon enough or ends up running on the
484 * wrong CPU (can happen when audit sleeps)
490 irq_work_queue(&__get_cpu_var(mce_irq_work));
493 DEFINE_PER_CPU(unsigned, mce_poll_count);
496 * Poll for corrected events or events that happened before reset.
497 * Those are just logged through /dev/mcelog.
499 * This is executed in standard interrupt context.
501 * Note: spec recommends to panic for fatal unsignalled
502 * errors here. However this would be quite problematic --
503 * we would need to reimplement the Monarch handling and
504 * it would mess up the exclusion between exception handler
505 * and poll hander -- * so we skip this for now.
506 * These cases should not happen anyways, or only when the CPU
507 * is already totally * confused. In this case it's likely it will
508 * not fully execute the machine check handler either.
510 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
515 percpu_inc(mce_poll_count);
517 mce_gather_info(&m, NULL);
519 for (i = 0; i < banks; i++) {
520 if (!mce_banks[i].ctl || !test_bit(i, *b))
529 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
530 if (!(m.status & MCI_STATUS_VAL))
534 * Uncorrected or signalled events are handled by the exception
535 * handler when it is enabled, so don't process those here.
537 * TBD do the same check for MCI_STATUS_EN here?
539 if (!(flags & MCP_UC) &&
540 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
543 if (m.status & MCI_STATUS_MISCV)
544 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
545 if (m.status & MCI_STATUS_ADDRV)
546 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
548 if (!(flags & MCP_TIMESTAMP))
551 * Don't get the IP here because it's unlikely to
552 * have anything to do with the actual error location.
554 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
556 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
560 * Clear state for this bank.
562 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
566 * Don't clear MCG_STATUS here because it's only defined for
572 EXPORT_SYMBOL_GPL(machine_check_poll);
575 * Do a quick check if any of the events requires a panic.
576 * This decides if we keep the events around or clear them.
578 static int mce_no_way_out(struct mce *m, char **msg)
582 for (i = 0; i < banks; i++) {
583 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
584 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
591 * Variable to establish order between CPUs while scanning.
592 * Each CPU spins initially until executing is equal its number.
594 static atomic_t mce_executing;
597 * Defines order of CPUs on entry. First CPU becomes Monarch.
599 static atomic_t mce_callin;
602 * Check if a timeout waiting for other CPUs happened.
604 static int mce_timed_out(u64 *t)
607 * The others already did panic for some reason.
608 * Bail out like in a timeout.
609 * rmb() to tell the compiler that system_state
610 * might have been modified by someone else.
613 if (atomic_read(&mce_paniced))
615 if (!monarch_timeout)
617 if ((s64)*t < SPINUNIT) {
618 /* CHECKME: Make panic default for 1 too? */
620 mce_panic("Timeout synchronizing machine check over CPUs",
627 touch_nmi_watchdog();
632 * The Monarch's reign. The Monarch is the CPU who entered
633 * the machine check handler first. It waits for the others to
634 * raise the exception too and then grades them. When any
635 * error is fatal panic. Only then let the others continue.
637 * The other CPUs entering the MCE handler will be controlled by the
638 * Monarch. They are called Subjects.
640 * This way we prevent any potential data corruption in a unrecoverable case
641 * and also makes sure always all CPU's errors are examined.
643 * Also this detects the case of a machine check event coming from outer
644 * space (not detected by any CPUs) In this case some external agent wants
645 * us to shut down, so panic too.
647 * The other CPUs might still decide to panic if the handler happens
648 * in a unrecoverable place, but in this case the system is in a semi-stable
649 * state and won't corrupt anything by itself. It's ok to let the others
650 * continue for a bit first.
652 * All the spin loops have timeouts; when a timeout happens a CPU
653 * typically elects itself to be Monarch.
655 static void mce_reign(void)
658 struct mce *m = NULL;
659 int global_worst = 0;
664 * This CPU is the Monarch and the other CPUs have run
665 * through their handlers.
666 * Grade the severity of the errors of all the CPUs.
668 for_each_possible_cpu(cpu) {
669 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
671 if (severity > global_worst) {
673 global_worst = severity;
674 m = &per_cpu(mces_seen, cpu);
679 * Cannot recover? Panic here then.
680 * This dumps all the mces in the log buffer and stops the
683 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
684 mce_panic("Fatal Machine check", m, msg);
687 * For UC somewhere we let the CPU who detects it handle it.
688 * Also must let continue the others, otherwise the handling
689 * CPU could deadlock on a lock.
693 * No machine check event found. Must be some external
694 * source or one CPU is hung. Panic.
696 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
697 mce_panic("Machine check from unknown source", NULL, NULL);
700 * Now clear all the mces_seen so that they don't reappear on
703 for_each_possible_cpu(cpu)
704 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
707 static atomic_t global_nwo;
710 * Start of Monarch synchronization. This waits until all CPUs have
711 * entered the exception handler and then determines if any of them
712 * saw a fatal event that requires panic. Then it executes them
713 * in the entry order.
714 * TBD double check parallel CPU hotunplug
716 static int mce_start(int *no_way_out)
719 int cpus = num_online_cpus();
720 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
725 atomic_add(*no_way_out, &global_nwo);
727 * global_nwo should be updated before mce_callin
730 order = atomic_inc_return(&mce_callin);
735 while (atomic_read(&mce_callin) != cpus) {
736 if (mce_timed_out(&timeout)) {
737 atomic_set(&global_nwo, 0);
744 * mce_callin should be read before global_nwo
750 * Monarch: Starts executing now, the others wait.
752 atomic_set(&mce_executing, 1);
755 * Subject: Now start the scanning loop one by one in
756 * the original callin order.
757 * This way when there are any shared banks it will be
758 * only seen by one CPU before cleared, avoiding duplicates.
760 while (atomic_read(&mce_executing) < order) {
761 if (mce_timed_out(&timeout)) {
762 atomic_set(&global_nwo, 0);
770 * Cache the global no_way_out state.
772 *no_way_out = atomic_read(&global_nwo);
778 * Synchronize between CPUs after main scanning loop.
779 * This invokes the bulk of the Monarch processing.
781 static int mce_end(int order)
784 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
792 * Allow others to run.
794 atomic_inc(&mce_executing);
797 /* CHECKME: Can this race with a parallel hotplug? */
798 int cpus = num_online_cpus();
801 * Monarch: Wait for everyone to go through their scanning
804 while (atomic_read(&mce_executing) <= cpus) {
805 if (mce_timed_out(&timeout))
815 * Subject: Wait for Monarch to finish.
817 while (atomic_read(&mce_executing) != 0) {
818 if (mce_timed_out(&timeout))
824 * Don't reset anything. That's done by the Monarch.
830 * Reset all global state.
833 atomic_set(&global_nwo, 0);
834 atomic_set(&mce_callin, 0);
838 * Let others run again.
840 atomic_set(&mce_executing, 0);
845 * Check if the address reported by the CPU is in a format we can parse.
846 * It would be possible to add code for most other cases, but all would
847 * be somewhat complicated (e.g. segment offset would require an instruction
848 * parser). So only support physical addresses up to page granuality for now.
850 static int mce_usable_address(struct mce *m)
852 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
854 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
856 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
861 static void mce_clear_state(unsigned long *toclear)
865 for (i = 0; i < banks; i++) {
866 if (test_bit(i, toclear))
867 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
872 * The actual machine check handler. This only handles real
873 * exceptions when something got corrupted coming in through int 18.
875 * This is executed in NMI context not subject to normal locking rules. This
876 * implies that most kernel services cannot be safely used. Don't even
877 * think about putting a printk in there!
879 * On Intel systems this is entered on all CPUs in parallel through
880 * MCE broadcast. However some CPUs might be broken beyond repair,
881 * so be always careful when synchronizing with others.
883 void do_machine_check(struct pt_regs *regs, long error_code)
885 struct mce m, *final;
890 * Establish sequential order between the CPUs entering the machine
895 * If no_way_out gets set, there is no safe way to recover from this
896 * MCE. If tolerant is cranked up, we'll try anyway.
900 * If kill_it gets set, there might be a way to recover from this
904 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
905 char *msg = "Unknown";
907 atomic_inc(&mce_entry);
909 percpu_inc(mce_exception_count);
911 if (notify_die(DIE_NMI, "machine check", regs, error_code,
912 18, SIGKILL) == NOTIFY_STOP)
917 mce_gather_info(&m, regs);
919 final = &__get_cpu_var(mces_seen);
922 no_way_out = mce_no_way_out(&m, &msg);
927 * When no restart IP must always kill or panic.
929 if (!(m.mcgstatus & MCG_STATUS_RIPV))
933 * Go through all the banks in exclusion of the other CPUs.
934 * This way we don't report duplicated events on shared banks
935 * because the first one to see it will clear it.
937 order = mce_start(&no_way_out);
938 for (i = 0; i < banks; i++) {
939 __clear_bit(i, toclear);
940 if (!mce_banks[i].ctl)
947 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
948 if ((m.status & MCI_STATUS_VAL) == 0)
952 * Non uncorrected or non signaled errors are handled by
953 * machine_check_poll. Leave them alone, unless this panics.
955 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
960 * Set taint even when machine check was not enabled.
962 add_taint(TAINT_MACHINE_CHECK);
964 severity = mce_severity(&m, tolerant, NULL);
967 * When machine check was for corrected handler don't touch,
968 * unless we're panicing.
970 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
972 __set_bit(i, toclear);
973 if (severity == MCE_NO_SEVERITY) {
975 * Machine check event was not enabled. Clear, but
982 * Kill on action required.
984 if (severity == MCE_AR_SEVERITY)
987 if (m.status & MCI_STATUS_MISCV)
988 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
989 if (m.status & MCI_STATUS_ADDRV)
990 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
993 * Action optional error. Queue address for later processing.
994 * When the ring overflows we just ignore the AO error.
995 * RED-PEN add some logging mechanism when
996 * usable_address or mce_add_ring fails.
997 * RED-PEN don't ignore overflow for tolerant == 0
999 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1000 mce_ring_add(m.addr >> PAGE_SHIFT);
1004 if (severity > worst) {
1011 mce_clear_state(toclear);
1014 * Do most of the synchronization with other CPUs.
1015 * When there's any problem use only local no_way_out state.
1017 if (mce_end(order) < 0)
1018 no_way_out = worst >= MCE_PANIC_SEVERITY;
1021 * If we have decided that we just CAN'T continue, and the user
1022 * has not set tolerant to an insane level, give up and die.
1024 * This is mainly used in the case when the system doesn't
1025 * support MCE broadcasting or it has been disabled.
1027 if (no_way_out && tolerant < 3)
1028 mce_panic("Fatal machine check on current CPU", final, msg);
1031 * If the error seems to be unrecoverable, something should be
1032 * done. Try to kill as little as possible. If we can kill just
1033 * one task, do that. If the user has set the tolerance very
1034 * high, don't try to do anything at all.
1037 if (kill_it && tolerant < 3)
1038 force_sig(SIGBUS, current);
1040 /* notify userspace ASAP */
1041 set_thread_flag(TIF_MCE_NOTIFY);
1044 mce_report_event(regs);
1045 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1047 atomic_dec(&mce_entry);
1050 EXPORT_SYMBOL_GPL(do_machine_check);
1052 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1053 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1055 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1059 * Called after mce notification in process context. This code
1060 * is allowed to sleep. Call the high level VM handler to process
1061 * any corrupted pages.
1062 * Assume that the work queue code only calls this one at a time
1064 * Note we don't disable preemption, so this code might run on the wrong
1065 * CPU. In this case the event is picked up by the scheduled work queue.
1066 * This is merely a fast path to expedite processing in some common
1069 void mce_notify_process(void)
1073 while (mce_ring_get(&pfn))
1074 memory_failure(pfn, MCE_VECTOR);
1077 static void mce_process_work(struct work_struct *dummy)
1079 mce_notify_process();
1082 #ifdef CONFIG_X86_MCE_INTEL
1084 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1085 * @cpu: The CPU on which the event occurred.
1086 * @status: Event status information
1088 * This function should be called by the thermal interrupt after the
1089 * event has been processed and the decision was made to log the event
1092 * The status parameter will be saved to the 'status' field of 'struct mce'
1093 * and historically has been the register value of the
1094 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1096 void mce_log_therm_throt_event(__u64 status)
1101 m.bank = MCE_THERMAL_BANK;
1105 #endif /* CONFIG_X86_MCE_INTEL */
1108 * Periodic polling timer for "silent" machine check errors. If the
1109 * poller finds an MCE, poll 2x faster. When the poller finds no more
1110 * errors, poll 2x slower (up to check_interval seconds).
1112 static int check_interval = 5 * 60; /* 5 minutes */
1114 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1115 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1117 static void mce_start_timer(unsigned long data)
1119 struct timer_list *t = &per_cpu(mce_timer, data);
1122 WARN_ON(smp_processor_id() != data);
1124 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1125 machine_check_poll(MCP_TIMESTAMP,
1126 &__get_cpu_var(mce_poll_banks));
1130 * Alert userspace if needed. If we logged an MCE, reduce the
1131 * polling interval, otherwise increase the polling interval.
1133 n = &__get_cpu_var(mce_next_interval);
1134 if (mce_notify_irq())
1135 *n = max(*n/2, HZ/100);
1137 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1139 t->expires = jiffies + *n;
1140 add_timer_on(t, smp_processor_id());
1143 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1144 static void mce_timer_delete_all(void)
1148 for_each_online_cpu(cpu)
1149 del_timer_sync(&per_cpu(mce_timer, cpu));
1152 static void mce_do_trigger(struct work_struct *work)
1154 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1157 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1160 * Notify the user(s) about new machine check events.
1161 * Can be called from interrupt context, but not from machine check/NMI
1164 int mce_notify_irq(void)
1166 /* Not more than two messages every minute */
1167 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1169 clear_thread_flag(TIF_MCE_NOTIFY);
1171 if (test_and_clear_bit(0, &mce_need_notify)) {
1172 /* wake processes polling /dev/mcelog */
1173 wake_up_interruptible(&mce_chrdev_wait);
1176 * There is no risk of missing notifications because
1177 * work_pending is always cleared before the function is
1180 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1181 schedule_work(&mce_trigger_work);
1183 if (__ratelimit(&ratelimit))
1184 pr_info(HW_ERR "Machine check events logged\n");
1190 EXPORT_SYMBOL_GPL(mce_notify_irq);
1192 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1196 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1199 for (i = 0; i < banks; i++) {
1200 struct mce_bank *b = &mce_banks[i];
1209 * Initialize Machine Checks for a CPU.
1211 static int __cpuinit __mcheck_cpu_cap_init(void)
1216 rdmsrl(MSR_IA32_MCG_CAP, cap);
1218 b = cap & MCG_BANKCNT_MASK;
1220 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1222 if (b > MAX_NR_BANKS) {
1224 "MCE: Using only %u machine check banks out of %u\n",
1229 /* Don't support asymmetric configurations today */
1230 WARN_ON(banks != 0 && b != banks);
1233 int err = __mcheck_cpu_mce_banks_init();
1239 /* Use accurate RIP reporting if available. */
1240 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1241 rip_msr = MSR_IA32_MCG_EIP;
1243 if (cap & MCG_SER_P)
1249 static void __mcheck_cpu_init_generic(void)
1251 mce_banks_t all_banks;
1256 * Log the machine checks left over from the previous reset.
1258 bitmap_fill(all_banks, MAX_NR_BANKS);
1259 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1261 set_in_cr4(X86_CR4_MCE);
1263 rdmsrl(MSR_IA32_MCG_CAP, cap);
1264 if (cap & MCG_CTL_P)
1265 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1267 for (i = 0; i < banks; i++) {
1268 struct mce_bank *b = &mce_banks[i];
1272 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1273 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1277 /* Add per CPU specific workarounds here */
1278 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1280 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1281 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1285 /* This should be disabled by the BIOS, but isn't always */
1286 if (c->x86_vendor == X86_VENDOR_AMD) {
1287 if (c->x86 == 15 && banks > 4) {
1289 * disable GART TBL walk error reporting, which
1290 * trips off incorrectly with the IOMMU & 3ware
1293 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1295 if (c->x86 <= 17 && mce_bootlog < 0) {
1297 * Lots of broken BIOS around that don't clear them
1298 * by default and leave crap in there. Don't log:
1303 * Various K7s with broken bank 0 around. Always disable
1306 if (c->x86 == 6 && banks > 0)
1307 mce_banks[0].ctl = 0;
1310 if (c->x86_vendor == X86_VENDOR_INTEL) {
1312 * SDM documents that on family 6 bank 0 should not be written
1313 * because it aliases to another special BIOS controlled
1315 * But it's not aliased anymore on model 0x1a+
1316 * Don't ignore bank 0 completely because there could be a
1317 * valid event later, merely don't write CTL0.
1320 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1321 mce_banks[0].init = 0;
1324 * All newer Intel systems support MCE broadcasting. Enable
1325 * synchronization with a one second timeout.
1327 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1328 monarch_timeout < 0)
1329 monarch_timeout = USEC_PER_SEC;
1332 * There are also broken BIOSes on some Pentium M and
1335 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1338 if (monarch_timeout < 0)
1339 monarch_timeout = 0;
1340 if (mce_bootlog != 0)
1341 mce_panic_timeout = 30;
1346 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1351 switch (c->x86_vendor) {
1352 case X86_VENDOR_INTEL:
1353 intel_p5_mcheck_init(c);
1356 case X86_VENDOR_CENTAUR:
1357 winchip_mcheck_init(c);
1365 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1367 switch (c->x86_vendor) {
1368 case X86_VENDOR_INTEL:
1369 mce_intel_feature_init(c);
1371 case X86_VENDOR_AMD:
1372 mce_amd_feature_init(c);
1379 static void __mcheck_cpu_init_timer(void)
1381 struct timer_list *t = &__get_cpu_var(mce_timer);
1382 int *n = &__get_cpu_var(mce_next_interval);
1384 setup_timer(t, mce_start_timer, smp_processor_id());
1389 *n = check_interval * HZ;
1392 t->expires = round_jiffies(jiffies + *n);
1393 add_timer_on(t, smp_processor_id());
1396 /* Handle unconfigured int18 (should never happen) */
1397 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1399 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1400 smp_processor_id());
1403 /* Call the installed machine check handler for this CPU setup. */
1404 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1405 unexpected_machine_check;
1408 * Called for each booted CPU to set up machine checks.
1409 * Must be called with preempt off:
1411 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1416 if (__mcheck_cpu_ancient_init(c))
1419 if (!mce_available(c))
1422 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1427 machine_check_vector = do_machine_check;
1429 __mcheck_cpu_init_generic();
1430 __mcheck_cpu_init_vendor(c);
1431 __mcheck_cpu_init_timer();
1432 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1433 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1437 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1440 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1441 static int mce_chrdev_open_count; /* #times opened */
1442 static int mce_chrdev_open_exclu; /* already open exclusive? */
1444 static int mce_chrdev_open(struct inode *inode, struct file *file)
1446 spin_lock(&mce_chrdev_state_lock);
1448 if (mce_chrdev_open_exclu ||
1449 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1450 spin_unlock(&mce_chrdev_state_lock);
1455 if (file->f_flags & O_EXCL)
1456 mce_chrdev_open_exclu = 1;
1457 mce_chrdev_open_count++;
1459 spin_unlock(&mce_chrdev_state_lock);
1461 return nonseekable_open(inode, file);
1464 static int mce_chrdev_release(struct inode *inode, struct file *file)
1466 spin_lock(&mce_chrdev_state_lock);
1468 mce_chrdev_open_count--;
1469 mce_chrdev_open_exclu = 0;
1471 spin_unlock(&mce_chrdev_state_lock);
1476 static void collect_tscs(void *data)
1478 unsigned long *cpu_tsc = (unsigned long *)data;
1480 rdtscll(cpu_tsc[smp_processor_id()]);
1483 static int mce_apei_read_done;
1485 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1486 static int __mce_read_apei(char __user **ubuf, size_t usize)
1492 if (usize < sizeof(struct mce))
1495 rc = apei_read_mce(&m, &record_id);
1496 /* Error or no more MCE record */
1498 mce_apei_read_done = 1;
1502 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1505 * In fact, we should have cleared the record after that has
1506 * been flushed to the disk or sent to network in
1507 * /sbin/mcelog, but we have no interface to support that now,
1508 * so just clear it to avoid duplication.
1510 rc = apei_clear_mce(record_id);
1512 mce_apei_read_done = 1;
1515 *ubuf += sizeof(struct mce);
1520 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1521 size_t usize, loff_t *off)
1523 char __user *buf = ubuf;
1524 unsigned long *cpu_tsc;
1525 unsigned prev, next;
1528 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1532 mutex_lock(&mce_chrdev_read_mutex);
1534 if (!mce_apei_read_done) {
1535 err = __mce_read_apei(&buf, usize);
1536 if (err || buf != ubuf)
1540 next = rcu_dereference_check_mce(mcelog.next);
1542 /* Only supports full reads right now */
1544 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1550 for (i = prev; i < next; i++) {
1551 unsigned long start = jiffies;
1552 struct mce *m = &mcelog.entry[i];
1554 while (!m->finished) {
1555 if (time_after_eq(jiffies, start + 2)) {
1556 memset(m, 0, sizeof(*m));
1562 err |= copy_to_user(buf, m, sizeof(*m));
1568 memset(mcelog.entry + prev, 0,
1569 (next - prev) * sizeof(struct mce));
1571 next = cmpxchg(&mcelog.next, prev, 0);
1572 } while (next != prev);
1574 synchronize_sched();
1577 * Collect entries that were still getting written before the
1580 on_each_cpu(collect_tscs, cpu_tsc, 1);
1582 for (i = next; i < MCE_LOG_LEN; i++) {
1583 struct mce *m = &mcelog.entry[i];
1585 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1586 err |= copy_to_user(buf, m, sizeof(*m));
1589 memset(m, 0, sizeof(*m));
1597 mutex_unlock(&mce_chrdev_read_mutex);
1600 return err ? err : buf - ubuf;
1603 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1605 poll_wait(file, &mce_chrdev_wait, wait);
1606 if (rcu_access_index(mcelog.next))
1607 return POLLIN | POLLRDNORM;
1608 if (!mce_apei_read_done && apei_check_mce())
1609 return POLLIN | POLLRDNORM;
1613 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1616 int __user *p = (int __user *)arg;
1618 if (!capable(CAP_SYS_ADMIN))
1622 case MCE_GET_RECORD_LEN:
1623 return put_user(sizeof(struct mce), p);
1624 case MCE_GET_LOG_LEN:
1625 return put_user(MCE_LOG_LEN, p);
1626 case MCE_GETCLEAR_FLAGS: {
1630 flags = mcelog.flags;
1631 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1633 return put_user(flags, p);
1640 /* Modified in mce-inject.c, so not static or const */
1641 struct file_operations mce_chrdev_ops = {
1642 .open = mce_chrdev_open,
1643 .release = mce_chrdev_release,
1644 .read = mce_chrdev_read,
1645 .poll = mce_chrdev_poll,
1646 .unlocked_ioctl = mce_chrdev_ioctl,
1647 .llseek = no_llseek,
1649 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1651 static struct miscdevice mce_chrdev_device = {
1658 * mce=off Disables machine check
1659 * mce=no_cmci Disables CMCI
1660 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1661 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1662 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1663 * monarchtimeout is how long to wait for other CPUs on machine
1664 * check, or 0 to not wait
1665 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1666 * mce=nobootlog Don't log MCEs from before booting.
1668 static int __init mcheck_enable(char *str)
1676 if (!strcmp(str, "off"))
1678 else if (!strcmp(str, "no_cmci"))
1679 mce_cmci_disabled = 1;
1680 else if (!strcmp(str, "dont_log_ce"))
1681 mce_dont_log_ce = 1;
1682 else if (!strcmp(str, "ignore_ce"))
1684 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1685 mce_bootlog = (str[0] == 'b');
1686 else if (isdigit(str[0])) {
1687 get_option(&str, &tolerant);
1690 get_option(&str, &monarch_timeout);
1693 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1699 __setup("mce", mcheck_enable);
1701 int __init mcheck_init(void)
1703 mcheck_intel_therm_init();
1709 * mce_syscore: PM support
1713 * Disable machine checks on suspend and shutdown. We can't really handle
1716 static int mce_disable_error_reporting(void)
1720 for (i = 0; i < banks; i++) {
1721 struct mce_bank *b = &mce_banks[i];
1724 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1729 static int mce_syscore_suspend(void)
1731 return mce_disable_error_reporting();
1734 static void mce_syscore_shutdown(void)
1736 mce_disable_error_reporting();
1740 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1741 * Only one CPU is active at this time, the others get re-added later using
1744 static void mce_syscore_resume(void)
1746 __mcheck_cpu_init_generic();
1747 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1750 static struct syscore_ops mce_syscore_ops = {
1751 .suspend = mce_syscore_suspend,
1752 .shutdown = mce_syscore_shutdown,
1753 .resume = mce_syscore_resume,
1757 * mce_sysdev: Sysfs support
1760 static void mce_cpu_restart(void *data)
1762 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1764 __mcheck_cpu_init_generic();
1765 __mcheck_cpu_init_timer();
1768 /* Reinit MCEs after user configuration changes */
1769 static void mce_restart(void)
1771 mce_timer_delete_all();
1772 on_each_cpu(mce_cpu_restart, NULL, 1);
1775 /* Toggle features for corrected errors */
1776 static void mce_disable_cmci(void *data)
1778 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1783 static void mce_enable_ce(void *all)
1785 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1790 __mcheck_cpu_init_timer();
1793 static struct sysdev_class mce_sysdev_class = {
1794 .name = "machinecheck",
1797 DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1800 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1802 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1804 return container_of(attr, struct mce_bank, attr);
1807 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1810 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1813 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1814 const char *buf, size_t size)
1818 if (strict_strtoull(buf, 0, &new) < 0)
1821 attr_to_bank(attr)->ctl = new;
1828 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1830 strcpy(buf, mce_helper);
1832 return strlen(mce_helper) + 1;
1835 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1836 const char *buf, size_t siz)
1840 strncpy(mce_helper, buf, sizeof(mce_helper));
1841 mce_helper[sizeof(mce_helper)-1] = 0;
1842 p = strchr(mce_helper, '\n');
1847 return strlen(mce_helper) + !!p;
1850 static ssize_t set_ignore_ce(struct sys_device *s,
1851 struct sysdev_attribute *attr,
1852 const char *buf, size_t size)
1856 if (strict_strtoull(buf, 0, &new) < 0)
1859 if (mce_ignore_ce ^ !!new) {
1861 /* disable ce features */
1862 mce_timer_delete_all();
1863 on_each_cpu(mce_disable_cmci, NULL, 1);
1866 /* enable ce features */
1868 on_each_cpu(mce_enable_ce, (void *)1, 1);
1874 static ssize_t set_cmci_disabled(struct sys_device *s,
1875 struct sysdev_attribute *attr,
1876 const char *buf, size_t size)
1880 if (strict_strtoull(buf, 0, &new) < 0)
1883 if (mce_cmci_disabled ^ !!new) {
1886 on_each_cpu(mce_disable_cmci, NULL, 1);
1887 mce_cmci_disabled = 1;
1890 mce_cmci_disabled = 0;
1891 on_each_cpu(mce_enable_ce, NULL, 1);
1897 static ssize_t store_int_with_restart(struct sys_device *s,
1898 struct sysdev_attribute *attr,
1899 const char *buf, size_t size)
1901 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1906 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1907 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1908 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1909 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1911 static struct sysdev_ext_attribute attr_check_interval = {
1912 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1913 store_int_with_restart),
1917 static struct sysdev_ext_attribute attr_ignore_ce = {
1918 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1922 static struct sysdev_ext_attribute attr_cmci_disabled = {
1923 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1927 static struct sysdev_attribute *mce_sysdev_attrs[] = {
1928 &attr_tolerant.attr,
1929 &attr_check_interval.attr,
1931 &attr_monarch_timeout.attr,
1932 &attr_dont_log_ce.attr,
1933 &attr_ignore_ce.attr,
1934 &attr_cmci_disabled.attr,
1938 static cpumask_var_t mce_sysdev_initialized;
1940 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1941 static __cpuinit int mce_sysdev_create(unsigned int cpu)
1943 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1947 if (!mce_available(&boot_cpu_data))
1950 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1952 sysdev->cls = &mce_sysdev_class;
1954 err = sysdev_register(sysdev);
1958 for (i = 0; mce_sysdev_attrs[i]; i++) {
1959 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
1963 for (j = 0; j < banks; j++) {
1964 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
1968 cpumask_set_cpu(cpu, mce_sysdev_initialized);
1973 sysdev_remove_file(sysdev, &mce_banks[j].attr);
1976 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
1978 sysdev_unregister(sysdev);
1983 static __cpuinit void mce_sysdev_remove(unsigned int cpu)
1985 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1988 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
1991 for (i = 0; mce_sysdev_attrs[i]; i++)
1992 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
1994 for (i = 0; i < banks; i++)
1995 sysdev_remove_file(sysdev, &mce_banks[i].attr);
1997 sysdev_unregister(sysdev);
1998 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
2001 /* Make sure there are no machine checks on offlined CPUs. */
2002 static void __cpuinit mce_disable_cpu(void *h)
2004 unsigned long action = *(unsigned long *)h;
2007 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2010 if (!(action & CPU_TASKS_FROZEN))
2012 for (i = 0; i < banks; i++) {
2013 struct mce_bank *b = &mce_banks[i];
2016 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2020 static void __cpuinit mce_reenable_cpu(void *h)
2022 unsigned long action = *(unsigned long *)h;
2025 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2028 if (!(action & CPU_TASKS_FROZEN))
2030 for (i = 0; i < banks; i++) {
2031 struct mce_bank *b = &mce_banks[i];
2034 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2038 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2039 static int __cpuinit
2040 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2042 unsigned int cpu = (unsigned long)hcpu;
2043 struct timer_list *t = &per_cpu(mce_timer, cpu);
2047 case CPU_ONLINE_FROZEN:
2048 mce_sysdev_create(cpu);
2049 if (threshold_cpu_callback)
2050 threshold_cpu_callback(action, cpu);
2053 case CPU_DEAD_FROZEN:
2054 if (threshold_cpu_callback)
2055 threshold_cpu_callback(action, cpu);
2056 mce_sysdev_remove(cpu);
2058 case CPU_DOWN_PREPARE:
2059 case CPU_DOWN_PREPARE_FROZEN:
2061 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2063 case CPU_DOWN_FAILED:
2064 case CPU_DOWN_FAILED_FROZEN:
2065 if (!mce_ignore_ce && check_interval) {
2066 t->expires = round_jiffies(jiffies +
2067 __get_cpu_var(mce_next_interval));
2068 add_timer_on(t, cpu);
2070 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2073 /* intentionally ignoring frozen here */
2074 cmci_rediscover(cpu);
2080 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2081 .notifier_call = mce_cpu_callback,
2084 static __init void mce_init_banks(void)
2088 for (i = 0; i < banks; i++) {
2089 struct mce_bank *b = &mce_banks[i];
2090 struct sysdev_attribute *a = &b->attr;
2092 sysfs_attr_init(&a->attr);
2093 a->attr.name = b->attrname;
2094 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2096 a->attr.mode = 0644;
2097 a->show = show_bank;
2098 a->store = set_bank;
2102 static __init int mcheck_init_device(void)
2107 if (!mce_available(&boot_cpu_data))
2110 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2114 err = sysdev_class_register(&mce_sysdev_class);
2118 for_each_online_cpu(i) {
2119 err = mce_sysdev_create(i);
2124 register_syscore_ops(&mce_syscore_ops);
2125 register_hotcpu_notifier(&mce_cpu_notifier);
2127 /* register character device /dev/mcelog */
2128 misc_register(&mce_chrdev_device);
2132 device_initcall(mcheck_init_device);
2135 * Old style boot options parsing. Only for compatibility.
2137 static int __init mcheck_disable(char *str)
2142 __setup("nomce", mcheck_disable);
2144 #ifdef CONFIG_DEBUG_FS
2145 struct dentry *mce_get_debugfs_dir(void)
2147 static struct dentry *dmce;
2150 dmce = debugfs_create_dir("mce", NULL);
2155 static void mce_reset(void)
2158 atomic_set(&mce_fake_paniced, 0);
2159 atomic_set(&mce_executing, 0);
2160 atomic_set(&mce_callin, 0);
2161 atomic_set(&global_nwo, 0);
2164 static int fake_panic_get(void *data, u64 *val)
2170 static int fake_panic_set(void *data, u64 val)
2177 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2178 fake_panic_set, "%llu\n");
2180 static int __init mcheck_debugfs_init(void)
2182 struct dentry *dmce, *ffake_panic;
2184 dmce = mce_get_debugfs_dir();
2187 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2194 late_initcall(mcheck_debugfs_init);