2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 int mce_disabled __read_mostly;
51 #define MISC_MCELOG_MINOR 227
53 #define SPINUNIT 100 /* 100ns */
57 DEFINE_PER_CPU(unsigned, mce_exception_count);
61 * 0: always panic on uncorrected errors, log corrected errors
62 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
63 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
64 * 3: never panic or SIGBUS, log all errors (for testing only)
66 static int tolerant __read_mostly = 1;
67 static int banks __read_mostly;
68 static int rip_msr __read_mostly;
69 static int mce_bootlog __read_mostly = -1;
70 static int monarch_timeout __read_mostly = -1;
71 static int mce_panic_timeout __read_mostly;
72 static int mce_dont_log_ce __read_mostly;
73 int mce_cmci_disabled __read_mostly;
74 int mce_ignore_ce __read_mostly;
75 int mce_ser __read_mostly;
77 struct mce_bank *mce_banks __read_mostly;
79 /* User mode helper program triggered by machine check event */
80 static unsigned long mce_need_notify;
81 static char mce_helper[128];
82 static char *mce_helper_argv[2] = { mce_helper, NULL };
84 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static int cpu_missing;
87 void (*mce_cpu_specific_poll)(struct mce *);
88 EXPORT_SYMBOL_GPL(mce_cpu_specific_poll);
90 static void default_decode_mce(struct mce *m)
92 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
93 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
97 * CPU/chipset specific EDAC code can register a callback here to print
98 * MCE errors in a human-readable form:
100 void (*x86_mce_decode_callback)(struct mce *m) = default_decode_mce;
101 EXPORT_SYMBOL(x86_mce_decode_callback);
103 /* MCA banks polled by the period polling timer for corrected events */
104 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
105 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
108 static DEFINE_PER_CPU(struct work_struct, mce_work);
110 /* Do initial initialization of a struct mce */
111 void mce_setup(struct mce *m)
113 memset(m, 0, sizeof(struct mce));
114 m->cpu = m->extcpu = smp_processor_id();
116 /* We hope get_seconds stays lockless */
117 m->time = get_seconds();
118 m->cpuvendor = boot_cpu_data.x86_vendor;
119 m->cpuid = cpuid_eax(1);
121 m->socketid = cpu_data(m->extcpu).phys_proc_id;
123 m->apicid = cpu_data(m->extcpu).initial_apicid;
124 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
127 DEFINE_PER_CPU(struct mce, injectm);
128 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
131 * Lockless MCE logging infrastructure.
132 * This avoids deadlocks on printk locks without having to break locks. Also
133 * separate MCEs from kernel messages to avoid bogus bug reports.
136 static struct mce_log mcelog = {
137 .signature = MCE_LOG_SIGNATURE,
139 .recordlen = sizeof(struct mce),
142 void mce_log(struct mce *mce)
144 unsigned next, entry;
149 entry = rcu_dereference(mcelog.next);
152 * When the buffer fills up discard new entries.
153 * Assume that the earlier errors are the more
156 if (entry >= MCE_LOG_LEN) {
157 set_bit(MCE_OVERFLOW,
158 (unsigned long *)&mcelog.flags);
161 /* Old left over entry. Skip: */
162 if (mcelog.entry[entry].finished) {
170 if (cmpxchg(&mcelog.next, entry, next) == entry)
173 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
175 mcelog.entry[entry].finished = 1;
179 set_bit(0, &mce_need_notify);
182 static void print_mce(struct mce *m)
184 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
185 m->extcpu, m->mcgstatus, m->bank, m->status);
188 pr_emerg("RIP%s %02x:<%016Lx> ",
189 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
192 if (m->cs == __KERNEL_CS)
193 print_symbol("{%s}", m->ip);
197 pr_emerg("TSC %llx ", m->tsc);
199 pr_cont("ADDR %llx ", m->addr);
201 pr_cont("MISC %llx ", m->misc);
204 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
205 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
208 * Print out human-readable details about the MCE error,
209 * (if the CPU has an implementation for that):
211 x86_mce_decode_callback(m);
214 static void print_mce_head(void)
216 pr_emerg("\nHARDWARE ERROR\n");
219 static void print_mce_tail(void)
221 pr_emerg("This is not a software problem!\n");
224 #define PANIC_TIMEOUT 5 /* 5 seconds */
226 static atomic_t mce_paniced;
228 static int fake_panic;
229 static atomic_t mce_fake_paniced;
231 /* Panic in progress. Enable interrupts and wait for final IPI */
232 static void wait_for_panic(void)
234 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
238 while (timeout-- > 0)
240 if (panic_timeout == 0)
241 panic_timeout = mce_panic_timeout;
242 panic("Panicing machine check CPU died");
245 static void mce_panic(char *msg, struct mce *final, char *exp)
251 * Make sure only one CPU runs in machine check panic
253 if (atomic_inc_return(&mce_paniced) > 1)
260 /* Don't log too much for fake panic */
261 if (atomic_inc_return(&mce_fake_paniced) > 1)
265 /* First print corrected ones that are still unlogged */
266 for (i = 0; i < MCE_LOG_LEN; i++) {
267 struct mce *m = &mcelog.entry[i];
268 if (!(m->status & MCI_STATUS_VAL))
270 if (!(m->status & MCI_STATUS_UC))
273 /* Now print uncorrected but with the final one last */
274 for (i = 0; i < MCE_LOG_LEN; i++) {
275 struct mce *m = &mcelog.entry[i];
276 if (!(m->status & MCI_STATUS_VAL))
278 if (!(m->status & MCI_STATUS_UC))
280 if (!final || memcmp(m, final, sizeof(struct mce)))
286 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
289 printk(KERN_EMERG "Machine check: %s\n", exp);
291 if (panic_timeout == 0)
292 panic_timeout = mce_panic_timeout;
295 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
298 /* Support code for software error injection */
300 static int msr_to_offset(u32 msr)
302 unsigned bank = __get_cpu_var(injectm.bank);
305 return offsetof(struct mce, ip);
306 if (msr == MSR_IA32_MCx_STATUS(bank))
307 return offsetof(struct mce, status);
308 if (msr == MSR_IA32_MCx_ADDR(bank))
309 return offsetof(struct mce, addr);
310 if (msr == MSR_IA32_MCx_MISC(bank))
311 return offsetof(struct mce, misc);
312 if (msr == MSR_IA32_MCG_STATUS)
313 return offsetof(struct mce, mcgstatus);
317 /* MSR access wrappers used for error injection */
318 static u64 mce_rdmsrl(u32 msr)
322 if (__get_cpu_var(injectm).finished) {
323 int offset = msr_to_offset(msr);
327 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
330 if (rdmsrl_safe(msr, &v)) {
331 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
333 * Return zero in case the access faulted. This should
334 * not happen normally but can happen if the CPU does
335 * something weird, or if the code is buggy.
343 static void mce_wrmsrl(u32 msr, u64 v)
345 if (__get_cpu_var(injectm).finished) {
346 int offset = msr_to_offset(msr);
349 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
355 static int under_injection(void)
357 return __get_cpu_var(injectm).finished;
361 * Simple lockless ring to communicate PFNs from the exception handler with the
362 * process context work function. This is vastly simplified because there's
363 * only a single reader and a single writer.
365 #define MCE_RING_SIZE 16 /* we use one entry less */
368 unsigned short start;
370 unsigned long ring[MCE_RING_SIZE];
372 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
374 /* Runs with CPU affinity in workqueue */
375 static int mce_ring_empty(void)
377 struct mce_ring *r = &__get_cpu_var(mce_ring);
379 return r->start == r->end;
382 static int mce_ring_get(unsigned long *pfn)
389 r = &__get_cpu_var(mce_ring);
390 if (r->start == r->end)
392 *pfn = r->ring[r->start];
393 r->start = (r->start + 1) % MCE_RING_SIZE;
400 /* Always runs in MCE context with preempt off */
401 static int mce_ring_add(unsigned long pfn)
403 struct mce_ring *r = &__get_cpu_var(mce_ring);
406 next = (r->end + 1) % MCE_RING_SIZE;
407 if (next == r->start)
409 r->ring[r->end] = pfn;
415 int mce_available(struct cpuinfo_x86 *c)
419 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
422 static void mce_schedule_work(void)
424 if (!mce_ring_empty()) {
425 struct work_struct *work = &__get_cpu_var(mce_work);
426 if (!work_pending(work))
432 * Get the address of the instruction at the time of the machine check
435 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
438 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
446 m->ip = mce_rdmsrl(rip_msr);
449 #ifdef CONFIG_X86_LOCAL_APIC
451 * Called after interrupts have been reenabled again
452 * when a MCE happened during an interrupts off region
455 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
468 static void mce_report_event(struct pt_regs *regs)
470 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
473 * Triggering the work queue here is just an insurance
474 * policy in case the syscall exit notify handler
475 * doesn't run soon enough or ends up running on the
476 * wrong CPU (can happen when audit sleeps)
482 #if defined(CONFIG_X86_LOCAL_APIC) && !defined(CONFIG_XEN)
484 * Without APIC do not notify. The event will be picked
491 * When interrupts are disabled we cannot use
492 * kernel services safely. Trigger an self interrupt
493 * through the APIC to instead do the notification
494 * after interrupts are reenabled again.
496 apic->send_IPI_self(MCE_SELF_VECTOR);
499 * Wait for idle afterwards again so that we don't leave the
500 * APIC in a non idle state because the normal APIC writes
503 apic_wait_icr_idle();
507 DEFINE_PER_CPU(unsigned, mce_poll_count);
510 * Poll for corrected events or events that happened before reset.
511 * Those are just logged through /dev/mcelog.
513 * This is executed in standard interrupt context.
515 * Note: spec recommends to panic for fatal unsignalled
516 * errors here. However this would be quite problematic --
517 * we would need to reimplement the Monarch handling and
518 * it would mess up the exclusion between exception handler
519 * and poll hander -- * so we skip this for now.
520 * These cases should not happen anyways, or only when the CPU
521 * is already totally * confused. In this case it's likely it will
522 * not fully execute the machine check handler either.
524 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
529 __get_cpu_var(mce_poll_count)++;
533 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
534 for (i = 0; i < banks; i++) {
535 if (!mce_banks[i].ctl || !test_bit(i, *b))
544 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
545 if (!(m.status & MCI_STATUS_VAL))
549 * Uncorrected or signalled events are handled by the exception
550 * handler when it is enabled, so don't process those here.
552 * TBD do the same check for MCI_STATUS_EN here?
554 if (!(flags & MCP_UC) &&
555 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
558 if (m.status & MCI_STATUS_MISCV)
559 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
560 if (m.status & MCI_STATUS_ADDRV)
561 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
563 if (!(flags & MCP_TIMESTAMP))
566 if (mce_cpu_specific_poll && !under_injection() && !mce_dont_log_ce)
567 mce_cpu_specific_poll(&m);
570 * Don't get the IP here because it's unlikely to
571 * have anything to do with the actual error location.
573 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
575 add_taint(TAINT_MACHINE_CHECK);
579 * Clear state for this bank.
581 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
585 * Don't clear MCG_STATUS here because it's only defined for
591 EXPORT_SYMBOL_GPL(machine_check_poll);
594 * Do a quick check if any of the events requires a panic.
595 * This decides if we keep the events around or clear them.
597 static int mce_no_way_out(struct mce *m, char **msg)
601 for (i = 0; i < banks; i++) {
602 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
603 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
610 * Variable to establish order between CPUs while scanning.
611 * Each CPU spins initially until executing is equal its number.
613 static atomic_t mce_executing;
616 * Defines order of CPUs on entry. First CPU becomes Monarch.
618 static atomic_t mce_callin;
621 * Check if a timeout waiting for other CPUs happened.
623 static int mce_timed_out(u64 *t)
626 * The others already did panic for some reason.
627 * Bail out like in a timeout.
628 * rmb() to tell the compiler that system_state
629 * might have been modified by someone else.
632 if (atomic_read(&mce_paniced))
634 if (!monarch_timeout)
636 if ((s64)*t < SPINUNIT) {
637 /* CHECKME: Make panic default for 1 too? */
639 mce_panic("Timeout synchronizing machine check over CPUs",
646 touch_nmi_watchdog();
651 * The Monarch's reign. The Monarch is the CPU who entered
652 * the machine check handler first. It waits for the others to
653 * raise the exception too and then grades them. When any
654 * error is fatal panic. Only then let the others continue.
656 * The other CPUs entering the MCE handler will be controlled by the
657 * Monarch. They are called Subjects.
659 * This way we prevent any potential data corruption in a unrecoverable case
660 * and also makes sure always all CPU's errors are examined.
662 * Also this detects the case of a machine check event coming from outer
663 * space (not detected by any CPUs) In this case some external agent wants
664 * us to shut down, so panic too.
666 * The other CPUs might still decide to panic if the handler happens
667 * in a unrecoverable place, but in this case the system is in a semi-stable
668 * state and won't corrupt anything by itself. It's ok to let the others
669 * continue for a bit first.
671 * All the spin loops have timeouts; when a timeout happens a CPU
672 * typically elects itself to be Monarch.
674 static void mce_reign(void)
677 struct mce *m = NULL;
678 int global_worst = 0;
683 * This CPU is the Monarch and the other CPUs have run
684 * through their handlers.
685 * Grade the severity of the errors of all the CPUs.
687 for_each_possible_cpu(cpu) {
688 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
690 if (severity > global_worst) {
692 global_worst = severity;
693 m = &per_cpu(mces_seen, cpu);
698 * Cannot recover? Panic here then.
699 * This dumps all the mces in the log buffer and stops the
702 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
703 mce_panic("Fatal Machine check", m, msg);
706 * For UC somewhere we let the CPU who detects it handle it.
707 * Also must let continue the others, otherwise the handling
708 * CPU could deadlock on a lock.
712 * No machine check event found. Must be some external
713 * source or one CPU is hung. Panic.
715 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
716 mce_panic("Machine check from unknown source", NULL, NULL);
719 * Now clear all the mces_seen so that they don't reappear on
722 for_each_possible_cpu(cpu)
723 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
726 static atomic_t global_nwo;
729 * Start of Monarch synchronization. This waits until all CPUs have
730 * entered the exception handler and then determines if any of them
731 * saw a fatal event that requires panic. Then it executes them
732 * in the entry order.
733 * TBD double check parallel CPU hotunplug
735 static int mce_start(int *no_way_out)
738 int cpus = num_online_cpus();
739 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
744 atomic_add(*no_way_out, &global_nwo);
746 * global_nwo should be updated before mce_callin
749 order = atomic_inc_return(&mce_callin);
754 while (atomic_read(&mce_callin) != cpus) {
755 if (mce_timed_out(&timeout)) {
756 atomic_set(&global_nwo, 0);
763 * mce_callin should be read before global_nwo
769 * Monarch: Starts executing now, the others wait.
771 atomic_set(&mce_executing, 1);
774 * Subject: Now start the scanning loop one by one in
775 * the original callin order.
776 * This way when there are any shared banks it will be
777 * only seen by one CPU before cleared, avoiding duplicates.
779 while (atomic_read(&mce_executing) < order) {
780 if (mce_timed_out(&timeout)) {
781 atomic_set(&global_nwo, 0);
789 * Cache the global no_way_out state.
791 *no_way_out = atomic_read(&global_nwo);
797 * Synchronize between CPUs after main scanning loop.
798 * This invokes the bulk of the Monarch processing.
800 static int mce_end(int order)
803 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
811 * Allow others to run.
813 atomic_inc(&mce_executing);
816 /* CHECKME: Can this race with a parallel hotplug? */
817 int cpus = num_online_cpus();
820 * Monarch: Wait for everyone to go through their scanning
823 while (atomic_read(&mce_executing) <= cpus) {
824 if (mce_timed_out(&timeout))
834 * Subject: Wait for Monarch to finish.
836 while (atomic_read(&mce_executing) != 0) {
837 if (mce_timed_out(&timeout))
843 * Don't reset anything. That's done by the Monarch.
849 * Reset all global state.
852 atomic_set(&global_nwo, 0);
853 atomic_set(&mce_callin, 0);
857 * Let others run again.
859 atomic_set(&mce_executing, 0);
864 * Check if the address reported by the CPU is in a format we can parse.
865 * It would be possible to add code for most other cases, but all would
866 * be somewhat complicated (e.g. segment offset would require an instruction
867 * parser). So only support physical addresses upto page granuality for now.
869 static int mce_usable_address(struct mce *m)
871 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
873 if ((m->misc & 0x3f) > PAGE_SHIFT)
875 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
880 static void mce_clear_state(unsigned long *toclear)
884 for (i = 0; i < banks; i++) {
885 if (test_bit(i, toclear))
886 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
891 * The actual machine check handler. This only handles real
892 * exceptions when something got corrupted coming in through int 18.
894 * This is executed in NMI context not subject to normal locking rules. This
895 * implies that most kernel services cannot be safely used. Don't even
896 * think about putting a printk in there!
898 * On Intel systems this is entered on all CPUs in parallel through
899 * MCE broadcast. However some CPUs might be broken beyond repair,
900 * so be always careful when synchronizing with others.
902 void do_machine_check(struct pt_regs *regs, long error_code)
904 struct mce m, *final;
909 * Establish sequential order between the CPUs entering the machine
914 * If no_way_out gets set, there is no safe way to recover from this
915 * MCE. If tolerant is cranked up, we'll try anyway.
919 * If kill_it gets set, there might be a way to recover from this
923 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
924 char *msg = "Unknown";
926 atomic_inc(&mce_entry);
928 __get_cpu_var(mce_exception_count)++;
930 if (notify_die(DIE_NMI, "machine check", regs, error_code,
931 18, SIGKILL) == NOTIFY_STOP)
938 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
939 final = &__get_cpu_var(mces_seen);
942 no_way_out = mce_no_way_out(&m, &msg);
947 * When no restart IP must always kill or panic.
949 if (!(m.mcgstatus & MCG_STATUS_RIPV))
953 * Go through all the banks in exclusion of the other CPUs.
954 * This way we don't report duplicated events on shared banks
955 * because the first one to see it will clear it.
957 order = mce_start(&no_way_out);
958 for (i = 0; i < banks; i++) {
959 __clear_bit(i, toclear);
960 if (!mce_banks[i].ctl)
967 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
968 if ((m.status & MCI_STATUS_VAL) == 0)
972 * Non uncorrected or non signaled errors are handled by
973 * machine_check_poll. Leave them alone, unless this panics.
975 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
980 * Set taint even when machine check was not enabled.
982 add_taint(TAINT_MACHINE_CHECK);
984 severity = mce_severity(&m, tolerant, NULL);
987 * When machine check was for corrected handler don't touch,
988 * unless we're panicing.
990 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
992 __set_bit(i, toclear);
993 if (severity == MCE_NO_SEVERITY) {
995 * Machine check event was not enabled. Clear, but
1002 * Kill on action required.
1004 if (severity == MCE_AR_SEVERITY)
1007 if (m.status & MCI_STATUS_MISCV)
1008 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1009 if (m.status & MCI_STATUS_ADDRV)
1010 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1013 * Action optional error. Queue address for later processing.
1014 * When the ring overflows we just ignore the AO error.
1015 * RED-PEN add some logging mechanism when
1016 * usable_address or mce_add_ring fails.
1017 * RED-PEN don't ignore overflow for tolerant == 0
1019 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1020 mce_ring_add(m.addr >> PAGE_SHIFT);
1022 mce_get_rip(&m, regs);
1025 if (severity > worst) {
1032 mce_clear_state(toclear);
1035 * Do most of the synchronization with other CPUs.
1036 * When there's any problem use only local no_way_out state.
1038 if (mce_end(order) < 0)
1039 no_way_out = worst >= MCE_PANIC_SEVERITY;
1042 * If we have decided that we just CAN'T continue, and the user
1043 * has not set tolerant to an insane level, give up and die.
1045 * This is mainly used in the case when the system doesn't
1046 * support MCE broadcasting or it has been disabled.
1048 if (no_way_out && tolerant < 3)
1049 mce_panic("Fatal machine check on current CPU", final, msg);
1052 * If the error seems to be unrecoverable, something should be
1053 * done. Try to kill as little as possible. If we can kill just
1054 * one task, do that. If the user has set the tolerance very
1055 * high, don't try to do anything at all.
1058 if (kill_it && tolerant < 3)
1059 force_sig(SIGBUS, current);
1061 /* notify userspace ASAP */
1062 set_thread_flag(TIF_MCE_NOTIFY);
1065 mce_report_event(regs);
1066 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1068 atomic_dec(&mce_entry);
1071 EXPORT_SYMBOL_GPL(do_machine_check);
1073 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1074 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1076 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1080 * Called after mce notification in process context. This code
1081 * is allowed to sleep. Call the high level VM handler to process
1082 * any corrupted pages.
1083 * Assume that the work queue code only calls this one at a time
1085 * Note we don't disable preemption, so this code might run on the wrong
1086 * CPU. In this case the event is picked up by the scheduled work queue.
1087 * This is merely a fast path to expedite processing in some common
1090 void mce_notify_process(void)
1094 while (mce_ring_get(&pfn))
1095 memory_failure(pfn, MCE_VECTOR);
1098 static void mce_process_work(struct work_struct *dummy)
1100 mce_notify_process();
1103 #ifdef CONFIG_X86_MCE_INTEL
1105 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1106 * @cpu: The CPU on which the event occurred.
1107 * @status: Event status information
1109 * This function should be called by the thermal interrupt after the
1110 * event has been processed and the decision was made to log the event
1113 * The status parameter will be saved to the 'status' field of 'struct mce'
1114 * and historically has been the register value of the
1115 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1117 void mce_log_therm_throt_event(__u64 status)
1122 m.bank = MCE_THERMAL_BANK;
1126 #endif /* CONFIG_X86_MCE_INTEL */
1129 * Periodic polling timer for "silent" machine check errors. If the
1130 * poller finds an MCE, poll 2x faster. When the poller finds no more
1131 * errors, poll 2x slower (up to check_interval seconds).
1133 * We will disable polling in DOM0 since all CMCI/Polling
1134 * mechanism will be done in XEN for Intel CPUs
1136 #if defined (CONFIG_X86_XEN_MCE)
1137 static int check_interval = 0; /* disable polling */
1139 static int check_interval = 5 * 60; /* 5 minutes */
1142 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1143 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1145 static void mcheck_timer(unsigned long data)
1147 struct timer_list *t = &per_cpu(mce_timer, data);
1150 WARN_ON(smp_processor_id() != data);
1152 if (mce_available(¤t_cpu_data)) {
1153 machine_check_poll(MCP_TIMESTAMP,
1154 &__get_cpu_var(mce_poll_banks));
1158 * Alert userspace if needed. If we logged an MCE, reduce the
1159 * polling interval, otherwise increase the polling interval.
1161 n = &__get_cpu_var(mce_next_interval);
1162 if (mce_notify_irq())
1163 *n = max(*n/2, HZ/100);
1165 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1167 t->expires = jiffies + *n;
1168 add_timer_on(t, smp_processor_id());
1171 static void mce_do_trigger(struct work_struct *work)
1173 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1176 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1179 * Notify the user(s) about new machine check events.
1180 * Can be called from interrupt context, but not from machine check/NMI
1183 int mce_notify_irq(void)
1185 /* Not more than two messages every minute */
1186 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1188 clear_thread_flag(TIF_MCE_NOTIFY);
1190 if (test_and_clear_bit(0, &mce_need_notify)) {
1191 wake_up_interruptible(&mce_wait);
1194 * There is no risk of missing notifications because
1195 * work_pending is always cleared before the function is
1198 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1199 schedule_work(&mce_trigger_work);
1201 if (__ratelimit(&ratelimit))
1202 printk(KERN_INFO "Machine check events logged\n");
1208 EXPORT_SYMBOL_GPL(mce_notify_irq);
1210 static int mce_banks_init(void)
1214 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1217 for (i = 0; i < banks; i++) {
1218 struct mce_bank *b = &mce_banks[i];
1227 * Initialize Machine Checks for a CPU.
1229 static int __cpuinit mce_cap_init(void)
1234 rdmsrl(MSR_IA32_MCG_CAP, cap);
1236 b = cap & MCG_BANKCNT_MASK;
1238 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1240 if (b > MAX_NR_BANKS) {
1242 "MCE: Using only %u machine check banks out of %u\n",
1247 /* Don't support asymmetric configurations today */
1248 WARN_ON(banks != 0 && b != banks);
1251 int err = mce_banks_init();
1257 /* Use accurate RIP reporting if available. */
1258 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1259 rip_msr = MSR_IA32_MCG_EIP;
1261 if (cap & MCG_SER_P)
1267 static void mce_init(void)
1269 mce_banks_t all_banks;
1274 * Log the machine checks left over from the previous reset.
1276 bitmap_fill(all_banks, MAX_NR_BANKS);
1277 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1279 set_in_cr4(X86_CR4_MCE);
1281 rdmsrl(MSR_IA32_MCG_CAP, cap);
1282 if (cap & MCG_CTL_P)
1283 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1285 for (i = 0; i < banks; i++) {
1286 struct mce_bank *b = &mce_banks[i];
1290 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1291 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1295 /* Add per CPU specific workarounds here */
1296 static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
1298 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1299 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1303 /* This should be disabled by the BIOS, but isn't always */
1304 if (c->x86_vendor == X86_VENDOR_AMD) {
1306 if (c->x86 == 15 && banks > 4) {
1308 * disable GART TBL walk error reporting, which
1309 * trips off incorrectly with the IOMMU & 3ware
1312 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1315 if (c->x86 <= 17 && mce_bootlog < 0) {
1317 * Lots of broken BIOS around that don't clear them
1318 * by default and leave crap in there. Don't log:
1323 * Various K7s with broken bank 0 around. Always disable
1326 if (c->x86 == 6 && banks > 0)
1327 mce_banks[0].ctl = 0;
1330 if (c->x86_vendor == X86_VENDOR_INTEL) {
1332 * SDM documents that on family 6 bank 0 should not be written
1333 * because it aliases to another special BIOS controlled
1335 * But it's not aliased anymore on model 0x1a+
1336 * Don't ignore bank 0 completely because there could be a
1337 * valid event later, merely don't write CTL0.
1340 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1341 mce_banks[0].init = 0;
1344 * All newer Intel systems support MCE broadcasting. Enable
1345 * synchronization with a one second timeout.
1347 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1348 monarch_timeout < 0)
1349 monarch_timeout = USEC_PER_SEC;
1352 * There are also broken BIOSes on some Pentium M and
1355 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1358 if (monarch_timeout < 0)
1359 monarch_timeout = 0;
1360 if (mce_bootlog != 0)
1361 mce_panic_timeout = 30;
1366 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1370 switch (c->x86_vendor) {
1371 case X86_VENDOR_INTEL:
1372 intel_p5_mcheck_init(c);
1374 case X86_VENDOR_CENTAUR:
1375 winchip_mcheck_init(c);
1380 static void mce_cpu_features(struct cpuinfo_x86 *c)
1382 #ifndef CONFIG_X86_64_XEN
1383 switch (c->x86_vendor) {
1384 case X86_VENDOR_INTEL:
1385 mce_intel_feature_init(c);
1387 case X86_VENDOR_AMD:
1388 mce_amd_feature_init(c);
1396 static void mce_init_timer(void)
1398 struct timer_list *t = &__get_cpu_var(mce_timer);
1399 int *n = &__get_cpu_var(mce_next_interval);
1401 setup_timer(t, mcheck_timer, smp_processor_id());
1406 *n = check_interval * HZ;
1409 t->expires = round_jiffies(jiffies + *n);
1410 add_timer_on(t, smp_processor_id());
1413 /* Handle unconfigured int18 (should never happen) */
1414 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1416 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1417 smp_processor_id());
1420 /* Call the installed machine check handler for this CPU setup. */
1421 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1422 unexpected_machine_check;
1425 * Called for each booted CPU to set up machine checks.
1426 * Must be called with preempt off:
1428 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1433 mce_ancient_init(c);
1435 if (!mce_available(c))
1438 if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
1443 machine_check_vector = do_machine_check;
1446 mce_cpu_features(c);
1448 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1452 * Character device to read and clear the MCE log.
1455 static DEFINE_SPINLOCK(mce_state_lock);
1456 static int open_count; /* #times opened */
1457 static int open_exclu; /* already open exclusive? */
1459 static int mce_open(struct inode *inode, struct file *file)
1461 spin_lock(&mce_state_lock);
1463 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1464 spin_unlock(&mce_state_lock);
1469 if (file->f_flags & O_EXCL)
1473 spin_unlock(&mce_state_lock);
1475 return nonseekable_open(inode, file);
1478 static int mce_release(struct inode *inode, struct file *file)
1480 spin_lock(&mce_state_lock);
1485 spin_unlock(&mce_state_lock);
1490 static void collect_tscs(void *data)
1492 unsigned long *cpu_tsc = (unsigned long *)data;
1494 rdtscll(cpu_tsc[smp_processor_id()]);
1497 static DEFINE_MUTEX(mce_read_mutex);
1499 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1502 char __user *buf = ubuf;
1503 unsigned long *cpu_tsc;
1504 unsigned prev, next;
1507 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1511 mutex_lock(&mce_read_mutex);
1512 next = rcu_dereference(mcelog.next);
1514 /* Only supports full reads right now */
1515 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1516 mutex_unlock(&mce_read_mutex);
1525 for (i = prev; i < next; i++) {
1526 unsigned long start = jiffies;
1528 while (!mcelog.entry[i].finished) {
1529 if (time_after_eq(jiffies, start + 2)) {
1530 memset(mcelog.entry + i, 0,
1531 sizeof(struct mce));
1537 err |= copy_to_user(buf, mcelog.entry + i,
1538 sizeof(struct mce));
1539 buf += sizeof(struct mce);
1544 memset(mcelog.entry + prev, 0,
1545 (next - prev) * sizeof(struct mce));
1547 next = cmpxchg(&mcelog.next, prev, 0);
1548 } while (next != prev);
1550 synchronize_sched();
1553 * Collect entries that were still getting written before the
1556 on_each_cpu(collect_tscs, cpu_tsc, 1);
1558 for (i = next; i < MCE_LOG_LEN; i++) {
1559 if (mcelog.entry[i].finished &&
1560 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1561 err |= copy_to_user(buf, mcelog.entry+i,
1562 sizeof(struct mce));
1564 buf += sizeof(struct mce);
1565 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1568 mutex_unlock(&mce_read_mutex);
1571 return err ? -EFAULT : buf - ubuf;
1574 static unsigned int mce_poll(struct file *file, poll_table *wait)
1576 poll_wait(file, &mce_wait, wait);
1577 if (rcu_dereference(mcelog.next))
1578 return POLLIN | POLLRDNORM;
1582 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1584 int __user *p = (int __user *)arg;
1586 if (!capable(CAP_SYS_ADMIN))
1590 case MCE_GET_RECORD_LEN:
1591 return put_user(sizeof(struct mce), p);
1592 case MCE_GET_LOG_LEN:
1593 return put_user(MCE_LOG_LEN, p);
1594 case MCE_GETCLEAR_FLAGS: {
1598 flags = mcelog.flags;
1599 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1601 return put_user(flags, p);
1608 /* Modified in mce-inject.c, so not static or const */
1609 struct file_operations mce_chrdev_ops = {
1611 .release = mce_release,
1614 .unlocked_ioctl = mce_ioctl,
1616 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1618 static struct miscdevice mce_log_device = {
1625 * mce=off Disables machine check
1626 * mce=no_cmci Disables CMCI
1627 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1628 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1629 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1630 * monarchtimeout is how long to wait for other CPUs on machine
1631 * check, or 0 to not wait
1632 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1633 * mce=nobootlog Don't log MCEs from before booting.
1635 static int __init mcheck_enable(char *str)
1643 if (!strcmp(str, "off"))
1645 else if (!strcmp(str, "no_cmci"))
1646 mce_cmci_disabled = 1;
1647 else if (!strcmp(str, "dont_log_ce"))
1648 mce_dont_log_ce = 1;
1649 else if (!strcmp(str, "ignore_ce"))
1651 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1652 mce_bootlog = (str[0] == 'b');
1653 else if (isdigit(str[0])) {
1654 get_option(&str, &tolerant);
1657 get_option(&str, &monarch_timeout);
1660 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1666 __setup("mce", mcheck_enable);
1673 * Disable machine checks on suspend and shutdown. We can't really handle
1676 static int mce_disable(void)
1680 for (i = 0; i < banks; i++) {
1681 struct mce_bank *b = &mce_banks[i];
1684 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1689 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1691 return mce_disable();
1694 static int mce_shutdown(struct sys_device *dev)
1696 return mce_disable();
1700 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1701 * Only one CPU is active at this time, the others get re-added later using
1704 static int mce_resume(struct sys_device *dev)
1707 mce_cpu_features(¤t_cpu_data);
1712 static void mce_cpu_restart(void *data)
1714 del_timer_sync(&__get_cpu_var(mce_timer));
1715 if (!mce_available(¤t_cpu_data))
1721 /* Reinit MCEs after user configuration changes */
1722 static void mce_restart(void)
1724 on_each_cpu(mce_cpu_restart, NULL, 1);
1727 /* Toggle features for corrected errors */
1728 static void mce_disable_ce(void *all)
1730 if (!mce_available(¤t_cpu_data))
1733 del_timer_sync(&__get_cpu_var(mce_timer));
1737 static void mce_enable_ce(void *all)
1739 if (!mce_available(¤t_cpu_data))
1747 static struct sysdev_class mce_sysclass = {
1748 .suspend = mce_suspend,
1749 .shutdown = mce_shutdown,
1750 .resume = mce_resume,
1751 .name = "machinecheck",
1754 DEFINE_PER_CPU(struct sys_device, mce_dev);
1757 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1759 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1761 return container_of(attr, struct mce_bank, attr);
1764 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1767 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1770 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1771 const char *buf, size_t size)
1775 if (strict_strtoull(buf, 0, &new) < 0)
1778 attr_to_bank(attr)->ctl = new;
1785 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1787 strcpy(buf, mce_helper);
1789 return strlen(mce_helper) + 1;
1792 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1793 const char *buf, size_t siz)
1797 strncpy(mce_helper, buf, sizeof(mce_helper));
1798 mce_helper[sizeof(mce_helper)-1] = 0;
1799 p = strchr(mce_helper, '\n');
1804 return strlen(mce_helper) + !!p;
1807 static ssize_t set_ignore_ce(struct sys_device *s,
1808 struct sysdev_attribute *attr,
1809 const char *buf, size_t size)
1813 if (strict_strtoull(buf, 0, &new) < 0)
1816 if (mce_ignore_ce ^ !!new) {
1818 /* disable ce features */
1819 on_each_cpu(mce_disable_ce, (void *)1, 1);
1822 /* enable ce features */
1824 on_each_cpu(mce_enable_ce, (void *)1, 1);
1830 static ssize_t set_cmci_disabled(struct sys_device *s,
1831 struct sysdev_attribute *attr,
1832 const char *buf, size_t size)
1836 if (strict_strtoull(buf, 0, &new) < 0)
1839 if (mce_cmci_disabled ^ !!new) {
1842 on_each_cpu(mce_disable_ce, NULL, 1);
1843 mce_cmci_disabled = 1;
1846 mce_cmci_disabled = 0;
1847 on_each_cpu(mce_enable_ce, NULL, 1);
1853 static ssize_t store_int_with_restart(struct sys_device *s,
1854 struct sysdev_attribute *attr,
1855 const char *buf, size_t size)
1857 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1862 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1863 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1864 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1865 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1867 static struct sysdev_ext_attribute attr_check_interval = {
1868 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1869 store_int_with_restart),
1873 static struct sysdev_ext_attribute attr_ignore_ce = {
1874 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1878 static struct sysdev_ext_attribute attr_cmci_disabled = {
1879 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1883 static struct sysdev_attribute *mce_attrs[] = {
1884 &attr_tolerant.attr,
1885 &attr_check_interval.attr,
1887 &attr_monarch_timeout.attr,
1888 &attr_dont_log_ce.attr,
1889 &attr_ignore_ce.attr,
1890 &attr_cmci_disabled.attr,
1894 static cpumask_var_t mce_dev_initialized;
1896 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1897 static __cpuinit int mce_create_device(unsigned int cpu)
1902 if (!mce_available(&boot_cpu_data))
1905 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1906 per_cpu(mce_dev, cpu).id = cpu;
1907 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1909 err = sysdev_register(&per_cpu(mce_dev, cpu));
1913 for (i = 0; mce_attrs[i]; i++) {
1914 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1918 for (j = 0; j < banks; j++) {
1919 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1920 &mce_banks[j].attr);
1924 cpumask_set_cpu(cpu, mce_dev_initialized);
1929 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1932 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1934 sysdev_unregister(&per_cpu(mce_dev, cpu));
1939 static __cpuinit void mce_remove_device(unsigned int cpu)
1943 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1946 for (i = 0; mce_attrs[i]; i++)
1947 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1949 for (i = 0; i < banks; i++)
1950 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1952 sysdev_unregister(&per_cpu(mce_dev, cpu));
1953 cpumask_clear_cpu(cpu, mce_dev_initialized);
1956 /* Make sure there are no machine checks on offlined CPUs. */
1957 static void mce_disable_cpu(void *h)
1959 unsigned long action = *(unsigned long *)h;
1962 if (!mce_available(¤t_cpu_data))
1964 if (!(action & CPU_TASKS_FROZEN))
1966 for (i = 0; i < banks; i++) {
1967 struct mce_bank *b = &mce_banks[i];
1970 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1974 static void mce_reenable_cpu(void *h)
1976 unsigned long action = *(unsigned long *)h;
1979 if (!mce_available(¤t_cpu_data))
1982 if (!(action & CPU_TASKS_FROZEN))
1984 for (i = 0; i < banks; i++) {
1985 struct mce_bank *b = &mce_banks[i];
1988 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1992 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1993 static int __cpuinit
1994 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1996 unsigned int cpu = (unsigned long)hcpu;
1997 struct timer_list *t = &per_cpu(mce_timer, cpu);
2001 case CPU_ONLINE_FROZEN:
2002 mce_create_device(cpu);
2003 if (threshold_cpu_callback)
2004 threshold_cpu_callback(action, cpu);
2007 case CPU_DEAD_FROZEN:
2008 if (threshold_cpu_callback)
2009 threshold_cpu_callback(action, cpu);
2010 mce_remove_device(cpu);
2012 case CPU_DOWN_PREPARE:
2013 case CPU_DOWN_PREPARE_FROZEN:
2015 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2017 case CPU_DOWN_FAILED:
2018 case CPU_DOWN_FAILED_FROZEN:
2019 if (!mce_ignore_ce && check_interval) {
2020 t->expires = round_jiffies(jiffies +
2021 __get_cpu_var(mce_next_interval));
2022 add_timer_on(t, cpu);
2024 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2027 /* intentionally ignoring frozen here */
2028 cmci_rediscover(cpu);
2034 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2035 .notifier_call = mce_cpu_callback,
2038 static __init void mce_init_banks(void)
2042 for (i = 0; i < banks; i++) {
2043 struct mce_bank *b = &mce_banks[i];
2044 struct sysdev_attribute *a = &b->attr;
2046 a->attr.name = b->attrname;
2047 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2049 a->attr.mode = 0644;
2050 a->show = show_bank;
2051 a->store = set_bank;
2055 static __init int mce_init_device(void)
2060 if (!mce_available(&boot_cpu_data))
2063 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2067 err = sysdev_class_register(&mce_sysclass);
2071 for_each_online_cpu(i) {
2072 err = mce_create_device(i);
2077 register_hotcpu_notifier(&mce_cpu_notifier);
2078 misc_register(&mce_log_device);
2080 #ifdef CONFIG_X86_XEN_MCE
2081 if (is_initial_xendomain()) {
2082 /* Register vIRQ handler for MCE LOG processing */
2083 extern int bind_virq_for_mce(void);
2085 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2086 bind_virq_for_mce();
2093 device_initcall(mce_init_device);
2096 * Old style boot options parsing. Only for compatibility.
2098 static int __init mcheck_disable(char *str)
2103 __setup("nomce", mcheck_disable);
2105 #ifdef CONFIG_DEBUG_FS
2106 struct dentry *mce_get_debugfs_dir(void)
2108 static struct dentry *dmce;
2111 dmce = debugfs_create_dir("mce", NULL);
2116 static void mce_reset(void)
2119 atomic_set(&mce_fake_paniced, 0);
2120 atomic_set(&mce_executing, 0);
2121 atomic_set(&mce_callin, 0);
2122 atomic_set(&global_nwo, 0);
2125 static int fake_panic_get(void *data, u64 *val)
2131 static int fake_panic_set(void *data, u64 val)
2138 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2139 fake_panic_set, "%llu\n");
2141 static int __init mce_debugfs_init(void)
2143 struct dentry *dmce, *ffake_panic;
2145 dmce = mce_get_debugfs_dir();
2148 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2155 late_initcall(mce_debugfs_init);