2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 #define CREATE_TRACE_POINTS
50 #include <trace/events/mce.h>
52 int mce_disabled __read_mostly;
54 #define MISC_MCELOG_MINOR 227
56 #define SPINUNIT 100 /* 100ns */
60 DEFINE_PER_CPU(unsigned, mce_exception_count);
64 * 0: always panic on uncorrected errors, log corrected errors
65 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
66 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
67 * 3: never panic or SIGBUS, log all errors (for testing only)
69 static int tolerant __read_mostly = 1;
70 static int banks __read_mostly;
71 static int rip_msr __read_mostly;
72 static int mce_bootlog __read_mostly = -1;
73 static int monarch_timeout __read_mostly = -1;
74 static int mce_panic_timeout __read_mostly;
75 static int mce_dont_log_ce __read_mostly;
76 int mce_cmci_disabled __read_mostly;
77 int mce_ignore_ce __read_mostly;
78 int mce_ser __read_mostly;
80 struct mce_bank *mce_banks __read_mostly;
82 /* User mode helper program triggered by machine check event */
83 static unsigned long mce_need_notify;
84 static char mce_helper[128];
85 static char *mce_helper_argv[2] = { mce_helper, NULL };
87 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
88 static DEFINE_PER_CPU(struct mce, mces_seen);
89 static int cpu_missing;
90 void (*mce_cpu_specific_poll)(struct mce *);
91 EXPORT_SYMBOL_GPL(mce_cpu_specific_poll);
94 * CPU/chipset specific EDAC code can register a notifier call here to print
95 * MCE errors in a human-readable form.
97 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
98 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
100 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
103 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
104 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
109 static struct notifier_block mce_dec_nb = {
110 .notifier_call = default_decode_mce,
114 /* MCA banks polled by the period polling timer for corrected events */
115 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
116 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
119 static DEFINE_PER_CPU(struct work_struct, mce_work);
121 /* Do initial initialization of a struct mce */
122 void mce_setup(struct mce *m)
124 memset(m, 0, sizeof(struct mce));
125 m->cpu = m->extcpu = smp_processor_id();
127 /* We hope get_seconds stays lockless */
128 m->time = get_seconds();
129 m->cpuvendor = boot_cpu_data.x86_vendor;
130 m->cpuid = cpuid_eax(1);
132 m->socketid = cpu_data(m->extcpu).phys_proc_id;
134 m->apicid = cpu_data(m->extcpu).initial_apicid;
135 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
138 DEFINE_PER_CPU(struct mce, injectm);
139 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
142 * Lockless MCE logging infrastructure.
143 * This avoids deadlocks on printk locks without having to break locks. Also
144 * separate MCEs from kernel messages to avoid bogus bug reports.
147 static struct mce_log mcelog = {
148 .signature = MCE_LOG_SIGNATURE,
150 .recordlen = sizeof(struct mce),
153 void mce_log(struct mce *mce)
155 unsigned next, entry;
157 /* Emit the trace record: */
158 trace_mce_record(mce);
163 entry = rcu_dereference(mcelog.next);
166 * When the buffer fills up discard new entries.
167 * Assume that the earlier errors are the more
170 if (entry >= MCE_LOG_LEN) {
171 set_bit(MCE_OVERFLOW,
172 (unsigned long *)&mcelog.flags);
175 /* Old left over entry. Skip: */
176 if (mcelog.entry[entry].finished) {
184 if (cmpxchg(&mcelog.next, entry, next) == entry)
187 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
189 mcelog.entry[entry].finished = 1;
193 set_bit(0, &mce_need_notify);
196 static void print_mce(struct mce *m)
198 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
199 m->extcpu, m->mcgstatus, m->bank, m->status);
202 pr_emerg("RIP%s %02x:<%016Lx> ",
203 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
206 if (m->cs == __KERNEL_CS)
207 print_symbol("{%s}", m->ip);
211 pr_emerg("TSC %llx ", m->tsc);
213 pr_cont("ADDR %llx ", m->addr);
215 pr_cont("MISC %llx ", m->misc);
218 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
219 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
222 * Print out human-readable details about the MCE error,
223 * (if the CPU has an implementation for that)
225 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
228 static void print_mce_head(void)
230 pr_emerg("\nHARDWARE ERROR\n");
233 static void print_mce_tail(void)
235 pr_emerg("This is not a software problem!\n");
238 #define PANIC_TIMEOUT 5 /* 5 seconds */
240 static atomic_t mce_paniced;
242 static int fake_panic;
243 static atomic_t mce_fake_paniced;
245 /* Panic in progress. Enable interrupts and wait for final IPI */
246 static void wait_for_panic(void)
248 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
252 while (timeout-- > 0)
254 if (panic_timeout == 0)
255 panic_timeout = mce_panic_timeout;
256 panic("Panicing machine check CPU died");
259 static void mce_panic(char *msg, struct mce *final, char *exp)
265 * Make sure only one CPU runs in machine check panic
267 if (atomic_inc_return(&mce_paniced) > 1)
274 /* Don't log too much for fake panic */
275 if (atomic_inc_return(&mce_fake_paniced) > 1)
279 /* First print corrected ones that are still unlogged */
280 for (i = 0; i < MCE_LOG_LEN; i++) {
281 struct mce *m = &mcelog.entry[i];
282 if (!(m->status & MCI_STATUS_VAL))
284 if (!(m->status & MCI_STATUS_UC))
287 /* Now print uncorrected but with the final one last */
288 for (i = 0; i < MCE_LOG_LEN; i++) {
289 struct mce *m = &mcelog.entry[i];
290 if (!(m->status & MCI_STATUS_VAL))
292 if (!(m->status & MCI_STATUS_UC))
294 if (!final || memcmp(m, final, sizeof(struct mce)))
300 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
303 printk(KERN_EMERG "Machine check: %s\n", exp);
305 if (panic_timeout == 0)
306 panic_timeout = mce_panic_timeout;
309 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
312 /* Support code for software error injection */
314 static int msr_to_offset(u32 msr)
316 unsigned bank = __get_cpu_var(injectm.bank);
319 return offsetof(struct mce, ip);
320 if (msr == MSR_IA32_MCx_STATUS(bank))
321 return offsetof(struct mce, status);
322 if (msr == MSR_IA32_MCx_ADDR(bank))
323 return offsetof(struct mce, addr);
324 if (msr == MSR_IA32_MCx_MISC(bank))
325 return offsetof(struct mce, misc);
326 if (msr == MSR_IA32_MCG_STATUS)
327 return offsetof(struct mce, mcgstatus);
331 /* MSR access wrappers used for error injection */
332 static u64 mce_rdmsrl(u32 msr)
336 if (__get_cpu_var(injectm).finished) {
337 int offset = msr_to_offset(msr);
341 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
344 if (rdmsrl_safe(msr, &v)) {
345 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
347 * Return zero in case the access faulted. This should
348 * not happen normally but can happen if the CPU does
349 * something weird, or if the code is buggy.
357 static void mce_wrmsrl(u32 msr, u64 v)
359 if (__get_cpu_var(injectm).finished) {
360 int offset = msr_to_offset(msr);
363 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
369 static int under_injection(void)
371 return __get_cpu_var(injectm).finished;
375 * Simple lockless ring to communicate PFNs from the exception handler with the
376 * process context work function. This is vastly simplified because there's
377 * only a single reader and a single writer.
379 #define MCE_RING_SIZE 16 /* we use one entry less */
382 unsigned short start;
384 unsigned long ring[MCE_RING_SIZE];
386 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
388 /* Runs with CPU affinity in workqueue */
389 static int mce_ring_empty(void)
391 struct mce_ring *r = &__get_cpu_var(mce_ring);
393 return r->start == r->end;
396 static int mce_ring_get(unsigned long *pfn)
403 r = &__get_cpu_var(mce_ring);
404 if (r->start == r->end)
406 *pfn = r->ring[r->start];
407 r->start = (r->start + 1) % MCE_RING_SIZE;
414 /* Always runs in MCE context with preempt off */
415 static int mce_ring_add(unsigned long pfn)
417 struct mce_ring *r = &__get_cpu_var(mce_ring);
420 next = (r->end + 1) % MCE_RING_SIZE;
421 if (next == r->start)
423 r->ring[r->end] = pfn;
429 int mce_available(struct cpuinfo_x86 *c)
433 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
436 static void mce_schedule_work(void)
438 if (!mce_ring_empty()) {
439 struct work_struct *work = &__get_cpu_var(mce_work);
440 if (!work_pending(work))
446 * Get the address of the instruction at the time of the machine check
449 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
452 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
460 m->ip = mce_rdmsrl(rip_msr);
463 #ifdef CONFIG_X86_LOCAL_APIC
465 * Called after interrupts have been reenabled again
466 * when a MCE happened during an interrupts off region
469 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
480 static void mce_report_event(struct pt_regs *regs)
482 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
485 * Triggering the work queue here is just an insurance
486 * policy in case the syscall exit notify handler
487 * doesn't run soon enough or ends up running on the
488 * wrong CPU (can happen when audit sleeps)
494 #ifdef CONFIG_X86_LOCAL_APIC
496 * Without APIC do not notify. The event will be picked
503 * When interrupts are disabled we cannot use
504 * kernel services safely. Trigger an self interrupt
505 * through the APIC to instead do the notification
506 * after interrupts are reenabled again.
508 apic->send_IPI_self(MCE_SELF_VECTOR);
511 * Wait for idle afterwards again so that we don't leave the
512 * APIC in a non idle state because the normal APIC writes
515 apic_wait_icr_idle();
519 DEFINE_PER_CPU(unsigned, mce_poll_count);
522 * Poll for corrected events or events that happened before reset.
523 * Those are just logged through /dev/mcelog.
525 * This is executed in standard interrupt context.
527 * Note: spec recommends to panic for fatal unsignalled
528 * errors here. However this would be quite problematic --
529 * we would need to reimplement the Monarch handling and
530 * it would mess up the exclusion between exception handler
531 * and poll hander -- * so we skip this for now.
532 * These cases should not happen anyways, or only when the CPU
533 * is already totally * confused. In this case it's likely it will
534 * not fully execute the machine check handler either.
536 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
541 __get_cpu_var(mce_poll_count)++;
545 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
546 for (i = 0; i < banks; i++) {
547 if (!mce_banks[i].ctl || !test_bit(i, *b))
556 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
557 if (!(m.status & MCI_STATUS_VAL))
561 * Uncorrected or signalled events are handled by the exception
562 * handler when it is enabled, so don't process those here.
564 * TBD do the same check for MCI_STATUS_EN here?
566 if (!(flags & MCP_UC) &&
567 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
570 if (m.status & MCI_STATUS_MISCV)
571 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
572 if (m.status & MCI_STATUS_ADDRV)
573 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
575 if (!(flags & MCP_TIMESTAMP))
578 if (mce_cpu_specific_poll && !under_injection() && !mce_dont_log_ce)
579 mce_cpu_specific_poll(&m);
582 * Don't get the IP here because it's unlikely to
583 * have anything to do with the actual error location.
585 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
587 add_taint(TAINT_MACHINE_CHECK);
591 * Clear state for this bank.
593 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
597 * Don't clear MCG_STATUS here because it's only defined for
603 EXPORT_SYMBOL_GPL(machine_check_poll);
606 * Do a quick check if any of the events requires a panic.
607 * This decides if we keep the events around or clear them.
609 static int mce_no_way_out(struct mce *m, char **msg)
613 for (i = 0; i < banks; i++) {
614 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
615 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
622 * Variable to establish order between CPUs while scanning.
623 * Each CPU spins initially until executing is equal its number.
625 static atomic_t mce_executing;
628 * Defines order of CPUs on entry. First CPU becomes Monarch.
630 static atomic_t mce_callin;
633 * Check if a timeout waiting for other CPUs happened.
635 static int mce_timed_out(u64 *t)
638 * The others already did panic for some reason.
639 * Bail out like in a timeout.
640 * rmb() to tell the compiler that system_state
641 * might have been modified by someone else.
644 if (atomic_read(&mce_paniced))
646 if (!monarch_timeout)
648 if ((s64)*t < SPINUNIT) {
649 /* CHECKME: Make panic default for 1 too? */
651 mce_panic("Timeout synchronizing machine check over CPUs",
658 touch_nmi_watchdog();
663 * The Monarch's reign. The Monarch is the CPU who entered
664 * the machine check handler first. It waits for the others to
665 * raise the exception too and then grades them. When any
666 * error is fatal panic. Only then let the others continue.
668 * The other CPUs entering the MCE handler will be controlled by the
669 * Monarch. They are called Subjects.
671 * This way we prevent any potential data corruption in a unrecoverable case
672 * and also makes sure always all CPU's errors are examined.
674 * Also this detects the case of a machine check event coming from outer
675 * space (not detected by any CPUs) In this case some external agent wants
676 * us to shut down, so panic too.
678 * The other CPUs might still decide to panic if the handler happens
679 * in a unrecoverable place, but in this case the system is in a semi-stable
680 * state and won't corrupt anything by itself. It's ok to let the others
681 * continue for a bit first.
683 * All the spin loops have timeouts; when a timeout happens a CPU
684 * typically elects itself to be Monarch.
686 static void mce_reign(void)
689 struct mce *m = NULL;
690 int global_worst = 0;
695 * This CPU is the Monarch and the other CPUs have run
696 * through their handlers.
697 * Grade the severity of the errors of all the CPUs.
699 for_each_possible_cpu(cpu) {
700 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
702 if (severity > global_worst) {
704 global_worst = severity;
705 m = &per_cpu(mces_seen, cpu);
710 * Cannot recover? Panic here then.
711 * This dumps all the mces in the log buffer and stops the
714 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
715 mce_panic("Fatal Machine check", m, msg);
718 * For UC somewhere we let the CPU who detects it handle it.
719 * Also must let continue the others, otherwise the handling
720 * CPU could deadlock on a lock.
724 * No machine check event found. Must be some external
725 * source or one CPU is hung. Panic.
727 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
728 mce_panic("Machine check from unknown source", NULL, NULL);
731 * Now clear all the mces_seen so that they don't reappear on
734 for_each_possible_cpu(cpu)
735 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
738 static atomic_t global_nwo;
741 * Start of Monarch synchronization. This waits until all CPUs have
742 * entered the exception handler and then determines if any of them
743 * saw a fatal event that requires panic. Then it executes them
744 * in the entry order.
745 * TBD double check parallel CPU hotunplug
747 static int mce_start(int *no_way_out)
750 int cpus = num_online_cpus();
751 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
756 atomic_add(*no_way_out, &global_nwo);
758 * global_nwo should be updated before mce_callin
761 order = atomic_inc_return(&mce_callin);
766 while (atomic_read(&mce_callin) != cpus) {
767 if (mce_timed_out(&timeout)) {
768 atomic_set(&global_nwo, 0);
775 * mce_callin should be read before global_nwo
781 * Monarch: Starts executing now, the others wait.
783 atomic_set(&mce_executing, 1);
786 * Subject: Now start the scanning loop one by one in
787 * the original callin order.
788 * This way when there are any shared banks it will be
789 * only seen by one CPU before cleared, avoiding duplicates.
791 while (atomic_read(&mce_executing) < order) {
792 if (mce_timed_out(&timeout)) {
793 atomic_set(&global_nwo, 0);
801 * Cache the global no_way_out state.
803 *no_way_out = atomic_read(&global_nwo);
809 * Synchronize between CPUs after main scanning loop.
810 * This invokes the bulk of the Monarch processing.
812 static int mce_end(int order)
815 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
823 * Allow others to run.
825 atomic_inc(&mce_executing);
828 /* CHECKME: Can this race with a parallel hotplug? */
829 int cpus = num_online_cpus();
832 * Monarch: Wait for everyone to go through their scanning
835 while (atomic_read(&mce_executing) <= cpus) {
836 if (mce_timed_out(&timeout))
846 * Subject: Wait for Monarch to finish.
848 while (atomic_read(&mce_executing) != 0) {
849 if (mce_timed_out(&timeout))
855 * Don't reset anything. That's done by the Monarch.
861 * Reset all global state.
864 atomic_set(&global_nwo, 0);
865 atomic_set(&mce_callin, 0);
869 * Let others run again.
871 atomic_set(&mce_executing, 0);
876 * Check if the address reported by the CPU is in a format we can parse.
877 * It would be possible to add code for most other cases, but all would
878 * be somewhat complicated (e.g. segment offset would require an instruction
879 * parser). So only support physical addresses upto page granuality for now.
881 static int mce_usable_address(struct mce *m)
883 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
885 if ((m->misc & 0x3f) > PAGE_SHIFT)
887 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
892 static void mce_clear_state(unsigned long *toclear)
896 for (i = 0; i < banks; i++) {
897 if (test_bit(i, toclear))
898 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
903 * The actual machine check handler. This only handles real
904 * exceptions when something got corrupted coming in through int 18.
906 * This is executed in NMI context not subject to normal locking rules. This
907 * implies that most kernel services cannot be safely used. Don't even
908 * think about putting a printk in there!
910 * On Intel systems this is entered on all CPUs in parallel through
911 * MCE broadcast. However some CPUs might be broken beyond repair,
912 * so be always careful when synchronizing with others.
914 void do_machine_check(struct pt_regs *regs, long error_code)
916 struct mce m, *final;
921 * Establish sequential order between the CPUs entering the machine
926 * If no_way_out gets set, there is no safe way to recover from this
927 * MCE. If tolerant is cranked up, we'll try anyway.
931 * If kill_it gets set, there might be a way to recover from this
935 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
936 char *msg = "Unknown";
938 atomic_inc(&mce_entry);
940 __get_cpu_var(mce_exception_count)++;
942 if (notify_die(DIE_NMI, "machine check", regs, error_code,
943 18, SIGKILL) == NOTIFY_STOP)
950 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
951 final = &__get_cpu_var(mces_seen);
954 no_way_out = mce_no_way_out(&m, &msg);
959 * When no restart IP must always kill or panic.
961 if (!(m.mcgstatus & MCG_STATUS_RIPV))
965 * Go through all the banks in exclusion of the other CPUs.
966 * This way we don't report duplicated events on shared banks
967 * because the first one to see it will clear it.
969 order = mce_start(&no_way_out);
970 for (i = 0; i < banks; i++) {
971 __clear_bit(i, toclear);
972 if (!mce_banks[i].ctl)
979 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
980 if ((m.status & MCI_STATUS_VAL) == 0)
984 * Non uncorrected or non signaled errors are handled by
985 * machine_check_poll. Leave them alone, unless this panics.
987 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
992 * Set taint even when machine check was not enabled.
994 add_taint(TAINT_MACHINE_CHECK);
996 severity = mce_severity(&m, tolerant, NULL);
999 * When machine check was for corrected handler don't touch,
1000 * unless we're panicing.
1002 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1004 __set_bit(i, toclear);
1005 if (severity == MCE_NO_SEVERITY) {
1007 * Machine check event was not enabled. Clear, but
1014 * Kill on action required.
1016 if (severity == MCE_AR_SEVERITY)
1019 if (m.status & MCI_STATUS_MISCV)
1020 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1021 if (m.status & MCI_STATUS_ADDRV)
1022 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1025 * Action optional error. Queue address for later processing.
1026 * When the ring overflows we just ignore the AO error.
1027 * RED-PEN add some logging mechanism when
1028 * usable_address or mce_add_ring fails.
1029 * RED-PEN don't ignore overflow for tolerant == 0
1031 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1032 mce_ring_add(m.addr >> PAGE_SHIFT);
1034 mce_get_rip(&m, regs);
1037 if (severity > worst) {
1044 mce_clear_state(toclear);
1047 * Do most of the synchronization with other CPUs.
1048 * When there's any problem use only local no_way_out state.
1050 if (mce_end(order) < 0)
1051 no_way_out = worst >= MCE_PANIC_SEVERITY;
1054 * If we have decided that we just CAN'T continue, and the user
1055 * has not set tolerant to an insane level, give up and die.
1057 * This is mainly used in the case when the system doesn't
1058 * support MCE broadcasting or it has been disabled.
1060 if (no_way_out && tolerant < 3)
1061 mce_panic("Fatal machine check on current CPU", final, msg);
1064 * If the error seems to be unrecoverable, something should be
1065 * done. Try to kill as little as possible. If we can kill just
1066 * one task, do that. If the user has set the tolerance very
1067 * high, don't try to do anything at all.
1070 if (kill_it && tolerant < 3)
1071 force_sig(SIGBUS, current);
1073 /* notify userspace ASAP */
1074 set_thread_flag(TIF_MCE_NOTIFY);
1077 mce_report_event(regs);
1078 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1080 atomic_dec(&mce_entry);
1083 EXPORT_SYMBOL_GPL(do_machine_check);
1085 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1086 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1088 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1092 * Called after mce notification in process context. This code
1093 * is allowed to sleep. Call the high level VM handler to process
1094 * any corrupted pages.
1095 * Assume that the work queue code only calls this one at a time
1097 * Note we don't disable preemption, so this code might run on the wrong
1098 * CPU. In this case the event is picked up by the scheduled work queue.
1099 * This is merely a fast path to expedite processing in some common
1102 void mce_notify_process(void)
1106 while (mce_ring_get(&pfn))
1107 memory_failure(pfn, MCE_VECTOR);
1110 static void mce_process_work(struct work_struct *dummy)
1112 mce_notify_process();
1115 #ifdef CONFIG_X86_MCE_INTEL
1117 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1118 * @cpu: The CPU on which the event occurred.
1119 * @status: Event status information
1121 * This function should be called by the thermal interrupt after the
1122 * event has been processed and the decision was made to log the event
1125 * The status parameter will be saved to the 'status' field of 'struct mce'
1126 * and historically has been the register value of the
1127 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1129 void mce_log_therm_throt_event(__u64 status)
1134 m.bank = MCE_THERMAL_BANK;
1138 #endif /* CONFIG_X86_MCE_INTEL */
1141 * Periodic polling timer for "silent" machine check errors. If the
1142 * poller finds an MCE, poll 2x faster. When the poller finds no more
1143 * errors, poll 2x slower (up to check_interval seconds).
1145 static int check_interval = 5 * 60; /* 5 minutes */
1147 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1148 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1150 static void mce_start_timer(unsigned long data)
1152 struct timer_list *t = &per_cpu(mce_timer, data);
1155 WARN_ON(smp_processor_id() != data);
1157 if (mce_available(¤t_cpu_data)) {
1158 machine_check_poll(MCP_TIMESTAMP,
1159 &__get_cpu_var(mce_poll_banks));
1163 * Alert userspace if needed. If we logged an MCE, reduce the
1164 * polling interval, otherwise increase the polling interval.
1166 n = &__get_cpu_var(mce_next_interval);
1167 if (mce_notify_irq())
1168 *n = max(*n/2, HZ/100);
1170 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1172 t->expires = jiffies + *n;
1173 add_timer_on(t, smp_processor_id());
1176 static void mce_do_trigger(struct work_struct *work)
1178 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1181 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1184 * Notify the user(s) about new machine check events.
1185 * Can be called from interrupt context, but not from machine check/NMI
1188 int mce_notify_irq(void)
1190 /* Not more than two messages every minute */
1191 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1193 clear_thread_flag(TIF_MCE_NOTIFY);
1195 if (test_and_clear_bit(0, &mce_need_notify)) {
1196 wake_up_interruptible(&mce_wait);
1199 * There is no risk of missing notifications because
1200 * work_pending is always cleared before the function is
1203 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1204 schedule_work(&mce_trigger_work);
1206 if (__ratelimit(&ratelimit))
1207 printk(KERN_INFO "Machine check events logged\n");
1213 EXPORT_SYMBOL_GPL(mce_notify_irq);
1215 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1219 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1222 for (i = 0; i < banks; i++) {
1223 struct mce_bank *b = &mce_banks[i];
1232 * Initialize Machine Checks for a CPU.
1234 static int __cpuinit __mcheck_cpu_cap_init(void)
1239 rdmsrl(MSR_IA32_MCG_CAP, cap);
1241 b = cap & MCG_BANKCNT_MASK;
1243 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1245 if (b > MAX_NR_BANKS) {
1247 "MCE: Using only %u machine check banks out of %u\n",
1252 /* Don't support asymmetric configurations today */
1253 WARN_ON(banks != 0 && b != banks);
1256 int err = __mcheck_cpu_mce_banks_init();
1262 /* Use accurate RIP reporting if available. */
1263 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1264 rip_msr = MSR_IA32_MCG_EIP;
1266 if (cap & MCG_SER_P)
1272 static void __mcheck_cpu_init_generic(void)
1274 mce_banks_t all_banks;
1279 * Log the machine checks left over from the previous reset.
1281 bitmap_fill(all_banks, MAX_NR_BANKS);
1282 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1284 set_in_cr4(X86_CR4_MCE);
1286 rdmsrl(MSR_IA32_MCG_CAP, cap);
1287 if (cap & MCG_CTL_P)
1288 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1290 for (i = 0; i < banks; i++) {
1291 struct mce_bank *b = &mce_banks[i];
1295 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1296 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1300 /* Add per CPU specific workarounds here */
1301 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1303 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1304 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1308 /* This should be disabled by the BIOS, but isn't always */
1309 if (c->x86_vendor == X86_VENDOR_AMD) {
1310 if (c->x86 == 15 && banks > 4) {
1312 * disable GART TBL walk error reporting, which
1313 * trips off incorrectly with the IOMMU & 3ware
1316 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1318 if (c->x86 <= 17 && mce_bootlog < 0) {
1320 * Lots of broken BIOS around that don't clear them
1321 * by default and leave crap in there. Don't log:
1326 * Various K7s with broken bank 0 around. Always disable
1329 if (c->x86 == 6 && banks > 0)
1330 mce_banks[0].ctl = 0;
1333 if (c->x86_vendor == X86_VENDOR_INTEL) {
1335 * SDM documents that on family 6 bank 0 should not be written
1336 * because it aliases to another special BIOS controlled
1338 * But it's not aliased anymore on model 0x1a+
1339 * Don't ignore bank 0 completely because there could be a
1340 * valid event later, merely don't write CTL0.
1343 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1344 mce_banks[0].init = 0;
1347 * All newer Intel systems support MCE broadcasting. Enable
1348 * synchronization with a one second timeout.
1350 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1351 monarch_timeout < 0)
1352 monarch_timeout = USEC_PER_SEC;
1355 * There are also broken BIOSes on some Pentium M and
1358 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1361 if (monarch_timeout < 0)
1362 monarch_timeout = 0;
1363 if (mce_bootlog != 0)
1364 mce_panic_timeout = 30;
1369 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1373 switch (c->x86_vendor) {
1374 case X86_VENDOR_INTEL:
1375 intel_p5_mcheck_init(c);
1377 case X86_VENDOR_CENTAUR:
1378 winchip_mcheck_init(c);
1383 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1385 switch (c->x86_vendor) {
1386 case X86_VENDOR_INTEL:
1387 mce_intel_feature_init(c);
1389 case X86_VENDOR_AMD:
1390 mce_amd_feature_init(c);
1397 static void __mcheck_cpu_init_timer(void)
1399 struct timer_list *t = &__get_cpu_var(mce_timer);
1400 int *n = &__get_cpu_var(mce_next_interval);
1402 setup_timer(t, mce_start_timer, smp_processor_id());
1407 *n = check_interval * HZ;
1410 t->expires = round_jiffies(jiffies + *n);
1411 add_timer_on(t, smp_processor_id());
1414 /* Handle unconfigured int18 (should never happen) */
1415 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1417 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1418 smp_processor_id());
1421 /* Call the installed machine check handler for this CPU setup. */
1422 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1423 unexpected_machine_check;
1426 * Called for each booted CPU to set up machine checks.
1427 * Must be called with preempt off:
1429 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1434 __mcheck_cpu_ancient_init(c);
1436 if (!mce_available(c))
1439 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1444 machine_check_vector = do_machine_check;
1446 __mcheck_cpu_init_generic();
1447 __mcheck_cpu_init_vendor(c);
1448 __mcheck_cpu_init_timer();
1449 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1454 * Character device to read and clear the MCE log.
1457 static DEFINE_SPINLOCK(mce_state_lock);
1458 static int open_count; /* #times opened */
1459 static int open_exclu; /* already open exclusive? */
1461 static int mce_open(struct inode *inode, struct file *file)
1463 spin_lock(&mce_state_lock);
1465 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1466 spin_unlock(&mce_state_lock);
1471 if (file->f_flags & O_EXCL)
1475 spin_unlock(&mce_state_lock);
1477 return nonseekable_open(inode, file);
1480 static int mce_release(struct inode *inode, struct file *file)
1482 spin_lock(&mce_state_lock);
1487 spin_unlock(&mce_state_lock);
1492 static void collect_tscs(void *data)
1494 unsigned long *cpu_tsc = (unsigned long *)data;
1496 rdtscll(cpu_tsc[smp_processor_id()]);
1499 static DEFINE_MUTEX(mce_read_mutex);
1501 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1504 char __user *buf = ubuf;
1505 unsigned long *cpu_tsc;
1506 unsigned prev, next;
1509 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1513 mutex_lock(&mce_read_mutex);
1514 next = rcu_dereference(mcelog.next);
1516 /* Only supports full reads right now */
1517 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1518 mutex_unlock(&mce_read_mutex);
1527 for (i = prev; i < next; i++) {
1528 unsigned long start = jiffies;
1530 while (!mcelog.entry[i].finished) {
1531 if (time_after_eq(jiffies, start + 2)) {
1532 memset(mcelog.entry + i, 0,
1533 sizeof(struct mce));
1539 err |= copy_to_user(buf, mcelog.entry + i,
1540 sizeof(struct mce));
1541 buf += sizeof(struct mce);
1546 memset(mcelog.entry + prev, 0,
1547 (next - prev) * sizeof(struct mce));
1549 next = cmpxchg(&mcelog.next, prev, 0);
1550 } while (next != prev);
1552 synchronize_sched();
1555 * Collect entries that were still getting written before the
1558 on_each_cpu(collect_tscs, cpu_tsc, 1);
1560 for (i = next; i < MCE_LOG_LEN; i++) {
1561 if (mcelog.entry[i].finished &&
1562 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1563 err |= copy_to_user(buf, mcelog.entry+i,
1564 sizeof(struct mce));
1566 buf += sizeof(struct mce);
1567 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1570 mutex_unlock(&mce_read_mutex);
1573 return err ? -EFAULT : buf - ubuf;
1576 static unsigned int mce_poll(struct file *file, poll_table *wait)
1578 poll_wait(file, &mce_wait, wait);
1579 if (rcu_dereference(mcelog.next))
1580 return POLLIN | POLLRDNORM;
1584 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1586 int __user *p = (int __user *)arg;
1588 if (!capable(CAP_SYS_ADMIN))
1592 case MCE_GET_RECORD_LEN:
1593 return put_user(sizeof(struct mce), p);
1594 case MCE_GET_LOG_LEN:
1595 return put_user(MCE_LOG_LEN, p);
1596 case MCE_GETCLEAR_FLAGS: {
1600 flags = mcelog.flags;
1601 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1603 return put_user(flags, p);
1610 /* Modified in mce-inject.c, so not static or const */
1611 struct file_operations mce_chrdev_ops = {
1613 .release = mce_release,
1616 .unlocked_ioctl = mce_ioctl,
1618 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1620 static struct miscdevice mce_log_device = {
1627 * mce=off Disables machine check
1628 * mce=no_cmci Disables CMCI
1629 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1630 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1631 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1632 * monarchtimeout is how long to wait for other CPUs on machine
1633 * check, or 0 to not wait
1634 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1635 * mce=nobootlog Don't log MCEs from before booting.
1637 static int __init mcheck_enable(char *str)
1645 if (!strcmp(str, "off"))
1647 else if (!strcmp(str, "no_cmci"))
1648 mce_cmci_disabled = 1;
1649 else if (!strcmp(str, "dont_log_ce"))
1650 mce_dont_log_ce = 1;
1651 else if (!strcmp(str, "ignore_ce"))
1653 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1654 mce_bootlog = (str[0] == 'b');
1655 else if (isdigit(str[0])) {
1656 get_option(&str, &tolerant);
1659 get_option(&str, &monarch_timeout);
1662 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1668 __setup("mce", mcheck_enable);
1670 int __init mcheck_init(void)
1672 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1674 mcheck_intel_therm_init();
1684 * Disable machine checks on suspend and shutdown. We can't really handle
1687 static int mce_disable_error_reporting(void)
1691 for (i = 0; i < banks; i++) {
1692 struct mce_bank *b = &mce_banks[i];
1695 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1700 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1702 return mce_disable_error_reporting();
1705 static int mce_shutdown(struct sys_device *dev)
1707 return mce_disable_error_reporting();
1711 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1712 * Only one CPU is active at this time, the others get re-added later using
1715 static int mce_resume(struct sys_device *dev)
1717 __mcheck_cpu_init_generic();
1718 __mcheck_cpu_init_vendor(¤t_cpu_data);
1723 static void mce_cpu_restart(void *data)
1725 del_timer_sync(&__get_cpu_var(mce_timer));
1726 if (!mce_available(¤t_cpu_data))
1728 __mcheck_cpu_init_generic();
1729 __mcheck_cpu_init_timer();
1732 /* Reinit MCEs after user configuration changes */
1733 static void mce_restart(void)
1735 on_each_cpu(mce_cpu_restart, NULL, 1);
1738 /* Toggle features for corrected errors */
1739 static void mce_disable_ce(void *all)
1741 if (!mce_available(¤t_cpu_data))
1744 del_timer_sync(&__get_cpu_var(mce_timer));
1748 static void mce_enable_ce(void *all)
1750 if (!mce_available(¤t_cpu_data))
1755 __mcheck_cpu_init_timer();
1758 static struct sysdev_class mce_sysclass = {
1759 .suspend = mce_suspend,
1760 .shutdown = mce_shutdown,
1761 .resume = mce_resume,
1762 .name = "machinecheck",
1765 DEFINE_PER_CPU(struct sys_device, mce_dev);
1768 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1770 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1772 return container_of(attr, struct mce_bank, attr);
1775 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1778 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1781 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1782 const char *buf, size_t size)
1786 if (strict_strtoull(buf, 0, &new) < 0)
1789 attr_to_bank(attr)->ctl = new;
1796 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1798 strcpy(buf, mce_helper);
1800 return strlen(mce_helper) + 1;
1803 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1804 const char *buf, size_t siz)
1808 strncpy(mce_helper, buf, sizeof(mce_helper));
1809 mce_helper[sizeof(mce_helper)-1] = 0;
1810 p = strchr(mce_helper, '\n');
1815 return strlen(mce_helper) + !!p;
1818 static ssize_t set_ignore_ce(struct sys_device *s,
1819 struct sysdev_attribute *attr,
1820 const char *buf, size_t size)
1824 if (strict_strtoull(buf, 0, &new) < 0)
1827 if (mce_ignore_ce ^ !!new) {
1829 /* disable ce features */
1830 on_each_cpu(mce_disable_ce, (void *)1, 1);
1833 /* enable ce features */
1835 on_each_cpu(mce_enable_ce, (void *)1, 1);
1841 static ssize_t set_cmci_disabled(struct sys_device *s,
1842 struct sysdev_attribute *attr,
1843 const char *buf, size_t size)
1847 if (strict_strtoull(buf, 0, &new) < 0)
1850 if (mce_cmci_disabled ^ !!new) {
1853 on_each_cpu(mce_disable_ce, NULL, 1);
1854 mce_cmci_disabled = 1;
1857 mce_cmci_disabled = 0;
1858 on_each_cpu(mce_enable_ce, NULL, 1);
1864 static ssize_t store_int_with_restart(struct sys_device *s,
1865 struct sysdev_attribute *attr,
1866 const char *buf, size_t size)
1868 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1873 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1874 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1875 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1876 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1878 static struct sysdev_ext_attribute attr_check_interval = {
1879 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1880 store_int_with_restart),
1884 static struct sysdev_ext_attribute attr_ignore_ce = {
1885 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1889 static struct sysdev_ext_attribute attr_cmci_disabled = {
1890 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1894 static struct sysdev_attribute *mce_attrs[] = {
1895 &attr_tolerant.attr,
1896 &attr_check_interval.attr,
1898 &attr_monarch_timeout.attr,
1899 &attr_dont_log_ce.attr,
1900 &attr_ignore_ce.attr,
1901 &attr_cmci_disabled.attr,
1905 static cpumask_var_t mce_dev_initialized;
1907 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1908 static __cpuinit int mce_create_device(unsigned int cpu)
1913 if (!mce_available(&boot_cpu_data))
1916 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1917 per_cpu(mce_dev, cpu).id = cpu;
1918 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1920 err = sysdev_register(&per_cpu(mce_dev, cpu));
1924 for (i = 0; mce_attrs[i]; i++) {
1925 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1929 for (j = 0; j < banks; j++) {
1930 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1931 &mce_banks[j].attr);
1935 cpumask_set_cpu(cpu, mce_dev_initialized);
1940 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1943 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1945 sysdev_unregister(&per_cpu(mce_dev, cpu));
1950 static __cpuinit void mce_remove_device(unsigned int cpu)
1954 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1957 for (i = 0; mce_attrs[i]; i++)
1958 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1960 for (i = 0; i < banks; i++)
1961 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1963 sysdev_unregister(&per_cpu(mce_dev, cpu));
1964 cpumask_clear_cpu(cpu, mce_dev_initialized);
1967 /* Make sure there are no machine checks on offlined CPUs. */
1968 static void __cpuinit mce_disable_cpu(void *h)
1970 unsigned long action = *(unsigned long *)h;
1973 if (!mce_available(¤t_cpu_data))
1976 if (!(action & CPU_TASKS_FROZEN))
1978 for (i = 0; i < banks; i++) {
1979 struct mce_bank *b = &mce_banks[i];
1982 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1986 static void __cpuinit mce_reenable_cpu(void *h)
1988 unsigned long action = *(unsigned long *)h;
1991 if (!mce_available(¤t_cpu_data))
1994 if (!(action & CPU_TASKS_FROZEN))
1996 for (i = 0; i < banks; i++) {
1997 struct mce_bank *b = &mce_banks[i];
2000 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2004 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2005 static int __cpuinit
2006 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2008 unsigned int cpu = (unsigned long)hcpu;
2009 struct timer_list *t = &per_cpu(mce_timer, cpu);
2013 case CPU_ONLINE_FROZEN:
2014 mce_create_device(cpu);
2015 if (threshold_cpu_callback)
2016 threshold_cpu_callback(action, cpu);
2019 case CPU_DEAD_FROZEN:
2020 if (threshold_cpu_callback)
2021 threshold_cpu_callback(action, cpu);
2022 mce_remove_device(cpu);
2024 case CPU_DOWN_PREPARE:
2025 case CPU_DOWN_PREPARE_FROZEN:
2027 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2029 case CPU_DOWN_FAILED:
2030 case CPU_DOWN_FAILED_FROZEN:
2031 if (!mce_ignore_ce && check_interval) {
2032 t->expires = round_jiffies(jiffies +
2033 __get_cpu_var(mce_next_interval));
2034 add_timer_on(t, cpu);
2036 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2039 /* intentionally ignoring frozen here */
2040 cmci_rediscover(cpu);
2046 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2047 .notifier_call = mce_cpu_callback,
2050 static __init void mce_init_banks(void)
2054 for (i = 0; i < banks; i++) {
2055 struct mce_bank *b = &mce_banks[i];
2056 struct sysdev_attribute *a = &b->attr;
2058 sysfs_attr_init(&a->attr);
2059 a->attr.name = b->attrname;
2060 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2062 a->attr.mode = 0644;
2063 a->show = show_bank;
2064 a->store = set_bank;
2068 static __init int mcheck_init_device(void)
2073 if (!mce_available(&boot_cpu_data))
2076 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2080 err = sysdev_class_register(&mce_sysclass);
2084 for_each_online_cpu(i) {
2085 err = mce_create_device(i);
2090 register_hotcpu_notifier(&mce_cpu_notifier);
2091 misc_register(&mce_log_device);
2096 device_initcall(mcheck_init_device);
2099 * Old style boot options parsing. Only for compatibility.
2101 static int __init mcheck_disable(char *str)
2106 __setup("nomce", mcheck_disable);
2108 #ifdef CONFIG_DEBUG_FS
2109 struct dentry *mce_get_debugfs_dir(void)
2111 static struct dentry *dmce;
2114 dmce = debugfs_create_dir("mce", NULL);
2119 static void mce_reset(void)
2122 atomic_set(&mce_fake_paniced, 0);
2123 atomic_set(&mce_executing, 0);
2124 atomic_set(&mce_callin, 0);
2125 atomic_set(&global_nwo, 0);
2128 static int fake_panic_get(void *data, u64 *val)
2134 static int fake_panic_set(void *data, u64 val)
2141 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2142 fake_panic_set, "%llu\n");
2144 static int __init mcheck_debugfs_init(void)
2146 struct dentry *dmce, *ffake_panic;
2148 dmce = mce_get_debugfs_dir();
2151 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2158 late_initcall(mcheck_debugfs_init);