2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
41 #include <asm/processor.h>
42 #include <asm/hw_irq.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
101 * CPU/chipset specific EDAC code can register a notifier call here to print
102 * MCE errors in a human-readable form.
104 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
105 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
107 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
110 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
111 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
116 static struct notifier_block mce_dec_nb = {
117 .notifier_call = default_decode_mce,
121 /* MCA banks polled by the period polling timer for corrected events */
122 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
123 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
126 static DEFINE_PER_CPU(struct work_struct, mce_work);
128 /* Do initial initialization of a struct mce */
129 void mce_setup(struct mce *m)
131 memset(m, 0, sizeof(struct mce));
132 m->cpu = m->extcpu = smp_processor_id();
134 /* We hope get_seconds stays lockless */
135 m->time = get_seconds();
136 m->cpuvendor = boot_cpu_data.x86_vendor;
137 m->cpuid = cpuid_eax(1);
139 m->socketid = cpu_data(m->extcpu).phys_proc_id;
141 m->apicid = cpu_data(m->extcpu).initial_apicid;
142 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
145 DEFINE_PER_CPU(struct mce, injectm);
146 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
149 * Lockless MCE logging infrastructure.
150 * This avoids deadlocks on printk locks without having to break locks. Also
151 * separate MCEs from kernel messages to avoid bogus bug reports.
154 static struct mce_log mcelog = {
155 .signature = MCE_LOG_SIGNATURE,
157 .recordlen = sizeof(struct mce),
160 void mce_log(struct mce *mce)
162 unsigned next, entry;
164 /* Emit the trace record: */
165 trace_mce_record(mce);
170 entry = rcu_dereference_check_mce(mcelog.next);
173 * If edac_mce is enabled, it will check the error type
174 * and will process it, if it is a known error.
175 * Otherwise, the error will be sent through mcelog
178 if (edac_mce_parse(mce))
182 * When the buffer fills up discard new entries.
183 * Assume that the earlier errors are the more
186 if (entry >= MCE_LOG_LEN) {
187 set_bit(MCE_OVERFLOW,
188 (unsigned long *)&mcelog.flags);
191 /* Old left over entry. Skip: */
192 if (mcelog.entry[entry].finished) {
200 if (cmpxchg(&mcelog.next, entry, next) == entry)
203 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
205 mcelog.entry[entry].finished = 1;
209 set_bit(0, &mce_need_notify);
212 static void print_mce(struct mce *m)
214 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
215 m->extcpu, m->mcgstatus, m->bank, m->status);
218 pr_emerg("RIP%s %02x:<%016Lx> ",
219 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
222 if (m->cs == __KERNEL_CS)
223 print_symbol("{%s}", m->ip);
227 pr_emerg("TSC %llx ", m->tsc);
229 pr_cont("ADDR %llx ", m->addr);
231 pr_cont("MISC %llx ", m->misc);
234 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
235 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
238 * Print out human-readable details about the MCE error,
239 * (if the CPU has an implementation for that)
241 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
244 static void print_mce_head(void)
246 pr_emerg("\nHARDWARE ERROR\n");
249 static void print_mce_tail(void)
251 pr_emerg("This is not a software problem!\n");
254 #define PANIC_TIMEOUT 5 /* 5 seconds */
256 static atomic_t mce_paniced;
258 static int fake_panic;
259 static atomic_t mce_fake_paniced;
261 /* Panic in progress. Enable interrupts and wait for final IPI */
262 static void wait_for_panic(void)
264 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
268 while (timeout-- > 0)
270 if (panic_timeout == 0)
271 panic_timeout = mce_panic_timeout;
272 panic("Panicing machine check CPU died");
275 static void mce_panic(char *msg, struct mce *final, char *exp)
281 * Make sure only one CPU runs in machine check panic
283 if (atomic_inc_return(&mce_paniced) > 1)
290 /* Don't log too much for fake panic */
291 if (atomic_inc_return(&mce_fake_paniced) > 1)
295 /* First print corrected ones that are still unlogged */
296 for (i = 0; i < MCE_LOG_LEN; i++) {
297 struct mce *m = &mcelog.entry[i];
298 if (!(m->status & MCI_STATUS_VAL))
300 if (!(m->status & MCI_STATUS_UC)) {
303 apei_err = apei_write_mce(m);
306 /* Now print uncorrected but with the final one last */
307 for (i = 0; i < MCE_LOG_LEN; i++) {
308 struct mce *m = &mcelog.entry[i];
309 if (!(m->status & MCI_STATUS_VAL))
311 if (!(m->status & MCI_STATUS_UC))
313 if (!final || memcmp(m, final, sizeof(struct mce))) {
316 apei_err = apei_write_mce(m);
322 apei_err = apei_write_mce(final);
325 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
328 printk(KERN_EMERG "Machine check: %s\n", exp);
330 if (panic_timeout == 0)
331 panic_timeout = mce_panic_timeout;
334 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
337 /* Support code for software error injection */
339 static int msr_to_offset(u32 msr)
341 unsigned bank = __get_cpu_var(injectm.bank);
344 return offsetof(struct mce, ip);
345 if (msr == MSR_IA32_MCx_STATUS(bank))
346 return offsetof(struct mce, status);
347 if (msr == MSR_IA32_MCx_ADDR(bank))
348 return offsetof(struct mce, addr);
349 if (msr == MSR_IA32_MCx_MISC(bank))
350 return offsetof(struct mce, misc);
351 if (msr == MSR_IA32_MCG_STATUS)
352 return offsetof(struct mce, mcgstatus);
356 /* MSR access wrappers used for error injection */
357 static u64 mce_rdmsrl(u32 msr)
361 if (__get_cpu_var(injectm).finished) {
362 int offset = msr_to_offset(msr);
366 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
369 if (rdmsrl_safe(msr, &v)) {
370 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
372 * Return zero in case the access faulted. This should
373 * not happen normally but can happen if the CPU does
374 * something weird, or if the code is buggy.
382 static void mce_wrmsrl(u32 msr, u64 v)
384 if (__get_cpu_var(injectm).finished) {
385 int offset = msr_to_offset(msr);
388 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
395 * Simple lockless ring to communicate PFNs from the exception handler with the
396 * process context work function. This is vastly simplified because there's
397 * only a single reader and a single writer.
399 #define MCE_RING_SIZE 16 /* we use one entry less */
402 unsigned short start;
404 unsigned long ring[MCE_RING_SIZE];
406 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
408 /* Runs with CPU affinity in workqueue */
409 static int mce_ring_empty(void)
411 struct mce_ring *r = &__get_cpu_var(mce_ring);
413 return r->start == r->end;
416 static int mce_ring_get(unsigned long *pfn)
423 r = &__get_cpu_var(mce_ring);
424 if (r->start == r->end)
426 *pfn = r->ring[r->start];
427 r->start = (r->start + 1) % MCE_RING_SIZE;
434 /* Always runs in MCE context with preempt off */
435 static int mce_ring_add(unsigned long pfn)
437 struct mce_ring *r = &__get_cpu_var(mce_ring);
440 next = (r->end + 1) % MCE_RING_SIZE;
441 if (next == r->start)
443 r->ring[r->end] = pfn;
449 int mce_available(struct cpuinfo_x86 *c)
453 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
456 static void mce_schedule_work(void)
458 if (!mce_ring_empty()) {
459 struct work_struct *work = &__get_cpu_var(mce_work);
460 if (!work_pending(work))
466 * Get the address of the instruction at the time of the machine check
469 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
472 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
480 m->ip = mce_rdmsrl(rip_msr);
483 #ifdef CONFIG_X86_LOCAL_APIC
485 * Called after interrupts have been reenabled again
486 * when a MCE happened during an interrupts off region
489 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
502 static void mce_report_event(struct pt_regs *regs)
504 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
507 * Triggering the work queue here is just an insurance
508 * policy in case the syscall exit notify handler
509 * doesn't run soon enough or ends up running on the
510 * wrong CPU (can happen when audit sleeps)
516 #if defined(CONFIG_X86_LOCAL_APIC) && !defined(CONFIG_XEN)
518 * Without APIC do not notify. The event will be picked
525 * When interrupts are disabled we cannot use
526 * kernel services safely. Trigger an self interrupt
527 * through the APIC to instead do the notification
528 * after interrupts are reenabled again.
530 apic->send_IPI_self(MCE_SELF_VECTOR);
533 * Wait for idle afterwards again so that we don't leave the
534 * APIC in a non idle state because the normal APIC writes
537 apic_wait_icr_idle();
541 DEFINE_PER_CPU(unsigned, mce_poll_count);
544 * Poll for corrected events or events that happened before reset.
545 * Those are just logged through /dev/mcelog.
547 * This is executed in standard interrupt context.
549 * Note: spec recommends to panic for fatal unsignalled
550 * errors here. However this would be quite problematic --
551 * we would need to reimplement the Monarch handling and
552 * it would mess up the exclusion between exception handler
553 * and poll hander -- * so we skip this for now.
554 * These cases should not happen anyways, or only when the CPU
555 * is already totally * confused. In this case it's likely it will
556 * not fully execute the machine check handler either.
558 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
563 percpu_inc(mce_poll_count);
567 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
568 for (i = 0; i < banks; i++) {
569 if (!mce_banks[i].ctl || !test_bit(i, *b))
578 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
579 if (!(m.status & MCI_STATUS_VAL))
583 * Uncorrected or signalled events are handled by the exception
584 * handler when it is enabled, so don't process those here.
586 * TBD do the same check for MCI_STATUS_EN here?
588 if (!(flags & MCP_UC) &&
589 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
592 if (m.status & MCI_STATUS_MISCV)
593 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
594 if (m.status & MCI_STATUS_ADDRV)
595 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
597 if (!(flags & MCP_TIMESTAMP))
600 * Don't get the IP here because it's unlikely to
601 * have anything to do with the actual error location.
603 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
605 add_taint(TAINT_MACHINE_CHECK);
609 * Clear state for this bank.
611 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
615 * Don't clear MCG_STATUS here because it's only defined for
621 EXPORT_SYMBOL_GPL(machine_check_poll);
624 * Do a quick check if any of the events requires a panic.
625 * This decides if we keep the events around or clear them.
627 static int mce_no_way_out(struct mce *m, char **msg)
631 for (i = 0; i < banks; i++) {
632 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
633 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
640 * Variable to establish order between CPUs while scanning.
641 * Each CPU spins initially until executing is equal its number.
643 static atomic_t mce_executing;
646 * Defines order of CPUs on entry. First CPU becomes Monarch.
648 static atomic_t mce_callin;
651 * Check if a timeout waiting for other CPUs happened.
653 static int mce_timed_out(u64 *t)
656 * The others already did panic for some reason.
657 * Bail out like in a timeout.
658 * rmb() to tell the compiler that system_state
659 * might have been modified by someone else.
662 if (atomic_read(&mce_paniced))
664 if (!monarch_timeout)
666 if ((s64)*t < SPINUNIT) {
667 /* CHECKME: Make panic default for 1 too? */
669 mce_panic("Timeout synchronizing machine check over CPUs",
676 touch_nmi_watchdog();
681 * The Monarch's reign. The Monarch is the CPU who entered
682 * the machine check handler first. It waits for the others to
683 * raise the exception too and then grades them. When any
684 * error is fatal panic. Only then let the others continue.
686 * The other CPUs entering the MCE handler will be controlled by the
687 * Monarch. They are called Subjects.
689 * This way we prevent any potential data corruption in a unrecoverable case
690 * and also makes sure always all CPU's errors are examined.
692 * Also this detects the case of a machine check event coming from outer
693 * space (not detected by any CPUs) In this case some external agent wants
694 * us to shut down, so panic too.
696 * The other CPUs might still decide to panic if the handler happens
697 * in a unrecoverable place, but in this case the system is in a semi-stable
698 * state and won't corrupt anything by itself. It's ok to let the others
699 * continue for a bit first.
701 * All the spin loops have timeouts; when a timeout happens a CPU
702 * typically elects itself to be Monarch.
704 static void mce_reign(void)
707 struct mce *m = NULL;
708 int global_worst = 0;
713 * This CPU is the Monarch and the other CPUs have run
714 * through their handlers.
715 * Grade the severity of the errors of all the CPUs.
717 for_each_possible_cpu(cpu) {
718 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
720 if (severity > global_worst) {
722 global_worst = severity;
723 m = &per_cpu(mces_seen, cpu);
728 * Cannot recover? Panic here then.
729 * This dumps all the mces in the log buffer and stops the
732 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
733 mce_panic("Fatal Machine check", m, msg);
736 * For UC somewhere we let the CPU who detects it handle it.
737 * Also must let continue the others, otherwise the handling
738 * CPU could deadlock on a lock.
742 * No machine check event found. Must be some external
743 * source or one CPU is hung. Panic.
745 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
746 mce_panic("Machine check from unknown source", NULL, NULL);
749 * Now clear all the mces_seen so that they don't reappear on
752 for_each_possible_cpu(cpu)
753 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
756 static atomic_t global_nwo;
759 * Start of Monarch synchronization. This waits until all CPUs have
760 * entered the exception handler and then determines if any of them
761 * saw a fatal event that requires panic. Then it executes them
762 * in the entry order.
763 * TBD double check parallel CPU hotunplug
765 static int mce_start(int *no_way_out)
768 int cpus = num_online_cpus();
769 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
774 atomic_add(*no_way_out, &global_nwo);
776 * global_nwo should be updated before mce_callin
779 order = atomic_inc_return(&mce_callin);
784 while (atomic_read(&mce_callin) != cpus) {
785 if (mce_timed_out(&timeout)) {
786 atomic_set(&global_nwo, 0);
793 * mce_callin should be read before global_nwo
799 * Monarch: Starts executing now, the others wait.
801 atomic_set(&mce_executing, 1);
804 * Subject: Now start the scanning loop one by one in
805 * the original callin order.
806 * This way when there are any shared banks it will be
807 * only seen by one CPU before cleared, avoiding duplicates.
809 while (atomic_read(&mce_executing) < order) {
810 if (mce_timed_out(&timeout)) {
811 atomic_set(&global_nwo, 0);
819 * Cache the global no_way_out state.
821 *no_way_out = atomic_read(&global_nwo);
827 * Synchronize between CPUs after main scanning loop.
828 * This invokes the bulk of the Monarch processing.
830 static int mce_end(int order)
833 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
841 * Allow others to run.
843 atomic_inc(&mce_executing);
846 /* CHECKME: Can this race with a parallel hotplug? */
847 int cpus = num_online_cpus();
850 * Monarch: Wait for everyone to go through their scanning
853 while (atomic_read(&mce_executing) <= cpus) {
854 if (mce_timed_out(&timeout))
864 * Subject: Wait for Monarch to finish.
866 while (atomic_read(&mce_executing) != 0) {
867 if (mce_timed_out(&timeout))
873 * Don't reset anything. That's done by the Monarch.
879 * Reset all global state.
882 atomic_set(&global_nwo, 0);
883 atomic_set(&mce_callin, 0);
887 * Let others run again.
889 atomic_set(&mce_executing, 0);
894 * Check if the address reported by the CPU is in a format we can parse.
895 * It would be possible to add code for most other cases, but all would
896 * be somewhat complicated (e.g. segment offset would require an instruction
897 * parser). So only support physical addresses upto page granuality for now.
899 static int mce_usable_address(struct mce *m)
901 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
903 if ((m->misc & 0x3f) > PAGE_SHIFT)
905 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
910 static void mce_clear_state(unsigned long *toclear)
914 for (i = 0; i < banks; i++) {
915 if (test_bit(i, toclear))
916 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
921 * The actual machine check handler. This only handles real
922 * exceptions when something got corrupted coming in through int 18.
924 * This is executed in NMI context not subject to normal locking rules. This
925 * implies that most kernel services cannot be safely used. Don't even
926 * think about putting a printk in there!
928 * On Intel systems this is entered on all CPUs in parallel through
929 * MCE broadcast. However some CPUs might be broken beyond repair,
930 * so be always careful when synchronizing with others.
932 void do_machine_check(struct pt_regs *regs, long error_code)
934 struct mce m, *final;
939 * Establish sequential order between the CPUs entering the machine
944 * If no_way_out gets set, there is no safe way to recover from this
945 * MCE. If tolerant is cranked up, we'll try anyway.
949 * If kill_it gets set, there might be a way to recover from this
953 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
954 char *msg = "Unknown";
956 atomic_inc(&mce_entry);
958 percpu_inc(mce_exception_count);
960 if (notify_die(DIE_NMI, "machine check", regs, error_code,
961 18, SIGKILL) == NOTIFY_STOP)
968 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
969 final = &__get_cpu_var(mces_seen);
972 no_way_out = mce_no_way_out(&m, &msg);
977 * When no restart IP must always kill or panic.
979 if (!(m.mcgstatus & MCG_STATUS_RIPV))
983 * Go through all the banks in exclusion of the other CPUs.
984 * This way we don't report duplicated events on shared banks
985 * because the first one to see it will clear it.
987 order = mce_start(&no_way_out);
988 for (i = 0; i < banks; i++) {
989 __clear_bit(i, toclear);
990 if (!mce_banks[i].ctl)
997 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
998 if ((m.status & MCI_STATUS_VAL) == 0)
1002 * Non uncorrected or non signaled errors are handled by
1003 * machine_check_poll. Leave them alone, unless this panics.
1005 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1010 * Set taint even when machine check was not enabled.
1012 add_taint(TAINT_MACHINE_CHECK);
1014 severity = mce_severity(&m, tolerant, NULL);
1017 * When machine check was for corrected handler don't touch,
1018 * unless we're panicing.
1020 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1022 __set_bit(i, toclear);
1023 if (severity == MCE_NO_SEVERITY) {
1025 * Machine check event was not enabled. Clear, but
1032 * Kill on action required.
1034 if (severity == MCE_AR_SEVERITY)
1037 if (m.status & MCI_STATUS_MISCV)
1038 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1039 if (m.status & MCI_STATUS_ADDRV)
1040 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1043 * Action optional error. Queue address for later processing.
1044 * When the ring overflows we just ignore the AO error.
1045 * RED-PEN add some logging mechanism when
1046 * usable_address or mce_add_ring fails.
1047 * RED-PEN don't ignore overflow for tolerant == 0
1049 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1050 mce_ring_add(m.addr >> PAGE_SHIFT);
1052 mce_get_rip(&m, regs);
1055 if (severity > worst) {
1062 mce_clear_state(toclear);
1065 * Do most of the synchronization with other CPUs.
1066 * When there's any problem use only local no_way_out state.
1068 if (mce_end(order) < 0)
1069 no_way_out = worst >= MCE_PANIC_SEVERITY;
1072 * If we have decided that we just CAN'T continue, and the user
1073 * has not set tolerant to an insane level, give up and die.
1075 * This is mainly used in the case when the system doesn't
1076 * support MCE broadcasting or it has been disabled.
1078 if (no_way_out && tolerant < 3)
1079 mce_panic("Fatal machine check on current CPU", final, msg);
1082 * If the error seems to be unrecoverable, something should be
1083 * done. Try to kill as little as possible. If we can kill just
1084 * one task, do that. If the user has set the tolerance very
1085 * high, don't try to do anything at all.
1088 if (kill_it && tolerant < 3)
1089 force_sig(SIGBUS, current);
1091 /* notify userspace ASAP */
1092 set_thread_flag(TIF_MCE_NOTIFY);
1095 mce_report_event(regs);
1096 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1098 atomic_dec(&mce_entry);
1101 EXPORT_SYMBOL_GPL(do_machine_check);
1103 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1104 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1106 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1110 * Called after mce notification in process context. This code
1111 * is allowed to sleep. Call the high level VM handler to process
1112 * any corrupted pages.
1113 * Assume that the work queue code only calls this one at a time
1115 * Note we don't disable preemption, so this code might run on the wrong
1116 * CPU. In this case the event is picked up by the scheduled work queue.
1117 * This is merely a fast path to expedite processing in some common
1120 void mce_notify_process(void)
1124 while (mce_ring_get(&pfn))
1125 memory_failure(pfn, MCE_VECTOR);
1128 static void mce_process_work(struct work_struct *dummy)
1130 mce_notify_process();
1133 #ifdef CONFIG_X86_MCE_INTEL
1135 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1136 * @cpu: The CPU on which the event occurred.
1137 * @status: Event status information
1139 * This function should be called by the thermal interrupt after the
1140 * event has been processed and the decision was made to log the event
1143 * The status parameter will be saved to the 'status' field of 'struct mce'
1144 * and historically has been the register value of the
1145 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1147 void mce_log_therm_throt_event(__u64 status)
1152 m.bank = MCE_THERMAL_BANK;
1156 #endif /* CONFIG_X86_MCE_INTEL */
1159 * Periodic polling timer for "silent" machine check errors. If the
1160 * poller finds an MCE, poll 2x faster. When the poller finds no more
1161 * errors, poll 2x slower (up to check_interval seconds).
1163 * We will disable polling in DOM0 since all CMCI/Polling
1164 * mechanism will be done in XEN for Intel CPUs
1166 #if defined (CONFIG_X86_XEN_MCE)
1167 static int check_interval = 0; /* disable polling */
1169 static int check_interval = 5 * 60; /* 5 minutes */
1172 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1173 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1175 static void mce_start_timer(unsigned long data)
1177 struct timer_list *t = &per_cpu(mce_timer, data);
1180 WARN_ON(smp_processor_id() != data);
1182 if (mce_available(¤t_cpu_data)) {
1183 machine_check_poll(MCP_TIMESTAMP,
1184 &__get_cpu_var(mce_poll_banks));
1188 * Alert userspace if needed. If we logged an MCE, reduce the
1189 * polling interval, otherwise increase the polling interval.
1191 n = &__get_cpu_var(mce_next_interval);
1192 if (mce_notify_irq())
1193 *n = max(*n/2, HZ/100);
1195 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1197 t->expires = jiffies + *n;
1198 add_timer_on(t, smp_processor_id());
1201 static void mce_do_trigger(struct work_struct *work)
1203 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1206 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1209 * Notify the user(s) about new machine check events.
1210 * Can be called from interrupt context, but not from machine check/NMI
1213 int mce_notify_irq(void)
1215 /* Not more than two messages every minute */
1216 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1218 clear_thread_flag(TIF_MCE_NOTIFY);
1220 if (test_and_clear_bit(0, &mce_need_notify)) {
1221 wake_up_interruptible(&mce_wait);
1224 * There is no risk of missing notifications because
1225 * work_pending is always cleared before the function is
1228 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1229 schedule_work(&mce_trigger_work);
1231 if (__ratelimit(&ratelimit))
1232 printk(KERN_INFO "Machine check events logged\n");
1238 EXPORT_SYMBOL_GPL(mce_notify_irq);
1240 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1244 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1247 for (i = 0; i < banks; i++) {
1248 struct mce_bank *b = &mce_banks[i];
1257 * Initialize Machine Checks for a CPU.
1259 static int __cpuinit __mcheck_cpu_cap_init(void)
1264 rdmsrl(MSR_IA32_MCG_CAP, cap);
1266 b = cap & MCG_BANKCNT_MASK;
1268 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1270 if (b > MAX_NR_BANKS) {
1272 "MCE: Using only %u machine check banks out of %u\n",
1277 /* Don't support asymmetric configurations today */
1278 WARN_ON(banks != 0 && b != banks);
1281 int err = __mcheck_cpu_mce_banks_init();
1287 /* Use accurate RIP reporting if available. */
1288 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1289 rip_msr = MSR_IA32_MCG_EIP;
1291 if (cap & MCG_SER_P)
1297 static void __mcheck_cpu_init_generic(void)
1299 mce_banks_t all_banks;
1304 * Log the machine checks left over from the previous reset.
1306 bitmap_fill(all_banks, MAX_NR_BANKS);
1307 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1309 set_in_cr4(X86_CR4_MCE);
1311 rdmsrl(MSR_IA32_MCG_CAP, cap);
1312 if (cap & MCG_CTL_P)
1313 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1315 for (i = 0; i < banks; i++) {
1316 struct mce_bank *b = &mce_banks[i];
1320 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1321 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1325 /* Add per CPU specific workarounds here */
1326 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1328 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1329 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1333 /* This should be disabled by the BIOS, but isn't always */
1334 if (c->x86_vendor == X86_VENDOR_AMD) {
1336 if (c->x86 == 15 && banks > 4) {
1338 * disable GART TBL walk error reporting, which
1339 * trips off incorrectly with the IOMMU & 3ware
1342 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1345 if (c->x86 <= 17 && mce_bootlog < 0) {
1347 * Lots of broken BIOS around that don't clear them
1348 * by default and leave crap in there. Don't log:
1353 * Various K7s with broken bank 0 around. Always disable
1356 if (c->x86 == 6 && banks > 0)
1357 mce_banks[0].ctl = 0;
1360 if (c->x86_vendor == X86_VENDOR_INTEL) {
1362 * SDM documents that on family 6 bank 0 should not be written
1363 * because it aliases to another special BIOS controlled
1365 * But it's not aliased anymore on model 0x1a+
1366 * Don't ignore bank 0 completely because there could be a
1367 * valid event later, merely don't write CTL0.
1370 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1371 mce_banks[0].init = 0;
1374 * All newer Intel systems support MCE broadcasting. Enable
1375 * synchronization with a one second timeout.
1377 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1378 monarch_timeout < 0)
1379 monarch_timeout = USEC_PER_SEC;
1382 * There are also broken BIOSes on some Pentium M and
1385 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1388 if (monarch_timeout < 0)
1389 monarch_timeout = 0;
1390 if (mce_bootlog != 0)
1391 mce_panic_timeout = 30;
1396 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1400 switch (c->x86_vendor) {
1401 case X86_VENDOR_INTEL:
1402 intel_p5_mcheck_init(c);
1404 case X86_VENDOR_CENTAUR:
1405 winchip_mcheck_init(c);
1410 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1412 #ifndef CONFIG_X86_64_XEN
1413 switch (c->x86_vendor) {
1414 case X86_VENDOR_INTEL:
1415 mce_intel_feature_init(c);
1417 case X86_VENDOR_AMD:
1418 mce_amd_feature_init(c);
1426 static void __mcheck_cpu_init_timer(void)
1428 struct timer_list *t = &__get_cpu_var(mce_timer);
1429 int *n = &__get_cpu_var(mce_next_interval);
1431 setup_timer(t, mce_start_timer, smp_processor_id());
1436 *n = check_interval * HZ;
1439 t->expires = round_jiffies(jiffies + *n);
1440 add_timer_on(t, smp_processor_id());
1443 /* Handle unconfigured int18 (should never happen) */
1444 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1446 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1447 smp_processor_id());
1450 /* Call the installed machine check handler for this CPU setup. */
1451 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1452 unexpected_machine_check;
1455 * Called for each booted CPU to set up machine checks.
1456 * Must be called with preempt off:
1458 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1463 __mcheck_cpu_ancient_init(c);
1465 if (!mce_available(c))
1468 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1473 machine_check_vector = do_machine_check;
1475 __mcheck_cpu_init_generic();
1476 __mcheck_cpu_init_vendor(c);
1477 __mcheck_cpu_init_timer();
1478 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1483 * Character device to read and clear the MCE log.
1486 static DEFINE_SPINLOCK(mce_state_lock);
1487 static int open_count; /* #times opened */
1488 static int open_exclu; /* already open exclusive? */
1490 static int mce_open(struct inode *inode, struct file *file)
1492 spin_lock(&mce_state_lock);
1494 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1495 spin_unlock(&mce_state_lock);
1500 if (file->f_flags & O_EXCL)
1504 spin_unlock(&mce_state_lock);
1506 return nonseekable_open(inode, file);
1509 static int mce_release(struct inode *inode, struct file *file)
1511 spin_lock(&mce_state_lock);
1516 spin_unlock(&mce_state_lock);
1521 static void collect_tscs(void *data)
1523 unsigned long *cpu_tsc = (unsigned long *)data;
1525 rdtscll(cpu_tsc[smp_processor_id()]);
1528 static int mce_apei_read_done;
1530 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1531 static int __mce_read_apei(char __user **ubuf, size_t usize)
1537 if (usize < sizeof(struct mce))
1540 rc = apei_read_mce(&m, &record_id);
1541 /* Error or no more MCE record */
1543 mce_apei_read_done = 1;
1547 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1550 * In fact, we should have cleared the record after that has
1551 * been flushed to the disk or sent to network in
1552 * /sbin/mcelog, but we have no interface to support that now,
1553 * so just clear it to avoid duplication.
1555 rc = apei_clear_mce(record_id);
1557 mce_apei_read_done = 1;
1560 *ubuf += sizeof(struct mce);
1565 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1568 char __user *buf = ubuf;
1569 unsigned long *cpu_tsc;
1570 unsigned prev, next;
1573 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1577 mutex_lock(&mce_read_mutex);
1579 if (!mce_apei_read_done) {
1580 err = __mce_read_apei(&buf, usize);
1581 if (err || buf != ubuf)
1585 next = rcu_dereference_check_mce(mcelog.next);
1587 /* Only supports full reads right now */
1589 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1595 for (i = prev; i < next; i++) {
1596 unsigned long start = jiffies;
1598 while (!mcelog.entry[i].finished) {
1599 if (time_after_eq(jiffies, start + 2)) {
1600 memset(mcelog.entry + i, 0,
1601 sizeof(struct mce));
1607 err |= copy_to_user(buf, mcelog.entry + i,
1608 sizeof(struct mce));
1609 buf += sizeof(struct mce);
1614 memset(mcelog.entry + prev, 0,
1615 (next - prev) * sizeof(struct mce));
1617 next = cmpxchg(&mcelog.next, prev, 0);
1618 } while (next != prev);
1620 synchronize_sched();
1623 * Collect entries that were still getting written before the
1626 on_each_cpu(collect_tscs, cpu_tsc, 1);
1628 for (i = next; i < MCE_LOG_LEN; i++) {
1629 if (mcelog.entry[i].finished &&
1630 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1631 err |= copy_to_user(buf, mcelog.entry+i,
1632 sizeof(struct mce));
1634 buf += sizeof(struct mce);
1635 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1643 mutex_unlock(&mce_read_mutex);
1646 return err ? err : buf - ubuf;
1649 static unsigned int mce_poll(struct file *file, poll_table *wait)
1651 poll_wait(file, &mce_wait, wait);
1652 if (rcu_dereference_check_mce(mcelog.next))
1653 return POLLIN | POLLRDNORM;
1654 if (!mce_apei_read_done && apei_check_mce())
1655 return POLLIN | POLLRDNORM;
1659 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1661 int __user *p = (int __user *)arg;
1663 if (!capable(CAP_SYS_ADMIN))
1667 case MCE_GET_RECORD_LEN:
1668 return put_user(sizeof(struct mce), p);
1669 case MCE_GET_LOG_LEN:
1670 return put_user(MCE_LOG_LEN, p);
1671 case MCE_GETCLEAR_FLAGS: {
1675 flags = mcelog.flags;
1676 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1678 return put_user(flags, p);
1685 /* Modified in mce-inject.c, so not static or const */
1686 struct file_operations mce_chrdev_ops = {
1688 .release = mce_release,
1691 .unlocked_ioctl = mce_ioctl,
1693 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1695 static struct miscdevice mce_log_device = {
1702 * mce=off Disables machine check
1703 * mce=no_cmci Disables CMCI
1704 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1705 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1706 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1707 * monarchtimeout is how long to wait for other CPUs on machine
1708 * check, or 0 to not wait
1709 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1710 * mce=nobootlog Don't log MCEs from before booting.
1712 static int __init mcheck_enable(char *str)
1720 if (!strcmp(str, "off"))
1722 else if (!strcmp(str, "no_cmci"))
1723 mce_cmci_disabled = 1;
1724 else if (!strcmp(str, "dont_log_ce"))
1725 mce_dont_log_ce = 1;
1726 else if (!strcmp(str, "ignore_ce"))
1728 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1729 mce_bootlog = (str[0] == 'b');
1730 else if (isdigit(str[0])) {
1731 get_option(&str, &tolerant);
1734 get_option(&str, &monarch_timeout);
1737 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1743 __setup("mce", mcheck_enable);
1745 int __init mcheck_init(void)
1747 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1749 mcheck_intel_therm_init();
1759 * Disable machine checks on suspend and shutdown. We can't really handle
1762 static int mce_disable_error_reporting(void)
1766 for (i = 0; i < banks; i++) {
1767 struct mce_bank *b = &mce_banks[i];
1770 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1775 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1777 return mce_disable_error_reporting();
1780 static int mce_shutdown(struct sys_device *dev)
1782 return mce_disable_error_reporting();
1786 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1787 * Only one CPU is active at this time, the others get re-added later using
1790 static int mce_resume(struct sys_device *dev)
1792 __mcheck_cpu_init_generic();
1793 __mcheck_cpu_init_vendor(¤t_cpu_data);
1798 static void mce_cpu_restart(void *data)
1800 del_timer_sync(&__get_cpu_var(mce_timer));
1801 if (!mce_available(¤t_cpu_data))
1803 __mcheck_cpu_init_generic();
1804 __mcheck_cpu_init_timer();
1807 /* Reinit MCEs after user configuration changes */
1808 static void mce_restart(void)
1810 on_each_cpu(mce_cpu_restart, NULL, 1);
1813 /* Toggle features for corrected errors */
1814 static void mce_disable_ce(void *all)
1816 if (!mce_available(¤t_cpu_data))
1819 del_timer_sync(&__get_cpu_var(mce_timer));
1823 static void mce_enable_ce(void *all)
1825 if (!mce_available(¤t_cpu_data))
1830 __mcheck_cpu_init_timer();
1833 static struct sysdev_class mce_sysclass = {
1834 .suspend = mce_suspend,
1835 .shutdown = mce_shutdown,
1836 .resume = mce_resume,
1837 .name = "machinecheck",
1840 DEFINE_PER_CPU(struct sys_device, mce_dev);
1843 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1845 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1847 return container_of(attr, struct mce_bank, attr);
1850 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1853 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1856 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1857 const char *buf, size_t size)
1861 if (strict_strtoull(buf, 0, &new) < 0)
1864 attr_to_bank(attr)->ctl = new;
1871 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1873 strcpy(buf, mce_helper);
1875 return strlen(mce_helper) + 1;
1878 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1879 const char *buf, size_t siz)
1883 strncpy(mce_helper, buf, sizeof(mce_helper));
1884 mce_helper[sizeof(mce_helper)-1] = 0;
1885 p = strchr(mce_helper, '\n');
1890 return strlen(mce_helper) + !!p;
1893 static ssize_t set_ignore_ce(struct sys_device *s,
1894 struct sysdev_attribute *attr,
1895 const char *buf, size_t size)
1899 if (strict_strtoull(buf, 0, &new) < 0)
1902 if (mce_ignore_ce ^ !!new) {
1904 /* disable ce features */
1905 on_each_cpu(mce_disable_ce, (void *)1, 1);
1908 /* enable ce features */
1910 on_each_cpu(mce_enable_ce, (void *)1, 1);
1916 static ssize_t set_cmci_disabled(struct sys_device *s,
1917 struct sysdev_attribute *attr,
1918 const char *buf, size_t size)
1922 if (strict_strtoull(buf, 0, &new) < 0)
1925 if (mce_cmci_disabled ^ !!new) {
1928 on_each_cpu(mce_disable_ce, NULL, 1);
1929 mce_cmci_disabled = 1;
1932 mce_cmci_disabled = 0;
1933 on_each_cpu(mce_enable_ce, NULL, 1);
1939 static ssize_t store_int_with_restart(struct sys_device *s,
1940 struct sysdev_attribute *attr,
1941 const char *buf, size_t size)
1943 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1948 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1949 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1950 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1951 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1953 static struct sysdev_ext_attribute attr_check_interval = {
1954 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1955 store_int_with_restart),
1959 static struct sysdev_ext_attribute attr_ignore_ce = {
1960 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1964 static struct sysdev_ext_attribute attr_cmci_disabled = {
1965 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1969 static struct sysdev_attribute *mce_attrs[] = {
1970 &attr_tolerant.attr,
1971 &attr_check_interval.attr,
1973 &attr_monarch_timeout.attr,
1974 &attr_dont_log_ce.attr,
1975 &attr_ignore_ce.attr,
1976 &attr_cmci_disabled.attr,
1980 static cpumask_var_t mce_dev_initialized;
1982 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1983 static __cpuinit int mce_create_device(unsigned int cpu)
1988 if (!mce_available(&boot_cpu_data))
1991 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1992 per_cpu(mce_dev, cpu).id = cpu;
1993 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1995 err = sysdev_register(&per_cpu(mce_dev, cpu));
1999 for (i = 0; mce_attrs[i]; i++) {
2000 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2004 for (j = 0; j < banks; j++) {
2005 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
2006 &mce_banks[j].attr);
2010 cpumask_set_cpu(cpu, mce_dev_initialized);
2015 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
2018 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2020 sysdev_unregister(&per_cpu(mce_dev, cpu));
2025 static __cpuinit void mce_remove_device(unsigned int cpu)
2029 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2032 for (i = 0; mce_attrs[i]; i++)
2033 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2035 for (i = 0; i < banks; i++)
2036 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2038 sysdev_unregister(&per_cpu(mce_dev, cpu));
2039 cpumask_clear_cpu(cpu, mce_dev_initialized);
2042 /* Make sure there are no machine checks on offlined CPUs. */
2043 static void __cpuinit mce_disable_cpu(void *h)
2045 unsigned long action = *(unsigned long *)h;
2048 if (!mce_available(¤t_cpu_data))
2051 if (!(action & CPU_TASKS_FROZEN))
2053 for (i = 0; i < banks; i++) {
2054 struct mce_bank *b = &mce_banks[i];
2057 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2061 static void __cpuinit mce_reenable_cpu(void *h)
2063 unsigned long action = *(unsigned long *)h;
2066 if (!mce_available(¤t_cpu_data))
2069 if (!(action & CPU_TASKS_FROZEN))
2071 for (i = 0; i < banks; i++) {
2072 struct mce_bank *b = &mce_banks[i];
2075 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2079 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2080 static int __cpuinit
2081 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2083 unsigned int cpu = (unsigned long)hcpu;
2084 struct timer_list *t = &per_cpu(mce_timer, cpu);
2088 case CPU_ONLINE_FROZEN:
2089 mce_create_device(cpu);
2090 if (threshold_cpu_callback)
2091 threshold_cpu_callback(action, cpu);
2094 case CPU_DEAD_FROZEN:
2095 if (threshold_cpu_callback)
2096 threshold_cpu_callback(action, cpu);
2097 mce_remove_device(cpu);
2099 case CPU_DOWN_PREPARE:
2100 case CPU_DOWN_PREPARE_FROZEN:
2102 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2104 case CPU_DOWN_FAILED:
2105 case CPU_DOWN_FAILED_FROZEN:
2106 if (!mce_ignore_ce && check_interval) {
2107 t->expires = round_jiffies(jiffies +
2108 __get_cpu_var(mce_next_interval));
2109 add_timer_on(t, cpu);
2111 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2114 /* intentionally ignoring frozen here */
2115 cmci_rediscover(cpu);
2121 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2122 .notifier_call = mce_cpu_callback,
2125 static __init void mce_init_banks(void)
2129 for (i = 0; i < banks; i++) {
2130 struct mce_bank *b = &mce_banks[i];
2131 struct sysdev_attribute *a = &b->attr;
2133 sysfs_attr_init(&a->attr);
2134 a->attr.name = b->attrname;
2135 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2137 a->attr.mode = 0644;
2138 a->show = show_bank;
2139 a->store = set_bank;
2143 static __init int mcheck_init_device(void)
2148 if (!mce_available(&boot_cpu_data))
2151 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2155 err = sysdev_class_register(&mce_sysclass);
2159 for_each_online_cpu(i) {
2160 err = mce_create_device(i);
2165 register_hotcpu_notifier(&mce_cpu_notifier);
2166 misc_register(&mce_log_device);
2168 #ifdef CONFIG_X86_XEN_MCE
2169 if (is_initial_xendomain()) {
2170 /* Register vIRQ handler for MCE LOG processing */
2171 extern int bind_virq_for_mce(void);
2173 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2174 bind_virq_for_mce();
2181 device_initcall(mcheck_init_device);
2184 * Old style boot options parsing. Only for compatibility.
2186 static int __init mcheck_disable(char *str)
2191 __setup("nomce", mcheck_disable);
2193 #ifdef CONFIG_DEBUG_FS
2194 struct dentry *mce_get_debugfs_dir(void)
2196 static struct dentry *dmce;
2199 dmce = debugfs_create_dir("mce", NULL);
2204 static void mce_reset(void)
2207 atomic_set(&mce_fake_paniced, 0);
2208 atomic_set(&mce_executing, 0);
2209 atomic_set(&mce_callin, 0);
2210 atomic_set(&global_nwo, 0);
2213 static int fake_panic_get(void *data, u64 *val)
2219 static int fake_panic_set(void *data, u64 val)
2226 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2227 fake_panic_set, "%llu\n");
2229 static int __init mcheck_debugfs_init(void)
2231 struct dentry *dmce, *ffake_panic;
2233 dmce = mce_get_debugfs_dir();
2236 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2243 late_initcall(mcheck_debugfs_init);