2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
41 #include <asm/processor.h>
42 #include <asm/hw_irq.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
99 void (*mce_cpu_specific_poll)(struct mce *);
100 EXPORT_SYMBOL_GPL(mce_cpu_specific_poll);
103 * CPU/chipset specific EDAC code can register a notifier call here to print
104 * MCE errors in a human-readable form.
106 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
107 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
109 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
112 pr_emerg(HW_ERR "No human readable MCE decoding support on this CPU type.\n");
113 pr_emerg(HW_ERR "Run the message through 'mcelog --ascii' to decode.\n");
118 static struct notifier_block mce_dec_nb = {
119 .notifier_call = default_decode_mce,
123 /* MCA banks polled by the period polling timer for corrected events */
124 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
125 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
128 static DEFINE_PER_CPU(struct work_struct, mce_work);
130 /* Do initial initialization of a struct mce */
131 void mce_setup(struct mce *m)
133 memset(m, 0, sizeof(struct mce));
134 m->cpu = m->extcpu = smp_processor_id();
136 /* We hope get_seconds stays lockless */
137 m->time = get_seconds();
138 m->cpuvendor = boot_cpu_data.x86_vendor;
139 m->cpuid = cpuid_eax(1);
142 m->socketid = cpu_data(m->extcpu).phys_proc_id;
144 m->apicid = cpu_data(m->extcpu).initial_apicid;
146 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
149 DEFINE_PER_CPU(struct mce, injectm);
150 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
153 * Lockless MCE logging infrastructure.
154 * This avoids deadlocks on printk locks without having to break locks. Also
155 * separate MCEs from kernel messages to avoid bogus bug reports.
158 static struct mce_log mcelog = {
159 .signature = MCE_LOG_SIGNATURE,
161 .recordlen = sizeof(struct mce),
164 void mce_log(struct mce *mce)
166 unsigned next, entry;
168 /* Emit the trace record: */
169 trace_mce_record(mce);
174 entry = rcu_dereference_check_mce(mcelog.next);
177 * If edac_mce is enabled, it will check the error type
178 * and will process it, if it is a known error.
179 * Otherwise, the error will be sent through mcelog
182 if (edac_mce_parse(mce))
186 * When the buffer fills up discard new entries.
187 * Assume that the earlier errors are the more
190 if (entry >= MCE_LOG_LEN) {
191 set_bit(MCE_OVERFLOW,
192 (unsigned long *)&mcelog.flags);
195 /* Old left over entry. Skip: */
196 if (mcelog.entry[entry].finished) {
204 if (cmpxchg(&mcelog.next, entry, next) == entry)
207 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
209 mcelog.entry[entry].finished = 1;
213 set_bit(0, &mce_need_notify);
216 static void print_mce(struct mce *m)
218 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
219 m->extcpu, m->mcgstatus, m->bank, m->status);
222 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
223 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
226 if (m->cs == __KERNEL_CS)
227 print_symbol("{%s}", m->ip);
231 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
233 pr_cont("ADDR %llx ", m->addr);
235 pr_cont("MISC %llx ", m->misc);
238 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
239 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
242 * Print out human-readable details about the MCE error,
243 * (if the CPU has an implementation for that)
245 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
248 #define PANIC_TIMEOUT 5 /* 5 seconds */
250 static atomic_t mce_paniced;
252 static int fake_panic;
253 static atomic_t mce_fake_paniced;
255 /* Panic in progress. Enable interrupts and wait for final IPI */
256 static void wait_for_panic(void)
258 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
262 while (timeout-- > 0)
264 if (panic_timeout == 0)
265 panic_timeout = mce_panic_timeout;
266 panic("Panicing machine check CPU died");
269 static void mce_panic(char *msg, struct mce *final, char *exp)
275 * Make sure only one CPU runs in machine check panic
277 if (atomic_inc_return(&mce_paniced) > 1)
284 /* Don't log too much for fake panic */
285 if (atomic_inc_return(&mce_fake_paniced) > 1)
288 /* First print corrected ones that are still unlogged */
289 for (i = 0; i < MCE_LOG_LEN; i++) {
290 struct mce *m = &mcelog.entry[i];
291 if (!(m->status & MCI_STATUS_VAL))
293 if (!(m->status & MCI_STATUS_UC)) {
296 apei_err = apei_write_mce(m);
299 /* Now print uncorrected but with the final one last */
300 for (i = 0; i < MCE_LOG_LEN; i++) {
301 struct mce *m = &mcelog.entry[i];
302 if (!(m->status & MCI_STATUS_VAL))
304 if (!(m->status & MCI_STATUS_UC))
306 if (!final || memcmp(m, final, sizeof(struct mce))) {
309 apei_err = apei_write_mce(m);
315 apei_err = apei_write_mce(final);
318 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
320 pr_emerg(HW_ERR "Machine check: %s\n", exp);
322 if (panic_timeout == 0)
323 panic_timeout = mce_panic_timeout;
326 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
329 /* Support code for software error injection */
331 static int msr_to_offset(u32 msr)
333 unsigned bank = __get_cpu_var(injectm.bank);
336 return offsetof(struct mce, ip);
337 if (msr == MSR_IA32_MCx_STATUS(bank))
338 return offsetof(struct mce, status);
339 if (msr == MSR_IA32_MCx_ADDR(bank))
340 return offsetof(struct mce, addr);
341 if (msr == MSR_IA32_MCx_MISC(bank))
342 return offsetof(struct mce, misc);
343 if (msr == MSR_IA32_MCG_STATUS)
344 return offsetof(struct mce, mcgstatus);
348 /* MSR access wrappers used for error injection */
349 static u64 mce_rdmsrl(u32 msr)
353 if (__get_cpu_var(injectm).finished) {
354 int offset = msr_to_offset(msr);
358 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
361 if (rdmsrl_safe(msr, &v)) {
362 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
364 * Return zero in case the access faulted. This should
365 * not happen normally but can happen if the CPU does
366 * something weird, or if the code is buggy.
374 static void mce_wrmsrl(u32 msr, u64 v)
376 if (__get_cpu_var(injectm).finished) {
377 int offset = msr_to_offset(msr);
380 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
386 static int under_injection(void)
388 return __get_cpu_var(injectm).finished;
392 * Simple lockless ring to communicate PFNs from the exception handler with the
393 * process context work function. This is vastly simplified because there's
394 * only a single reader and a single writer.
396 #define MCE_RING_SIZE 16 /* we use one entry less */
399 unsigned short start;
401 unsigned long ring[MCE_RING_SIZE];
403 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
405 /* Runs with CPU affinity in workqueue */
406 static int mce_ring_empty(void)
408 struct mce_ring *r = &__get_cpu_var(mce_ring);
410 return r->start == r->end;
413 static int mce_ring_get(unsigned long *pfn)
420 r = &__get_cpu_var(mce_ring);
421 if (r->start == r->end)
423 *pfn = r->ring[r->start];
424 r->start = (r->start + 1) % MCE_RING_SIZE;
431 /* Always runs in MCE context with preempt off */
432 static int mce_ring_add(unsigned long pfn)
434 struct mce_ring *r = &__get_cpu_var(mce_ring);
437 next = (r->end + 1) % MCE_RING_SIZE;
438 if (next == r->start)
440 r->ring[r->end] = pfn;
446 int mce_available(struct cpuinfo_x86 *c)
450 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
453 static void mce_schedule_work(void)
455 if (!mce_ring_empty()) {
456 struct work_struct *work = &__get_cpu_var(mce_work);
457 if (!work_pending(work))
463 * Get the address of the instruction at the time of the machine check
466 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
469 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
477 m->ip = mce_rdmsrl(rip_msr);
480 #ifdef CONFIG_X86_LOCAL_APIC
482 * Called after interrupts have been reenabled again
483 * when a MCE happened during an interrupts off region
486 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
499 static void mce_report_event(struct pt_regs *regs)
501 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
504 * Triggering the work queue here is just an insurance
505 * policy in case the syscall exit notify handler
506 * doesn't run soon enough or ends up running on the
507 * wrong CPU (can happen when audit sleeps)
513 #if defined(CONFIG_X86_LOCAL_APIC) && !defined(CONFIG_XEN)
515 * Without APIC do not notify. The event will be picked
522 * When interrupts are disabled we cannot use
523 * kernel services safely. Trigger an self interrupt
524 * through the APIC to instead do the notification
525 * after interrupts are reenabled again.
527 apic->send_IPI_self(MCE_SELF_VECTOR);
530 * Wait for idle afterwards again so that we don't leave the
531 * APIC in a non idle state because the normal APIC writes
534 apic_wait_icr_idle();
538 DEFINE_PER_CPU(unsigned, mce_poll_count);
541 * Poll for corrected events or events that happened before reset.
542 * Those are just logged through /dev/mcelog.
544 * This is executed in standard interrupt context.
546 * Note: spec recommends to panic for fatal unsignalled
547 * errors here. However this would be quite problematic --
548 * we would need to reimplement the Monarch handling and
549 * it would mess up the exclusion between exception handler
550 * and poll hander -- * so we skip this for now.
551 * These cases should not happen anyways, or only when the CPU
552 * is already totally * confused. In this case it's likely it will
553 * not fully execute the machine check handler either.
555 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
560 percpu_inc(mce_poll_count);
564 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
565 for (i = 0; i < banks; i++) {
566 if (!mce_banks[i].ctl || !test_bit(i, *b))
575 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
576 if (!(m.status & MCI_STATUS_VAL))
580 * Uncorrected or signalled events are handled by the exception
581 * handler when it is enabled, so don't process those here.
583 * TBD do the same check for MCI_STATUS_EN here?
585 if (!(flags & MCP_UC) &&
586 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
589 if (m.status & MCI_STATUS_MISCV)
590 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
591 if (m.status & MCI_STATUS_ADDRV)
592 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
594 if (!(flags & MCP_TIMESTAMP))
597 if (mce_cpu_specific_poll && !under_injection() && !mce_dont_log_ce)
598 mce_cpu_specific_poll(&m);
601 * Don't get the IP here because it's unlikely to
602 * have anything to do with the actual error location.
604 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
606 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
607 add_taint(TAINT_MACHINE_CHECK);
611 * Clear state for this bank.
613 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
617 * Don't clear MCG_STATUS here because it's only defined for
623 EXPORT_SYMBOL_GPL(machine_check_poll);
626 * Do a quick check if any of the events requires a panic.
627 * This decides if we keep the events around or clear them.
629 static int mce_no_way_out(struct mce *m, char **msg)
633 for (i = 0; i < banks; i++) {
634 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
635 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
642 * Variable to establish order between CPUs while scanning.
643 * Each CPU spins initially until executing is equal its number.
645 static atomic_t mce_executing;
648 * Defines order of CPUs on entry. First CPU becomes Monarch.
650 static atomic_t mce_callin;
653 * Check if a timeout waiting for other CPUs happened.
655 static int mce_timed_out(u64 *t)
658 * The others already did panic for some reason.
659 * Bail out like in a timeout.
660 * rmb() to tell the compiler that system_state
661 * might have been modified by someone else.
664 if (atomic_read(&mce_paniced))
666 if (!monarch_timeout)
668 if ((s64)*t < SPINUNIT) {
669 /* CHECKME: Make panic default for 1 too? */
671 mce_panic("Timeout synchronizing machine check over CPUs",
678 touch_nmi_watchdog();
683 * The Monarch's reign. The Monarch is the CPU who entered
684 * the machine check handler first. It waits for the others to
685 * raise the exception too and then grades them. When any
686 * error is fatal panic. Only then let the others continue.
688 * The other CPUs entering the MCE handler will be controlled by the
689 * Monarch. They are called Subjects.
691 * This way we prevent any potential data corruption in a unrecoverable case
692 * and also makes sure always all CPU's errors are examined.
694 * Also this detects the case of a machine check event coming from outer
695 * space (not detected by any CPUs) In this case some external agent wants
696 * us to shut down, so panic too.
698 * The other CPUs might still decide to panic if the handler happens
699 * in a unrecoverable place, but in this case the system is in a semi-stable
700 * state and won't corrupt anything by itself. It's ok to let the others
701 * continue for a bit first.
703 * All the spin loops have timeouts; when a timeout happens a CPU
704 * typically elects itself to be Monarch.
706 static void mce_reign(void)
709 struct mce *m = NULL;
710 int global_worst = 0;
715 * This CPU is the Monarch and the other CPUs have run
716 * through their handlers.
717 * Grade the severity of the errors of all the CPUs.
719 for_each_possible_cpu(cpu) {
720 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
722 if (severity > global_worst) {
724 global_worst = severity;
725 m = &per_cpu(mces_seen, cpu);
730 * Cannot recover? Panic here then.
731 * This dumps all the mces in the log buffer and stops the
734 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
735 mce_panic("Fatal Machine check", m, msg);
738 * For UC somewhere we let the CPU who detects it handle it.
739 * Also must let continue the others, otherwise the handling
740 * CPU could deadlock on a lock.
744 * No machine check event found. Must be some external
745 * source or one CPU is hung. Panic.
747 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
748 mce_panic("Machine check from unknown source", NULL, NULL);
751 * Now clear all the mces_seen so that they don't reappear on
754 for_each_possible_cpu(cpu)
755 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
758 static atomic_t global_nwo;
761 * Start of Monarch synchronization. This waits until all CPUs have
762 * entered the exception handler and then determines if any of them
763 * saw a fatal event that requires panic. Then it executes them
764 * in the entry order.
765 * TBD double check parallel CPU hotunplug
767 static int mce_start(int *no_way_out)
770 int cpus = num_online_cpus();
771 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
776 atomic_add(*no_way_out, &global_nwo);
778 * global_nwo should be updated before mce_callin
781 order = atomic_inc_return(&mce_callin);
786 while (atomic_read(&mce_callin) != cpus) {
787 if (mce_timed_out(&timeout)) {
788 atomic_set(&global_nwo, 0);
795 * mce_callin should be read before global_nwo
801 * Monarch: Starts executing now, the others wait.
803 atomic_set(&mce_executing, 1);
806 * Subject: Now start the scanning loop one by one in
807 * the original callin order.
808 * This way when there are any shared banks it will be
809 * only seen by one CPU before cleared, avoiding duplicates.
811 while (atomic_read(&mce_executing) < order) {
812 if (mce_timed_out(&timeout)) {
813 atomic_set(&global_nwo, 0);
821 * Cache the global no_way_out state.
823 *no_way_out = atomic_read(&global_nwo);
829 * Synchronize between CPUs after main scanning loop.
830 * This invokes the bulk of the Monarch processing.
832 static int mce_end(int order)
835 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
843 * Allow others to run.
845 atomic_inc(&mce_executing);
848 /* CHECKME: Can this race with a parallel hotplug? */
849 int cpus = num_online_cpus();
852 * Monarch: Wait for everyone to go through their scanning
855 while (atomic_read(&mce_executing) <= cpus) {
856 if (mce_timed_out(&timeout))
866 * Subject: Wait for Monarch to finish.
868 while (atomic_read(&mce_executing) != 0) {
869 if (mce_timed_out(&timeout))
875 * Don't reset anything. That's done by the Monarch.
881 * Reset all global state.
884 atomic_set(&global_nwo, 0);
885 atomic_set(&mce_callin, 0);
889 * Let others run again.
891 atomic_set(&mce_executing, 0);
896 * Check if the address reported by the CPU is in a format we can parse.
897 * It would be possible to add code for most other cases, but all would
898 * be somewhat complicated (e.g. segment offset would require an instruction
899 * parser). So only support physical addresses upto page granuality for now.
901 static int mce_usable_address(struct mce *m)
903 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
905 if ((m->misc & 0x3f) > PAGE_SHIFT)
907 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
912 static void mce_clear_state(unsigned long *toclear)
916 for (i = 0; i < banks; i++) {
917 if (test_bit(i, toclear))
918 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
923 * The actual machine check handler. This only handles real
924 * exceptions when something got corrupted coming in through int 18.
926 * This is executed in NMI context not subject to normal locking rules. This
927 * implies that most kernel services cannot be safely used. Don't even
928 * think about putting a printk in there!
930 * On Intel systems this is entered on all CPUs in parallel through
931 * MCE broadcast. However some CPUs might be broken beyond repair,
932 * so be always careful when synchronizing with others.
934 void do_machine_check(struct pt_regs *regs, long error_code)
936 struct mce m, *final;
941 * Establish sequential order between the CPUs entering the machine
946 * If no_way_out gets set, there is no safe way to recover from this
947 * MCE. If tolerant is cranked up, we'll try anyway.
951 * If kill_it gets set, there might be a way to recover from this
955 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
956 char *msg = "Unknown";
958 atomic_inc(&mce_entry);
960 percpu_inc(mce_exception_count);
962 if (notify_die(DIE_NMI, "machine check", regs, error_code,
963 18, SIGKILL) == NOTIFY_STOP)
970 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
971 final = &__get_cpu_var(mces_seen);
974 no_way_out = mce_no_way_out(&m, &msg);
979 * When no restart IP must always kill or panic.
981 if (!(m.mcgstatus & MCG_STATUS_RIPV))
985 * Go through all the banks in exclusion of the other CPUs.
986 * This way we don't report duplicated events on shared banks
987 * because the first one to see it will clear it.
989 order = mce_start(&no_way_out);
990 for (i = 0; i < banks; i++) {
991 __clear_bit(i, toclear);
992 if (!mce_banks[i].ctl)
999 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1000 if ((m.status & MCI_STATUS_VAL) == 0)
1004 * Non uncorrected or non signaled errors are handled by
1005 * machine_check_poll. Leave them alone, unless this panics.
1007 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1012 * Set taint even when machine check was not enabled.
1014 add_taint(TAINT_MACHINE_CHECK);
1016 severity = mce_severity(&m, tolerant, NULL);
1019 * When machine check was for corrected handler don't touch,
1020 * unless we're panicing.
1022 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1024 __set_bit(i, toclear);
1025 if (severity == MCE_NO_SEVERITY) {
1027 * Machine check event was not enabled. Clear, but
1034 * Kill on action required.
1036 if (severity == MCE_AR_SEVERITY)
1039 if (m.status & MCI_STATUS_MISCV)
1040 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1041 if (m.status & MCI_STATUS_ADDRV)
1042 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1045 * Action optional error. Queue address for later processing.
1046 * When the ring overflows we just ignore the AO error.
1047 * RED-PEN add some logging mechanism when
1048 * usable_address or mce_add_ring fails.
1049 * RED-PEN don't ignore overflow for tolerant == 0
1051 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1052 mce_ring_add(m.addr >> PAGE_SHIFT);
1054 mce_get_rip(&m, regs);
1057 if (severity > worst) {
1064 mce_clear_state(toclear);
1067 * Do most of the synchronization with other CPUs.
1068 * When there's any problem use only local no_way_out state.
1070 if (mce_end(order) < 0)
1071 no_way_out = worst >= MCE_PANIC_SEVERITY;
1074 * If we have decided that we just CAN'T continue, and the user
1075 * has not set tolerant to an insane level, give up and die.
1077 * This is mainly used in the case when the system doesn't
1078 * support MCE broadcasting or it has been disabled.
1080 if (no_way_out && tolerant < 3)
1081 mce_panic("Fatal machine check on current CPU", final, msg);
1084 * If the error seems to be unrecoverable, something should be
1085 * done. Try to kill as little as possible. If we can kill just
1086 * one task, do that. If the user has set the tolerance very
1087 * high, don't try to do anything at all.
1090 if (kill_it && tolerant < 3)
1091 force_sig(SIGBUS, current);
1093 /* notify userspace ASAP */
1094 set_thread_flag(TIF_MCE_NOTIFY);
1097 mce_report_event(regs);
1098 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1100 atomic_dec(&mce_entry);
1103 EXPORT_SYMBOL_GPL(do_machine_check);
1105 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1106 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1108 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1112 * Called after mce notification in process context. This code
1113 * is allowed to sleep. Call the high level VM handler to process
1114 * any corrupted pages.
1115 * Assume that the work queue code only calls this one at a time
1117 * Note we don't disable preemption, so this code might run on the wrong
1118 * CPU. In this case the event is picked up by the scheduled work queue.
1119 * This is merely a fast path to expedite processing in some common
1122 void mce_notify_process(void)
1126 while (mce_ring_get(&pfn))
1127 memory_failure(pfn, MCE_VECTOR);
1130 static void mce_process_work(struct work_struct *dummy)
1132 mce_notify_process();
1135 #ifdef CONFIG_X86_MCE_INTEL
1137 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1138 * @cpu: The CPU on which the event occurred.
1139 * @status: Event status information
1141 * This function should be called by the thermal interrupt after the
1142 * event has been processed and the decision was made to log the event
1145 * The status parameter will be saved to the 'status' field of 'struct mce'
1146 * and historically has been the register value of the
1147 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1149 void mce_log_therm_throt_event(__u64 status)
1154 m.bank = MCE_THERMAL_BANK;
1158 #endif /* CONFIG_X86_MCE_INTEL */
1161 * Periodic polling timer for "silent" machine check errors. If the
1162 * poller finds an MCE, poll 2x faster. When the poller finds no more
1163 * errors, poll 2x slower (up to check_interval seconds).
1165 * We will disable polling in DOM0 since all CMCI/Polling
1166 * mechanism will be done in XEN for Intel CPUs
1168 #if defined (CONFIG_X86_XEN_MCE)
1169 static int check_interval = 0; /* disable polling */
1171 static int check_interval = 5 * 60; /* 5 minutes */
1174 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1175 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1177 static void mce_start_timer(unsigned long data)
1179 struct timer_list *t = &per_cpu(mce_timer, data);
1182 WARN_ON(smp_processor_id() != data);
1184 if (mce_available(¤t_cpu_data)) {
1185 machine_check_poll(MCP_TIMESTAMP,
1186 &__get_cpu_var(mce_poll_banks));
1190 * Alert userspace if needed. If we logged an MCE, reduce the
1191 * polling interval, otherwise increase the polling interval.
1193 n = &__get_cpu_var(mce_next_interval);
1194 if (mce_notify_irq())
1195 *n = max(*n/2, HZ/100);
1197 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1199 t->expires = jiffies + *n;
1200 add_timer_on(t, smp_processor_id());
1203 static void mce_do_trigger(struct work_struct *work)
1205 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1208 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1211 * Notify the user(s) about new machine check events.
1212 * Can be called from interrupt context, but not from machine check/NMI
1215 int mce_notify_irq(void)
1217 /* Not more than two messages every minute */
1218 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1220 clear_thread_flag(TIF_MCE_NOTIFY);
1222 if (test_and_clear_bit(0, &mce_need_notify)) {
1223 wake_up_interruptible(&mce_wait);
1226 * There is no risk of missing notifications because
1227 * work_pending is always cleared before the function is
1230 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1231 schedule_work(&mce_trigger_work);
1233 if (__ratelimit(&ratelimit))
1234 pr_info(HW_ERR "Machine check events logged\n");
1240 EXPORT_SYMBOL_GPL(mce_notify_irq);
1242 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1246 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1249 for (i = 0; i < banks; i++) {
1250 struct mce_bank *b = &mce_banks[i];
1259 * Initialize Machine Checks for a CPU.
1261 static int __cpuinit __mcheck_cpu_cap_init(void)
1266 rdmsrl(MSR_IA32_MCG_CAP, cap);
1268 b = cap & MCG_BANKCNT_MASK;
1270 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1272 if (b > MAX_NR_BANKS) {
1274 "MCE: Using only %u machine check banks out of %u\n",
1279 /* Don't support asymmetric configurations today */
1280 WARN_ON(banks != 0 && b != banks);
1283 int err = __mcheck_cpu_mce_banks_init();
1289 /* Use accurate RIP reporting if available. */
1290 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1291 rip_msr = MSR_IA32_MCG_EIP;
1293 if (cap & MCG_SER_P)
1299 static void __mcheck_cpu_init_generic(void)
1301 mce_banks_t all_banks;
1306 * Log the machine checks left over from the previous reset.
1308 bitmap_fill(all_banks, MAX_NR_BANKS);
1309 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1311 set_in_cr4(X86_CR4_MCE);
1313 rdmsrl(MSR_IA32_MCG_CAP, cap);
1314 if (cap & MCG_CTL_P)
1315 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1317 for (i = 0; i < banks; i++) {
1318 struct mce_bank *b = &mce_banks[i];
1322 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1323 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1327 /* Add per CPU specific workarounds here */
1328 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1330 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1331 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1335 /* This should be disabled by the BIOS, but isn't always */
1336 if (c->x86_vendor == X86_VENDOR_AMD) {
1338 if (c->x86 == 15 && banks > 4) {
1340 * disable GART TBL walk error reporting, which
1341 * trips off incorrectly with the IOMMU & 3ware
1344 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1347 if (c->x86 <= 17 && mce_bootlog < 0) {
1349 * Lots of broken BIOS around that don't clear them
1350 * by default and leave crap in there. Don't log:
1355 * Various K7s with broken bank 0 around. Always disable
1358 if (c->x86 == 6 && banks > 0)
1359 mce_banks[0].ctl = 0;
1362 if (c->x86_vendor == X86_VENDOR_INTEL) {
1364 * SDM documents that on family 6 bank 0 should not be written
1365 * because it aliases to another special BIOS controlled
1367 * But it's not aliased anymore on model 0x1a+
1368 * Don't ignore bank 0 completely because there could be a
1369 * valid event later, merely don't write CTL0.
1372 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1373 mce_banks[0].init = 0;
1376 * All newer Intel systems support MCE broadcasting. Enable
1377 * synchronization with a one second timeout.
1379 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1380 monarch_timeout < 0)
1381 monarch_timeout = USEC_PER_SEC;
1384 * There are also broken BIOSes on some Pentium M and
1387 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1390 if (monarch_timeout < 0)
1391 monarch_timeout = 0;
1392 if (mce_bootlog != 0)
1393 mce_panic_timeout = 30;
1398 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1402 switch (c->x86_vendor) {
1403 case X86_VENDOR_INTEL:
1404 intel_p5_mcheck_init(c);
1406 case X86_VENDOR_CENTAUR:
1407 winchip_mcheck_init(c);
1412 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1414 #ifndef CONFIG_X86_64_XEN
1415 switch (c->x86_vendor) {
1416 case X86_VENDOR_INTEL:
1417 mce_intel_feature_init(c);
1419 case X86_VENDOR_AMD:
1420 mce_amd_feature_init(c);
1428 static void __mcheck_cpu_init_timer(void)
1430 struct timer_list *t = &__get_cpu_var(mce_timer);
1431 int *n = &__get_cpu_var(mce_next_interval);
1433 setup_timer(t, mce_start_timer, smp_processor_id());
1438 *n = check_interval * HZ;
1441 t->expires = round_jiffies(jiffies + *n);
1442 add_timer_on(t, smp_processor_id());
1445 /* Handle unconfigured int18 (should never happen) */
1446 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1448 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1449 smp_processor_id());
1452 /* Call the installed machine check handler for this CPU setup. */
1453 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1454 unexpected_machine_check;
1457 * Called for each booted CPU to set up machine checks.
1458 * Must be called with preempt off:
1460 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1465 __mcheck_cpu_ancient_init(c);
1467 if (!mce_available(c))
1470 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1475 machine_check_vector = do_machine_check;
1477 __mcheck_cpu_init_generic();
1478 __mcheck_cpu_init_vendor(c);
1479 __mcheck_cpu_init_timer();
1480 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1485 * Character device to read and clear the MCE log.
1488 static DEFINE_SPINLOCK(mce_state_lock);
1489 static int open_count; /* #times opened */
1490 static int open_exclu; /* already open exclusive? */
1492 static int mce_open(struct inode *inode, struct file *file)
1494 spin_lock(&mce_state_lock);
1496 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1497 spin_unlock(&mce_state_lock);
1502 if (file->f_flags & O_EXCL)
1506 spin_unlock(&mce_state_lock);
1508 return nonseekable_open(inode, file);
1511 static int mce_release(struct inode *inode, struct file *file)
1513 spin_lock(&mce_state_lock);
1518 spin_unlock(&mce_state_lock);
1523 static void collect_tscs(void *data)
1525 unsigned long *cpu_tsc = (unsigned long *)data;
1527 rdtscll(cpu_tsc[smp_processor_id()]);
1530 static int mce_apei_read_done;
1532 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1533 static int __mce_read_apei(char __user **ubuf, size_t usize)
1539 if (usize < sizeof(struct mce))
1542 rc = apei_read_mce(&m, &record_id);
1543 /* Error or no more MCE record */
1545 mce_apei_read_done = 1;
1549 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1552 * In fact, we should have cleared the record after that has
1553 * been flushed to the disk or sent to network in
1554 * /sbin/mcelog, but we have no interface to support that now,
1555 * so just clear it to avoid duplication.
1557 rc = apei_clear_mce(record_id);
1559 mce_apei_read_done = 1;
1562 *ubuf += sizeof(struct mce);
1567 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1570 char __user *buf = ubuf;
1571 unsigned long *cpu_tsc;
1572 unsigned prev, next;
1575 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1579 mutex_lock(&mce_read_mutex);
1581 if (!mce_apei_read_done) {
1582 err = __mce_read_apei(&buf, usize);
1583 if (err || buf != ubuf)
1587 next = rcu_dereference_check_mce(mcelog.next);
1589 /* Only supports full reads right now */
1591 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1597 for (i = prev; i < next; i++) {
1598 unsigned long start = jiffies;
1600 while (!mcelog.entry[i].finished) {
1601 if (time_after_eq(jiffies, start + 2)) {
1602 memset(mcelog.entry + i, 0,
1603 sizeof(struct mce));
1609 err |= copy_to_user(buf, mcelog.entry + i,
1610 sizeof(struct mce));
1611 buf += sizeof(struct mce);
1616 memset(mcelog.entry + prev, 0,
1617 (next - prev) * sizeof(struct mce));
1619 next = cmpxchg(&mcelog.next, prev, 0);
1620 } while (next != prev);
1622 synchronize_sched();
1625 * Collect entries that were still getting written before the
1628 on_each_cpu(collect_tscs, cpu_tsc, 1);
1630 for (i = next; i < MCE_LOG_LEN; i++) {
1631 if (mcelog.entry[i].finished &&
1632 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1633 err |= copy_to_user(buf, mcelog.entry+i,
1634 sizeof(struct mce));
1636 buf += sizeof(struct mce);
1637 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1645 mutex_unlock(&mce_read_mutex);
1648 return err ? err : buf - ubuf;
1651 static unsigned int mce_poll(struct file *file, poll_table *wait)
1653 poll_wait(file, &mce_wait, wait);
1654 if (rcu_dereference_check_mce(mcelog.next))
1655 return POLLIN | POLLRDNORM;
1656 if (!mce_apei_read_done && apei_check_mce())
1657 return POLLIN | POLLRDNORM;
1661 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1663 int __user *p = (int __user *)arg;
1665 if (!capable(CAP_SYS_ADMIN))
1669 case MCE_GET_RECORD_LEN:
1670 return put_user(sizeof(struct mce), p);
1671 case MCE_GET_LOG_LEN:
1672 return put_user(MCE_LOG_LEN, p);
1673 case MCE_GETCLEAR_FLAGS: {
1677 flags = mcelog.flags;
1678 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1680 return put_user(flags, p);
1687 /* Modified in mce-inject.c, so not static or const */
1688 struct file_operations mce_chrdev_ops = {
1690 .release = mce_release,
1693 .unlocked_ioctl = mce_ioctl,
1695 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1697 static struct miscdevice mce_log_device = {
1704 * mce=off Disables machine check
1705 * mce=no_cmci Disables CMCI
1706 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1707 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1708 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1709 * monarchtimeout is how long to wait for other CPUs on machine
1710 * check, or 0 to not wait
1711 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1712 * mce=nobootlog Don't log MCEs from before booting.
1714 static int __init mcheck_enable(char *str)
1722 if (!strcmp(str, "off"))
1724 else if (!strcmp(str, "no_cmci"))
1725 mce_cmci_disabled = 1;
1726 else if (!strcmp(str, "dont_log_ce"))
1727 mce_dont_log_ce = 1;
1728 else if (!strcmp(str, "ignore_ce"))
1730 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1731 mce_bootlog = (str[0] == 'b');
1732 else if (isdigit(str[0])) {
1733 get_option(&str, &tolerant);
1736 get_option(&str, &monarch_timeout);
1739 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1745 __setup("mce", mcheck_enable);
1747 int __init mcheck_init(void)
1749 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1751 mcheck_intel_therm_init();
1761 * Disable machine checks on suspend and shutdown. We can't really handle
1764 static int mce_disable_error_reporting(void)
1768 for (i = 0; i < banks; i++) {
1769 struct mce_bank *b = &mce_banks[i];
1772 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1777 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1779 return mce_disable_error_reporting();
1782 static int mce_shutdown(struct sys_device *dev)
1784 return mce_disable_error_reporting();
1788 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1789 * Only one CPU is active at this time, the others get re-added later using
1792 static int mce_resume(struct sys_device *dev)
1794 __mcheck_cpu_init_generic();
1795 __mcheck_cpu_init_vendor(¤t_cpu_data);
1800 static void mce_cpu_restart(void *data)
1802 del_timer_sync(&__get_cpu_var(mce_timer));
1803 if (!mce_available(¤t_cpu_data))
1805 __mcheck_cpu_init_generic();
1806 __mcheck_cpu_init_timer();
1809 /* Reinit MCEs after user configuration changes */
1810 static void mce_restart(void)
1812 on_each_cpu(mce_cpu_restart, NULL, 1);
1815 /* Toggle features for corrected errors */
1816 static void mce_disable_ce(void *all)
1818 if (!mce_available(¤t_cpu_data))
1821 del_timer_sync(&__get_cpu_var(mce_timer));
1825 static void mce_enable_ce(void *all)
1827 if (!mce_available(¤t_cpu_data))
1832 __mcheck_cpu_init_timer();
1835 static struct sysdev_class mce_sysclass = {
1836 .suspend = mce_suspend,
1837 .shutdown = mce_shutdown,
1838 .resume = mce_resume,
1839 .name = "machinecheck",
1842 DEFINE_PER_CPU(struct sys_device, mce_dev);
1845 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1847 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1849 return container_of(attr, struct mce_bank, attr);
1852 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1855 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1858 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1859 const char *buf, size_t size)
1863 if (strict_strtoull(buf, 0, &new) < 0)
1866 attr_to_bank(attr)->ctl = new;
1873 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1875 strcpy(buf, mce_helper);
1877 return strlen(mce_helper) + 1;
1880 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1881 const char *buf, size_t siz)
1885 strncpy(mce_helper, buf, sizeof(mce_helper));
1886 mce_helper[sizeof(mce_helper)-1] = 0;
1887 p = strchr(mce_helper, '\n');
1892 return strlen(mce_helper) + !!p;
1895 static ssize_t set_ignore_ce(struct sys_device *s,
1896 struct sysdev_attribute *attr,
1897 const char *buf, size_t size)
1901 if (strict_strtoull(buf, 0, &new) < 0)
1904 if (mce_ignore_ce ^ !!new) {
1906 /* disable ce features */
1907 on_each_cpu(mce_disable_ce, (void *)1, 1);
1910 /* enable ce features */
1912 on_each_cpu(mce_enable_ce, (void *)1, 1);
1918 static ssize_t set_cmci_disabled(struct sys_device *s,
1919 struct sysdev_attribute *attr,
1920 const char *buf, size_t size)
1924 if (strict_strtoull(buf, 0, &new) < 0)
1927 if (mce_cmci_disabled ^ !!new) {
1930 on_each_cpu(mce_disable_ce, NULL, 1);
1931 mce_cmci_disabled = 1;
1934 mce_cmci_disabled = 0;
1935 on_each_cpu(mce_enable_ce, NULL, 1);
1941 static ssize_t store_int_with_restart(struct sys_device *s,
1942 struct sysdev_attribute *attr,
1943 const char *buf, size_t size)
1945 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1950 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1951 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1952 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1953 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1955 static struct sysdev_ext_attribute attr_check_interval = {
1956 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1957 store_int_with_restart),
1961 static struct sysdev_ext_attribute attr_ignore_ce = {
1962 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1966 static struct sysdev_ext_attribute attr_cmci_disabled = {
1967 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1971 static struct sysdev_attribute *mce_attrs[] = {
1972 &attr_tolerant.attr,
1973 &attr_check_interval.attr,
1975 &attr_monarch_timeout.attr,
1976 &attr_dont_log_ce.attr,
1977 &attr_ignore_ce.attr,
1978 &attr_cmci_disabled.attr,
1982 static cpumask_var_t mce_dev_initialized;
1984 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1985 static __cpuinit int mce_create_device(unsigned int cpu)
1990 if (!mce_available(&boot_cpu_data))
1993 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1994 per_cpu(mce_dev, cpu).id = cpu;
1995 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1997 err = sysdev_register(&per_cpu(mce_dev, cpu));
2001 for (i = 0; mce_attrs[i]; i++) {
2002 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2006 for (j = 0; j < banks; j++) {
2007 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
2008 &mce_banks[j].attr);
2012 cpumask_set_cpu(cpu, mce_dev_initialized);
2017 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
2020 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2022 sysdev_unregister(&per_cpu(mce_dev, cpu));
2027 static __cpuinit void mce_remove_device(unsigned int cpu)
2031 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2034 for (i = 0; mce_attrs[i]; i++)
2035 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2037 for (i = 0; i < banks; i++)
2038 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2040 sysdev_unregister(&per_cpu(mce_dev, cpu));
2041 cpumask_clear_cpu(cpu, mce_dev_initialized);
2044 /* Make sure there are no machine checks on offlined CPUs. */
2045 static void __cpuinit mce_disable_cpu(void *h)
2047 unsigned long action = *(unsigned long *)h;
2050 if (!mce_available(¤t_cpu_data))
2053 if (!(action & CPU_TASKS_FROZEN))
2055 for (i = 0; i < banks; i++) {
2056 struct mce_bank *b = &mce_banks[i];
2059 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2063 static void __cpuinit mce_reenable_cpu(void *h)
2065 unsigned long action = *(unsigned long *)h;
2068 if (!mce_available(¤t_cpu_data))
2071 if (!(action & CPU_TASKS_FROZEN))
2073 for (i = 0; i < banks; i++) {
2074 struct mce_bank *b = &mce_banks[i];
2077 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2081 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2082 static int __cpuinit
2083 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2085 unsigned int cpu = (unsigned long)hcpu;
2086 struct timer_list *t = &per_cpu(mce_timer, cpu);
2090 case CPU_ONLINE_FROZEN:
2091 mce_create_device(cpu);
2092 if (threshold_cpu_callback)
2093 threshold_cpu_callback(action, cpu);
2096 case CPU_DEAD_FROZEN:
2097 if (threshold_cpu_callback)
2098 threshold_cpu_callback(action, cpu);
2099 mce_remove_device(cpu);
2101 case CPU_DOWN_PREPARE:
2102 case CPU_DOWN_PREPARE_FROZEN:
2104 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2106 case CPU_DOWN_FAILED:
2107 case CPU_DOWN_FAILED_FROZEN:
2108 if (!mce_ignore_ce && check_interval) {
2109 t->expires = round_jiffies(jiffies +
2110 __get_cpu_var(mce_next_interval));
2111 add_timer_on(t, cpu);
2113 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2116 /* intentionally ignoring frozen here */
2117 cmci_rediscover(cpu);
2123 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2124 .notifier_call = mce_cpu_callback,
2127 static __init void mce_init_banks(void)
2131 for (i = 0; i < banks; i++) {
2132 struct mce_bank *b = &mce_banks[i];
2133 struct sysdev_attribute *a = &b->attr;
2135 sysfs_attr_init(&a->attr);
2136 a->attr.name = b->attrname;
2137 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2139 a->attr.mode = 0644;
2140 a->show = show_bank;
2141 a->store = set_bank;
2145 static __init int mcheck_init_device(void)
2150 if (!mce_available(&boot_cpu_data))
2153 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2157 err = sysdev_class_register(&mce_sysclass);
2161 for_each_online_cpu(i) {
2162 err = mce_create_device(i);
2167 register_hotcpu_notifier(&mce_cpu_notifier);
2168 misc_register(&mce_log_device);
2170 #ifdef CONFIG_X86_XEN_MCE
2171 if (is_initial_xendomain()) {
2172 /* Register vIRQ handler for MCE LOG processing */
2173 extern int bind_virq_for_mce(void);
2175 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2176 bind_virq_for_mce();
2183 device_initcall(mcheck_init_device);
2186 * Old style boot options parsing. Only for compatibility.
2188 static int __init mcheck_disable(char *str)
2193 __setup("nomce", mcheck_disable);
2195 #ifdef CONFIG_DEBUG_FS
2196 struct dentry *mce_get_debugfs_dir(void)
2198 static struct dentry *dmce;
2201 dmce = debugfs_create_dir("mce", NULL);
2206 static void mce_reset(void)
2209 atomic_set(&mce_fake_paniced, 0);
2210 atomic_set(&mce_executing, 0);
2211 atomic_set(&mce_callin, 0);
2212 atomic_set(&global_nwo, 0);
2215 static int fake_panic_get(void *data, u64 *val)
2221 static int fake_panic_set(void *data, u64 val)
2228 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2229 fake_panic_set, "%llu\n");
2231 static int __init mcheck_debugfs_init(void)
2233 struct dentry *dmce, *ffake_panic;
2235 dmce = mce_get_debugfs_dir();
2238 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2245 late_initcall(mcheck_debugfs_init);