2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
40 #include <linux/irq_work.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
105 /* MCA banks polled by the period polling timer for corrected events */
106 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce *m)
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
123 m->socketid = cpu_data(m->extcpu).phys_proc_id;
125 m->apicid = cpu_data(m->extcpu).initial_apicid;
126 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
129 DEFINE_PER_CPU(struct mce, injectm);
130 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
133 * Lockless MCE logging infrastructure.
134 * This avoids deadlocks on printk locks without having to break locks. Also
135 * separate MCEs from kernel messages to avoid bogus bug reports.
138 static struct mce_log mcelog = {
139 .signature = MCE_LOG_SIGNATURE,
141 .recordlen = sizeof(struct mce),
144 void mce_log(struct mce *mce)
146 unsigned next, entry;
148 /* Emit the trace record: */
149 trace_mce_record(mce);
154 entry = rcu_dereference_check_mce(mcelog.next);
157 * If edac_mce is enabled, it will check the error type
158 * and will process it, if it is a known error.
159 * Otherwise, the error will be sent through mcelog
162 if (edac_mce_parse(mce))
166 * When the buffer fills up discard new entries.
167 * Assume that the earlier errors are the more
170 if (entry >= MCE_LOG_LEN) {
171 set_bit(MCE_OVERFLOW,
172 (unsigned long *)&mcelog.flags);
175 /* Old left over entry. Skip: */
176 if (mcelog.entry[entry].finished) {
184 if (cmpxchg(&mcelog.next, entry, next) == entry)
187 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
189 mcelog.entry[entry].finished = 1;
193 set_bit(0, &mce_need_notify);
196 static void print_mce(struct mce *m)
200 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
201 m->extcpu, m->mcgstatus, m->bank, m->status);
204 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
205 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
208 if (m->cs == __KERNEL_CS)
209 print_symbol("{%s}", m->ip);
213 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
215 pr_cont("ADDR %llx ", m->addr);
217 pr_cont("MISC %llx ", m->misc);
221 * Note this output is parsed by external tools and old fields
222 * should not be changed.
224 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
225 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
226 cpu_data(m->extcpu).microcode);
229 * Print out human-readable details about the MCE error,
230 * (if the CPU has an implementation for that)
232 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
233 if (ret == NOTIFY_STOP)
236 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
239 #define PANIC_TIMEOUT 5 /* 5 seconds */
241 static atomic_t mce_paniced;
243 static int fake_panic;
244 static atomic_t mce_fake_paniced;
246 /* Panic in progress. Enable interrupts and wait for final IPI */
247 static void wait_for_panic(void)
249 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
253 while (timeout-- > 0)
255 if (panic_timeout == 0)
256 panic_timeout = mce_panic_timeout;
257 panic("Panicing machine check CPU died");
260 static void mce_panic(char *msg, struct mce *final, char *exp)
266 * Make sure only one CPU runs in machine check panic
268 if (atomic_inc_return(&mce_paniced) > 1)
275 /* Don't log too much for fake panic */
276 if (atomic_inc_return(&mce_fake_paniced) > 1)
279 /* First print corrected ones that are still unlogged */
280 for (i = 0; i < MCE_LOG_LEN; i++) {
281 struct mce *m = &mcelog.entry[i];
282 if (!(m->status & MCI_STATUS_VAL))
284 if (!(m->status & MCI_STATUS_UC)) {
287 apei_err = apei_write_mce(m);
290 /* Now print uncorrected but with the final one last */
291 for (i = 0; i < MCE_LOG_LEN; i++) {
292 struct mce *m = &mcelog.entry[i];
293 if (!(m->status & MCI_STATUS_VAL))
295 if (!(m->status & MCI_STATUS_UC))
297 if (!final || memcmp(m, final, sizeof(struct mce))) {
300 apei_err = apei_write_mce(m);
306 apei_err = apei_write_mce(final);
309 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
311 pr_emerg(HW_ERR "Machine check: %s\n", exp);
313 if (panic_timeout == 0)
314 panic_timeout = mce_panic_timeout;
317 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
320 /* Support code for software error injection */
322 static int msr_to_offset(u32 msr)
324 unsigned bank = __this_cpu_read(injectm.bank);
327 return offsetof(struct mce, ip);
328 if (msr == MSR_IA32_MCx_STATUS(bank))
329 return offsetof(struct mce, status);
330 if (msr == MSR_IA32_MCx_ADDR(bank))
331 return offsetof(struct mce, addr);
332 if (msr == MSR_IA32_MCx_MISC(bank))
333 return offsetof(struct mce, misc);
334 if (msr == MSR_IA32_MCG_STATUS)
335 return offsetof(struct mce, mcgstatus);
339 /* MSR access wrappers used for error injection */
340 static u64 mce_rdmsrl(u32 msr)
344 if (__this_cpu_read(injectm.finished)) {
345 int offset = msr_to_offset(msr);
349 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
352 if (rdmsrl_safe(msr, &v)) {
353 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
355 * Return zero in case the access faulted. This should
356 * not happen normally but can happen if the CPU does
357 * something weird, or if the code is buggy.
365 static void mce_wrmsrl(u32 msr, u64 v)
367 if (__this_cpu_read(injectm.finished)) {
368 int offset = msr_to_offset(msr);
371 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
378 * Collect all global (w.r.t. this processor) status about this machine
379 * check into our "mce" struct so that we can use it later to assess
380 * the severity of the problem as we read per-bank specific details.
382 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
386 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
389 * Get the address of the instruction at the time of
390 * the machine check error.
392 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
396 /* Use accurate RIP reporting if available. */
398 m->ip = mce_rdmsrl(rip_msr);
403 * Simple lockless ring to communicate PFNs from the exception handler with the
404 * process context work function. This is vastly simplified because there's
405 * only a single reader and a single writer.
407 #define MCE_RING_SIZE 16 /* we use one entry less */
410 unsigned short start;
412 unsigned long ring[MCE_RING_SIZE];
414 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
416 /* Runs with CPU affinity in workqueue */
417 static int mce_ring_empty(void)
419 struct mce_ring *r = &__get_cpu_var(mce_ring);
421 return r->start == r->end;
424 static int mce_ring_get(unsigned long *pfn)
431 r = &__get_cpu_var(mce_ring);
432 if (r->start == r->end)
434 *pfn = r->ring[r->start];
435 r->start = (r->start + 1) % MCE_RING_SIZE;
442 /* Always runs in MCE context with preempt off */
443 static int mce_ring_add(unsigned long pfn)
445 struct mce_ring *r = &__get_cpu_var(mce_ring);
448 next = (r->end + 1) % MCE_RING_SIZE;
449 if (next == r->start)
451 r->ring[r->end] = pfn;
457 int mce_available(struct cpuinfo_x86 *c)
461 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
464 static void mce_schedule_work(void)
466 if (!mce_ring_empty()) {
467 struct work_struct *work = &__get_cpu_var(mce_work);
468 if (!work_pending(work))
473 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
475 static void mce_irq_work_cb(struct irq_work *entry)
481 static void mce_report_event(struct pt_regs *regs)
483 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
486 * Triggering the work queue here is just an insurance
487 * policy in case the syscall exit notify handler
488 * doesn't run soon enough or ends up running on the
489 * wrong CPU (can happen when audit sleeps)
495 irq_work_queue(&__get_cpu_var(mce_irq_work));
498 DEFINE_PER_CPU(unsigned, mce_poll_count);
501 * Poll for corrected events or events that happened before reset.
502 * Those are just logged through /dev/mcelog.
504 * This is executed in standard interrupt context.
506 * Note: spec recommends to panic for fatal unsignalled
507 * errors here. However this would be quite problematic --
508 * we would need to reimplement the Monarch handling and
509 * it would mess up the exclusion between exception handler
510 * and poll hander -- * so we skip this for now.
511 * These cases should not happen anyways, or only when the CPU
512 * is already totally * confused. In this case it's likely it will
513 * not fully execute the machine check handler either.
515 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
520 percpu_inc(mce_poll_count);
522 mce_gather_info(&m, NULL);
524 for (i = 0; i < banks; i++) {
525 if (!mce_banks[i].ctl || !test_bit(i, *b))
534 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
535 if (!(m.status & MCI_STATUS_VAL))
539 * Uncorrected or signalled events are handled by the exception
540 * handler when it is enabled, so don't process those here.
542 * TBD do the same check for MCI_STATUS_EN here?
544 if (!(flags & MCP_UC) &&
545 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
548 if (m.status & MCI_STATUS_MISCV)
549 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
550 if (m.status & MCI_STATUS_ADDRV)
551 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
553 if (!(flags & MCP_TIMESTAMP))
556 * Don't get the IP here because it's unlikely to
557 * have anything to do with the actual error location.
559 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
561 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
565 * Clear state for this bank.
567 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
571 * Don't clear MCG_STATUS here because it's only defined for
577 EXPORT_SYMBOL_GPL(machine_check_poll);
580 * Do a quick check if any of the events requires a panic.
581 * This decides if we keep the events around or clear them.
583 static int mce_no_way_out(struct mce *m, char **msg)
587 for (i = 0; i < banks; i++) {
588 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
589 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
596 * Variable to establish order between CPUs while scanning.
597 * Each CPU spins initially until executing is equal its number.
599 static atomic_t mce_executing;
602 * Defines order of CPUs on entry. First CPU becomes Monarch.
604 static atomic_t mce_callin;
607 * Check if a timeout waiting for other CPUs happened.
609 static int mce_timed_out(u64 *t)
612 * The others already did panic for some reason.
613 * Bail out like in a timeout.
614 * rmb() to tell the compiler that system_state
615 * might have been modified by someone else.
618 if (atomic_read(&mce_paniced))
620 if (!monarch_timeout)
622 if ((s64)*t < SPINUNIT) {
623 /* CHECKME: Make panic default for 1 too? */
625 mce_panic("Timeout synchronizing machine check over CPUs",
632 touch_nmi_watchdog();
637 * The Monarch's reign. The Monarch is the CPU who entered
638 * the machine check handler first. It waits for the others to
639 * raise the exception too and then grades them. When any
640 * error is fatal panic. Only then let the others continue.
642 * The other CPUs entering the MCE handler will be controlled by the
643 * Monarch. They are called Subjects.
645 * This way we prevent any potential data corruption in a unrecoverable case
646 * and also makes sure always all CPU's errors are examined.
648 * Also this detects the case of a machine check event coming from outer
649 * space (not detected by any CPUs) In this case some external agent wants
650 * us to shut down, so panic too.
652 * The other CPUs might still decide to panic if the handler happens
653 * in a unrecoverable place, but in this case the system is in a semi-stable
654 * state and won't corrupt anything by itself. It's ok to let the others
655 * continue for a bit first.
657 * All the spin loops have timeouts; when a timeout happens a CPU
658 * typically elects itself to be Monarch.
660 static void mce_reign(void)
663 struct mce *m = NULL;
664 int global_worst = 0;
669 * This CPU is the Monarch and the other CPUs have run
670 * through their handlers.
671 * Grade the severity of the errors of all the CPUs.
673 for_each_possible_cpu(cpu) {
674 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
676 if (severity > global_worst) {
678 global_worst = severity;
679 m = &per_cpu(mces_seen, cpu);
684 * Cannot recover? Panic here then.
685 * This dumps all the mces in the log buffer and stops the
688 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
689 mce_panic("Fatal Machine check", m, msg);
692 * For UC somewhere we let the CPU who detects it handle it.
693 * Also must let continue the others, otherwise the handling
694 * CPU could deadlock on a lock.
698 * No machine check event found. Must be some external
699 * source or one CPU is hung. Panic.
701 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
702 mce_panic("Machine check from unknown source", NULL, NULL);
705 * Now clear all the mces_seen so that they don't reappear on
708 for_each_possible_cpu(cpu)
709 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
712 static atomic_t global_nwo;
715 * Start of Monarch synchronization. This waits until all CPUs have
716 * entered the exception handler and then determines if any of them
717 * saw a fatal event that requires panic. Then it executes them
718 * in the entry order.
719 * TBD double check parallel CPU hotunplug
721 static int mce_start(int *no_way_out)
724 int cpus = num_online_cpus();
725 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
730 atomic_add(*no_way_out, &global_nwo);
732 * global_nwo should be updated before mce_callin
735 order = atomic_inc_return(&mce_callin);
740 while (atomic_read(&mce_callin) != cpus) {
741 if (mce_timed_out(&timeout)) {
742 atomic_set(&global_nwo, 0);
749 * mce_callin should be read before global_nwo
755 * Monarch: Starts executing now, the others wait.
757 atomic_set(&mce_executing, 1);
760 * Subject: Now start the scanning loop one by one in
761 * the original callin order.
762 * This way when there are any shared banks it will be
763 * only seen by one CPU before cleared, avoiding duplicates.
765 while (atomic_read(&mce_executing) < order) {
766 if (mce_timed_out(&timeout)) {
767 atomic_set(&global_nwo, 0);
775 * Cache the global no_way_out state.
777 *no_way_out = atomic_read(&global_nwo);
783 * Synchronize between CPUs after main scanning loop.
784 * This invokes the bulk of the Monarch processing.
786 static int mce_end(int order)
789 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
797 * Allow others to run.
799 atomic_inc(&mce_executing);
802 /* CHECKME: Can this race with a parallel hotplug? */
803 int cpus = num_online_cpus();
806 * Monarch: Wait for everyone to go through their scanning
809 while (atomic_read(&mce_executing) <= cpus) {
810 if (mce_timed_out(&timeout))
820 * Subject: Wait for Monarch to finish.
822 while (atomic_read(&mce_executing) != 0) {
823 if (mce_timed_out(&timeout))
829 * Don't reset anything. That's done by the Monarch.
835 * Reset all global state.
838 atomic_set(&global_nwo, 0);
839 atomic_set(&mce_callin, 0);
843 * Let others run again.
845 atomic_set(&mce_executing, 0);
850 * Check if the address reported by the CPU is in a format we can parse.
851 * It would be possible to add code for most other cases, but all would
852 * be somewhat complicated (e.g. segment offset would require an instruction
853 * parser). So only support physical addresses up to page granuality for now.
855 static int mce_usable_address(struct mce *m)
857 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
859 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
861 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
866 static void mce_clear_state(unsigned long *toclear)
870 for (i = 0; i < banks; i++) {
871 if (test_bit(i, toclear))
872 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
877 * The actual machine check handler. This only handles real
878 * exceptions when something got corrupted coming in through int 18.
880 * This is executed in NMI context not subject to normal locking rules. This
881 * implies that most kernel services cannot be safely used. Don't even
882 * think about putting a printk in there!
884 * On Intel systems this is entered on all CPUs in parallel through
885 * MCE broadcast. However some CPUs might be broken beyond repair,
886 * so be always careful when synchronizing with others.
888 void do_machine_check(struct pt_regs *regs, long error_code)
890 struct mce m, *final;
895 * Establish sequential order between the CPUs entering the machine
900 * If no_way_out gets set, there is no safe way to recover from this
901 * MCE. If tolerant is cranked up, we'll try anyway.
905 * If kill_it gets set, there might be a way to recover from this
909 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
910 char *msg = "Unknown";
912 atomic_inc(&mce_entry);
914 percpu_inc(mce_exception_count);
916 if (notify_die(DIE_NMI, "machine check", regs, error_code,
917 18, SIGKILL) == NOTIFY_STOP)
922 mce_gather_info(&m, regs);
924 final = &__get_cpu_var(mces_seen);
927 no_way_out = mce_no_way_out(&m, &msg);
932 * When no restart IP must always kill or panic.
934 if (!(m.mcgstatus & MCG_STATUS_RIPV))
938 * Go through all the banks in exclusion of the other CPUs.
939 * This way we don't report duplicated events on shared banks
940 * because the first one to see it will clear it.
942 order = mce_start(&no_way_out);
943 for (i = 0; i < banks; i++) {
944 __clear_bit(i, toclear);
945 if (!mce_banks[i].ctl)
952 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
953 if ((m.status & MCI_STATUS_VAL) == 0)
957 * Non uncorrected or non signaled errors are handled by
958 * machine_check_poll. Leave them alone, unless this panics.
960 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
965 * Set taint even when machine check was not enabled.
967 add_taint(TAINT_MACHINE_CHECK);
969 severity = mce_severity(&m, tolerant, NULL);
972 * When machine check was for corrected handler don't touch,
973 * unless we're panicing.
975 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
977 __set_bit(i, toclear);
978 if (severity == MCE_NO_SEVERITY) {
980 * Machine check event was not enabled. Clear, but
987 * Kill on action required.
989 if (severity == MCE_AR_SEVERITY)
992 if (m.status & MCI_STATUS_MISCV)
993 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
994 if (m.status & MCI_STATUS_ADDRV)
995 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
998 * Action optional error. Queue address for later processing.
999 * When the ring overflows we just ignore the AO error.
1000 * RED-PEN add some logging mechanism when
1001 * usable_address or mce_add_ring fails.
1002 * RED-PEN don't ignore overflow for tolerant == 0
1004 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1005 mce_ring_add(m.addr >> PAGE_SHIFT);
1009 if (severity > worst) {
1016 mce_clear_state(toclear);
1019 * Do most of the synchronization with other CPUs.
1020 * When there's any problem use only local no_way_out state.
1022 if (mce_end(order) < 0)
1023 no_way_out = worst >= MCE_PANIC_SEVERITY;
1026 * If we have decided that we just CAN'T continue, and the user
1027 * has not set tolerant to an insane level, give up and die.
1029 * This is mainly used in the case when the system doesn't
1030 * support MCE broadcasting or it has been disabled.
1032 if (no_way_out && tolerant < 3)
1033 mce_panic("Fatal machine check on current CPU", final, msg);
1036 * If the error seems to be unrecoverable, something should be
1037 * done. Try to kill as little as possible. If we can kill just
1038 * one task, do that. If the user has set the tolerance very
1039 * high, don't try to do anything at all.
1042 if (kill_it && tolerant < 3)
1043 force_sig(SIGBUS, current);
1045 /* notify userspace ASAP */
1046 set_thread_flag(TIF_MCE_NOTIFY);
1049 mce_report_event(regs);
1050 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1052 atomic_dec(&mce_entry);
1055 EXPORT_SYMBOL_GPL(do_machine_check);
1057 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1058 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1060 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1064 * Called after mce notification in process context. This code
1065 * is allowed to sleep. Call the high level VM handler to process
1066 * any corrupted pages.
1067 * Assume that the work queue code only calls this one at a time
1069 * Note we don't disable preemption, so this code might run on the wrong
1070 * CPU. In this case the event is picked up by the scheduled work queue.
1071 * This is merely a fast path to expedite processing in some common
1074 void mce_notify_process(void)
1078 while (mce_ring_get(&pfn))
1079 memory_failure(pfn, MCE_VECTOR);
1082 static void mce_process_work(struct work_struct *dummy)
1084 mce_notify_process();
1087 #ifdef CONFIG_X86_MCE_INTEL
1089 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1090 * @cpu: The CPU on which the event occurred.
1091 * @status: Event status information
1093 * This function should be called by the thermal interrupt after the
1094 * event has been processed and the decision was made to log the event
1097 * The status parameter will be saved to the 'status' field of 'struct mce'
1098 * and historically has been the register value of the
1099 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1101 void mce_log_therm_throt_event(__u64 status)
1106 m.bank = MCE_THERMAL_BANK;
1110 #endif /* CONFIG_X86_MCE_INTEL */
1113 * Periodic polling timer for "silent" machine check errors. If the
1114 * poller finds an MCE, poll 2x faster. When the poller finds no more
1115 * errors, poll 2x slower (up to check_interval seconds).
1117 static int check_interval = 5 * 60; /* 5 minutes */
1119 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1120 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1122 static void mce_start_timer(unsigned long data)
1124 struct timer_list *t = &per_cpu(mce_timer, data);
1127 WARN_ON(smp_processor_id() != data);
1129 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1130 machine_check_poll(MCP_TIMESTAMP,
1131 &__get_cpu_var(mce_poll_banks));
1135 * Alert userspace if needed. If we logged an MCE, reduce the
1136 * polling interval, otherwise increase the polling interval.
1138 n = &__get_cpu_var(mce_next_interval);
1139 if (mce_notify_irq())
1140 *n = max(*n/2, HZ/100);
1142 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1144 t->expires = jiffies + *n;
1145 add_timer_on(t, smp_processor_id());
1148 static void mce_do_trigger(struct work_struct *work)
1150 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1153 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1156 * Notify the user(s) about new machine check events.
1157 * Can be called from interrupt context, but not from machine check/NMI
1160 int mce_notify_irq(void)
1162 /* Not more than two messages every minute */
1163 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1165 clear_thread_flag(TIF_MCE_NOTIFY);
1167 if (test_and_clear_bit(0, &mce_need_notify)) {
1168 /* wake processes polling /dev/mcelog */
1169 wake_up_interruptible(&mce_chrdev_wait);
1172 * There is no risk of missing notifications because
1173 * work_pending is always cleared before the function is
1176 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1177 schedule_work(&mce_trigger_work);
1179 if (__ratelimit(&ratelimit))
1180 pr_info(HW_ERR "Machine check events logged\n");
1186 EXPORT_SYMBOL_GPL(mce_notify_irq);
1188 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1192 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1195 for (i = 0; i < banks; i++) {
1196 struct mce_bank *b = &mce_banks[i];
1205 * Initialize Machine Checks for a CPU.
1207 static int __cpuinit __mcheck_cpu_cap_init(void)
1212 rdmsrl(MSR_IA32_MCG_CAP, cap);
1214 b = cap & MCG_BANKCNT_MASK;
1216 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1218 if (b > MAX_NR_BANKS) {
1220 "MCE: Using only %u machine check banks out of %u\n",
1225 /* Don't support asymmetric configurations today */
1226 WARN_ON(banks != 0 && b != banks);
1229 int err = __mcheck_cpu_mce_banks_init();
1235 /* Use accurate RIP reporting if available. */
1236 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1237 rip_msr = MSR_IA32_MCG_EIP;
1239 if (cap & MCG_SER_P)
1245 static void __mcheck_cpu_init_generic(void)
1247 mce_banks_t all_banks;
1252 * Log the machine checks left over from the previous reset.
1254 bitmap_fill(all_banks, MAX_NR_BANKS);
1255 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1257 set_in_cr4(X86_CR4_MCE);
1259 rdmsrl(MSR_IA32_MCG_CAP, cap);
1260 if (cap & MCG_CTL_P)
1261 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1263 for (i = 0; i < banks; i++) {
1264 struct mce_bank *b = &mce_banks[i];
1268 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1269 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1273 /* Add per CPU specific workarounds here */
1274 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1276 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1277 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1281 /* This should be disabled by the BIOS, but isn't always */
1282 if (c->x86_vendor == X86_VENDOR_AMD) {
1283 if (c->x86 == 15 && banks > 4) {
1285 * disable GART TBL walk error reporting, which
1286 * trips off incorrectly with the IOMMU & 3ware
1289 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1291 if (c->x86 <= 17 && mce_bootlog < 0) {
1293 * Lots of broken BIOS around that don't clear them
1294 * by default and leave crap in there. Don't log:
1299 * Various K7s with broken bank 0 around. Always disable
1302 if (c->x86 == 6 && banks > 0)
1303 mce_banks[0].ctl = 0;
1306 if (c->x86_vendor == X86_VENDOR_INTEL) {
1308 * SDM documents that on family 6 bank 0 should not be written
1309 * because it aliases to another special BIOS controlled
1311 * But it's not aliased anymore on model 0x1a+
1312 * Don't ignore bank 0 completely because there could be a
1313 * valid event later, merely don't write CTL0.
1316 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1317 mce_banks[0].init = 0;
1320 * All newer Intel systems support MCE broadcasting. Enable
1321 * synchronization with a one second timeout.
1323 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1324 monarch_timeout < 0)
1325 monarch_timeout = USEC_PER_SEC;
1328 * There are also broken BIOSes on some Pentium M and
1331 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1334 if (monarch_timeout < 0)
1335 monarch_timeout = 0;
1336 if (mce_bootlog != 0)
1337 mce_panic_timeout = 30;
1342 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1347 switch (c->x86_vendor) {
1348 case X86_VENDOR_INTEL:
1349 intel_p5_mcheck_init(c);
1352 case X86_VENDOR_CENTAUR:
1353 winchip_mcheck_init(c);
1361 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1363 switch (c->x86_vendor) {
1364 case X86_VENDOR_INTEL:
1365 mce_intel_feature_init(c);
1367 case X86_VENDOR_AMD:
1368 mce_amd_feature_init(c);
1375 static void __mcheck_cpu_init_timer(void)
1377 struct timer_list *t = &__get_cpu_var(mce_timer);
1378 int *n = &__get_cpu_var(mce_next_interval);
1380 setup_timer(t, mce_start_timer, smp_processor_id());
1385 *n = check_interval * HZ;
1388 t->expires = round_jiffies(jiffies + *n);
1389 add_timer_on(t, smp_processor_id());
1392 /* Handle unconfigured int18 (should never happen) */
1393 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1395 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1396 smp_processor_id());
1399 /* Call the installed machine check handler for this CPU setup. */
1400 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1401 unexpected_machine_check;
1404 * Called for each booted CPU to set up machine checks.
1405 * Must be called with preempt off:
1407 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1412 if (__mcheck_cpu_ancient_init(c))
1415 if (!mce_available(c))
1418 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1423 machine_check_vector = do_machine_check;
1425 __mcheck_cpu_init_generic();
1426 __mcheck_cpu_init_vendor(c);
1427 __mcheck_cpu_init_timer();
1428 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1429 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1433 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1436 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1437 static int mce_chrdev_open_count; /* #times opened */
1438 static int mce_chrdev_open_exclu; /* already open exclusive? */
1440 static int mce_chrdev_open(struct inode *inode, struct file *file)
1442 spin_lock(&mce_chrdev_state_lock);
1444 if (mce_chrdev_open_exclu ||
1445 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1446 spin_unlock(&mce_chrdev_state_lock);
1451 if (file->f_flags & O_EXCL)
1452 mce_chrdev_open_exclu = 1;
1453 mce_chrdev_open_count++;
1455 spin_unlock(&mce_chrdev_state_lock);
1457 return nonseekable_open(inode, file);
1460 static int mce_chrdev_release(struct inode *inode, struct file *file)
1462 spin_lock(&mce_chrdev_state_lock);
1464 mce_chrdev_open_count--;
1465 mce_chrdev_open_exclu = 0;
1467 spin_unlock(&mce_chrdev_state_lock);
1472 static void collect_tscs(void *data)
1474 unsigned long *cpu_tsc = (unsigned long *)data;
1476 rdtscll(cpu_tsc[smp_processor_id()]);
1479 static int mce_apei_read_done;
1481 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1482 static int __mce_read_apei(char __user **ubuf, size_t usize)
1488 if (usize < sizeof(struct mce))
1491 rc = apei_read_mce(&m, &record_id);
1492 /* Error or no more MCE record */
1494 mce_apei_read_done = 1;
1498 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1501 * In fact, we should have cleared the record after that has
1502 * been flushed to the disk or sent to network in
1503 * /sbin/mcelog, but we have no interface to support that now,
1504 * so just clear it to avoid duplication.
1506 rc = apei_clear_mce(record_id);
1508 mce_apei_read_done = 1;
1511 *ubuf += sizeof(struct mce);
1516 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1517 size_t usize, loff_t *off)
1519 char __user *buf = ubuf;
1520 unsigned long *cpu_tsc;
1521 unsigned prev, next;
1524 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1528 mutex_lock(&mce_chrdev_read_mutex);
1530 if (!mce_apei_read_done) {
1531 err = __mce_read_apei(&buf, usize);
1532 if (err || buf != ubuf)
1536 next = rcu_dereference_check_mce(mcelog.next);
1538 /* Only supports full reads right now */
1540 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1546 for (i = prev; i < next; i++) {
1547 unsigned long start = jiffies;
1548 struct mce *m = &mcelog.entry[i];
1550 while (!m->finished) {
1551 if (time_after_eq(jiffies, start + 2)) {
1552 memset(m, 0, sizeof(*m));
1558 err |= copy_to_user(buf, m, sizeof(*m));
1564 memset(mcelog.entry + prev, 0,
1565 (next - prev) * sizeof(struct mce));
1567 next = cmpxchg(&mcelog.next, prev, 0);
1568 } while (next != prev);
1570 synchronize_sched();
1573 * Collect entries that were still getting written before the
1576 on_each_cpu(collect_tscs, cpu_tsc, 1);
1578 for (i = next; i < MCE_LOG_LEN; i++) {
1579 struct mce *m = &mcelog.entry[i];
1581 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1582 err |= copy_to_user(buf, m, sizeof(*m));
1585 memset(m, 0, sizeof(*m));
1593 mutex_unlock(&mce_chrdev_read_mutex);
1596 return err ? err : buf - ubuf;
1599 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1601 poll_wait(file, &mce_chrdev_wait, wait);
1602 if (rcu_access_index(mcelog.next))
1603 return POLLIN | POLLRDNORM;
1604 if (!mce_apei_read_done && apei_check_mce())
1605 return POLLIN | POLLRDNORM;
1609 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1612 int __user *p = (int __user *)arg;
1614 if (!capable(CAP_SYS_ADMIN))
1618 case MCE_GET_RECORD_LEN:
1619 return put_user(sizeof(struct mce), p);
1620 case MCE_GET_LOG_LEN:
1621 return put_user(MCE_LOG_LEN, p);
1622 case MCE_GETCLEAR_FLAGS: {
1626 flags = mcelog.flags;
1627 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1629 return put_user(flags, p);
1636 /* Modified in mce-inject.c, so not static or const */
1637 struct file_operations mce_chrdev_ops = {
1638 .open = mce_chrdev_open,
1639 .release = mce_chrdev_release,
1640 .read = mce_chrdev_read,
1641 .poll = mce_chrdev_poll,
1642 .unlocked_ioctl = mce_chrdev_ioctl,
1643 .llseek = no_llseek,
1645 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1647 static struct miscdevice mce_chrdev_device = {
1654 * mce=off Disables machine check
1655 * mce=no_cmci Disables CMCI
1656 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1657 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1658 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1659 * monarchtimeout is how long to wait for other CPUs on machine
1660 * check, or 0 to not wait
1661 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1662 * mce=nobootlog Don't log MCEs from before booting.
1664 static int __init mcheck_enable(char *str)
1672 if (!strcmp(str, "off"))
1674 else if (!strcmp(str, "no_cmci"))
1675 mce_cmci_disabled = 1;
1676 else if (!strcmp(str, "dont_log_ce"))
1677 mce_dont_log_ce = 1;
1678 else if (!strcmp(str, "ignore_ce"))
1680 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1681 mce_bootlog = (str[0] == 'b');
1682 else if (isdigit(str[0])) {
1683 get_option(&str, &tolerant);
1686 get_option(&str, &monarch_timeout);
1689 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1695 __setup("mce", mcheck_enable);
1697 int __init mcheck_init(void)
1699 mcheck_intel_therm_init();
1705 * mce_syscore: PM support
1709 * Disable machine checks on suspend and shutdown. We can't really handle
1712 static int mce_disable_error_reporting(void)
1716 for (i = 0; i < banks; i++) {
1717 struct mce_bank *b = &mce_banks[i];
1720 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1725 static int mce_syscore_suspend(void)
1727 return mce_disable_error_reporting();
1730 static void mce_syscore_shutdown(void)
1732 mce_disable_error_reporting();
1736 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1737 * Only one CPU is active at this time, the others get re-added later using
1740 static void mce_syscore_resume(void)
1742 __mcheck_cpu_init_generic();
1743 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1746 static struct syscore_ops mce_syscore_ops = {
1747 .suspend = mce_syscore_suspend,
1748 .shutdown = mce_syscore_shutdown,
1749 .resume = mce_syscore_resume,
1753 * mce_sysdev: Sysfs support
1756 static void mce_cpu_restart(void *data)
1758 del_timer_sync(&__get_cpu_var(mce_timer));
1759 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1761 __mcheck_cpu_init_generic();
1762 __mcheck_cpu_init_timer();
1765 /* Reinit MCEs after user configuration changes */
1766 static void mce_restart(void)
1768 on_each_cpu(mce_cpu_restart, NULL, 1);
1771 /* Toggle features for corrected errors */
1772 static void mce_disable_ce(void *all)
1774 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1777 del_timer_sync(&__get_cpu_var(mce_timer));
1781 static void mce_enable_ce(void *all)
1783 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1788 __mcheck_cpu_init_timer();
1791 static struct sysdev_class mce_sysdev_class = {
1792 .name = "machinecheck",
1795 DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1798 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1800 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1802 return container_of(attr, struct mce_bank, attr);
1805 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1808 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1811 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1812 const char *buf, size_t size)
1816 if (strict_strtoull(buf, 0, &new) < 0)
1819 attr_to_bank(attr)->ctl = new;
1826 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1828 strcpy(buf, mce_helper);
1830 return strlen(mce_helper) + 1;
1833 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1834 const char *buf, size_t siz)
1838 strncpy(mce_helper, buf, sizeof(mce_helper));
1839 mce_helper[sizeof(mce_helper)-1] = 0;
1840 p = strchr(mce_helper, '\n');
1845 return strlen(mce_helper) + !!p;
1848 static ssize_t set_ignore_ce(struct sys_device *s,
1849 struct sysdev_attribute *attr,
1850 const char *buf, size_t size)
1854 if (strict_strtoull(buf, 0, &new) < 0)
1857 if (mce_ignore_ce ^ !!new) {
1859 /* disable ce features */
1860 on_each_cpu(mce_disable_ce, (void *)1, 1);
1863 /* enable ce features */
1865 on_each_cpu(mce_enable_ce, (void *)1, 1);
1871 static ssize_t set_cmci_disabled(struct sys_device *s,
1872 struct sysdev_attribute *attr,
1873 const char *buf, size_t size)
1877 if (strict_strtoull(buf, 0, &new) < 0)
1880 if (mce_cmci_disabled ^ !!new) {
1883 on_each_cpu(mce_disable_ce, NULL, 1);
1884 mce_cmci_disabled = 1;
1887 mce_cmci_disabled = 0;
1888 on_each_cpu(mce_enable_ce, NULL, 1);
1894 static ssize_t store_int_with_restart(struct sys_device *s,
1895 struct sysdev_attribute *attr,
1896 const char *buf, size_t size)
1898 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1903 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1904 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1905 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1906 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1908 static struct sysdev_ext_attribute attr_check_interval = {
1909 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1910 store_int_with_restart),
1914 static struct sysdev_ext_attribute attr_ignore_ce = {
1915 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1919 static struct sysdev_ext_attribute attr_cmci_disabled = {
1920 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1924 static struct sysdev_attribute *mce_sysdev_attrs[] = {
1925 &attr_tolerant.attr,
1926 &attr_check_interval.attr,
1928 &attr_monarch_timeout.attr,
1929 &attr_dont_log_ce.attr,
1930 &attr_ignore_ce.attr,
1931 &attr_cmci_disabled.attr,
1935 static cpumask_var_t mce_sysdev_initialized;
1937 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1938 static __cpuinit int mce_sysdev_create(unsigned int cpu)
1940 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1944 if (!mce_available(&boot_cpu_data))
1947 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1949 sysdev->cls = &mce_sysdev_class;
1951 err = sysdev_register(sysdev);
1955 for (i = 0; mce_sysdev_attrs[i]; i++) {
1956 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
1960 for (j = 0; j < banks; j++) {
1961 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
1965 cpumask_set_cpu(cpu, mce_sysdev_initialized);
1970 sysdev_remove_file(sysdev, &mce_banks[j].attr);
1973 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
1975 sysdev_unregister(sysdev);
1980 static __cpuinit void mce_sysdev_remove(unsigned int cpu)
1982 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1985 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
1988 for (i = 0; mce_sysdev_attrs[i]; i++)
1989 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
1991 for (i = 0; i < banks; i++)
1992 sysdev_remove_file(sysdev, &mce_banks[i].attr);
1994 sysdev_unregister(sysdev);
1995 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
1998 /* Make sure there are no machine checks on offlined CPUs. */
1999 static void __cpuinit mce_disable_cpu(void *h)
2001 unsigned long action = *(unsigned long *)h;
2004 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2007 if (!(action & CPU_TASKS_FROZEN))
2009 for (i = 0; i < banks; i++) {
2010 struct mce_bank *b = &mce_banks[i];
2013 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2017 static void __cpuinit mce_reenable_cpu(void *h)
2019 unsigned long action = *(unsigned long *)h;
2022 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2025 if (!(action & CPU_TASKS_FROZEN))
2027 for (i = 0; i < banks; i++) {
2028 struct mce_bank *b = &mce_banks[i];
2031 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2035 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2036 static int __cpuinit
2037 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2039 unsigned int cpu = (unsigned long)hcpu;
2040 struct timer_list *t = &per_cpu(mce_timer, cpu);
2044 case CPU_ONLINE_FROZEN:
2045 mce_sysdev_create(cpu);
2046 if (threshold_cpu_callback)
2047 threshold_cpu_callback(action, cpu);
2050 case CPU_DEAD_FROZEN:
2051 if (threshold_cpu_callback)
2052 threshold_cpu_callback(action, cpu);
2053 mce_sysdev_remove(cpu);
2055 case CPU_DOWN_PREPARE:
2056 case CPU_DOWN_PREPARE_FROZEN:
2058 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2060 case CPU_DOWN_FAILED:
2061 case CPU_DOWN_FAILED_FROZEN:
2062 if (!mce_ignore_ce && check_interval) {
2063 t->expires = round_jiffies(jiffies +
2064 __get_cpu_var(mce_next_interval));
2065 add_timer_on(t, cpu);
2067 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2070 /* intentionally ignoring frozen here */
2071 cmci_rediscover(cpu);
2077 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2078 .notifier_call = mce_cpu_callback,
2081 static __init void mce_init_banks(void)
2085 for (i = 0; i < banks; i++) {
2086 struct mce_bank *b = &mce_banks[i];
2087 struct sysdev_attribute *a = &b->attr;
2089 sysfs_attr_init(&a->attr);
2090 a->attr.name = b->attrname;
2091 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2093 a->attr.mode = 0644;
2094 a->show = show_bank;
2095 a->store = set_bank;
2099 static __init int mcheck_init_device(void)
2104 if (!mce_available(&boot_cpu_data))
2107 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2111 err = sysdev_class_register(&mce_sysdev_class);
2115 for_each_online_cpu(i) {
2116 err = mce_sysdev_create(i);
2121 register_syscore_ops(&mce_syscore_ops);
2122 register_hotcpu_notifier(&mce_cpu_notifier);
2124 /* register character device /dev/mcelog */
2125 misc_register(&mce_chrdev_device);
2129 device_initcall(mcheck_init_device);
2132 * Old style boot options parsing. Only for compatibility.
2134 static int __init mcheck_disable(char *str)
2139 __setup("nomce", mcheck_disable);
2141 #ifdef CONFIG_DEBUG_FS
2142 struct dentry *mce_get_debugfs_dir(void)
2144 static struct dentry *dmce;
2147 dmce = debugfs_create_dir("mce", NULL);
2152 static void mce_reset(void)
2155 atomic_set(&mce_fake_paniced, 0);
2156 atomic_set(&mce_executing, 0);
2157 atomic_set(&mce_callin, 0);
2158 atomic_set(&global_nwo, 0);
2161 static int fake_panic_get(void *data, u64 *val)
2167 static int fake_panic_set(void *data, u64 val)
2174 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2175 fake_panic_set, "%llu\n");
2177 static int __init mcheck_debugfs_init(void)
2179 struct dentry *dmce, *ffake_panic;
2181 dmce = mce_get_debugfs_dir();
2184 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2191 late_initcall(mcheck_debugfs_init);