2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/smp.h>
39 #include <linux/debugfs.h>
40 #include <linux/edac_mce.h>
42 #include <asm/processor.h>
43 #include <asm/hw_irq.h>
50 #include "mce-internal.h"
52 static DEFINE_MUTEX(mce_read_mutex);
54 #define rcu_dereference_check_mce(p) \
55 rcu_dereference_index_check((p), \
56 rcu_read_lock_sched_held() || \
57 lockdep_is_held(&mce_read_mutex))
59 #define CREATE_TRACE_POINTS
60 #include <trace/events/mce.h>
62 int mce_disabled __read_mostly;
64 #define MISC_MCELOG_MINOR 227
66 #define SPINUNIT 100 /* 100ns */
70 DEFINE_PER_CPU(unsigned, mce_exception_count);
74 * 0: always panic on uncorrected errors, log corrected errors
75 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
76 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
77 * 3: never panic or SIGBUS, log all errors (for testing only)
79 static int tolerant __read_mostly = 1;
80 static int banks __read_mostly;
81 static int rip_msr __read_mostly;
82 static int mce_bootlog __read_mostly = -1;
83 static int monarch_timeout __read_mostly = -1;
84 static int mce_panic_timeout __read_mostly;
85 static int mce_dont_log_ce __read_mostly;
86 int mce_cmci_disabled __read_mostly;
87 int mce_ignore_ce __read_mostly;
88 int mce_ser __read_mostly;
90 struct mce_bank *mce_banks __read_mostly;
92 /* User mode helper program triggered by machine check event */
93 static unsigned long mce_need_notify;
94 static char mce_helper[128];
95 static char *mce_helper_argv[2] = { mce_helper, NULL };
97 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
98 static DEFINE_PER_CPU(struct mce, mces_seen);
99 static int cpu_missing;
102 * CPU/chipset specific EDAC code can register a notifier call here to print
103 * MCE errors in a human-readable form.
105 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
106 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
108 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
111 pr_emerg(HW_ERR "No human readable MCE decoding support on this CPU type.\n");
112 pr_emerg(HW_ERR "Run the message through 'mcelog --ascii' to decode.\n");
117 static struct notifier_block mce_dec_nb = {
118 .notifier_call = default_decode_mce,
122 /* MCA banks polled by the period polling timer for corrected events */
123 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
124 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
127 static DEFINE_PER_CPU(struct work_struct, mce_work);
129 /* Do initial initialization of a struct mce */
130 void mce_setup(struct mce *m)
132 memset(m, 0, sizeof(struct mce));
133 m->cpu = m->extcpu = smp_processor_id();
135 /* We hope get_seconds stays lockless */
136 m->time = get_seconds();
137 m->cpuvendor = boot_cpu_data.x86_vendor;
138 m->cpuid = cpuid_eax(1);
141 m->socketid = cpu_data(m->extcpu).phys_proc_id;
143 m->apicid = cpu_data(m->extcpu).initial_apicid;
145 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
148 DEFINE_PER_CPU(struct mce, injectm);
149 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
152 * Lockless MCE logging infrastructure.
153 * This avoids deadlocks on printk locks without having to break locks. Also
154 * separate MCEs from kernel messages to avoid bogus bug reports.
157 static struct mce_log mcelog = {
158 .signature = MCE_LOG_SIGNATURE,
160 .recordlen = sizeof(struct mce),
163 void mce_log(struct mce *mce)
165 unsigned next, entry;
167 /* Emit the trace record: */
168 trace_mce_record(mce);
173 entry = rcu_dereference_check_mce(mcelog.next);
176 * If edac_mce is enabled, it will check the error type
177 * and will process it, if it is a known error.
178 * Otherwise, the error will be sent through mcelog
181 if (edac_mce_parse(mce))
185 * When the buffer fills up discard new entries.
186 * Assume that the earlier errors are the more
189 if (entry >= MCE_LOG_LEN) {
190 set_bit(MCE_OVERFLOW,
191 (unsigned long *)&mcelog.flags);
194 /* Old left over entry. Skip: */
195 if (mcelog.entry[entry].finished) {
203 if (cmpxchg(&mcelog.next, entry, next) == entry)
206 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
208 mcelog.entry[entry].finished = 1;
212 set_bit(0, &mce_need_notify);
215 static void print_mce(struct mce *m)
217 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
218 m->extcpu, m->mcgstatus, m->bank, m->status);
221 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
222 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
225 if (m->cs == __KERNEL_CS)
226 print_symbol("{%s}", m->ip);
230 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
232 pr_cont("ADDR %llx ", m->addr);
234 pr_cont("MISC %llx ", m->misc);
237 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
238 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
241 * Print out human-readable details about the MCE error,
242 * (if the CPU has an implementation for that)
244 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
247 #define PANIC_TIMEOUT 5 /* 5 seconds */
249 static atomic_t mce_paniced;
251 static int fake_panic;
252 static atomic_t mce_fake_paniced;
254 /* Panic in progress. Enable interrupts and wait for final IPI */
255 static void wait_for_panic(void)
257 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
261 while (timeout-- > 0)
263 if (panic_timeout == 0)
264 panic_timeout = mce_panic_timeout;
265 panic("Panicing machine check CPU died");
268 static void mce_panic(char *msg, struct mce *final, char *exp)
274 * Make sure only one CPU runs in machine check panic
276 if (atomic_inc_return(&mce_paniced) > 1)
283 /* Don't log too much for fake panic */
284 if (atomic_inc_return(&mce_fake_paniced) > 1)
287 /* First print corrected ones that are still unlogged */
288 for (i = 0; i < MCE_LOG_LEN; i++) {
289 struct mce *m = &mcelog.entry[i];
290 if (!(m->status & MCI_STATUS_VAL))
292 if (!(m->status & MCI_STATUS_UC)) {
295 apei_err = apei_write_mce(m);
298 /* Now print uncorrected but with the final one last */
299 for (i = 0; i < MCE_LOG_LEN; i++) {
300 struct mce *m = &mcelog.entry[i];
301 if (!(m->status & MCI_STATUS_VAL))
303 if (!(m->status & MCI_STATUS_UC))
305 if (!final || memcmp(m, final, sizeof(struct mce))) {
308 apei_err = apei_write_mce(m);
314 apei_err = apei_write_mce(final);
317 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
319 pr_emerg(HW_ERR "Machine check: %s\n", exp);
321 if (panic_timeout == 0)
322 panic_timeout = mce_panic_timeout;
325 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
328 /* Support code for software error injection */
330 static int msr_to_offset(u32 msr)
332 unsigned bank = __this_cpu_read(injectm.bank);
335 return offsetof(struct mce, ip);
336 if (msr == MSR_IA32_MCx_STATUS(bank))
337 return offsetof(struct mce, status);
338 if (msr == MSR_IA32_MCx_ADDR(bank))
339 return offsetof(struct mce, addr);
340 if (msr == MSR_IA32_MCx_MISC(bank))
341 return offsetof(struct mce, misc);
342 if (msr == MSR_IA32_MCG_STATUS)
343 return offsetof(struct mce, mcgstatus);
347 /* MSR access wrappers used for error injection */
348 static u64 mce_rdmsrl(u32 msr)
352 if (__this_cpu_read(injectm.finished)) {
353 int offset = msr_to_offset(msr);
357 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
360 if (rdmsrl_safe(msr, &v)) {
361 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
363 * Return zero in case the access faulted. This should
364 * not happen normally but can happen if the CPU does
365 * something weird, or if the code is buggy.
373 static void mce_wrmsrl(u32 msr, u64 v)
375 if (__this_cpu_read(injectm.finished)) {
376 int offset = msr_to_offset(msr);
379 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
386 * Simple lockless ring to communicate PFNs from the exception handler with the
387 * process context work function. This is vastly simplified because there's
388 * only a single reader and a single writer.
390 #define MCE_RING_SIZE 16 /* we use one entry less */
393 unsigned short start;
395 unsigned long ring[MCE_RING_SIZE];
397 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
399 /* Runs with CPU affinity in workqueue */
400 static int mce_ring_empty(void)
402 struct mce_ring *r = &__get_cpu_var(mce_ring);
404 return r->start == r->end;
407 static int mce_ring_get(unsigned long *pfn)
414 r = &__get_cpu_var(mce_ring);
415 if (r->start == r->end)
417 *pfn = r->ring[r->start];
418 r->start = (r->start + 1) % MCE_RING_SIZE;
425 /* Always runs in MCE context with preempt off */
426 static int mce_ring_add(unsigned long pfn)
428 struct mce_ring *r = &__get_cpu_var(mce_ring);
431 next = (r->end + 1) % MCE_RING_SIZE;
432 if (next == r->start)
434 r->ring[r->end] = pfn;
440 int mce_available(struct cpuinfo_x86 *c)
444 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
447 static void mce_schedule_work(void)
449 if (!mce_ring_empty()) {
450 struct work_struct *work = &__get_cpu_var(mce_work);
451 if (!work_pending(work))
457 * Get the address of the instruction at the time of the machine check
460 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
463 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
471 m->ip = mce_rdmsrl(rip_msr);
474 #ifdef CONFIG_X86_LOCAL_APIC
476 * Called after interrupts have been reenabled again
477 * when a MCE happened during an interrupts off region
480 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
493 static void mce_report_event(struct pt_regs *regs)
495 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
498 * Triggering the work queue here is just an insurance
499 * policy in case the syscall exit notify handler
500 * doesn't run soon enough or ends up running on the
501 * wrong CPU (can happen when audit sleeps)
507 #if defined(CONFIG_X86_LOCAL_APIC) && !defined(CONFIG_XEN)
509 * Without APIC do not notify. The event will be picked
516 * When interrupts are disabled we cannot use
517 * kernel services safely. Trigger an self interrupt
518 * through the APIC to instead do the notification
519 * after interrupts are reenabled again.
521 apic->send_IPI_self(MCE_SELF_VECTOR);
524 * Wait for idle afterwards again so that we don't leave the
525 * APIC in a non idle state because the normal APIC writes
528 apic_wait_icr_idle();
532 DEFINE_PER_CPU(unsigned, mce_poll_count);
535 * Poll for corrected events or events that happened before reset.
536 * Those are just logged through /dev/mcelog.
538 * This is executed in standard interrupt context.
540 * Note: spec recommends to panic for fatal unsignalled
541 * errors here. However this would be quite problematic --
542 * we would need to reimplement the Monarch handling and
543 * it would mess up the exclusion between exception handler
544 * and poll hander -- * so we skip this for now.
545 * These cases should not happen anyways, or only when the CPU
546 * is already totally * confused. In this case it's likely it will
547 * not fully execute the machine check handler either.
549 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
554 percpu_inc(mce_poll_count);
558 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
559 for (i = 0; i < banks; i++) {
560 if (!mce_banks[i].ctl || !test_bit(i, *b))
569 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
570 if (!(m.status & MCI_STATUS_VAL))
574 * Uncorrected or signalled events are handled by the exception
575 * handler when it is enabled, so don't process those here.
577 * TBD do the same check for MCI_STATUS_EN here?
579 if (!(flags & MCP_UC) &&
580 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
583 if (m.status & MCI_STATUS_MISCV)
584 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
585 if (m.status & MCI_STATUS_ADDRV)
586 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
588 if (!(flags & MCP_TIMESTAMP))
591 * Don't get the IP here because it's unlikely to
592 * have anything to do with the actual error location.
594 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
596 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
597 add_taint(TAINT_MACHINE_CHECK);
601 * Clear state for this bank.
603 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
607 * Don't clear MCG_STATUS here because it's only defined for
613 EXPORT_SYMBOL_GPL(machine_check_poll);
616 * Do a quick check if any of the events requires a panic.
617 * This decides if we keep the events around or clear them.
619 static int mce_no_way_out(struct mce *m, char **msg)
623 for (i = 0; i < banks; i++) {
624 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
625 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
632 * Variable to establish order between CPUs while scanning.
633 * Each CPU spins initially until executing is equal its number.
635 static atomic_t mce_executing;
638 * Defines order of CPUs on entry. First CPU becomes Monarch.
640 static atomic_t mce_callin;
643 * Check if a timeout waiting for other CPUs happened.
645 static int mce_timed_out(u64 *t)
648 * The others already did panic for some reason.
649 * Bail out like in a timeout.
650 * rmb() to tell the compiler that system_state
651 * might have been modified by someone else.
654 if (atomic_read(&mce_paniced))
656 if (!monarch_timeout)
658 if ((s64)*t < SPINUNIT) {
659 /* CHECKME: Make panic default for 1 too? */
661 mce_panic("Timeout synchronizing machine check over CPUs",
668 touch_nmi_watchdog();
673 * The Monarch's reign. The Monarch is the CPU who entered
674 * the machine check handler first. It waits for the others to
675 * raise the exception too and then grades them. When any
676 * error is fatal panic. Only then let the others continue.
678 * The other CPUs entering the MCE handler will be controlled by the
679 * Monarch. They are called Subjects.
681 * This way we prevent any potential data corruption in a unrecoverable case
682 * and also makes sure always all CPU's errors are examined.
684 * Also this detects the case of a machine check event coming from outer
685 * space (not detected by any CPUs) In this case some external agent wants
686 * us to shut down, so panic too.
688 * The other CPUs might still decide to panic if the handler happens
689 * in a unrecoverable place, but in this case the system is in a semi-stable
690 * state and won't corrupt anything by itself. It's ok to let the others
691 * continue for a bit first.
693 * All the spin loops have timeouts; when a timeout happens a CPU
694 * typically elects itself to be Monarch.
696 static void mce_reign(void)
699 struct mce *m = NULL;
700 int global_worst = 0;
705 * This CPU is the Monarch and the other CPUs have run
706 * through their handlers.
707 * Grade the severity of the errors of all the CPUs.
709 for_each_possible_cpu(cpu) {
710 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
712 if (severity > global_worst) {
714 global_worst = severity;
715 m = &per_cpu(mces_seen, cpu);
720 * Cannot recover? Panic here then.
721 * This dumps all the mces in the log buffer and stops the
724 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
725 mce_panic("Fatal Machine check", m, msg);
728 * For UC somewhere we let the CPU who detects it handle it.
729 * Also must let continue the others, otherwise the handling
730 * CPU could deadlock on a lock.
734 * No machine check event found. Must be some external
735 * source or one CPU is hung. Panic.
737 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
738 mce_panic("Machine check from unknown source", NULL, NULL);
741 * Now clear all the mces_seen so that they don't reappear on
744 for_each_possible_cpu(cpu)
745 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
748 static atomic_t global_nwo;
751 * Start of Monarch synchronization. This waits until all CPUs have
752 * entered the exception handler and then determines if any of them
753 * saw a fatal event that requires panic. Then it executes them
754 * in the entry order.
755 * TBD double check parallel CPU hotunplug
757 static int mce_start(int *no_way_out)
760 int cpus = num_online_cpus();
761 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
766 atomic_add(*no_way_out, &global_nwo);
768 * global_nwo should be updated before mce_callin
771 order = atomic_inc_return(&mce_callin);
776 while (atomic_read(&mce_callin) != cpus) {
777 if (mce_timed_out(&timeout)) {
778 atomic_set(&global_nwo, 0);
785 * mce_callin should be read before global_nwo
791 * Monarch: Starts executing now, the others wait.
793 atomic_set(&mce_executing, 1);
796 * Subject: Now start the scanning loop one by one in
797 * the original callin order.
798 * This way when there are any shared banks it will be
799 * only seen by one CPU before cleared, avoiding duplicates.
801 while (atomic_read(&mce_executing) < order) {
802 if (mce_timed_out(&timeout)) {
803 atomic_set(&global_nwo, 0);
811 * Cache the global no_way_out state.
813 *no_way_out = atomic_read(&global_nwo);
819 * Synchronize between CPUs after main scanning loop.
820 * This invokes the bulk of the Monarch processing.
822 static int mce_end(int order)
825 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
833 * Allow others to run.
835 atomic_inc(&mce_executing);
838 /* CHECKME: Can this race with a parallel hotplug? */
839 int cpus = num_online_cpus();
842 * Monarch: Wait for everyone to go through their scanning
845 while (atomic_read(&mce_executing) <= cpus) {
846 if (mce_timed_out(&timeout))
856 * Subject: Wait for Monarch to finish.
858 while (atomic_read(&mce_executing) != 0) {
859 if (mce_timed_out(&timeout))
865 * Don't reset anything. That's done by the Monarch.
871 * Reset all global state.
874 atomic_set(&global_nwo, 0);
875 atomic_set(&mce_callin, 0);
879 * Let others run again.
881 atomic_set(&mce_executing, 0);
886 * Check if the address reported by the CPU is in a format we can parse.
887 * It would be possible to add code for most other cases, but all would
888 * be somewhat complicated (e.g. segment offset would require an instruction
889 * parser). So only support physical addresses up to page granuality for now.
891 static int mce_usable_address(struct mce *m)
893 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
895 if ((m->misc & 0x3f) > PAGE_SHIFT)
897 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
902 static void mce_clear_state(unsigned long *toclear)
906 for (i = 0; i < banks; i++) {
907 if (test_bit(i, toclear))
908 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
913 * The actual machine check handler. This only handles real
914 * exceptions when something got corrupted coming in through int 18.
916 * This is executed in NMI context not subject to normal locking rules. This
917 * implies that most kernel services cannot be safely used. Don't even
918 * think about putting a printk in there!
920 * On Intel systems this is entered on all CPUs in parallel through
921 * MCE broadcast. However some CPUs might be broken beyond repair,
922 * so be always careful when synchronizing with others.
924 void do_machine_check(struct pt_regs *regs, long error_code)
926 struct mce m, *final;
931 * Establish sequential order between the CPUs entering the machine
936 * If no_way_out gets set, there is no safe way to recover from this
937 * MCE. If tolerant is cranked up, we'll try anyway.
941 * If kill_it gets set, there might be a way to recover from this
945 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
946 char *msg = "Unknown";
948 atomic_inc(&mce_entry);
950 percpu_inc(mce_exception_count);
952 if (notify_die(DIE_NMI, "machine check", regs, error_code,
953 18, SIGKILL) == NOTIFY_STOP)
960 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
961 final = &__get_cpu_var(mces_seen);
964 no_way_out = mce_no_way_out(&m, &msg);
969 * When no restart IP must always kill or panic.
971 if (!(m.mcgstatus & MCG_STATUS_RIPV))
975 * Go through all the banks in exclusion of the other CPUs.
976 * This way we don't report duplicated events on shared banks
977 * because the first one to see it will clear it.
979 order = mce_start(&no_way_out);
980 for (i = 0; i < banks; i++) {
981 __clear_bit(i, toclear);
982 if (!mce_banks[i].ctl)
989 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
990 if ((m.status & MCI_STATUS_VAL) == 0)
994 * Non uncorrected or non signaled errors are handled by
995 * machine_check_poll. Leave them alone, unless this panics.
997 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1002 * Set taint even when machine check was not enabled.
1004 add_taint(TAINT_MACHINE_CHECK);
1006 severity = mce_severity(&m, tolerant, NULL);
1009 * When machine check was for corrected handler don't touch,
1010 * unless we're panicing.
1012 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1014 __set_bit(i, toclear);
1015 if (severity == MCE_NO_SEVERITY) {
1017 * Machine check event was not enabled. Clear, but
1024 * Kill on action required.
1026 if (severity == MCE_AR_SEVERITY)
1029 if (m.status & MCI_STATUS_MISCV)
1030 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1031 if (m.status & MCI_STATUS_ADDRV)
1032 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1035 * Action optional error. Queue address for later processing.
1036 * When the ring overflows we just ignore the AO error.
1037 * RED-PEN add some logging mechanism when
1038 * usable_address or mce_add_ring fails.
1039 * RED-PEN don't ignore overflow for tolerant == 0
1041 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1042 mce_ring_add(m.addr >> PAGE_SHIFT);
1044 mce_get_rip(&m, regs);
1047 if (severity > worst) {
1054 mce_clear_state(toclear);
1057 * Do most of the synchronization with other CPUs.
1058 * When there's any problem use only local no_way_out state.
1060 if (mce_end(order) < 0)
1061 no_way_out = worst >= MCE_PANIC_SEVERITY;
1064 * If we have decided that we just CAN'T continue, and the user
1065 * has not set tolerant to an insane level, give up and die.
1067 * This is mainly used in the case when the system doesn't
1068 * support MCE broadcasting or it has been disabled.
1070 if (no_way_out && tolerant < 3)
1071 mce_panic("Fatal machine check on current CPU", final, msg);
1074 * If the error seems to be unrecoverable, something should be
1075 * done. Try to kill as little as possible. If we can kill just
1076 * one task, do that. If the user has set the tolerance very
1077 * high, don't try to do anything at all.
1080 if (kill_it && tolerant < 3)
1081 force_sig(SIGBUS, current);
1083 /* notify userspace ASAP */
1084 set_thread_flag(TIF_MCE_NOTIFY);
1087 mce_report_event(regs);
1088 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1090 atomic_dec(&mce_entry);
1093 EXPORT_SYMBOL_GPL(do_machine_check);
1095 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1096 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1098 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1102 * Called after mce notification in process context. This code
1103 * is allowed to sleep. Call the high level VM handler to process
1104 * any corrupted pages.
1105 * Assume that the work queue code only calls this one at a time
1107 * Note we don't disable preemption, so this code might run on the wrong
1108 * CPU. In this case the event is picked up by the scheduled work queue.
1109 * This is merely a fast path to expedite processing in some common
1112 void mce_notify_process(void)
1116 while (mce_ring_get(&pfn))
1117 memory_failure(pfn, MCE_VECTOR);
1120 static void mce_process_work(struct work_struct *dummy)
1122 mce_notify_process();
1125 #ifdef CONFIG_X86_MCE_INTEL
1127 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1128 * @cpu: The CPU on which the event occurred.
1129 * @status: Event status information
1131 * This function should be called by the thermal interrupt after the
1132 * event has been processed and the decision was made to log the event
1135 * The status parameter will be saved to the 'status' field of 'struct mce'
1136 * and historically has been the register value of the
1137 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1139 void mce_log_therm_throt_event(__u64 status)
1144 m.bank = MCE_THERMAL_BANK;
1148 #endif /* CONFIG_X86_MCE_INTEL */
1151 * Periodic polling timer for "silent" machine check errors. If the
1152 * poller finds an MCE, poll 2x faster. When the poller finds no more
1153 * errors, poll 2x slower (up to check_interval seconds).
1155 * We will disable polling in DOM0 since all CMCI/Polling
1156 * mechanism will be done in XEN for Intel CPUs
1158 #if defined (CONFIG_X86_XEN_MCE)
1159 static int check_interval = 0; /* disable polling */
1161 static int check_interval = 5 * 60; /* 5 minutes */
1164 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1165 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1167 static void mce_start_timer(unsigned long data)
1169 struct timer_list *t = &per_cpu(mce_timer, data);
1172 WARN_ON(smp_processor_id() != data);
1174 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1175 machine_check_poll(MCP_TIMESTAMP,
1176 &__get_cpu_var(mce_poll_banks));
1180 * Alert userspace if needed. If we logged an MCE, reduce the
1181 * polling interval, otherwise increase the polling interval.
1183 n = &__get_cpu_var(mce_next_interval);
1184 if (mce_notify_irq())
1185 *n = max(*n/2, HZ/100);
1187 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1189 t->expires = jiffies + *n;
1190 add_timer_on(t, smp_processor_id());
1193 static void mce_do_trigger(struct work_struct *work)
1195 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1198 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1201 * Notify the user(s) about new machine check events.
1202 * Can be called from interrupt context, but not from machine check/NMI
1205 int mce_notify_irq(void)
1207 /* Not more than two messages every minute */
1208 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1210 clear_thread_flag(TIF_MCE_NOTIFY);
1212 if (test_and_clear_bit(0, &mce_need_notify)) {
1213 wake_up_interruptible(&mce_wait);
1216 * There is no risk of missing notifications because
1217 * work_pending is always cleared before the function is
1220 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1221 schedule_work(&mce_trigger_work);
1223 if (__ratelimit(&ratelimit))
1224 pr_info(HW_ERR "Machine check events logged\n");
1230 EXPORT_SYMBOL_GPL(mce_notify_irq);
1232 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1236 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1239 for (i = 0; i < banks; i++) {
1240 struct mce_bank *b = &mce_banks[i];
1249 * Initialize Machine Checks for a CPU.
1251 static int __cpuinit __mcheck_cpu_cap_init(void)
1256 rdmsrl(MSR_IA32_MCG_CAP, cap);
1258 b = cap & MCG_BANKCNT_MASK;
1260 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1262 if (b > MAX_NR_BANKS) {
1264 "MCE: Using only %u machine check banks out of %u\n",
1269 /* Don't support asymmetric configurations today */
1270 WARN_ON(banks != 0 && b != banks);
1273 int err = __mcheck_cpu_mce_banks_init();
1279 /* Use accurate RIP reporting if available. */
1280 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1281 rip_msr = MSR_IA32_MCG_EIP;
1283 if (cap & MCG_SER_P)
1289 static void __mcheck_cpu_init_generic(void)
1291 mce_banks_t all_banks;
1296 * Log the machine checks left over from the previous reset.
1298 bitmap_fill(all_banks, MAX_NR_BANKS);
1299 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1301 set_in_cr4(X86_CR4_MCE);
1303 rdmsrl(MSR_IA32_MCG_CAP, cap);
1304 if (cap & MCG_CTL_P)
1305 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1307 for (i = 0; i < banks; i++) {
1308 struct mce_bank *b = &mce_banks[i];
1312 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1313 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1317 /* Add per CPU specific workarounds here */
1318 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1320 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1321 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1325 /* This should be disabled by the BIOS, but isn't always */
1326 if (c->x86_vendor == X86_VENDOR_AMD) {
1328 if (c->x86 == 15 && banks > 4) {
1330 * disable GART TBL walk error reporting, which
1331 * trips off incorrectly with the IOMMU & 3ware
1334 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1337 if (c->x86 <= 17 && mce_bootlog < 0) {
1339 * Lots of broken BIOS around that don't clear them
1340 * by default and leave crap in there. Don't log:
1345 * Various K7s with broken bank 0 around. Always disable
1348 if (c->x86 == 6 && banks > 0)
1349 mce_banks[0].ctl = 0;
1352 if (c->x86_vendor == X86_VENDOR_INTEL) {
1354 * SDM documents that on family 6 bank 0 should not be written
1355 * because it aliases to another special BIOS controlled
1357 * But it's not aliased anymore on model 0x1a+
1358 * Don't ignore bank 0 completely because there could be a
1359 * valid event later, merely don't write CTL0.
1362 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1363 mce_banks[0].init = 0;
1366 * All newer Intel systems support MCE broadcasting. Enable
1367 * synchronization with a one second timeout.
1369 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1370 monarch_timeout < 0)
1371 monarch_timeout = USEC_PER_SEC;
1374 * There are also broken BIOSes on some Pentium M and
1377 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1380 if (monarch_timeout < 0)
1381 monarch_timeout = 0;
1382 if (mce_bootlog != 0)
1383 mce_panic_timeout = 30;
1388 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1392 switch (c->x86_vendor) {
1393 case X86_VENDOR_INTEL:
1394 intel_p5_mcheck_init(c);
1396 case X86_VENDOR_CENTAUR:
1397 winchip_mcheck_init(c);
1402 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1404 #ifndef CONFIG_X86_64_XEN
1405 switch (c->x86_vendor) {
1406 case X86_VENDOR_INTEL:
1407 mce_intel_feature_init(c);
1409 case X86_VENDOR_AMD:
1410 mce_amd_feature_init(c);
1418 static void __mcheck_cpu_init_timer(void)
1420 struct timer_list *t = &__get_cpu_var(mce_timer);
1421 int *n = &__get_cpu_var(mce_next_interval);
1423 setup_timer(t, mce_start_timer, smp_processor_id());
1428 *n = check_interval * HZ;
1431 t->expires = round_jiffies(jiffies + *n);
1432 add_timer_on(t, smp_processor_id());
1435 /* Handle unconfigured int18 (should never happen) */
1436 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1438 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1439 smp_processor_id());
1442 /* Call the installed machine check handler for this CPU setup. */
1443 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1444 unexpected_machine_check;
1447 * Called for each booted CPU to set up machine checks.
1448 * Must be called with preempt off:
1450 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1455 __mcheck_cpu_ancient_init(c);
1457 if (!mce_available(c))
1460 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1465 machine_check_vector = do_machine_check;
1467 __mcheck_cpu_init_generic();
1468 __mcheck_cpu_init_vendor(c);
1469 __mcheck_cpu_init_timer();
1470 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1475 * Character device to read and clear the MCE log.
1478 static DEFINE_SPINLOCK(mce_state_lock);
1479 static int open_count; /* #times opened */
1480 static int open_exclu; /* already open exclusive? */
1482 static int mce_open(struct inode *inode, struct file *file)
1484 spin_lock(&mce_state_lock);
1486 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1487 spin_unlock(&mce_state_lock);
1492 if (file->f_flags & O_EXCL)
1496 spin_unlock(&mce_state_lock);
1498 return nonseekable_open(inode, file);
1501 static int mce_release(struct inode *inode, struct file *file)
1503 spin_lock(&mce_state_lock);
1508 spin_unlock(&mce_state_lock);
1513 static void collect_tscs(void *data)
1515 unsigned long *cpu_tsc = (unsigned long *)data;
1517 rdtscll(cpu_tsc[smp_processor_id()]);
1520 static int mce_apei_read_done;
1522 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1523 static int __mce_read_apei(char __user **ubuf, size_t usize)
1529 if (usize < sizeof(struct mce))
1532 rc = apei_read_mce(&m, &record_id);
1533 /* Error or no more MCE record */
1535 mce_apei_read_done = 1;
1539 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1542 * In fact, we should have cleared the record after that has
1543 * been flushed to the disk or sent to network in
1544 * /sbin/mcelog, but we have no interface to support that now,
1545 * so just clear it to avoid duplication.
1547 rc = apei_clear_mce(record_id);
1549 mce_apei_read_done = 1;
1552 *ubuf += sizeof(struct mce);
1557 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1560 char __user *buf = ubuf;
1561 unsigned long *cpu_tsc;
1562 unsigned prev, next;
1565 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1569 mutex_lock(&mce_read_mutex);
1571 if (!mce_apei_read_done) {
1572 err = __mce_read_apei(&buf, usize);
1573 if (err || buf != ubuf)
1577 next = rcu_dereference_check_mce(mcelog.next);
1579 /* Only supports full reads right now */
1581 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1587 for (i = prev; i < next; i++) {
1588 unsigned long start = jiffies;
1590 while (!mcelog.entry[i].finished) {
1591 if (time_after_eq(jiffies, start + 2)) {
1592 memset(mcelog.entry + i, 0,
1593 sizeof(struct mce));
1599 err |= copy_to_user(buf, mcelog.entry + i,
1600 sizeof(struct mce));
1601 buf += sizeof(struct mce);
1606 memset(mcelog.entry + prev, 0,
1607 (next - prev) * sizeof(struct mce));
1609 next = cmpxchg(&mcelog.next, prev, 0);
1610 } while (next != prev);
1612 synchronize_sched();
1615 * Collect entries that were still getting written before the
1618 on_each_cpu(collect_tscs, cpu_tsc, 1);
1620 for (i = next; i < MCE_LOG_LEN; i++) {
1621 if (mcelog.entry[i].finished &&
1622 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1623 err |= copy_to_user(buf, mcelog.entry+i,
1624 sizeof(struct mce));
1626 buf += sizeof(struct mce);
1627 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1635 mutex_unlock(&mce_read_mutex);
1638 return err ? err : buf - ubuf;
1641 static unsigned int mce_poll(struct file *file, poll_table *wait)
1643 poll_wait(file, &mce_wait, wait);
1644 if (rcu_access_index(mcelog.next))
1645 return POLLIN | POLLRDNORM;
1646 if (!mce_apei_read_done && apei_check_mce())
1647 return POLLIN | POLLRDNORM;
1651 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1653 int __user *p = (int __user *)arg;
1655 if (!capable(CAP_SYS_ADMIN))
1659 case MCE_GET_RECORD_LEN:
1660 return put_user(sizeof(struct mce), p);
1661 case MCE_GET_LOG_LEN:
1662 return put_user(MCE_LOG_LEN, p);
1663 case MCE_GETCLEAR_FLAGS: {
1667 flags = mcelog.flags;
1668 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1670 return put_user(flags, p);
1677 /* Modified in mce-inject.c, so not static or const */
1678 struct file_operations mce_chrdev_ops = {
1680 .release = mce_release,
1683 .unlocked_ioctl = mce_ioctl,
1684 .llseek = no_llseek,
1686 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1688 static struct miscdevice mce_log_device = {
1695 * mce=off Disables machine check
1696 * mce=no_cmci Disables CMCI
1697 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1698 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1699 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1700 * monarchtimeout is how long to wait for other CPUs on machine
1701 * check, or 0 to not wait
1702 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1703 * mce=nobootlog Don't log MCEs from before booting.
1705 static int __init mcheck_enable(char *str)
1713 if (!strcmp(str, "off"))
1715 else if (!strcmp(str, "no_cmci"))
1716 mce_cmci_disabled = 1;
1717 else if (!strcmp(str, "dont_log_ce"))
1718 mce_dont_log_ce = 1;
1719 else if (!strcmp(str, "ignore_ce"))
1721 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1722 mce_bootlog = (str[0] == 'b');
1723 else if (isdigit(str[0])) {
1724 get_option(&str, &tolerant);
1727 get_option(&str, &monarch_timeout);
1730 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1736 __setup("mce", mcheck_enable);
1738 int __init mcheck_init(void)
1740 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1742 mcheck_intel_therm_init();
1752 * Disable machine checks on suspend and shutdown. We can't really handle
1755 static int mce_disable_error_reporting(void)
1759 for (i = 0; i < banks; i++) {
1760 struct mce_bank *b = &mce_banks[i];
1763 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1768 static int mce_suspend(void)
1770 return mce_disable_error_reporting();
1773 static void mce_shutdown(void)
1775 mce_disable_error_reporting();
1779 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1780 * Only one CPU is active at this time, the others get re-added later using
1783 static void mce_resume(void)
1785 __mcheck_cpu_init_generic();
1786 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1789 static struct syscore_ops mce_syscore_ops = {
1790 .suspend = mce_suspend,
1791 .shutdown = mce_shutdown,
1792 .resume = mce_resume,
1795 static void mce_cpu_restart(void *data)
1797 del_timer_sync(&__get_cpu_var(mce_timer));
1798 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1800 __mcheck_cpu_init_generic();
1801 __mcheck_cpu_init_timer();
1804 /* Reinit MCEs after user configuration changes */
1805 static void mce_restart(void)
1807 on_each_cpu(mce_cpu_restart, NULL, 1);
1810 /* Toggle features for corrected errors */
1811 static void mce_disable_ce(void *all)
1813 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1816 del_timer_sync(&__get_cpu_var(mce_timer));
1820 static void mce_enable_ce(void *all)
1822 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1827 __mcheck_cpu_init_timer();
1830 static struct sysdev_class mce_sysclass = {
1831 .name = "machinecheck",
1834 DEFINE_PER_CPU(struct sys_device, mce_dev);
1837 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1839 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1841 return container_of(attr, struct mce_bank, attr);
1844 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1847 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1850 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1851 const char *buf, size_t size)
1855 if (strict_strtoull(buf, 0, &new) < 0)
1858 attr_to_bank(attr)->ctl = new;
1865 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1867 strcpy(buf, mce_helper);
1869 return strlen(mce_helper) + 1;
1872 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1873 const char *buf, size_t siz)
1877 strncpy(mce_helper, buf, sizeof(mce_helper));
1878 mce_helper[sizeof(mce_helper)-1] = 0;
1879 p = strchr(mce_helper, '\n');
1884 return strlen(mce_helper) + !!p;
1887 static ssize_t set_ignore_ce(struct sys_device *s,
1888 struct sysdev_attribute *attr,
1889 const char *buf, size_t size)
1893 if (strict_strtoull(buf, 0, &new) < 0)
1896 if (mce_ignore_ce ^ !!new) {
1898 /* disable ce features */
1899 on_each_cpu(mce_disable_ce, (void *)1, 1);
1902 /* enable ce features */
1904 on_each_cpu(mce_enable_ce, (void *)1, 1);
1910 static ssize_t set_cmci_disabled(struct sys_device *s,
1911 struct sysdev_attribute *attr,
1912 const char *buf, size_t size)
1916 if (strict_strtoull(buf, 0, &new) < 0)
1919 if (mce_cmci_disabled ^ !!new) {
1922 on_each_cpu(mce_disable_ce, NULL, 1);
1923 mce_cmci_disabled = 1;
1926 mce_cmci_disabled = 0;
1927 on_each_cpu(mce_enable_ce, NULL, 1);
1933 static ssize_t store_int_with_restart(struct sys_device *s,
1934 struct sysdev_attribute *attr,
1935 const char *buf, size_t size)
1937 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1942 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1943 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1944 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1945 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1947 static struct sysdev_ext_attribute attr_check_interval = {
1948 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1949 store_int_with_restart),
1953 static struct sysdev_ext_attribute attr_ignore_ce = {
1954 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1958 static struct sysdev_ext_attribute attr_cmci_disabled = {
1959 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1963 static struct sysdev_attribute *mce_attrs[] = {
1964 &attr_tolerant.attr,
1965 &attr_check_interval.attr,
1967 &attr_monarch_timeout.attr,
1968 &attr_dont_log_ce.attr,
1969 &attr_ignore_ce.attr,
1970 &attr_cmci_disabled.attr,
1974 static cpumask_var_t mce_dev_initialized;
1976 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1977 static __cpuinit int mce_create_device(unsigned int cpu)
1982 if (!mce_available(&boot_cpu_data))
1985 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1986 per_cpu(mce_dev, cpu).id = cpu;
1987 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1989 err = sysdev_register(&per_cpu(mce_dev, cpu));
1993 for (i = 0; mce_attrs[i]; i++) {
1994 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1998 for (j = 0; j < banks; j++) {
1999 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
2000 &mce_banks[j].attr);
2004 cpumask_set_cpu(cpu, mce_dev_initialized);
2009 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
2012 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2014 sysdev_unregister(&per_cpu(mce_dev, cpu));
2019 static __cpuinit void mce_remove_device(unsigned int cpu)
2023 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2026 for (i = 0; mce_attrs[i]; i++)
2027 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2029 for (i = 0; i < banks; i++)
2030 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2032 sysdev_unregister(&per_cpu(mce_dev, cpu));
2033 cpumask_clear_cpu(cpu, mce_dev_initialized);
2036 /* Make sure there are no machine checks on offlined CPUs. */
2037 static void __cpuinit mce_disable_cpu(void *h)
2039 unsigned long action = *(unsigned long *)h;
2042 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2045 if (!(action & CPU_TASKS_FROZEN))
2047 for (i = 0; i < banks; i++) {
2048 struct mce_bank *b = &mce_banks[i];
2051 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2055 static void __cpuinit mce_reenable_cpu(void *h)
2057 unsigned long action = *(unsigned long *)h;
2060 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2063 if (!(action & CPU_TASKS_FROZEN))
2065 for (i = 0; i < banks; i++) {
2066 struct mce_bank *b = &mce_banks[i];
2069 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2073 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2074 static int __cpuinit
2075 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2077 unsigned int cpu = (unsigned long)hcpu;
2078 struct timer_list *t = &per_cpu(mce_timer, cpu);
2082 case CPU_ONLINE_FROZEN:
2083 mce_create_device(cpu);
2084 if (threshold_cpu_callback)
2085 threshold_cpu_callback(action, cpu);
2088 case CPU_DEAD_FROZEN:
2089 if (threshold_cpu_callback)
2090 threshold_cpu_callback(action, cpu);
2091 mce_remove_device(cpu);
2093 case CPU_DOWN_PREPARE:
2094 case CPU_DOWN_PREPARE_FROZEN:
2096 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2098 case CPU_DOWN_FAILED:
2099 case CPU_DOWN_FAILED_FROZEN:
2100 if (!mce_ignore_ce && check_interval) {
2101 t->expires = round_jiffies(jiffies +
2102 __get_cpu_var(mce_next_interval));
2103 add_timer_on(t, cpu);
2105 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2108 /* intentionally ignoring frozen here */
2109 cmci_rediscover(cpu);
2115 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2116 .notifier_call = mce_cpu_callback,
2119 static __init void mce_init_banks(void)
2123 for (i = 0; i < banks; i++) {
2124 struct mce_bank *b = &mce_banks[i];
2125 struct sysdev_attribute *a = &b->attr;
2127 sysfs_attr_init(&a->attr);
2128 a->attr.name = b->attrname;
2129 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2131 a->attr.mode = 0644;
2132 a->show = show_bank;
2133 a->store = set_bank;
2137 static __init int mcheck_init_device(void)
2142 if (!mce_available(&boot_cpu_data))
2145 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2149 err = sysdev_class_register(&mce_sysclass);
2153 for_each_online_cpu(i) {
2154 err = mce_create_device(i);
2159 register_syscore_ops(&mce_syscore_ops);
2160 register_hotcpu_notifier(&mce_cpu_notifier);
2161 misc_register(&mce_log_device);
2163 #ifdef CONFIG_X86_XEN_MCE
2164 if (is_initial_xendomain()) {
2165 /* Register vIRQ handler for MCE LOG processing */
2166 extern int bind_virq_for_mce(void);
2168 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2169 bind_virq_for_mce();
2176 device_initcall(mcheck_init_device);
2179 * Old style boot options parsing. Only for compatibility.
2181 static int __init mcheck_disable(char *str)
2186 __setup("nomce", mcheck_disable);
2188 #ifdef CONFIG_DEBUG_FS
2189 struct dentry *mce_get_debugfs_dir(void)
2191 static struct dentry *dmce;
2194 dmce = debugfs_create_dir("mce", NULL);
2199 static void mce_reset(void)
2202 atomic_set(&mce_fake_paniced, 0);
2203 atomic_set(&mce_executing, 0);
2204 atomic_set(&mce_callin, 0);
2205 atomic_set(&global_nwo, 0);
2208 static int fake_panic_get(void *data, u64 *val)
2214 static int fake_panic_set(void *data, u64 val)
2221 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2222 fake_panic_set, "%llu\n");
2224 static int __init mcheck_debugfs_init(void)
2226 struct dentry *dmce, *ffake_panic;
2228 dmce = mce_get_debugfs_dir();
2231 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2238 late_initcall(mcheck_debugfs_init);