2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
105 /* MCA banks polled by the period polling timer for corrected events */
106 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce *m)
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
124 m->socketid = cpu_data(m->extcpu).phys_proc_id;
126 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
131 DEFINE_PER_CPU(struct mce, injectm);
132 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
135 * Lockless MCE logging infrastructure.
136 * This avoids deadlocks on printk locks without having to break locks. Also
137 * separate MCEs from kernel messages to avoid bogus bug reports.
140 static struct mce_log mcelog = {
141 .signature = MCE_LOG_SIGNATURE,
143 .recordlen = sizeof(struct mce),
146 void mce_log(struct mce *mce)
148 unsigned next, entry;
151 /* Emit the trace record: */
152 trace_mce_record(mce);
154 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
155 if (ret == NOTIFY_STOP)
161 entry = rcu_dereference_check_mce(mcelog.next);
165 * When the buffer fills up discard new entries.
166 * Assume that the earlier errors are the more
169 if (entry >= MCE_LOG_LEN) {
170 set_bit(MCE_OVERFLOW,
171 (unsigned long *)&mcelog.flags);
174 /* Old left over entry. Skip: */
175 if (mcelog.entry[entry].finished) {
183 if (cmpxchg(&mcelog.next, entry, next) == entry)
186 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
188 mcelog.entry[entry].finished = 1;
192 set_bit(0, &mce_need_notify);
195 static void print_mce(struct mce *m)
199 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
200 m->extcpu, m->mcgstatus, m->bank, m->status);
203 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
204 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
207 if (m->cs == __KERNEL_CS)
208 print_symbol("{%s}", m->ip);
212 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
214 pr_cont("ADDR %llx ", m->addr);
216 pr_cont("MISC %llx ", m->misc);
220 * Note this output is parsed by external tools and old fields
221 * should not be changed.
224 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
225 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
226 cpu_data(m->extcpu).microcode);
228 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
229 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
233 * Print out human-readable details about the MCE error,
234 * (if the CPU has an implementation for that)
236 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
237 if (ret == NOTIFY_STOP)
240 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
243 #define PANIC_TIMEOUT 5 /* 5 seconds */
245 static atomic_t mce_paniced;
247 static int fake_panic;
248 static atomic_t mce_fake_paniced;
250 /* Panic in progress. Enable interrupts and wait for final IPI */
251 static void wait_for_panic(void)
253 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
257 while (timeout-- > 0)
259 if (panic_timeout == 0)
260 panic_timeout = mce_panic_timeout;
261 panic("Panicing machine check CPU died");
264 static void mce_panic(char *msg, struct mce *final, char *exp)
270 * Make sure only one CPU runs in machine check panic
272 if (atomic_inc_return(&mce_paniced) > 1)
279 /* Don't log too much for fake panic */
280 if (atomic_inc_return(&mce_fake_paniced) > 1)
283 /* First print corrected ones that are still unlogged */
284 for (i = 0; i < MCE_LOG_LEN; i++) {
285 struct mce *m = &mcelog.entry[i];
286 if (!(m->status & MCI_STATUS_VAL))
288 if (!(m->status & MCI_STATUS_UC)) {
291 apei_err = apei_write_mce(m);
294 /* Now print uncorrected but with the final one last */
295 for (i = 0; i < MCE_LOG_LEN; i++) {
296 struct mce *m = &mcelog.entry[i];
297 if (!(m->status & MCI_STATUS_VAL))
299 if (!(m->status & MCI_STATUS_UC))
301 if (!final || memcmp(m, final, sizeof(struct mce))) {
304 apei_err = apei_write_mce(m);
310 apei_err = apei_write_mce(final);
313 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
315 pr_emerg(HW_ERR "Machine check: %s\n", exp);
317 if (panic_timeout == 0)
318 panic_timeout = mce_panic_timeout;
321 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
324 /* Support code for software error injection */
326 static int msr_to_offset(u32 msr)
328 unsigned bank = __this_cpu_read(injectm.bank);
331 return offsetof(struct mce, ip);
332 if (msr == MSR_IA32_MCx_STATUS(bank))
333 return offsetof(struct mce, status);
334 if (msr == MSR_IA32_MCx_ADDR(bank))
335 return offsetof(struct mce, addr);
336 if (msr == MSR_IA32_MCx_MISC(bank))
337 return offsetof(struct mce, misc);
338 if (msr == MSR_IA32_MCG_STATUS)
339 return offsetof(struct mce, mcgstatus);
343 /* MSR access wrappers used for error injection */
344 static u64 mce_rdmsrl(u32 msr)
348 if (__this_cpu_read(injectm.finished)) {
349 int offset = msr_to_offset(msr);
353 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
356 if (rdmsrl_safe(msr, &v)) {
357 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
359 * Return zero in case the access faulted. This should
360 * not happen normally but can happen if the CPU does
361 * something weird, or if the code is buggy.
369 static void mce_wrmsrl(u32 msr, u64 v)
371 if (__this_cpu_read(injectm.finished)) {
372 int offset = msr_to_offset(msr);
375 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
382 * Collect all global (w.r.t. this processor) status about this machine
383 * check into our "mce" struct so that we can use it later to assess
384 * the severity of the problem as we read per-bank specific details.
386 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
390 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
393 * Get the address of the instruction at the time of
394 * the machine check error.
396 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
400 /* Use accurate RIP reporting if available. */
402 m->ip = mce_rdmsrl(rip_msr);
407 * Simple lockless ring to communicate PFNs from the exception handler with the
408 * process context work function. This is vastly simplified because there's
409 * only a single reader and a single writer.
411 #define MCE_RING_SIZE 16 /* we use one entry less */
414 unsigned short start;
416 unsigned long ring[MCE_RING_SIZE];
418 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
420 /* Runs with CPU affinity in workqueue */
421 static int mce_ring_empty(void)
423 struct mce_ring *r = &__get_cpu_var(mce_ring);
425 return r->start == r->end;
428 static int mce_ring_get(unsigned long *pfn)
435 r = &__get_cpu_var(mce_ring);
436 if (r->start == r->end)
438 *pfn = r->ring[r->start];
439 r->start = (r->start + 1) % MCE_RING_SIZE;
446 /* Always runs in MCE context with preempt off */
447 static int mce_ring_add(unsigned long pfn)
449 struct mce_ring *r = &__get_cpu_var(mce_ring);
452 next = (r->end + 1) % MCE_RING_SIZE;
453 if (next == r->start)
455 r->ring[r->end] = pfn;
461 int mce_available(struct cpuinfo_x86 *c)
465 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
468 static void mce_schedule_work(void)
470 if (!mce_ring_empty()) {
471 struct work_struct *work = &__get_cpu_var(mce_work);
472 if (!work_pending(work))
477 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
479 static void mce_irq_work_cb(struct irq_work *entry)
485 static void mce_report_event(struct pt_regs *regs)
487 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
490 * Triggering the work queue here is just an insurance
491 * policy in case the syscall exit notify handler
492 * doesn't run soon enough or ends up running on the
493 * wrong CPU (can happen when audit sleeps)
499 irq_work_queue(&__get_cpu_var(mce_irq_work));
502 DEFINE_PER_CPU(unsigned, mce_poll_count);
505 * Poll for corrected events or events that happened before reset.
506 * Those are just logged through /dev/mcelog.
508 * This is executed in standard interrupt context.
510 * Note: spec recommends to panic for fatal unsignalled
511 * errors here. However this would be quite problematic --
512 * we would need to reimplement the Monarch handling and
513 * it would mess up the exclusion between exception handler
514 * and poll hander -- * so we skip this for now.
515 * These cases should not happen anyways, or only when the CPU
516 * is already totally * confused. In this case it's likely it will
517 * not fully execute the machine check handler either.
519 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
524 percpu_inc(mce_poll_count);
526 mce_gather_info(&m, NULL);
528 for (i = 0; i < banks; i++) {
529 if (!mce_banks[i].ctl || !test_bit(i, *b))
538 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
539 if (!(m.status & MCI_STATUS_VAL))
543 * Uncorrected or signalled events are handled by the exception
544 * handler when it is enabled, so don't process those here.
546 * TBD do the same check for MCI_STATUS_EN here?
548 if (!(flags & MCP_UC) &&
549 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
552 if (m.status & MCI_STATUS_MISCV)
553 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
554 if (m.status & MCI_STATUS_ADDRV)
555 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
557 if (!(flags & MCP_TIMESTAMP))
560 * Don't get the IP here because it's unlikely to
561 * have anything to do with the actual error location.
563 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
567 * Clear state for this bank.
569 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
573 * Don't clear MCG_STATUS here because it's only defined for
579 EXPORT_SYMBOL_GPL(machine_check_poll);
582 * Do a quick check if any of the events requires a panic.
583 * This decides if we keep the events around or clear them.
585 static int mce_no_way_out(struct mce *m, char **msg)
589 for (i = 0; i < banks; i++) {
590 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
591 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
598 * Variable to establish order between CPUs while scanning.
599 * Each CPU spins initially until executing is equal its number.
601 static atomic_t mce_executing;
604 * Defines order of CPUs on entry. First CPU becomes Monarch.
606 static atomic_t mce_callin;
609 * Check if a timeout waiting for other CPUs happened.
611 static int mce_timed_out(u64 *t)
614 * The others already did panic for some reason.
615 * Bail out like in a timeout.
616 * rmb() to tell the compiler that system_state
617 * might have been modified by someone else.
620 if (atomic_read(&mce_paniced))
622 if (!monarch_timeout)
624 if ((s64)*t < SPINUNIT) {
625 /* CHECKME: Make panic default for 1 too? */
627 mce_panic("Timeout synchronizing machine check over CPUs",
634 touch_nmi_watchdog();
639 * The Monarch's reign. The Monarch is the CPU who entered
640 * the machine check handler first. It waits for the others to
641 * raise the exception too and then grades them. When any
642 * error is fatal panic. Only then let the others continue.
644 * The other CPUs entering the MCE handler will be controlled by the
645 * Monarch. They are called Subjects.
647 * This way we prevent any potential data corruption in a unrecoverable case
648 * and also makes sure always all CPU's errors are examined.
650 * Also this detects the case of a machine check event coming from outer
651 * space (not detected by any CPUs) In this case some external agent wants
652 * us to shut down, so panic too.
654 * The other CPUs might still decide to panic if the handler happens
655 * in a unrecoverable place, but in this case the system is in a semi-stable
656 * state and won't corrupt anything by itself. It's ok to let the others
657 * continue for a bit first.
659 * All the spin loops have timeouts; when a timeout happens a CPU
660 * typically elects itself to be Monarch.
662 static void mce_reign(void)
665 struct mce *m = NULL;
666 int global_worst = 0;
671 * This CPU is the Monarch and the other CPUs have run
672 * through their handlers.
673 * Grade the severity of the errors of all the CPUs.
675 for_each_possible_cpu(cpu) {
676 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
678 if (severity > global_worst) {
680 global_worst = severity;
681 m = &per_cpu(mces_seen, cpu);
686 * Cannot recover? Panic here then.
687 * This dumps all the mces in the log buffer and stops the
690 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
691 mce_panic("Fatal Machine check", m, msg);
694 * For UC somewhere we let the CPU who detects it handle it.
695 * Also must let continue the others, otherwise the handling
696 * CPU could deadlock on a lock.
700 * No machine check event found. Must be some external
701 * source or one CPU is hung. Panic.
703 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
704 mce_panic("Machine check from unknown source", NULL, NULL);
707 * Now clear all the mces_seen so that they don't reappear on
710 for_each_possible_cpu(cpu)
711 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
714 static atomic_t global_nwo;
717 * Start of Monarch synchronization. This waits until all CPUs have
718 * entered the exception handler and then determines if any of them
719 * saw a fatal event that requires panic. Then it executes them
720 * in the entry order.
721 * TBD double check parallel CPU hotunplug
723 static int mce_start(int *no_way_out)
726 int cpus = num_online_cpus();
727 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
732 atomic_add(*no_way_out, &global_nwo);
734 * global_nwo should be updated before mce_callin
737 order = atomic_inc_return(&mce_callin);
742 while (atomic_read(&mce_callin) != cpus) {
743 if (mce_timed_out(&timeout)) {
744 atomic_set(&global_nwo, 0);
751 * mce_callin should be read before global_nwo
757 * Monarch: Starts executing now, the others wait.
759 atomic_set(&mce_executing, 1);
762 * Subject: Now start the scanning loop one by one in
763 * the original callin order.
764 * This way when there are any shared banks it will be
765 * only seen by one CPU before cleared, avoiding duplicates.
767 while (atomic_read(&mce_executing) < order) {
768 if (mce_timed_out(&timeout)) {
769 atomic_set(&global_nwo, 0);
777 * Cache the global no_way_out state.
779 *no_way_out = atomic_read(&global_nwo);
785 * Synchronize between CPUs after main scanning loop.
786 * This invokes the bulk of the Monarch processing.
788 static int mce_end(int order)
791 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
799 * Allow others to run.
801 atomic_inc(&mce_executing);
804 /* CHECKME: Can this race with a parallel hotplug? */
805 int cpus = num_online_cpus();
808 * Monarch: Wait for everyone to go through their scanning
811 while (atomic_read(&mce_executing) <= cpus) {
812 if (mce_timed_out(&timeout))
822 * Subject: Wait for Monarch to finish.
824 while (atomic_read(&mce_executing) != 0) {
825 if (mce_timed_out(&timeout))
831 * Don't reset anything. That's done by the Monarch.
837 * Reset all global state.
840 atomic_set(&global_nwo, 0);
841 atomic_set(&mce_callin, 0);
845 * Let others run again.
847 atomic_set(&mce_executing, 0);
852 * Check if the address reported by the CPU is in a format we can parse.
853 * It would be possible to add code for most other cases, but all would
854 * be somewhat complicated (e.g. segment offset would require an instruction
855 * parser). So only support physical addresses up to page granuality for now.
857 static int mce_usable_address(struct mce *m)
859 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
861 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
863 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
868 static void mce_clear_state(unsigned long *toclear)
872 for (i = 0; i < banks; i++) {
873 if (test_bit(i, toclear))
874 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
879 * The actual machine check handler. This only handles real
880 * exceptions when something got corrupted coming in through int 18.
882 * This is executed in NMI context not subject to normal locking rules. This
883 * implies that most kernel services cannot be safely used. Don't even
884 * think about putting a printk in there!
886 * On Intel systems this is entered on all CPUs in parallel through
887 * MCE broadcast. However some CPUs might be broken beyond repair,
888 * so be always careful when synchronizing with others.
890 void do_machine_check(struct pt_regs *regs, long error_code)
892 struct mce m, *final;
897 * Establish sequential order between the CPUs entering the machine
902 * If no_way_out gets set, there is no safe way to recover from this
903 * MCE. If tolerant is cranked up, we'll try anyway.
907 * If kill_it gets set, there might be a way to recover from this
911 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
912 char *msg = "Unknown";
914 atomic_inc(&mce_entry);
916 percpu_inc(mce_exception_count);
921 mce_gather_info(&m, regs);
923 final = &__get_cpu_var(mces_seen);
926 no_way_out = mce_no_way_out(&m, &msg);
931 * When no restart IP must always kill or panic.
933 if (!(m.mcgstatus & MCG_STATUS_RIPV))
937 * Go through all the banks in exclusion of the other CPUs.
938 * This way we don't report duplicated events on shared banks
939 * because the first one to see it will clear it.
941 order = mce_start(&no_way_out);
942 for (i = 0; i < banks; i++) {
943 __clear_bit(i, toclear);
944 if (!mce_banks[i].ctl)
951 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
952 if ((m.status & MCI_STATUS_VAL) == 0)
956 * Non uncorrected or non signaled errors are handled by
957 * machine_check_poll. Leave them alone, unless this panics.
959 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
964 * Set taint even when machine check was not enabled.
966 add_taint(TAINT_MACHINE_CHECK);
968 severity = mce_severity(&m, tolerant, NULL);
971 * When machine check was for corrected handler don't touch,
972 * unless we're panicing.
974 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
976 __set_bit(i, toclear);
977 if (severity == MCE_NO_SEVERITY) {
979 * Machine check event was not enabled. Clear, but
986 * Kill on action required.
988 if (severity == MCE_AR_SEVERITY)
991 if (m.status & MCI_STATUS_MISCV)
992 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
993 if (m.status & MCI_STATUS_ADDRV)
994 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
997 * Action optional error. Queue address for later processing.
998 * When the ring overflows we just ignore the AO error.
999 * RED-PEN add some logging mechanism when
1000 * usable_address or mce_add_ring fails.
1001 * RED-PEN don't ignore overflow for tolerant == 0
1003 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1004 mce_ring_add(m.addr >> PAGE_SHIFT);
1008 if (severity > worst) {
1015 mce_clear_state(toclear);
1018 * Do most of the synchronization with other CPUs.
1019 * When there's any problem use only local no_way_out state.
1021 if (mce_end(order) < 0)
1022 no_way_out = worst >= MCE_PANIC_SEVERITY;
1025 * If we have decided that we just CAN'T continue, and the user
1026 * has not set tolerant to an insane level, give up and die.
1028 * This is mainly used in the case when the system doesn't
1029 * support MCE broadcasting or it has been disabled.
1031 if (no_way_out && tolerant < 3)
1032 mce_panic("Fatal machine check on current CPU", final, msg);
1035 * If the error seems to be unrecoverable, something should be
1036 * done. Try to kill as little as possible. If we can kill just
1037 * one task, do that. If the user has set the tolerance very
1038 * high, don't try to do anything at all.
1041 if (kill_it && tolerant < 3)
1042 force_sig(SIGBUS, current);
1044 /* notify userspace ASAP */
1045 set_thread_flag(TIF_MCE_NOTIFY);
1048 mce_report_event(regs);
1049 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1051 atomic_dec(&mce_entry);
1054 EXPORT_SYMBOL_GPL(do_machine_check);
1056 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1057 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1059 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1063 * Called after mce notification in process context. This code
1064 * is allowed to sleep. Call the high level VM handler to process
1065 * any corrupted pages.
1066 * Assume that the work queue code only calls this one at a time
1068 * Note we don't disable preemption, so this code might run on the wrong
1069 * CPU. In this case the event is picked up by the scheduled work queue.
1070 * This is merely a fast path to expedite processing in some common
1073 void mce_notify_process(void)
1077 while (mce_ring_get(&pfn))
1078 memory_failure(pfn, MCE_VECTOR);
1081 static void mce_process_work(struct work_struct *dummy)
1083 mce_notify_process();
1086 #ifdef CONFIG_X86_MCE_INTEL
1088 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1089 * @cpu: The CPU on which the event occurred.
1090 * @status: Event status information
1092 * This function should be called by the thermal interrupt after the
1093 * event has been processed and the decision was made to log the event
1096 * The status parameter will be saved to the 'status' field of 'struct mce'
1097 * and historically has been the register value of the
1098 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1100 void mce_log_therm_throt_event(__u64 status)
1105 m.bank = MCE_THERMAL_BANK;
1109 #endif /* CONFIG_X86_MCE_INTEL */
1112 * Periodic polling timer for "silent" machine check errors. If the
1113 * poller finds an MCE, poll 2x faster. When the poller finds no more
1114 * errors, poll 2x slower (up to check_interval seconds).
1116 * We will disable polling in DOM0 since all CMCI/Polling
1117 * mechanism will be done in XEN for Intel CPUs
1119 #if defined (CONFIG_X86_XEN_MCE)
1120 static int check_interval = 0; /* disable polling */
1122 static int check_interval = 5 * 60; /* 5 minutes */
1125 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1126 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1128 static void mce_start_timer(unsigned long data)
1130 struct timer_list *t = &per_cpu(mce_timer, data);
1133 WARN_ON(smp_processor_id() != data);
1135 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1136 machine_check_poll(MCP_TIMESTAMP,
1137 &__get_cpu_var(mce_poll_banks));
1141 * Alert userspace if needed. If we logged an MCE, reduce the
1142 * polling interval, otherwise increase the polling interval.
1144 n = &__get_cpu_var(mce_next_interval);
1145 if (mce_notify_irq())
1146 *n = max(*n/2, HZ/100);
1148 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1150 t->expires = jiffies + *n;
1151 add_timer_on(t, smp_processor_id());
1154 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1155 static void mce_timer_delete_all(void)
1159 for_each_online_cpu(cpu)
1160 del_timer_sync(&per_cpu(mce_timer, cpu));
1163 static void mce_do_trigger(struct work_struct *work)
1165 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1168 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1171 * Notify the user(s) about new machine check events.
1172 * Can be called from interrupt context, but not from machine check/NMI
1175 int mce_notify_irq(void)
1177 /* Not more than two messages every minute */
1178 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1180 clear_thread_flag(TIF_MCE_NOTIFY);
1182 if (test_and_clear_bit(0, &mce_need_notify)) {
1183 /* wake processes polling /dev/mcelog */
1184 wake_up_interruptible(&mce_chrdev_wait);
1187 * There is no risk of missing notifications because
1188 * work_pending is always cleared before the function is
1191 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1192 schedule_work(&mce_trigger_work);
1194 if (__ratelimit(&ratelimit))
1195 pr_info(HW_ERR "Machine check events logged\n");
1201 EXPORT_SYMBOL_GPL(mce_notify_irq);
1203 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1207 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1210 for (i = 0; i < banks; i++) {
1211 struct mce_bank *b = &mce_banks[i];
1220 * Initialize Machine Checks for a CPU.
1222 static int __cpuinit __mcheck_cpu_cap_init(void)
1227 rdmsrl(MSR_IA32_MCG_CAP, cap);
1229 b = cap & MCG_BANKCNT_MASK;
1231 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1233 if (b > MAX_NR_BANKS) {
1235 "MCE: Using only %u machine check banks out of %u\n",
1240 /* Don't support asymmetric configurations today */
1241 WARN_ON(banks != 0 && b != banks);
1244 int err = __mcheck_cpu_mce_banks_init();
1250 /* Use accurate RIP reporting if available. */
1251 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1252 rip_msr = MSR_IA32_MCG_EIP;
1254 if (cap & MCG_SER_P)
1260 static void __mcheck_cpu_init_generic(void)
1262 mce_banks_t all_banks;
1267 * Log the machine checks left over from the previous reset.
1269 bitmap_fill(all_banks, MAX_NR_BANKS);
1270 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1272 set_in_cr4(X86_CR4_MCE);
1274 rdmsrl(MSR_IA32_MCG_CAP, cap);
1275 if (cap & MCG_CTL_P)
1276 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1278 for (i = 0; i < banks; i++) {
1279 struct mce_bank *b = &mce_banks[i];
1283 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1284 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1288 /* Add per CPU specific workarounds here */
1289 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1291 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1292 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1296 /* This should be disabled by the BIOS, but isn't always */
1297 if (c->x86_vendor == X86_VENDOR_AMD) {
1299 if (c->x86 == 15 && banks > 4) {
1301 * disable GART TBL walk error reporting, which
1302 * trips off incorrectly with the IOMMU & 3ware
1305 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1308 if (c->x86 <= 17 && mce_bootlog < 0) {
1310 * Lots of broken BIOS around that don't clear them
1311 * by default and leave crap in there. Don't log:
1316 * Various K7s with broken bank 0 around. Always disable
1319 if (c->x86 == 6 && banks > 0)
1320 mce_banks[0].ctl = 0;
1323 if (c->x86_vendor == X86_VENDOR_INTEL) {
1325 * SDM documents that on family 6 bank 0 should not be written
1326 * because it aliases to another special BIOS controlled
1328 * But it's not aliased anymore on model 0x1a+
1329 * Don't ignore bank 0 completely because there could be a
1330 * valid event later, merely don't write CTL0.
1333 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1334 mce_banks[0].init = 0;
1337 * All newer Intel systems support MCE broadcasting. Enable
1338 * synchronization with a one second timeout.
1340 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1341 monarch_timeout < 0)
1342 monarch_timeout = USEC_PER_SEC;
1345 * There are also broken BIOSes on some Pentium M and
1348 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1351 if (monarch_timeout < 0)
1352 monarch_timeout = 0;
1353 if (mce_bootlog != 0)
1354 mce_panic_timeout = 30;
1359 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1364 switch (c->x86_vendor) {
1365 case X86_VENDOR_INTEL:
1366 intel_p5_mcheck_init(c);
1369 case X86_VENDOR_CENTAUR:
1370 winchip_mcheck_init(c);
1378 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1380 #ifndef CONFIG_X86_64_XEN
1381 switch (c->x86_vendor) {
1382 case X86_VENDOR_INTEL:
1383 mce_intel_feature_init(c);
1385 case X86_VENDOR_AMD:
1386 mce_amd_feature_init(c);
1394 static void __mcheck_cpu_init_timer(void)
1396 struct timer_list *t = &__get_cpu_var(mce_timer);
1397 int *n = &__get_cpu_var(mce_next_interval);
1399 setup_timer(t, mce_start_timer, smp_processor_id());
1404 *n = check_interval * HZ;
1407 t->expires = round_jiffies(jiffies + *n);
1408 add_timer_on(t, smp_processor_id());
1411 /* Handle unconfigured int18 (should never happen) */
1412 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1414 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1415 smp_processor_id());
1418 /* Call the installed machine check handler for this CPU setup. */
1419 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1420 unexpected_machine_check;
1423 * Called for each booted CPU to set up machine checks.
1424 * Must be called with preempt off:
1426 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1431 if (__mcheck_cpu_ancient_init(c))
1434 if (!mce_available(c))
1437 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1442 machine_check_vector = do_machine_check;
1444 __mcheck_cpu_init_generic();
1445 __mcheck_cpu_init_vendor(c);
1446 __mcheck_cpu_init_timer();
1447 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1448 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1452 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1455 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1456 static int mce_chrdev_open_count; /* #times opened */
1457 static int mce_chrdev_open_exclu; /* already open exclusive? */
1459 static int mce_chrdev_open(struct inode *inode, struct file *file)
1461 spin_lock(&mce_chrdev_state_lock);
1463 if (mce_chrdev_open_exclu ||
1464 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1465 spin_unlock(&mce_chrdev_state_lock);
1470 if (file->f_flags & O_EXCL)
1471 mce_chrdev_open_exclu = 1;
1472 mce_chrdev_open_count++;
1474 spin_unlock(&mce_chrdev_state_lock);
1476 return nonseekable_open(inode, file);
1479 static int mce_chrdev_release(struct inode *inode, struct file *file)
1481 spin_lock(&mce_chrdev_state_lock);
1483 mce_chrdev_open_count--;
1484 mce_chrdev_open_exclu = 0;
1486 spin_unlock(&mce_chrdev_state_lock);
1491 static void collect_tscs(void *data)
1493 unsigned long *cpu_tsc = (unsigned long *)data;
1495 rdtscll(cpu_tsc[smp_processor_id()]);
1498 static int mce_apei_read_done;
1500 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1501 static int __mce_read_apei(char __user **ubuf, size_t usize)
1507 if (usize < sizeof(struct mce))
1510 rc = apei_read_mce(&m, &record_id);
1511 /* Error or no more MCE record */
1513 mce_apei_read_done = 1;
1517 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1520 * In fact, we should have cleared the record after that has
1521 * been flushed to the disk or sent to network in
1522 * /sbin/mcelog, but we have no interface to support that now,
1523 * so just clear it to avoid duplication.
1525 rc = apei_clear_mce(record_id);
1527 mce_apei_read_done = 1;
1530 *ubuf += sizeof(struct mce);
1535 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1536 size_t usize, loff_t *off)
1538 char __user *buf = ubuf;
1539 unsigned long *cpu_tsc;
1540 unsigned prev, next;
1543 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1547 mutex_lock(&mce_chrdev_read_mutex);
1549 if (!mce_apei_read_done) {
1550 err = __mce_read_apei(&buf, usize);
1551 if (err || buf != ubuf)
1555 next = rcu_dereference_check_mce(mcelog.next);
1557 /* Only supports full reads right now */
1559 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1565 for (i = prev; i < next; i++) {
1566 unsigned long start = jiffies;
1567 struct mce *m = &mcelog.entry[i];
1569 while (!m->finished) {
1570 if (time_after_eq(jiffies, start + 2)) {
1571 memset(m, 0, sizeof(*m));
1577 err |= copy_to_user(buf, m, sizeof(*m));
1583 memset(mcelog.entry + prev, 0,
1584 (next - prev) * sizeof(struct mce));
1586 next = cmpxchg(&mcelog.next, prev, 0);
1587 } while (next != prev);
1589 synchronize_sched();
1592 * Collect entries that were still getting written before the
1595 on_each_cpu(collect_tscs, cpu_tsc, 1);
1597 for (i = next; i < MCE_LOG_LEN; i++) {
1598 struct mce *m = &mcelog.entry[i];
1600 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1601 err |= copy_to_user(buf, m, sizeof(*m));
1604 memset(m, 0, sizeof(*m));
1612 mutex_unlock(&mce_chrdev_read_mutex);
1615 return err ? err : buf - ubuf;
1618 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1620 poll_wait(file, &mce_chrdev_wait, wait);
1621 if (rcu_access_index(mcelog.next))
1622 return POLLIN | POLLRDNORM;
1623 if (!mce_apei_read_done && apei_check_mce())
1624 return POLLIN | POLLRDNORM;
1628 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1631 int __user *p = (int __user *)arg;
1633 if (!capable(CAP_SYS_ADMIN))
1637 case MCE_GET_RECORD_LEN:
1638 return put_user(sizeof(struct mce), p);
1639 case MCE_GET_LOG_LEN:
1640 return put_user(MCE_LOG_LEN, p);
1641 case MCE_GETCLEAR_FLAGS: {
1645 flags = mcelog.flags;
1646 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1648 return put_user(flags, p);
1655 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1656 size_t usize, loff_t *off);
1658 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1659 const char __user *ubuf,
1660 size_t usize, loff_t *off))
1664 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1666 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1667 size_t usize, loff_t *off)
1670 return mce_write(filp, ubuf, usize, off);
1675 static const struct file_operations mce_chrdev_ops = {
1676 .open = mce_chrdev_open,
1677 .release = mce_chrdev_release,
1678 .read = mce_chrdev_read,
1679 .write = mce_chrdev_write,
1680 .poll = mce_chrdev_poll,
1681 .unlocked_ioctl = mce_chrdev_ioctl,
1682 .llseek = no_llseek,
1685 static struct miscdevice mce_chrdev_device = {
1692 * mce=off Disables machine check
1693 * mce=no_cmci Disables CMCI
1694 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1695 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1696 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1697 * monarchtimeout is how long to wait for other CPUs on machine
1698 * check, or 0 to not wait
1699 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1700 * mce=nobootlog Don't log MCEs from before booting.
1702 static int __init mcheck_enable(char *str)
1710 if (!strcmp(str, "off"))
1712 else if (!strcmp(str, "no_cmci"))
1713 mce_cmci_disabled = 1;
1714 else if (!strcmp(str, "dont_log_ce"))
1715 mce_dont_log_ce = 1;
1716 else if (!strcmp(str, "ignore_ce"))
1718 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1719 mce_bootlog = (str[0] == 'b');
1720 else if (isdigit(str[0])) {
1721 get_option(&str, &tolerant);
1724 get_option(&str, &monarch_timeout);
1727 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1733 __setup("mce", mcheck_enable);
1735 int __init mcheck_init(void)
1737 mcheck_intel_therm_init();
1743 * mce_syscore: PM support
1747 * Disable machine checks on suspend and shutdown. We can't really handle
1750 static int mce_disable_error_reporting(void)
1754 for (i = 0; i < banks; i++) {
1755 struct mce_bank *b = &mce_banks[i];
1758 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1763 static int mce_syscore_suspend(void)
1765 return mce_disable_error_reporting();
1768 static void mce_syscore_shutdown(void)
1770 mce_disable_error_reporting();
1774 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1775 * Only one CPU is active at this time, the others get re-added later using
1778 static void mce_syscore_resume(void)
1780 __mcheck_cpu_init_generic();
1781 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1784 static struct syscore_ops mce_syscore_ops = {
1785 .suspend = mce_syscore_suspend,
1786 .shutdown = mce_syscore_shutdown,
1787 .resume = mce_syscore_resume,
1791 * mce_sysdev: Sysfs support
1794 static void mce_cpu_restart(void *data)
1796 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1798 __mcheck_cpu_init_generic();
1799 __mcheck_cpu_init_timer();
1802 /* Reinit MCEs after user configuration changes */
1803 static void mce_restart(void)
1805 mce_timer_delete_all();
1806 on_each_cpu(mce_cpu_restart, NULL, 1);
1809 /* Toggle features for corrected errors */
1810 static void mce_disable_cmci(void *data)
1812 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1817 static void mce_enable_ce(void *all)
1819 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1824 __mcheck_cpu_init_timer();
1827 static struct sysdev_class mce_sysdev_class = {
1828 .name = "machinecheck",
1831 DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1834 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1836 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1838 return container_of(attr, struct mce_bank, attr);
1841 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1844 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1847 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1848 const char *buf, size_t size)
1852 if (strict_strtoull(buf, 0, &new) < 0)
1855 attr_to_bank(attr)->ctl = new;
1862 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1864 strcpy(buf, mce_helper);
1866 return strlen(mce_helper) + 1;
1869 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1870 const char *buf, size_t siz)
1874 strncpy(mce_helper, buf, sizeof(mce_helper));
1875 mce_helper[sizeof(mce_helper)-1] = 0;
1876 p = strchr(mce_helper, '\n');
1881 return strlen(mce_helper) + !!p;
1884 static ssize_t set_ignore_ce(struct sys_device *s,
1885 struct sysdev_attribute *attr,
1886 const char *buf, size_t size)
1890 if (strict_strtoull(buf, 0, &new) < 0)
1893 if (mce_ignore_ce ^ !!new) {
1895 /* disable ce features */
1896 mce_timer_delete_all();
1897 on_each_cpu(mce_disable_cmci, NULL, 1);
1900 /* enable ce features */
1902 on_each_cpu(mce_enable_ce, (void *)1, 1);
1908 static ssize_t set_cmci_disabled(struct sys_device *s,
1909 struct sysdev_attribute *attr,
1910 const char *buf, size_t size)
1914 if (strict_strtoull(buf, 0, &new) < 0)
1917 if (mce_cmci_disabled ^ !!new) {
1920 on_each_cpu(mce_disable_cmci, NULL, 1);
1921 mce_cmci_disabled = 1;
1924 mce_cmci_disabled = 0;
1925 on_each_cpu(mce_enable_ce, NULL, 1);
1931 static ssize_t store_int_with_restart(struct sys_device *s,
1932 struct sysdev_attribute *attr,
1933 const char *buf, size_t size)
1935 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1940 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1941 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1942 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1943 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1945 static struct sysdev_ext_attribute attr_check_interval = {
1946 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1947 store_int_with_restart),
1951 static struct sysdev_ext_attribute attr_ignore_ce = {
1952 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1956 static struct sysdev_ext_attribute attr_cmci_disabled = {
1957 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1961 static struct sysdev_attribute *mce_sysdev_attrs[] = {
1962 &attr_tolerant.attr,
1963 &attr_check_interval.attr,
1965 &attr_monarch_timeout.attr,
1966 &attr_dont_log_ce.attr,
1967 &attr_ignore_ce.attr,
1968 &attr_cmci_disabled.attr,
1972 static cpumask_var_t mce_sysdev_initialized;
1974 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1975 static __cpuinit int mce_sysdev_create(unsigned int cpu)
1977 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1981 if (!mce_available(&boot_cpu_data))
1984 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1986 sysdev->cls = &mce_sysdev_class;
1988 err = sysdev_register(sysdev);
1992 for (i = 0; mce_sysdev_attrs[i]; i++) {
1993 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
1997 for (j = 0; j < banks; j++) {
1998 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
2002 cpumask_set_cpu(cpu, mce_sysdev_initialized);
2007 sysdev_remove_file(sysdev, &mce_banks[j].attr);
2010 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2012 sysdev_unregister(sysdev);
2017 static __cpuinit void mce_sysdev_remove(unsigned int cpu)
2019 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
2022 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
2025 for (i = 0; mce_sysdev_attrs[i]; i++)
2026 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2028 for (i = 0; i < banks; i++)
2029 sysdev_remove_file(sysdev, &mce_banks[i].attr);
2031 sysdev_unregister(sysdev);
2032 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
2035 /* Make sure there are no machine checks on offlined CPUs. */
2036 static void __cpuinit mce_disable_cpu(void *h)
2038 unsigned long action = *(unsigned long *)h;
2041 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2044 if (!(action & CPU_TASKS_FROZEN))
2046 for (i = 0; i < banks; i++) {
2047 struct mce_bank *b = &mce_banks[i];
2050 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2054 static void __cpuinit mce_reenable_cpu(void *h)
2056 unsigned long action = *(unsigned long *)h;
2059 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2062 if (!(action & CPU_TASKS_FROZEN))
2064 for (i = 0; i < banks; i++) {
2065 struct mce_bank *b = &mce_banks[i];
2068 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2072 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2073 static int __cpuinit
2074 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2076 unsigned int cpu = (unsigned long)hcpu;
2077 struct timer_list *t = &per_cpu(mce_timer, cpu);
2081 case CPU_ONLINE_FROZEN:
2082 mce_sysdev_create(cpu);
2083 if (threshold_cpu_callback)
2084 threshold_cpu_callback(action, cpu);
2087 case CPU_DEAD_FROZEN:
2088 if (threshold_cpu_callback)
2089 threshold_cpu_callback(action, cpu);
2090 mce_sysdev_remove(cpu);
2092 case CPU_DOWN_PREPARE:
2093 case CPU_DOWN_PREPARE_FROZEN:
2095 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2097 case CPU_DOWN_FAILED:
2098 case CPU_DOWN_FAILED_FROZEN:
2099 if (!mce_ignore_ce && check_interval) {
2100 t->expires = round_jiffies(jiffies +
2101 __get_cpu_var(mce_next_interval));
2102 add_timer_on(t, cpu);
2104 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2107 /* intentionally ignoring frozen here */
2108 cmci_rediscover(cpu);
2114 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2115 .notifier_call = mce_cpu_callback,
2118 static __init void mce_init_banks(void)
2122 for (i = 0; i < banks; i++) {
2123 struct mce_bank *b = &mce_banks[i];
2124 struct sysdev_attribute *a = &b->attr;
2126 sysfs_attr_init(&a->attr);
2127 a->attr.name = b->attrname;
2128 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2130 a->attr.mode = 0644;
2131 a->show = show_bank;
2132 a->store = set_bank;
2136 static __init int mcheck_init_device(void)
2141 if (!mce_available(&boot_cpu_data))
2144 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2148 err = sysdev_class_register(&mce_sysdev_class);
2152 for_each_online_cpu(i) {
2153 err = mce_sysdev_create(i);
2158 register_syscore_ops(&mce_syscore_ops);
2159 register_hotcpu_notifier(&mce_cpu_notifier);
2161 /* register character device /dev/mcelog */
2162 misc_register(&mce_chrdev_device);
2164 #ifdef CONFIG_X86_XEN_MCE
2165 if (is_initial_xendomain()) {
2166 /* Register vIRQ handler for MCE LOG processing */
2167 extern int bind_virq_for_mce(void);
2169 printk(KERN_DEBUG "MCE: bind virq for DOM0 logging\n");
2170 bind_virq_for_mce();
2176 device_initcall(mcheck_init_device);
2179 * Old style boot options parsing. Only for compatibility.
2181 static int __init mcheck_disable(char *str)
2186 __setup("nomce", mcheck_disable);
2188 #ifdef CONFIG_DEBUG_FS
2189 struct dentry *mce_get_debugfs_dir(void)
2191 static struct dentry *dmce;
2194 dmce = debugfs_create_dir("mce", NULL);
2199 static void mce_reset(void)
2202 atomic_set(&mce_fake_paniced, 0);
2203 atomic_set(&mce_executing, 0);
2204 atomic_set(&mce_callin, 0);
2205 atomic_set(&global_nwo, 0);
2208 static int fake_panic_get(void *data, u64 *val)
2214 static int fake_panic_set(void *data, u64 val)
2221 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2222 fake_panic_set, "%llu\n");
2224 static int __init mcheck_debugfs_init(void)
2226 struct dentry *dmce, *ffake_panic;
2228 dmce = mce_get_debugfs_dir();
2231 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2238 late_initcall(mcheck_debugfs_init);