ASoC: Disable register synchronisation for low frequency WM8996 SYSCLK

commit fed22007113cb857e917913ce016d9b539dc3a80 upstream.

With a low frequency SYSCLK and a fast I2C clock register synchronisation
may occasionally take too long to take effect, causing I/O issues. Disable
synchronisation in order to avoid any issues.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index a33b04d..e2afc05 100644 (file)
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -1932,6 +1932,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
        int lfclk = 0;
        int ratediv = 0;
+       int sync = WM8996_REG_SYNC;
        int src;
        int old;
 
@@ -1976,6 +1977,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
        case 32000:
        case 32768:
                lfclk = WM8996_LFCLK_ENA;
+               sync = 0;
                break;
        default:
                dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
@@ -1989,6 +1991,8 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
                            WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
                            src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
        snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
+       snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
+                           WM8996_REG_SYNC, sync);
        snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
                            WM8996_SYSCLK_ENA, old);
 

diff --git a/sound/soc/codecs/wm8996.h b/sound/soc/codecs/wm8996.h
index 0fde643..de9ac3e 100644 (file)
--- a/sound/soc/codecs/wm8996.h
+++ b/sound/soc/codecs/wm8996.h
@@ -1567,6 +1567,10 @@ int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
 /*
  * R257 (0x101) - Control Interface (1)
  */
+#define WM8996_REG_SYNC                         0x8000  /* REG_SYNC */
+#define WM8996_REG_SYNC_MASK                    0x8000  /* REG_SYNC */
+#define WM8996_REG_SYNC_SHIFT                       15  /* REG_SYNC */
+#define WM8996_REG_SYNC_WIDTH                        1  /* REG_SYNC */
 #define WM8996_AUTO_INC                         0x0004  /* AUTO_INC */
 #define WM8996_AUTO_INC_MASK                    0x0004  /* AUTO_INC */
 #define WM8996_AUTO_INC_SHIFT                        2  /* AUTO_INC */