tg3: Fix 5717 serdes powerdown problem
authorMatt Carlson <mcarlson@broadcom.com>
Mon, 2 Apr 2012 09:01:40 +0000 (09:01 +0000)
committerLuis Henriques <luis.henriques@canonical.com>
Mon, 30 Apr 2012 18:14:58 +0000 (19:14 +0100)
BugLink: http://bugs.launchpad.net/bugs/981162

[ Upstream commit 085f1afc56619bda424941412fdeaff1e32c21dc ]

If port 0 of a 5717 serdes device powers down, it hides the phy from
port 1.  This patch works around the problem by keeping port 0's phy
powered up.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>

drivers/net/ethernet/broadcom/tg3.c

index cd36234..45de1e5 100644 (file)
@@ -2794,7 +2794,9 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
-            (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
+            (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
+           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
+            !tp->pci_fn))
                return;
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||