2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
72 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
78 unsigned long segment_offset;
80 if (!seg || !trb || trb < seg->trbs)
83 segment_offset = trb - seg->trbs;
84 if (segment_offset > TRBS_PER_SEGMENT)
86 return seg->dma + (segment_offset * sizeof(*trb));
89 /* Does this link TRB point to the first segment in a ring,
90 * or was the previous TRB the last TRB on the last segment in the ERST?
92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
93 struct xhci_segment *seg, union xhci_trb *trb)
95 if (ring == xhci->event_ring)
96 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
97 (seg->next == xhci->event_ring->first_seg);
99 return trb->link.control & LINK_TOGGLE;
102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
103 * segment? I.e. would the updated event TRB pointer step off the end of the
106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
107 struct xhci_segment *seg, union xhci_trb *trb)
109 if (ring == xhci->event_ring)
110 return trb == &seg->trbs[TRBS_PER_SEGMENT];
112 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
115 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
117 struct xhci_link_trb *link = &ring->enqueue->link;
118 return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
122 * TRB is in a new segment. This does not skip over link TRBs, and it does not
123 * effect the ring dequeue or enqueue pointers.
125 static void next_trb(struct xhci_hcd *xhci,
126 struct xhci_ring *ring,
127 struct xhci_segment **seg,
128 union xhci_trb **trb)
130 if (last_trb(xhci, ring, *seg, *trb)) {
132 *trb = ((*seg)->trbs);
139 * See Cycle bit rules. SW is the consumer for the event ring only.
140 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
142 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
144 union xhci_trb *next = ++(ring->dequeue);
145 unsigned long long addr;
148 /* Update the dequeue pointer further if that was a link TRB or we're at
149 * the end of an event ring segment (which doesn't have link TRBS)
151 while (last_trb(xhci, ring, ring->deq_seg, next)) {
152 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
153 ring->cycle_state = (ring->cycle_state ? 0 : 1);
155 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
157 (unsigned int) ring->cycle_state);
159 ring->deq_seg = ring->deq_seg->next;
160 ring->dequeue = ring->deq_seg->trbs;
161 next = ring->dequeue;
163 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
164 if (ring == xhci->event_ring)
165 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
166 else if (ring == xhci->cmd_ring)
167 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
169 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
173 * See Cycle bit rules. SW is the consumer for the event ring only.
174 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
176 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
177 * chain bit is set), then set the chain bit in all the following link TRBs.
178 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
179 * have their chain bit cleared (so that each Link TRB is a separate TD).
181 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
182 * set, but other sections talk about dealing with the chain bit set. This was
183 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
184 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
186 * @more_trbs_coming: Will you enqueue more TRBs before calling
187 * prepare_transfer()?
189 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
190 bool consumer, bool more_trbs_coming)
193 union xhci_trb *next;
194 unsigned long long addr;
196 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
197 next = ++(ring->enqueue);
200 /* Update the dequeue pointer further if that was a link TRB or we're at
201 * the end of an event ring segment (which doesn't have link TRBS)
203 while (last_trb(xhci, ring, ring->enq_seg, next)) {
205 if (ring != xhci->event_ring) {
207 * If the caller doesn't plan on enqueueing more
208 * TDs before ringing the doorbell, then we
209 * don't want to give the link TRB to the
210 * hardware just yet. We'll give the link TRB
211 * back in prepare_ring() just before we enqueue
212 * the TD at the top of the ring.
214 if (!chain && !more_trbs_coming)
217 /* If we're not dealing with 0.95 hardware,
218 * carry over the chain bit of the previous TRB
219 * (which may mean the chain bit is cleared).
221 if (!xhci_link_trb_quirk(xhci)) {
222 next->link.control &= ~TRB_CHAIN;
223 next->link.control |= chain;
225 /* Give this link TRB to the hardware */
227 next->link.control ^= TRB_CYCLE;
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
231 ring->cycle_state = (ring->cycle_state ? 0 : 1);
233 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
235 (unsigned int) ring->cycle_state);
238 ring->enq_seg = ring->enq_seg->next;
239 ring->enqueue = ring->enq_seg->trbs;
240 next = ring->enqueue;
242 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
243 if (ring == xhci->event_ring)
244 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
245 else if (ring == xhci->cmd_ring)
246 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
248 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
252 * Check to see if there's room to enqueue num_trbs on the ring. See rules
254 * FIXME: this would be simpler and faster if we just kept track of the number
255 * of free TRBs in a ring.
257 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
258 unsigned int num_trbs)
261 union xhci_trb *enq = ring->enqueue;
262 struct xhci_segment *enq_seg = ring->enq_seg;
263 struct xhci_segment *cur_seg;
264 unsigned int left_on_ring;
266 /* If we are currently pointing to a link TRB, advance the
267 * enqueue pointer before checking for space */
268 while (last_trb(xhci, ring, enq_seg, enq)) {
269 enq_seg = enq_seg->next;
273 /* Check if ring is empty */
274 if (enq == ring->dequeue) {
275 /* Can't use link trbs */
276 left_on_ring = TRBS_PER_SEGMENT - 1;
277 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
278 cur_seg = cur_seg->next)
279 left_on_ring += TRBS_PER_SEGMENT - 1;
281 /* Always need one TRB free in the ring. */
283 if (num_trbs > left_on_ring) {
284 xhci_warn(xhci, "Not enough room on ring; "
285 "need %u TRBs, %u TRBs left\n",
286 num_trbs, left_on_ring);
291 /* Make sure there's an extra empty TRB available */
292 for (i = 0; i <= num_trbs; ++i) {
293 if (enq == ring->dequeue)
296 while (last_trb(xhci, ring, enq_seg, enq)) {
297 enq_seg = enq_seg->next;
304 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
309 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
310 xhci->event_ring->dequeue);
311 if (deq == 0 && !in_interrupt())
312 xhci_warn(xhci, "WARN something wrong with SW event ring "
314 /* Update HC event ring dequeue pointer */
315 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
316 temp &= ERST_PTR_MASK;
317 /* Don't clear the EHB bit (which is RW1C) because
318 * there might be more events to service.
321 xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
322 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
323 &xhci->ir_set->erst_dequeue);
326 /* Ring the host controller doorbell after placing a command on the ring */
327 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
331 xhci_dbg(xhci, "// Ding dong!\n");
332 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
333 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
334 /* Flush PCI posted writes */
335 xhci_readl(xhci, &xhci->dba->doorbell[0]);
338 static void ring_ep_doorbell(struct xhci_hcd *xhci,
339 unsigned int slot_id,
340 unsigned int ep_index,
341 unsigned int stream_id)
343 struct xhci_virt_ep *ep;
344 unsigned int ep_state;
346 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
348 ep = &xhci->devs[slot_id]->eps[ep_index];
349 ep_state = ep->ep_state;
350 /* Don't ring the doorbell for this endpoint if there are pending
351 * cancellations because the we don't want to interrupt processing.
352 * We don't want to restart any stream rings if there's a set dequeue
353 * pointer command pending because the device can choose to start any
354 * stream once the endpoint is on the HW schedule.
355 * FIXME - check all the stream rings for pending cancellations.
357 if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
358 && !(ep_state & EP_HALTED)) {
359 field = xhci_readl(xhci, db_addr) & DB_MASK;
360 field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id);
361 xhci_writel(xhci, field, db_addr);
362 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
363 * isn't time-critical and we shouldn't make the CPU wait for
366 xhci_readl(xhci, db_addr);
370 /* Ring the doorbell for any rings with pending URBs */
371 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
372 unsigned int slot_id,
373 unsigned int ep_index)
375 unsigned int stream_id;
376 struct xhci_virt_ep *ep;
378 ep = &xhci->devs[slot_id]->eps[ep_index];
380 /* A ring has pending URBs if its TD list is not empty */
381 if (!(ep->ep_state & EP_HAS_STREAMS)) {
382 if (!(list_empty(&ep->ring->td_list)))
383 ring_ep_doorbell(xhci, slot_id, ep_index, 0);
387 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
389 struct xhci_stream_info *stream_info = ep->stream_info;
390 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
391 ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
396 * Find the segment that trb is in. Start searching in start_seg.
397 * If we must move past a segment that has a link TRB with a toggle cycle state
398 * bit set, then we will toggle the value pointed at by cycle_state.
400 static struct xhci_segment *find_trb_seg(
401 struct xhci_segment *start_seg,
402 union xhci_trb *trb, int *cycle_state)
404 struct xhci_segment *cur_seg = start_seg;
405 struct xhci_generic_trb *generic_trb;
407 while (cur_seg->trbs > trb ||
408 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
409 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
410 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
411 TRB_TYPE(TRB_LINK) &&
412 (generic_trb->field[3] & LINK_TOGGLE))
413 *cycle_state = ~(*cycle_state) & 0x1;
414 cur_seg = cur_seg->next;
415 if (cur_seg == start_seg)
416 /* Looped over the entire list. Oops! */
423 * Move the xHC's endpoint ring dequeue pointer past cur_td.
424 * Record the new state of the xHC's endpoint ring dequeue segment,
425 * dequeue pointer, and new consumer cycle state in state.
426 * Update our internal representation of the ring's dequeue pointer.
428 * We do this in three jumps:
429 * - First we update our new ring state to be the same as when the xHC stopped.
430 * - Then we traverse the ring to find the segment that contains
431 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
432 * any link TRBs with the toggle cycle bit set.
433 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
434 * if we've moved it past a link TRB with the toggle cycle bit set.
436 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
437 unsigned int slot_id, unsigned int ep_index,
438 unsigned int stream_id, struct xhci_td *cur_td,
439 struct xhci_dequeue_state *state)
441 struct xhci_virt_device *dev = xhci->devs[slot_id];
442 struct xhci_ring *ep_ring;
443 struct xhci_generic_trb *trb;
444 struct xhci_ep_ctx *ep_ctx;
447 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
448 ep_index, stream_id);
450 xhci_warn(xhci, "WARN can't find new dequeue state "
451 "for invalid stream ID %u.\n",
455 state->new_cycle_state = 0;
456 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
457 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
458 dev->eps[ep_index].stopped_trb,
459 &state->new_cycle_state);
460 if (!state->new_deq_seg)
462 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
463 xhci_dbg(xhci, "Finding endpoint context\n");
464 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
465 state->new_cycle_state = 0x1 & ep_ctx->deq;
467 state->new_deq_ptr = cur_td->last_trb;
468 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
469 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
471 &state->new_cycle_state);
472 if (!state->new_deq_seg)
475 trb = &state->new_deq_ptr->generic;
476 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
477 (trb->field[3] & LINK_TOGGLE))
478 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
479 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
481 /* Don't update the ring cycle state for the producer (us). */
482 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
484 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
485 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
486 (unsigned long long) addr);
487 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
488 ep_ring->dequeue = state->new_deq_ptr;
489 ep_ring->deq_seg = state->new_deq_seg;
492 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
493 struct xhci_td *cur_td)
495 struct xhci_segment *cur_seg;
496 union xhci_trb *cur_trb;
498 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
500 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
501 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
502 TRB_TYPE(TRB_LINK)) {
503 /* Unchain any chained Link TRBs, but
504 * leave the pointers intact.
506 cur_trb->generic.field[3] &= ~TRB_CHAIN;
507 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
508 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
509 "in seg %p (0x%llx dma)\n",
511 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
513 (unsigned long long)cur_seg->dma);
515 cur_trb->generic.field[0] = 0;
516 cur_trb->generic.field[1] = 0;
517 cur_trb->generic.field[2] = 0;
518 /* Preserve only the cycle bit of this TRB */
519 cur_trb->generic.field[3] &= TRB_CYCLE;
520 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
521 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
522 "in seg %p (0x%llx dma)\n",
524 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
526 (unsigned long long)cur_seg->dma);
528 if (cur_trb == cur_td->last_trb)
533 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
534 unsigned int ep_index, unsigned int stream_id,
535 struct xhci_segment *deq_seg,
536 union xhci_trb *deq_ptr, u32 cycle_state);
538 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
539 unsigned int slot_id, unsigned int ep_index,
540 unsigned int stream_id,
541 struct xhci_dequeue_state *deq_state)
543 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
545 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
546 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
547 deq_state->new_deq_seg,
548 (unsigned long long)deq_state->new_deq_seg->dma,
549 deq_state->new_deq_ptr,
550 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
551 deq_state->new_cycle_state);
552 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
553 deq_state->new_deq_seg,
554 deq_state->new_deq_ptr,
555 (u32) deq_state->new_cycle_state);
556 /* Stop the TD queueing code from ringing the doorbell until
557 * this command completes. The HC won't set the dequeue pointer
558 * if the ring is running, and ringing the doorbell starts the
561 ep->ep_state |= SET_DEQ_PENDING;
564 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
565 struct xhci_virt_ep *ep)
567 ep->ep_state &= ~EP_HALT_PENDING;
568 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
569 * timer is running on another CPU, we don't decrement stop_cmds_pending
570 * (since we didn't successfully stop the watchdog timer).
572 if (del_timer(&ep->stop_cmd_timer))
573 ep->stop_cmds_pending--;
576 /* Must be called with xhci->lock held in interrupt context */
577 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
578 struct xhci_td *cur_td, int status, char *adjective)
580 struct usb_hcd *hcd = xhci_to_hcd(xhci);
582 cur_td->urb->hcpriv = NULL;
583 usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb);
584 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb);
586 spin_unlock(&xhci->lock);
587 usb_hcd_giveback_urb(hcd, cur_td->urb, status);
589 spin_lock(&xhci->lock);
590 xhci_dbg(xhci, "%s URB given back\n", adjective);
594 * When we get a command completion for a Stop Endpoint Command, we need to
595 * unlink any cancelled TDs from the ring. There are two ways to do that:
597 * 1. If the HW was in the middle of processing the TD that needs to be
598 * cancelled, then we must move the ring's dequeue pointer past the last TRB
599 * in the TD with a Set Dequeue Pointer Command.
600 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
601 * bit cleared) so that the HW will skip over them.
603 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
606 unsigned int slot_id;
607 unsigned int ep_index;
608 struct xhci_ring *ep_ring;
609 struct xhci_virt_ep *ep;
610 struct list_head *entry;
611 struct xhci_td *cur_td = NULL;
612 struct xhci_td *last_unlinked_td;
614 struct xhci_dequeue_state deq_state;
616 memset(&deq_state, 0, sizeof(deq_state));
617 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
618 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
619 ep = &xhci->devs[slot_id]->eps[ep_index];
621 if (list_empty(&ep->cancelled_td_list)) {
622 xhci_stop_watchdog_timer_in_irq(xhci, ep);
623 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
627 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
628 * We have the xHCI lock, so nothing can modify this list until we drop
629 * it. We're also in the event handler, so we can't get re-interrupted
630 * if another Stop Endpoint command completes
632 list_for_each(entry, &ep->cancelled_td_list) {
633 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
634 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
636 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
637 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
639 /* This shouldn't happen unless a driver is mucking
640 * with the stream ID after submission. This will
641 * leave the TD on the hardware ring, and the hardware
642 * will try to execute it, and may access a buffer
643 * that has already been freed. In the best case, the
644 * hardware will execute it, and the event handler will
645 * ignore the completion event for that TD, since it was
646 * removed from the td_list for that endpoint. In
647 * short, don't muck with the stream ID after
650 xhci_warn(xhci, "WARN Cancelled URB %p "
651 "has invalid stream ID %u.\n",
653 cur_td->urb->stream_id);
654 goto remove_finished_td;
657 * If we stopped on the TD we need to cancel, then we have to
658 * move the xHC endpoint ring dequeue pointer past this TD.
660 if (cur_td == ep->stopped_td)
661 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
662 cur_td->urb->stream_id,
665 td_to_noop(xhci, ep_ring, cur_td);
668 * The event handler won't see a completion for this TD anymore,
669 * so remove it from the endpoint ring's TD list. Keep it in
670 * the cancelled TD list for URB completion later.
672 list_del(&cur_td->td_list);
674 last_unlinked_td = cur_td;
675 xhci_stop_watchdog_timer_in_irq(xhci, ep);
677 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
678 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
679 xhci_queue_new_dequeue_state(xhci,
681 ep->stopped_td->urb->stream_id,
683 xhci_ring_cmd_db(xhci);
685 /* Otherwise ring the doorbell(s) to restart queued transfers */
686 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
688 ep->stopped_td = NULL;
689 ep->stopped_trb = NULL;
692 * Drop the lock and complete the URBs in the cancelled TD list.
693 * New TDs to be cancelled might be added to the end of the list before
694 * we can complete all the URBs for the TDs we already unlinked.
695 * So stop when we've completed the URB for the last TD we unlinked.
698 cur_td = list_entry(ep->cancelled_td_list.next,
699 struct xhci_td, cancelled_td_list);
700 list_del(&cur_td->cancelled_td_list);
702 /* Clean up the cancelled URB */
703 /* Doesn't matter what we pass for status, since the core will
704 * just overwrite it (because the URB has been unlinked).
706 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
708 /* Stop processing the cancelled list if the watchdog timer is
711 if (xhci->xhc_state & XHCI_STATE_DYING)
713 } while (cur_td != last_unlinked_td);
715 /* Return to the event handler with xhci->lock re-acquired */
718 /* Watchdog timer function for when a stop endpoint command fails to complete.
719 * In this case, we assume the host controller is broken or dying or dead. The
720 * host may still be completing some other events, so we have to be careful to
721 * let the event ring handler and the URB dequeueing/enqueueing functions know
722 * through xhci->state.
724 * The timer may also fire if the host takes a very long time to respond to the
725 * command, and the stop endpoint command completion handler cannot delete the
726 * timer before the timer function is called. Another endpoint cancellation may
727 * sneak in before the timer function can grab the lock, and that may queue
728 * another stop endpoint command and add the timer back. So we cannot use a
729 * simple flag to say whether there is a pending stop endpoint command for a
730 * particular endpoint.
732 * Instead we use a combination of that flag and a counter for the number of
733 * pending stop endpoint commands. If the timer is the tail end of the last
734 * stop endpoint command, and the endpoint's command is still pending, we assume
737 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
739 struct xhci_hcd *xhci;
740 struct xhci_virt_ep *ep;
741 struct xhci_virt_ep *temp_ep;
742 struct xhci_ring *ring;
743 struct xhci_td *cur_td;
746 ep = (struct xhci_virt_ep *) arg;
749 spin_lock(&xhci->lock);
751 ep->stop_cmds_pending--;
752 if (xhci->xhc_state & XHCI_STATE_DYING) {
753 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
754 "xHCI as DYING, exiting.\n");
755 spin_unlock(&xhci->lock);
758 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
759 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
761 spin_unlock(&xhci->lock);
765 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
766 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
767 /* Oops, HC is dead or dying or at least not responding to the stop
770 xhci->xhc_state |= XHCI_STATE_DYING;
771 /* Disable interrupts from the host controller and start halting it */
773 spin_unlock(&xhci->lock);
775 ret = xhci_halt(xhci);
777 spin_lock(&xhci->lock);
779 /* This is bad; the host is not responding to commands and it's
780 * not allowing itself to be halted. At least interrupts are
781 * disabled, so we can set HC_STATE_HALT and notify the
782 * USB core. But if we call usb_hc_died(), it will attempt to
783 * disconnect all device drivers under this host. Those
784 * disconnect() methods will wait for all URBs to be unlinked,
785 * so we must complete them.
787 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
788 xhci_warn(xhci, "Completing active URBs anyway.\n");
789 /* We could turn all TDs on the rings to no-ops. This won't
790 * help if the host has cached part of the ring, and is slow if
791 * we want to preserve the cycle bit. Skip it and hope the host
792 * doesn't touch the memory.
795 for (i = 0; i < MAX_HC_SLOTS; i++) {
798 for (j = 0; j < 31; j++) {
799 temp_ep = &xhci->devs[i]->eps[j];
800 ring = temp_ep->ring;
803 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
804 "ep index %u\n", i, j);
805 while (!list_empty(&ring->td_list)) {
806 cur_td = list_first_entry(&ring->td_list,
809 list_del(&cur_td->td_list);
810 if (!list_empty(&cur_td->cancelled_td_list))
811 list_del(&cur_td->cancelled_td_list);
812 xhci_giveback_urb_in_irq(xhci, cur_td,
813 -ESHUTDOWN, "killed");
815 while (!list_empty(&temp_ep->cancelled_td_list)) {
816 cur_td = list_first_entry(
817 &temp_ep->cancelled_td_list,
820 list_del(&cur_td->cancelled_td_list);
821 xhci_giveback_urb_in_irq(xhci, cur_td,
822 -ESHUTDOWN, "killed");
826 spin_unlock(&xhci->lock);
827 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
828 xhci_dbg(xhci, "Calling usb_hc_died()\n");
829 usb_hc_died(xhci_to_hcd(xhci));
830 xhci_dbg(xhci, "xHCI host controller is dead.\n");
834 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
835 * we need to clear the set deq pending flag in the endpoint ring state, so that
836 * the TD queueing code can ring the doorbell again. We also need to ring the
837 * endpoint doorbell to restart the ring, but only if there aren't more
838 * cancellations pending.
840 static void handle_set_deq_completion(struct xhci_hcd *xhci,
841 struct xhci_event_cmd *event,
844 unsigned int slot_id;
845 unsigned int ep_index;
846 unsigned int stream_id;
847 struct xhci_ring *ep_ring;
848 struct xhci_virt_device *dev;
849 struct xhci_ep_ctx *ep_ctx;
850 struct xhci_slot_ctx *slot_ctx;
852 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
853 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
854 stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
855 dev = xhci->devs[slot_id];
857 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
859 xhci_warn(xhci, "WARN Set TR deq ptr command for "
860 "freed stream ID %u\n",
862 /* XXX: Harmless??? */
863 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
867 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
868 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
870 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
871 unsigned int ep_state;
872 unsigned int slot_state;
874 switch (GET_COMP_CODE(event->status)) {
876 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
877 "of stream ID configuration\n");
880 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
881 "to incorrect slot or ep state.\n");
882 ep_state = ep_ctx->ep_info;
883 ep_state &= EP_STATE_MASK;
884 slot_state = slot_ctx->dev_state;
885 slot_state = GET_SLOT_STATE(slot_state);
886 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
887 slot_state, ep_state);
890 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
891 "slot %u was not enabled.\n", slot_id);
894 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
895 "completion code of %u.\n",
896 GET_COMP_CODE(event->status));
899 /* OK what do we do now? The endpoint state is hosed, and we
900 * should never get to this point if the synchronization between
901 * queueing, and endpoint state are correct. This might happen
902 * if the device gets disconnected after we've finished
903 * cancelling URBs, which might not be an error...
906 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
910 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
911 /* Restart any rings with pending URBs */
912 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
915 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
916 struct xhci_event_cmd *event,
920 unsigned int ep_index;
922 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
923 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
924 /* This command will only fail if the endpoint wasn't halted,
927 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
928 (unsigned int) GET_COMP_CODE(event->status));
930 /* HW with the reset endpoint quirk needs to have a configure endpoint
931 * command complete before the endpoint can be used. Queue that here
932 * because the HW can't handle two commands being queued in a row.
934 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
935 xhci_dbg(xhci, "Queueing configure endpoint command\n");
936 xhci_queue_configure_endpoint(xhci,
937 xhci->devs[slot_id]->in_ctx->dma, slot_id,
939 xhci_ring_cmd_db(xhci);
941 /* Clear our internal halted state and restart the ring(s) */
942 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
943 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
947 /* Check to see if a command in the device's command queue matches this one.
948 * Signal the completion or free the command, and return 1. Return 0 if the
949 * completed command isn't at the head of the command list.
951 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
952 struct xhci_virt_device *virt_dev,
953 struct xhci_event_cmd *event)
955 struct xhci_command *command;
957 if (list_empty(&virt_dev->cmd_list))
960 command = list_entry(virt_dev->cmd_list.next,
961 struct xhci_command, cmd_list);
962 if (xhci->cmd_ring->dequeue != command->command_trb)
966 GET_COMP_CODE(event->status);
967 list_del(&command->cmd_list);
968 if (command->completion)
969 complete(command->completion);
971 xhci_free_command(xhci, command);
975 static void handle_cmd_completion(struct xhci_hcd *xhci,
976 struct xhci_event_cmd *event)
978 int slot_id = TRB_TO_SLOT_ID(event->flags);
980 dma_addr_t cmd_dequeue_dma;
981 struct xhci_input_control_ctx *ctrl_ctx;
982 struct xhci_virt_device *virt_dev;
983 unsigned int ep_index;
984 struct xhci_ring *ep_ring;
985 unsigned int ep_state;
987 cmd_dma = event->cmd_trb;
988 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
989 xhci->cmd_ring->dequeue);
990 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
991 if (cmd_dequeue_dma == 0) {
992 xhci->error_bitmask |= 1 << 4;
995 /* Does the DMA address match our internal dequeue pointer address? */
996 if (cmd_dma != (u64) cmd_dequeue_dma) {
997 xhci->error_bitmask |= 1 << 5;
1000 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1001 case TRB_TYPE(TRB_ENABLE_SLOT):
1002 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1003 xhci->slot_id = slot_id;
1006 complete(&xhci->addr_dev);
1008 case TRB_TYPE(TRB_DISABLE_SLOT):
1009 if (xhci->devs[slot_id])
1010 xhci_free_virt_device(xhci, slot_id);
1012 case TRB_TYPE(TRB_CONFIG_EP):
1013 virt_dev = xhci->devs[slot_id];
1014 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1017 * Configure endpoint commands can come from the USB core
1018 * configuration or alt setting changes, or because the HW
1019 * needed an extra configure endpoint command after a reset
1020 * endpoint command or streams were being configured.
1021 * If the command was for a halted endpoint, the xHCI driver
1022 * is not waiting on the configure endpoint command.
1024 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1026 /* Input ctx add_flags are the endpoint index plus one */
1027 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1028 /* A usb_set_interface() call directly after clearing a halted
1029 * condition may race on this quirky hardware. Not worth
1030 * worrying about, since this is prototype hardware. Not sure
1031 * if this will work for streams, but streams support was
1032 * untested on this prototype.
1034 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1035 ep_index != (unsigned int) -1 &&
1036 ctrl_ctx->add_flags - SLOT_FLAG ==
1037 ctrl_ctx->drop_flags) {
1038 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1039 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1040 if (!(ep_state & EP_HALTED))
1041 goto bandwidth_change;
1042 xhci_dbg(xhci, "Completed config ep cmd - "
1043 "last ep index = %d, state = %d\n",
1044 ep_index, ep_state);
1045 /* Clear internal halted state and restart ring(s) */
1046 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1048 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1052 xhci_dbg(xhci, "Completed config ep cmd\n");
1053 xhci->devs[slot_id]->cmd_status =
1054 GET_COMP_CODE(event->status);
1055 complete(&xhci->devs[slot_id]->cmd_completion);
1057 case TRB_TYPE(TRB_EVAL_CONTEXT):
1058 virt_dev = xhci->devs[slot_id];
1059 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1061 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1062 complete(&xhci->devs[slot_id]->cmd_completion);
1064 case TRB_TYPE(TRB_ADDR_DEV):
1065 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1066 complete(&xhci->addr_dev);
1068 case TRB_TYPE(TRB_STOP_RING):
1069 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
1071 case TRB_TYPE(TRB_SET_DEQ):
1072 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1074 case TRB_TYPE(TRB_CMD_NOOP):
1075 ++xhci->noops_handled;
1077 case TRB_TYPE(TRB_RESET_EP):
1078 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1080 case TRB_TYPE(TRB_RESET_DEV):
1081 xhci_dbg(xhci, "Completed reset device command.\n");
1082 slot_id = TRB_TO_SLOT_ID(
1083 xhci->cmd_ring->dequeue->generic.field[3]);
1084 virt_dev = xhci->devs[slot_id];
1086 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1088 xhci_warn(xhci, "Reset device command completion "
1089 "for disabled slot %u\n", slot_id);
1091 case TRB_TYPE(TRB_NEC_GET_FW):
1092 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1093 xhci->error_bitmask |= 1 << 6;
1096 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1097 NEC_FW_MAJOR(event->status),
1098 NEC_FW_MINOR(event->status));
1101 /* Skip over unknown commands on the event ring */
1102 xhci->error_bitmask |= 1 << 6;
1105 inc_deq(xhci, xhci->cmd_ring, false);
1108 static void handle_vendor_event(struct xhci_hcd *xhci,
1109 union xhci_trb *event)
1113 trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1114 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1115 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1116 handle_cmd_completion(xhci, &event->event_cmd);
1119 static void handle_port_status(struct xhci_hcd *xhci,
1120 union xhci_trb *event)
1124 /* Port status change events always have a successful completion code */
1125 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1126 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1127 xhci->error_bitmask |= 1 << 8;
1129 /* FIXME: core doesn't care about all port link state changes yet */
1130 port_id = GET_PORT_ID(event->generic.field[0]);
1131 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1133 /* Update event ring dequeue pointer before dropping the lock */
1134 inc_deq(xhci, xhci->event_ring, true);
1135 xhci_set_hc_event_deq(xhci);
1137 spin_unlock(&xhci->lock);
1138 /* Pass this up to the core */
1139 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1140 spin_lock(&xhci->lock);
1144 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1145 * at end_trb, which may be in another segment. If the suspect DMA address is a
1146 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1149 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1150 union xhci_trb *start_trb,
1151 union xhci_trb *end_trb,
1152 dma_addr_t suspect_dma)
1154 dma_addr_t start_dma;
1155 dma_addr_t end_seg_dma;
1156 dma_addr_t end_trb_dma;
1157 struct xhci_segment *cur_seg;
1159 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1160 cur_seg = start_seg;
1165 /* We may get an event for a Link TRB in the middle of a TD */
1166 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1167 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1168 /* If the end TRB isn't in this segment, this is set to 0 */
1169 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1171 if (end_trb_dma > 0) {
1172 /* The end TRB is in this segment, so suspect should be here */
1173 if (start_dma <= end_trb_dma) {
1174 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1177 /* Case for one segment with
1178 * a TD wrapped around to the top
1180 if ((suspect_dma >= start_dma &&
1181 suspect_dma <= end_seg_dma) ||
1182 (suspect_dma >= cur_seg->dma &&
1183 suspect_dma <= end_trb_dma))
1188 /* Might still be somewhere in this segment */
1189 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1192 cur_seg = cur_seg->next;
1193 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1194 } while (cur_seg != start_seg);
1199 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1200 unsigned int slot_id, unsigned int ep_index,
1201 unsigned int stream_id,
1202 struct xhci_td *td, union xhci_trb *event_trb)
1204 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1205 ep->ep_state |= EP_HALTED;
1206 ep->stopped_td = td;
1207 ep->stopped_trb = event_trb;
1208 ep->stopped_stream = stream_id;
1210 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1211 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1213 ep->stopped_td = NULL;
1214 ep->stopped_trb = NULL;
1215 ep->stopped_stream = 0;
1217 xhci_ring_cmd_db(xhci);
1220 /* Check if an error has halted the endpoint ring. The class driver will
1221 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1222 * However, a babble and other errors also halt the endpoint ring, and the class
1223 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1224 * Ring Dequeue Pointer command manually.
1226 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1227 struct xhci_ep_ctx *ep_ctx,
1228 unsigned int trb_comp_code)
1230 /* TRB completion codes that may require a manual halt cleanup */
1231 if (trb_comp_code == COMP_TX_ERR ||
1232 trb_comp_code == COMP_BABBLE ||
1233 trb_comp_code == COMP_SPLIT_ERR)
1234 /* The 0.96 spec says a babbling control endpoint
1235 * is not halted. The 0.96 spec says it is. Some HW
1236 * claims to be 0.95 compliant, but it halts the control
1237 * endpoint anyway. Check if a babble halted the
1240 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1246 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1248 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1249 /* Vendor defined "informational" completion code,
1250 * treat as not-an-error.
1252 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1254 xhci_dbg(xhci, "Treating code as success.\n");
1261 * Finish the td processing, remove the td from td list;
1262 * Return 1 if the urb can be given back.
1264 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1265 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1266 struct xhci_virt_ep *ep, int *status, bool skip)
1268 struct xhci_virt_device *xdev;
1269 struct xhci_ring *ep_ring;
1270 unsigned int slot_id;
1272 struct urb *urb = NULL;
1273 struct xhci_ep_ctx *ep_ctx;
1277 slot_id = TRB_TO_SLOT_ID(event->flags);
1278 xdev = xhci->devs[slot_id];
1279 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1280 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1281 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1282 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1287 if (trb_comp_code == COMP_STOP_INVAL ||
1288 trb_comp_code == COMP_STOP) {
1289 /* The Endpoint Stop Command completion will take care of any
1290 * stopped TDs. A stopped TD may be restarted, so don't update
1291 * the ring dequeue pointer or take this TD off any lists yet.
1293 ep->stopped_td = td;
1294 ep->stopped_trb = event_trb;
1297 if (trb_comp_code == COMP_STALL) {
1298 /* The transfer is completed from the driver's
1299 * perspective, but we need to issue a set dequeue
1300 * command for this stalled endpoint to move the dequeue
1301 * pointer past the TD. We can't do that here because
1302 * the halt condition must be cleared first. Let the
1303 * USB class driver clear the stall later.
1305 ep->stopped_td = td;
1306 ep->stopped_trb = event_trb;
1307 ep->stopped_stream = ep_ring->stream_id;
1308 } else if (xhci_requires_manual_halt_cleanup(xhci,
1309 ep_ctx, trb_comp_code)) {
1310 /* Other types of errors halt the endpoint, but the
1311 * class driver doesn't call usb_reset_endpoint() unless
1312 * the error is -EPIPE. Clear the halted status in the
1313 * xHCI hardware manually.
1315 xhci_cleanup_halted_endpoint(xhci,
1316 slot_id, ep_index, ep_ring->stream_id,
1319 /* Update ring dequeue pointer */
1320 while (ep_ring->dequeue != td->last_trb)
1321 inc_deq(xhci, ep_ring, false);
1322 inc_deq(xhci, ep_ring, false);
1326 /* Clean up the endpoint's TD list */
1329 /* Do one last check of the actual transfer length.
1330 * If the host controller said we transferred more data than
1331 * the buffer length, urb->actual_length will be a very big
1332 * number (since it's unsigned). Play it safe and say we didn't
1333 * transfer anything.
1335 if (urb->actual_length > urb->transfer_buffer_length) {
1336 xhci_warn(xhci, "URB transfer length is wrong, "
1337 "xHC issue? req. len = %u, "
1339 urb->transfer_buffer_length,
1340 urb->actual_length);
1341 urb->actual_length = 0;
1342 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1343 *status = -EREMOTEIO;
1347 list_del(&td->td_list);
1348 /* Was this TD slated to be cancelled but completed anyway? */
1349 if (!list_empty(&td->cancelled_td_list))
1350 list_del(&td->cancelled_td_list);
1359 * Process control tds, update urb status and actual_length.
1361 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1362 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1363 struct xhci_virt_ep *ep, int *status)
1365 struct xhci_virt_device *xdev;
1366 struct xhci_ring *ep_ring;
1367 unsigned int slot_id;
1369 struct xhci_ep_ctx *ep_ctx;
1372 slot_id = TRB_TO_SLOT_ID(event->flags);
1373 xdev = xhci->devs[slot_id];
1374 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1375 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1376 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1377 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1379 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1380 switch (trb_comp_code) {
1382 if (event_trb == ep_ring->dequeue) {
1383 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1384 "without IOC set??\n");
1385 *status = -ESHUTDOWN;
1386 } else if (event_trb != td->last_trb) {
1387 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1388 "without IOC set??\n");
1389 *status = -ESHUTDOWN;
1391 xhci_dbg(xhci, "Successful control transfer!\n");
1396 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1397 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1398 *status = -EREMOTEIO;
1403 if (!xhci_requires_manual_halt_cleanup(xhci,
1404 ep_ctx, trb_comp_code))
1406 xhci_dbg(xhci, "TRB error code %u, "
1407 "halted endpoint index = %u\n",
1408 trb_comp_code, ep_index);
1409 /* else fall through */
1411 /* Did we transfer part of the data (middle) phase? */
1412 if (event_trb != ep_ring->dequeue &&
1413 event_trb != td->last_trb)
1414 td->urb->actual_length =
1415 td->urb->transfer_buffer_length
1416 - TRB_LEN(event->transfer_len);
1418 td->urb->actual_length = 0;
1420 xhci_cleanup_halted_endpoint(xhci,
1421 slot_id, ep_index, 0, td, event_trb);
1422 return finish_td(xhci, td, event_trb, event, ep, status, true);
1425 * Did we transfer any data, despite the errors that might have
1426 * happened? I.e. did we get past the setup stage?
1428 if (event_trb != ep_ring->dequeue) {
1429 /* The event was for the status stage */
1430 if (event_trb == td->last_trb) {
1431 if (td->urb->actual_length != 0) {
1432 /* Don't overwrite a previously set error code
1434 if ((*status == -EINPROGRESS || *status == 0) &&
1435 (td->urb->transfer_flags
1436 & URB_SHORT_NOT_OK))
1437 /* Did we already see a short data
1439 *status = -EREMOTEIO;
1441 td->urb->actual_length =
1442 td->urb->transfer_buffer_length;
1445 /* Maybe the event was for the data stage? */
1446 if (trb_comp_code != COMP_STOP_INVAL) {
1447 /* We didn't stop on a link TRB in the middle */
1448 td->urb->actual_length =
1449 td->urb->transfer_buffer_length -
1450 TRB_LEN(event->transfer_len);
1451 xhci_dbg(xhci, "Waiting for status "
1458 return finish_td(xhci, td, event_trb, event, ep, status, false);
1462 * Process bulk and interrupt tds, update urb status and actual_length.
1464 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1465 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1466 struct xhci_virt_ep *ep, int *status)
1468 struct xhci_ring *ep_ring;
1469 union xhci_trb *cur_trb;
1470 struct xhci_segment *cur_seg;
1473 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1474 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1476 switch (trb_comp_code) {
1478 /* Double check that the HW transferred everything. */
1479 if (event_trb != td->last_trb) {
1480 xhci_warn(xhci, "WARN Successful completion "
1482 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1483 *status = -EREMOTEIO;
1487 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1488 xhci_dbg(xhci, "Successful bulk "
1491 xhci_dbg(xhci, "Successful interrupt "
1497 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1498 *status = -EREMOTEIO;
1503 /* Others already handled above */
1506 dev_dbg(&td->urb->dev->dev,
1507 "ep %#x - asked for %d bytes, "
1508 "%d bytes untransferred\n",
1509 td->urb->ep->desc.bEndpointAddress,
1510 td->urb->transfer_buffer_length,
1511 TRB_LEN(event->transfer_len));
1512 /* Fast path - was this the last TRB in the TD for this URB? */
1513 if (event_trb == td->last_trb) {
1514 if (TRB_LEN(event->transfer_len) != 0) {
1515 td->urb->actual_length =
1516 td->urb->transfer_buffer_length -
1517 TRB_LEN(event->transfer_len);
1518 if (td->urb->transfer_buffer_length <
1519 td->urb->actual_length) {
1520 xhci_warn(xhci, "HC gave bad length "
1521 "of %d bytes left\n",
1522 TRB_LEN(event->transfer_len));
1523 td->urb->actual_length = 0;
1524 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1525 *status = -EREMOTEIO;
1529 /* Don't overwrite a previously set error code */
1530 if (*status == -EINPROGRESS) {
1531 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1532 *status = -EREMOTEIO;
1537 td->urb->actual_length =
1538 td->urb->transfer_buffer_length;
1539 /* Ignore a short packet completion if the
1540 * untransferred length was zero.
1542 if (*status == -EREMOTEIO)
1546 /* Slow path - walk the list, starting from the dequeue
1547 * pointer, to get the actual length transferred.
1549 td->urb->actual_length = 0;
1550 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1551 cur_trb != event_trb;
1552 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1553 if ((cur_trb->generic.field[3] &
1554 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1555 (cur_trb->generic.field[3] &
1556 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1557 td->urb->actual_length +=
1558 TRB_LEN(cur_trb->generic.field[2]);
1560 /* If the ring didn't stop on a Link or No-op TRB, add
1561 * in the actual bytes transferred from the Normal TRB
1563 if (trb_comp_code != COMP_STOP_INVAL)
1564 td->urb->actual_length +=
1565 TRB_LEN(cur_trb->generic.field[2]) -
1566 TRB_LEN(event->transfer_len);
1569 return finish_td(xhci, td, event_trb, event, ep, status, false);
1573 * If this function returns an error condition, it means it got a Transfer
1574 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1575 * At this point, the host controller is probably hosed and should be reset.
1577 static int handle_tx_event(struct xhci_hcd *xhci,
1578 struct xhci_transfer_event *event)
1580 struct xhci_virt_device *xdev;
1581 struct xhci_virt_ep *ep;
1582 struct xhci_ring *ep_ring;
1583 unsigned int slot_id;
1585 struct xhci_td *td = NULL;
1586 dma_addr_t event_dma;
1587 struct xhci_segment *event_seg;
1588 union xhci_trb *event_trb;
1589 struct urb *urb = NULL;
1590 int status = -EINPROGRESS;
1591 struct xhci_ep_ctx *ep_ctx;
1595 slot_id = TRB_TO_SLOT_ID(event->flags);
1596 xdev = xhci->devs[slot_id];
1598 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1602 /* Endpoint ID is 1 based, our index is zero based */
1603 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1604 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1605 ep = &xdev->eps[ep_index];
1606 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1607 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1609 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1610 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1611 "or incorrect stream ring\n");
1615 event_dma = event->buffer;
1616 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1617 /* Look for common error cases */
1618 switch (trb_comp_code) {
1619 /* Skip codes that require special handling depending on
1626 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1628 case COMP_STOP_INVAL:
1629 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1632 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1633 ep->ep_state |= EP_HALTED;
1637 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1640 case COMP_SPLIT_ERR:
1642 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1646 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1647 status = -EOVERFLOW;
1650 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1654 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1656 case COMP_BUFF_OVER:
1657 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1661 * When the Isoch ring is empty, the xHC will generate
1662 * a Ring Overrun Event for IN Isoch endpoint or Ring
1663 * Underrun Event for OUT Isoch endpoint.
1665 xhci_dbg(xhci, "underrun event on endpoint\n");
1666 if (!list_empty(&ep_ring->td_list))
1667 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1668 "still with TDs queued?\n",
1669 TRB_TO_SLOT_ID(event->flags), ep_index);
1672 xhci_dbg(xhci, "overrun event on endpoint\n");
1673 if (!list_empty(&ep_ring->td_list))
1674 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1675 "still with TDs queued?\n",
1676 TRB_TO_SLOT_ID(event->flags), ep_index);
1678 case COMP_MISSED_INT:
1680 * When encounter missed service error, one or more isoc tds
1681 * may be missed by xHC.
1682 * Set skip flag of the ep_ring; Complete the missed tds as
1683 * short transfer when process the ep_ring next time.
1686 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1689 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1693 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1699 /* This TRB should be in the TD at the head of this ring's
1702 if (list_empty(&ep_ring->td_list)) {
1703 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1704 "with no TDs queued?\n",
1705 TRB_TO_SLOT_ID(event->flags), ep_index);
1706 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1707 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1708 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1711 xhci_dbg(xhci, "td_list is empty while skip "
1712 "flag set. Clear skip flag.\n");
1718 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1719 /* Is this a TRB in the currently executing TD? */
1720 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1721 td->last_trb, event_dma);
1722 if (event_seg && ep->skip) {
1723 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
1727 (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
1728 /* HC is busted, give up! */
1729 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
1730 "part of current TD\n");
1735 event_trb = &event_seg->trbs[(event_dma -
1736 event_seg->dma) / sizeof(*event_trb)];
1738 * No-op TRB should not trigger interrupts.
1739 * If event_trb is a no-op TRB, it means the
1740 * corresponding TD has been cancelled. Just ignore
1743 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
1744 == TRB_TYPE(TRB_TR_NOOP)) {
1745 xhci_dbg(xhci, "event_trb is a no-op TRB. "
1751 /* Now update the urb's actual_length and give back to
1754 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
1755 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
1758 ret = process_bulk_intr_td(xhci, td, event_trb, event,
1763 * Do not update event ring dequeue pointer if ep->skip is set.
1764 * Will roll back to continue process missed tds.
1766 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
1767 inc_deq(xhci, xhci->event_ring, true);
1768 xhci_set_hc_event_deq(xhci);
1773 /* Leave the TD around for the reset endpoint function
1774 * to use(but only if it's not a control endpoint,
1775 * since we already queued the Set TR dequeue pointer
1776 * command for stalled control endpoints).
1778 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1779 (trb_comp_code != COMP_STALL &&
1780 trb_comp_code != COMP_BABBLE))
1783 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1784 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1786 urb, urb->actual_length, status);
1787 spin_unlock(&xhci->lock);
1788 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1789 spin_lock(&xhci->lock);
1793 * If ep->skip is set, it means there are missed tds on the
1794 * endpoint ring need to take care of.
1795 * Process them as short transfer until reach the td pointed by
1798 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
1804 * This function handles all OS-owned events on the event ring. It may drop
1805 * xhci->lock between event processing (e.g. to pass up port status changes).
1807 void xhci_handle_event(struct xhci_hcd *xhci)
1809 union xhci_trb *event;
1810 int update_ptrs = 1;
1813 xhci_dbg(xhci, "In %s\n", __func__);
1814 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1815 xhci->error_bitmask |= 1 << 1;
1819 event = xhci->event_ring->dequeue;
1820 /* Does the HC or OS own the TRB? */
1821 if ((event->event_cmd.flags & TRB_CYCLE) !=
1822 xhci->event_ring->cycle_state) {
1823 xhci->error_bitmask |= 1 << 2;
1826 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1828 /* FIXME: Handle more event types. */
1829 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1830 case TRB_TYPE(TRB_COMPLETION):
1831 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1832 handle_cmd_completion(xhci, &event->event_cmd);
1833 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1835 case TRB_TYPE(TRB_PORT_STATUS):
1836 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1837 handle_port_status(xhci, event);
1838 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1841 case TRB_TYPE(TRB_TRANSFER):
1842 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1843 ret = handle_tx_event(xhci, &event->trans_event);
1844 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1846 xhci->error_bitmask |= 1 << 9;
1851 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
1852 handle_vendor_event(xhci, event);
1854 xhci->error_bitmask |= 1 << 3;
1856 /* Any of the above functions may drop and re-acquire the lock, so check
1857 * to make sure a watchdog timer didn't mark the host as non-responsive.
1859 if (xhci->xhc_state & XHCI_STATE_DYING) {
1860 xhci_dbg(xhci, "xHCI host dying, returning from "
1861 "event handler.\n");
1866 /* Update SW and HC event ring dequeue pointer */
1867 inc_deq(xhci, xhci->event_ring, true);
1868 xhci_set_hc_event_deq(xhci);
1870 /* Are there more items on the event ring? */
1871 xhci_handle_event(xhci);
1874 /**** Endpoint Ring Operations ****/
1877 * Generic function for queueing a TRB on a ring.
1878 * The caller must have checked to make sure there's room on the ring.
1880 * @more_trbs_coming: Will you enqueue more TRBs before calling
1881 * prepare_transfer()?
1883 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1884 bool consumer, bool more_trbs_coming,
1885 u32 field1, u32 field2, u32 field3, u32 field4)
1887 struct xhci_generic_trb *trb;
1889 trb = &ring->enqueue->generic;
1890 trb->field[0] = field1;
1891 trb->field[1] = field2;
1892 trb->field[2] = field3;
1893 trb->field[3] = field4;
1894 inc_enq(xhci, ring, consumer, more_trbs_coming);
1898 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1899 * FIXME allocate segments if the ring is full.
1901 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1902 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1904 /* Make sure the endpoint has been added to xHC schedule */
1905 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1907 case EP_STATE_DISABLED:
1909 * USB core changed config/interfaces without notifying us,
1910 * or hardware is reporting the wrong state.
1912 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1914 case EP_STATE_ERROR:
1915 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1916 /* FIXME event handling code for error needs to clear it */
1917 /* XXX not sure if this should be -ENOENT or not */
1919 case EP_STATE_HALTED:
1920 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1921 case EP_STATE_STOPPED:
1922 case EP_STATE_RUNNING:
1925 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1927 * FIXME issue Configure Endpoint command to try to get the HC
1928 * back into a known state.
1932 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1933 /* FIXME allocate more room */
1934 xhci_err(xhci, "ERROR no room on ep ring\n");
1938 if (enqueue_is_link_trb(ep_ring)) {
1939 struct xhci_ring *ring = ep_ring;
1940 union xhci_trb *next;
1942 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
1943 next = ring->enqueue;
1945 while (last_trb(xhci, ring, ring->enq_seg, next)) {
1947 /* If we're not dealing with 0.95 hardware,
1948 * clear the chain bit.
1950 if (!xhci_link_trb_quirk(xhci))
1951 next->link.control &= ~TRB_CHAIN;
1953 next->link.control |= TRB_CHAIN;
1956 next->link.control ^= (u32) TRB_CYCLE;
1958 /* Toggle the cycle bit after the last ring segment. */
1959 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
1960 ring->cycle_state = (ring->cycle_state ? 0 : 1);
1961 if (!in_interrupt()) {
1962 xhci_dbg(xhci, "queue_trb: Toggle cycle "
1963 "state for ring %p = %i\n",
1964 ring, (unsigned int)ring->cycle_state);
1967 ring->enq_seg = ring->enq_seg->next;
1968 ring->enqueue = ring->enq_seg->trbs;
1969 next = ring->enqueue;
1976 static int prepare_transfer(struct xhci_hcd *xhci,
1977 struct xhci_virt_device *xdev,
1978 unsigned int ep_index,
1979 unsigned int stream_id,
1980 unsigned int num_trbs,
1982 struct xhci_td **td,
1986 struct xhci_ring *ep_ring;
1987 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1989 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
1991 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
1996 ret = prepare_ring(xhci, ep_ring,
1997 ep_ctx->ep_info & EP_STATE_MASK,
1998 num_trbs, mem_flags);
2001 *td = kzalloc(sizeof(struct xhci_td), mem_flags);
2004 INIT_LIST_HEAD(&(*td)->td_list);
2005 INIT_LIST_HEAD(&(*td)->cancelled_td_list);
2007 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
2008 if (unlikely(ret)) {
2014 urb->hcpriv = (void *) (*td);
2015 /* Add this TD to the tail of the endpoint ring's TD list */
2016 list_add_tail(&(*td)->td_list, &ep_ring->td_list);
2017 (*td)->start_seg = ep_ring->enq_seg;
2018 (*td)->first_trb = ep_ring->enqueue;
2023 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2025 int num_sgs, num_trbs, running_total, temp, i;
2026 struct scatterlist *sg;
2029 num_sgs = urb->num_sgs;
2030 temp = urb->transfer_buffer_length;
2032 xhci_dbg(xhci, "count sg list trbs: \n");
2034 for_each_sg(urb->sg, sg, num_sgs, i) {
2035 unsigned int previous_total_trbs = num_trbs;
2036 unsigned int len = sg_dma_len(sg);
2038 /* Scatter gather list entries may cross 64KB boundaries */
2039 running_total = TRB_MAX_BUFF_SIZE -
2040 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2041 if (running_total != 0)
2044 /* How many more 64KB chunks to transfer, how many more TRBs? */
2045 while (running_total < sg_dma_len(sg)) {
2047 running_total += TRB_MAX_BUFF_SIZE;
2049 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2050 i, (unsigned long long)sg_dma_address(sg),
2051 len, len, num_trbs - previous_total_trbs);
2053 len = min_t(int, len, temp);
2058 xhci_dbg(xhci, "\n");
2059 if (!in_interrupt())
2060 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
2061 urb->ep->desc.bEndpointAddress,
2062 urb->transfer_buffer_length,
2067 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2070 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2071 "TRBs, %d left\n", __func__,
2072 urb->ep->desc.bEndpointAddress, num_trbs);
2073 if (running_total != urb->transfer_buffer_length)
2074 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2075 "queued %#x (%d), asked for %#x (%d)\n",
2077 urb->ep->desc.bEndpointAddress,
2078 running_total, running_total,
2079 urb->transfer_buffer_length,
2080 urb->transfer_buffer_length);
2083 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2084 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2085 struct xhci_generic_trb *start_trb, struct xhci_td *td)
2088 * Pass all the TRBs to the hardware at once and make sure this write
2092 start_trb->field[3] |= start_cycle;
2093 ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2097 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2098 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2099 * (comprised of sg list entries) can take several service intervals to
2102 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2103 struct urb *urb, int slot_id, unsigned int ep_index)
2105 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2106 xhci->devs[slot_id]->out_ctx, ep_index);
2110 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2111 ep_interval = urb->interval;
2112 /* Convert to microframes */
2113 if (urb->dev->speed == USB_SPEED_LOW ||
2114 urb->dev->speed == USB_SPEED_FULL)
2116 /* FIXME change this to a warning and a suggestion to use the new API
2117 * to set the polling interval (once the API is added).
2119 if (xhci_interval != ep_interval) {
2120 if (!printk_ratelimit())
2121 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2122 " (%d microframe%s) than xHCI "
2123 "(%d microframe%s)\n",
2125 ep_interval == 1 ? "" : "s",
2127 xhci_interval == 1 ? "" : "s");
2128 urb->interval = xhci_interval;
2129 /* Convert back to frames for LS/FS devices */
2130 if (urb->dev->speed == USB_SPEED_LOW ||
2131 urb->dev->speed == USB_SPEED_FULL)
2134 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2138 * The TD size is the number of bytes remaining in the TD (including this TRB),
2139 * right shifted by 10.
2140 * It must fit in bits 21:17, so it can't be bigger than 31.
2142 static u32 xhci_td_remainder(unsigned int remainder)
2144 u32 max = (1 << (21 - 17 + 1)) - 1;
2146 if ((remainder >> 10) >= max)
2149 return (remainder >> 10) << 17;
2152 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2153 struct urb *urb, int slot_id, unsigned int ep_index)
2155 struct xhci_ring *ep_ring;
2156 unsigned int num_trbs;
2158 struct scatterlist *sg;
2160 int trb_buff_len, this_sg_len, running_total;
2163 bool more_trbs_coming;
2165 struct xhci_generic_trb *start_trb;
2168 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2172 num_trbs = count_sg_trbs_needed(xhci, urb);
2173 num_sgs = urb->num_sgs;
2175 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2176 ep_index, urb->stream_id,
2177 num_trbs, urb, &td, mem_flags);
2178 if (trb_buff_len < 0)
2179 return trb_buff_len;
2181 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2182 * until we've finished creating all the other TRBs. The ring's cycle
2183 * state may change as we enqueue the other TRBs, so save it too.
2185 start_trb = &ep_ring->enqueue->generic;
2186 start_cycle = ep_ring->cycle_state;
2190 * How much data is in the first TRB?
2192 * There are three forces at work for TRB buffer pointers and lengths:
2193 * 1. We don't want to walk off the end of this sg-list entry buffer.
2194 * 2. The transfer length that the driver requested may be smaller than
2195 * the amount of memory allocated for this scatter-gather list.
2196 * 3. TRBs buffers can't cross 64KB boundaries.
2199 addr = (u64) sg_dma_address(sg);
2200 this_sg_len = sg_dma_len(sg);
2201 trb_buff_len = TRB_MAX_BUFF_SIZE -
2202 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2203 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2204 if (trb_buff_len > urb->transfer_buffer_length)
2205 trb_buff_len = urb->transfer_buffer_length;
2206 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2210 /* Queue the first TRB, even if it's zero-length */
2213 u32 length_field = 0;
2216 /* Don't change the cycle bit of the first TRB until later */
2220 field |= ep_ring->cycle_state;
2222 /* Chain all the TRBs together; clear the chain bit in the last
2223 * TRB to indicate it's the last TRB in the chain.
2228 /* FIXME - add check for ZERO_PACKET flag before this */
2229 td->last_trb = ep_ring->enqueue;
2232 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2233 "64KB boundary at %#x, end dma = %#x\n",
2234 (unsigned int) addr, trb_buff_len, trb_buff_len,
2235 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2236 (unsigned int) addr + trb_buff_len);
2237 if (TRB_MAX_BUFF_SIZE -
2238 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
2239 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2240 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2241 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2242 (unsigned int) addr + trb_buff_len);
2244 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2246 length_field = TRB_LEN(trb_buff_len) |
2250 more_trbs_coming = true;
2252 more_trbs_coming = false;
2253 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2254 lower_32_bits(addr),
2255 upper_32_bits(addr),
2257 /* We always want to know if the TRB was short,
2258 * or we won't get an event when it completes.
2259 * (Unless we use event data TRBs, which are a
2260 * waste of space and HC resources.)
2262 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2264 running_total += trb_buff_len;
2266 /* Calculate length for next transfer --
2267 * Are we done queueing all the TRBs for this sg entry?
2269 this_sg_len -= trb_buff_len;
2270 if (this_sg_len == 0) {
2275 addr = (u64) sg_dma_address(sg);
2276 this_sg_len = sg_dma_len(sg);
2278 addr += trb_buff_len;
2281 trb_buff_len = TRB_MAX_BUFF_SIZE -
2282 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2283 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2284 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2286 urb->transfer_buffer_length - running_total;
2287 } while (running_total < urb->transfer_buffer_length);
2289 check_trb_math(urb, num_trbs, running_total);
2290 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2291 start_cycle, start_trb, td);
2295 /* This is very similar to what ehci-q.c qtd_fill() does */
2296 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2297 struct urb *urb, int slot_id, unsigned int ep_index)
2299 struct xhci_ring *ep_ring;
2302 struct xhci_generic_trb *start_trb;
2304 bool more_trbs_coming;
2306 u32 field, length_field;
2308 int running_total, trb_buff_len, ret;
2312 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2314 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2319 /* How much data is (potentially) left before the 64KB boundary? */
2320 running_total = TRB_MAX_BUFF_SIZE -
2321 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2323 /* If there's some data on this 64KB chunk, or we have to send a
2324 * zero-length transfer, we need at least one TRB
2326 if (running_total != 0 || urb->transfer_buffer_length == 0)
2328 /* How many more 64KB chunks to transfer, how many more TRBs? */
2329 while (running_total < urb->transfer_buffer_length) {
2331 running_total += TRB_MAX_BUFF_SIZE;
2333 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2335 if (!in_interrupt())
2336 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2337 urb->ep->desc.bEndpointAddress,
2338 urb->transfer_buffer_length,
2339 urb->transfer_buffer_length,
2340 (unsigned long long)urb->transfer_dma,
2343 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2344 ep_index, urb->stream_id,
2345 num_trbs, urb, &td, mem_flags);
2350 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2351 * until we've finished creating all the other TRBs. The ring's cycle
2352 * state may change as we enqueue the other TRBs, so save it too.
2354 start_trb = &ep_ring->enqueue->generic;
2355 start_cycle = ep_ring->cycle_state;
2358 /* How much data is in the first TRB? */
2359 addr = (u64) urb->transfer_dma;
2360 trb_buff_len = TRB_MAX_BUFF_SIZE -
2361 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2362 if (urb->transfer_buffer_length < trb_buff_len)
2363 trb_buff_len = urb->transfer_buffer_length;
2367 /* Queue the first TRB, even if it's zero-length */
2372 /* Don't change the cycle bit of the first TRB until later */
2376 field |= ep_ring->cycle_state;
2378 /* Chain all the TRBs together; clear the chain bit in the last
2379 * TRB to indicate it's the last TRB in the chain.
2384 /* FIXME - add check for ZERO_PACKET flag before this */
2385 td->last_trb = ep_ring->enqueue;
2388 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2390 length_field = TRB_LEN(trb_buff_len) |
2394 more_trbs_coming = true;
2396 more_trbs_coming = false;
2397 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2398 lower_32_bits(addr),
2399 upper_32_bits(addr),
2401 /* We always want to know if the TRB was short,
2402 * or we won't get an event when it completes.
2403 * (Unless we use event data TRBs, which are a
2404 * waste of space and HC resources.)
2406 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2408 running_total += trb_buff_len;
2410 /* Calculate length for next transfer */
2411 addr += trb_buff_len;
2412 trb_buff_len = urb->transfer_buffer_length - running_total;
2413 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2414 trb_buff_len = TRB_MAX_BUFF_SIZE;
2415 } while (running_total < urb->transfer_buffer_length);
2417 check_trb_math(urb, num_trbs, running_total);
2418 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2419 start_cycle, start_trb, td);
2423 /* Caller must have locked xhci->lock */
2424 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2425 struct urb *urb, int slot_id, unsigned int ep_index)
2427 struct xhci_ring *ep_ring;
2430 struct usb_ctrlrequest *setup;
2431 struct xhci_generic_trb *start_trb;
2433 u32 field, length_field;
2436 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2441 * Need to copy setup packet into setup TRB, so we can't use the setup
2444 if (!urb->setup_packet)
2447 if (!in_interrupt())
2448 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2450 /* 1 TRB for setup, 1 for status */
2453 * Don't need to check if we need additional event data and normal TRBs,
2454 * since data in control transfers will never get bigger than 16MB
2455 * XXX: can we get a buffer that crosses 64KB boundaries?
2457 if (urb->transfer_buffer_length > 0)
2459 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2460 ep_index, urb->stream_id,
2461 num_trbs, urb, &td, mem_flags);
2466 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2467 * until we've finished creating all the other TRBs. The ring's cycle
2468 * state may change as we enqueue the other TRBs, so save it too.
2470 start_trb = &ep_ring->enqueue->generic;
2471 start_cycle = ep_ring->cycle_state;
2473 /* Queue setup TRB - see section 6.4.1.2.1 */
2474 /* FIXME better way to translate setup_packet into two u32 fields? */
2475 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2476 queue_trb(xhci, ep_ring, false, true,
2477 /* FIXME endianness is probably going to bite my ass here. */
2478 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2479 setup->wIndex | setup->wLength << 16,
2480 TRB_LEN(8) | TRB_INTR_TARGET(0),
2481 /* Immediate data in pointer */
2482 TRB_IDT | TRB_TYPE(TRB_SETUP));
2484 /* If there's data, queue data TRBs */
2486 length_field = TRB_LEN(urb->transfer_buffer_length) |
2487 xhci_td_remainder(urb->transfer_buffer_length) |
2489 if (urb->transfer_buffer_length > 0) {
2490 if (setup->bRequestType & USB_DIR_IN)
2491 field |= TRB_DIR_IN;
2492 queue_trb(xhci, ep_ring, false, true,
2493 lower_32_bits(urb->transfer_dma),
2494 upper_32_bits(urb->transfer_dma),
2496 /* Event on short tx */
2497 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2500 /* Save the DMA address of the last TRB in the TD */
2501 td->last_trb = ep_ring->enqueue;
2503 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2504 /* If the device sent data, the status stage is an OUT transfer */
2505 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2509 queue_trb(xhci, ep_ring, false, false,
2513 /* Event on completion */
2514 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2516 giveback_first_trb(xhci, slot_id, ep_index, 0,
2517 start_cycle, start_trb, td);
2521 /**** Command Ring Operations ****/
2523 /* Generic function for queueing a command TRB on the command ring.
2524 * Check to make sure there's room on the command ring for one command TRB.
2525 * Also check that there's room reserved for commands that must not fail.
2526 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2527 * then only check for the number of reserved spots.
2528 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2529 * because the command event handler may want to resubmit a failed command.
2531 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2532 u32 field3, u32 field4, bool command_must_succeed)
2534 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2537 if (!command_must_succeed)
2540 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
2541 reserved_trbs, GFP_ATOMIC);
2543 xhci_err(xhci, "ERR: No room for command on command ring\n");
2544 if (command_must_succeed)
2545 xhci_err(xhci, "ERR: Reserved TRB counting for "
2546 "unfailable commands failed.\n");
2549 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
2550 field4 | xhci->cmd_ring->cycle_state);
2554 /* Queue a no-op command on the command ring */
2555 static int queue_cmd_noop(struct xhci_hcd *xhci)
2557 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2561 * Place a no-op command on the command ring to test the command and
2564 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2566 if (queue_cmd_noop(xhci) < 0)
2568 xhci->noops_submitted++;
2569 return xhci_ring_cmd_db;
2572 /* Queue a slot enable or disable request on the command ring */
2573 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2575 return queue_command(xhci, 0, 0, 0,
2576 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2579 /* Queue an address device command TRB */
2580 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2583 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2584 upper_32_bits(in_ctx_ptr), 0,
2585 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2589 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
2590 u32 field1, u32 field2, u32 field3, u32 field4)
2592 return queue_command(xhci, field1, field2, field3, field4, false);
2595 /* Queue a reset device command TRB */
2596 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
2598 return queue_command(xhci, 0, 0, 0,
2599 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
2603 /* Queue a configure endpoint command TRB */
2604 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2605 u32 slot_id, bool command_must_succeed)
2607 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2608 upper_32_bits(in_ctx_ptr), 0,
2609 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2610 command_must_succeed);
2613 /* Queue an evaluate context command TRB */
2614 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2617 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2618 upper_32_bits(in_ctx_ptr), 0,
2619 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2623 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2624 unsigned int ep_index)
2626 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2627 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2628 u32 type = TRB_TYPE(TRB_STOP_RING);
2630 return queue_command(xhci, 0, 0, 0,
2631 trb_slot_id | trb_ep_index | type, false);
2634 /* Set Transfer Ring Dequeue Pointer command.
2635 * This should not be used for endpoints that have streams enabled.
2637 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2638 unsigned int ep_index, unsigned int stream_id,
2639 struct xhci_segment *deq_seg,
2640 union xhci_trb *deq_ptr, u32 cycle_state)
2643 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2644 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2645 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
2646 u32 type = TRB_TYPE(TRB_SET_DEQ);
2648 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2650 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2651 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2655 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2656 upper_32_bits(addr), trb_stream_id,
2657 trb_slot_id | trb_ep_index | type, false);
2660 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2661 unsigned int ep_index)
2663 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2664 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2665 u32 type = TRB_TYPE(TRB_RESET_EP);
2667 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,