drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 /*
  72  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  73  * address of the TRB.
  74  */
  75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  76                 union xhci_trb *trb)
  77 {
  78         unsigned long segment_offset;
  79
  80         if (!seg || !trb || trb < seg->trbs)
  81                 return 0;
  82         /* offset in TRBs */
  83         segment_offset = trb - seg->trbs;
  84         if (segment_offset > TRBS_PER_SEGMENT)
  85                 return 0;
  86         return seg->dma + (segment_offset * sizeof(*trb));
  87 }
  88
  89 /* Does this link TRB point to the first segment in a ring,
  90  * or was the previous TRB the last TRB on the last segment in the ERST?
  91  */
  92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  93                 struct xhci_segment *seg, union xhci_trb *trb)
  94 {
  95         if (ring == xhci->event_ring)
  96                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  97                         (seg->next == xhci->event_ring->first_seg);
  98         else
  99                 return trb->link.control & LINK_TOGGLE;
 100 }
 101
 102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 103  * segment?  I.e. would the updated event TRB pointer step off the end of the
 104  * event seg?
 105  */
 106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 107                 struct xhci_segment *seg, union xhci_trb *trb)
 108 {
 109         if (ring == xhci->event_ring)
 110                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 111         else
 112                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 113 }
 114
 115 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
 116 {
 117         struct xhci_link_trb *link = &ring->enqueue->link;
 118         return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
 119 }
 120
 121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 122  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 123  * effect the ring dequeue or enqueue pointers.
 124  */
 125 static void next_trb(struct xhci_hcd *xhci,
 126                 struct xhci_ring *ring,
 127                 struct xhci_segment **seg,
 128                 union xhci_trb **trb)
 129 {
 130         if (last_trb(xhci, ring, *seg, *trb)) {
 131                 *seg = (*seg)->next;
 132                 *trb = ((*seg)->trbs);
 133         } else {
 134                 *trb = (*trb)++;
 135         }
 136 }
 137
 138 /*
 139  * See Cycle bit rules. SW is the consumer for the event ring only.
 140  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 141  */
 142 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 143 {
 144         union xhci_trb *next = ++(ring->dequeue);
 145         unsigned long long addr;
 146
 147         ring->deq_updates++;
 148         /* Update the dequeue pointer further if that was a link TRB or we're at
 149          * the end of an event ring segment (which doesn't have link TRBS)
 150          */
 151         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 152                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 153                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 154                         if (!in_interrupt())
 155                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 156                                                 ring,
 157                                                 (unsigned int) ring->cycle_state);
 158                 }
 159                 ring->deq_seg = ring->deq_seg->next;
 160                 ring->dequeue = ring->deq_seg->trbs;
 161                 next = ring->dequeue;
 162         }
 163         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 164         if (ring == xhci->event_ring)
 165                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 166         else if (ring == xhci->cmd_ring)
 167                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 168         else
 169                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 170 }
 171
 172 /*
 173  * See Cycle bit rules. SW is the consumer for the event ring only.
 174  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 175  *
 176  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 177  * chain bit is set), then set the chain bit in all the following link TRBs.
 178  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 179  * have their chain bit cleared (so that each Link TRB is a separate TD).
 180  *
 181  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 182  * set, but other sections talk about dealing with the chain bit set.  This was
 183  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 184  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 185  *
 186  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 187  *                      prepare_transfer()?
 188  */
 189 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 190                 bool consumer, bool more_trbs_coming)
 191 {
 192         u32 chain;
 193         union xhci_trb *next;
 194         unsigned long long addr;
 195
 196         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 197         next = ++(ring->enqueue);
 198
 199         ring->enq_updates++;
 200         /* Update the dequeue pointer further if that was a link TRB or we're at
 201          * the end of an event ring segment (which doesn't have link TRBS)
 202          */
 203         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 204                 if (!consumer) {
 205                         if (ring != xhci->event_ring) {
 206                                 /*
 207                                  * If the caller doesn't plan on enqueueing more
 208                                  * TDs before ringing the doorbell, then we
 209                                  * don't want to give the link TRB to the
 210                                  * hardware just yet.  We'll give the link TRB
 211                                  * back in prepare_ring() just before we enqueue
 212                                  * the TD at the top of the ring.
 213                                  */
 214                                 if (!chain && !more_trbs_coming)
 215                                         break;
 216
 217                                 /* If we're not dealing with 0.95 hardware,
 218                                  * carry over the chain bit of the previous TRB
 219                                  * (which may mean the chain bit is cleared).
 220                                  */
 221                                 if (!xhci_link_trb_quirk(xhci)) {
 222                                         next->link.control &= ~TRB_CHAIN;
 223                                         next->link.control |= chain;
 224                                 }
 225                                 /* Give this link TRB to the hardware */
 226                                 wmb();
 227                                 next->link.control ^= TRB_CYCLE;
 228                         }
 229                         /* Toggle the cycle bit after the last ring segment. */
 230                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 231                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 232                                 if (!in_interrupt())
 233                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 234                                                         ring,
 235                                                         (unsigned int) ring->cycle_state);
 236                         }
 237                 }
 238                 ring->enq_seg = ring->enq_seg->next;
 239                 ring->enqueue = ring->enq_seg->trbs;
 240                 next = ring->enqueue;
 241         }
 242         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 243         if (ring == xhci->event_ring)
 244                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 245         else if (ring == xhci->cmd_ring)
 246                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 247         else
 248                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 249 }
 250
 251 /*
 252  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 253  * above.
 254  * FIXME: this would be simpler and faster if we just kept track of the number
 255  * of free TRBs in a ring.
 256  */
 257 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 258                 unsigned int num_trbs)
 259 {
 260         int i;
 261         union xhci_trb *enq = ring->enqueue;
 262         struct xhci_segment *enq_seg = ring->enq_seg;
 263         struct xhci_segment *cur_seg;
 264         unsigned int left_on_ring;
 265
 266         /* If we are currently pointing to a link TRB, advance the
 267          * enqueue pointer before checking for space */
 268         while (last_trb(xhci, ring, enq_seg, enq)) {
 269                 enq_seg = enq_seg->next;
 270                 enq = enq_seg->trbs;
 271         }
 272
 273         /* Check if ring is empty */
 274         if (enq == ring->dequeue) {
 275                 /* Can't use link trbs */
 276                 left_on_ring = TRBS_PER_SEGMENT - 1;
 277                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 278                                 cur_seg = cur_seg->next)
 279                         left_on_ring += TRBS_PER_SEGMENT - 1;
 280
 281                 /* Always need one TRB free in the ring. */
 282                 left_on_ring -= 1;
 283                 if (num_trbs > left_on_ring) {
 284                         xhci_warn(xhci, "Not enough room on ring; "
 285                                         "need %u TRBs, %u TRBs left\n",
 286                                         num_trbs, left_on_ring);
 287                         return 0;
 288                 }
 289                 return 1;
 290         }
 291         /* Make sure there's an extra empty TRB available */
 292         for (i = 0; i <= num_trbs; ++i) {
 293                 if (enq == ring->dequeue)
 294                         return 0;
 295                 enq++;
 296                 while (last_trb(xhci, ring, enq_seg, enq)) {
 297                         enq_seg = enq_seg->next;
 298                         enq = enq_seg->trbs;
 299                 }
 300         }
 301         return 1;
 302 }
 303
 304 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 305 {
 306         u64 temp;
 307         dma_addr_t deq;
 308
 309         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 310                         xhci->event_ring->dequeue);
 311         if (deq == 0 && !in_interrupt())
 312                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 313                                 "dequeue ptr.\n");
 314         /* Update HC event ring dequeue pointer */
 315         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 316         temp &= ERST_PTR_MASK;
 317         /* Don't clear the EHB bit (which is RW1C) because
 318          * there might be more events to service.
 319          */
 320         temp &= ~ERST_EHB;
 321         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 322         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 323                         &xhci->ir_set->erst_dequeue);
 324 }
 325
 326 /* Ring the host controller doorbell after placing a command on the ring */
 327 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 328 {
 329         u32 temp;
 330
 331         xhci_dbg(xhci, "// Ding dong!\n");
 332         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 333         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 334         /* Flush PCI posted writes */
 335         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 336 }
 337
 338 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 339                 unsigned int slot_id,
 340                 unsigned int ep_index,
 341                 unsigned int stream_id)
 342 {
 343         struct xhci_virt_ep *ep;
 344         unsigned int ep_state;
 345         u32 field;
 346         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 347
 348         ep = &xhci->devs[slot_id]->eps[ep_index];
 349         ep_state = ep->ep_state;
 350         /* Don't ring the doorbell for this endpoint if there are pending
 351          * cancellations because the we don't want to interrupt processing.
 352          * We don't want to restart any stream rings if there's a set dequeue
 353          * pointer command pending because the device can choose to start any
 354          * stream once the endpoint is on the HW schedule.
 355          * FIXME - check all the stream rings for pending cancellations.
 356          */
 357         if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
 358                         && !(ep_state & EP_HALTED)) {
 359                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 360                 field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id);
 361                 xhci_writel(xhci, field, db_addr);
 362                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 363                  * isn't time-critical and we shouldn't make the CPU wait for
 364                  * the flush.
 365                  */
 366                 xhci_readl(xhci, db_addr);
 367         }
 368 }
 369
 370 /* Ring the doorbell for any rings with pending URBs */
 371 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 372                 unsigned int slot_id,
 373                 unsigned int ep_index)
 374 {
 375         unsigned int stream_id;
 376         struct xhci_virt_ep *ep;
 377
 378         ep = &xhci->devs[slot_id]->eps[ep_index];
 379
 380         /* A ring has pending URBs if its TD list is not empty */
 381         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 382                 if (!(list_empty(&ep->ring->td_list)))
 383                         ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 384                 return;
 385         }
 386
 387         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 388                         stream_id++) {
 389                 struct xhci_stream_info *stream_info = ep->stream_info;
 390                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 391                         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
 392         }
 393 }
 394
 395 /*
 396  * Find the segment that trb is in.  Start searching in start_seg.
 397  * If we must move past a segment that has a link TRB with a toggle cycle state
 398  * bit set, then we will toggle the value pointed at by cycle_state.
 399  */
 400 static struct xhci_segment *find_trb_seg(
 401                 struct xhci_segment *start_seg,
 402                 union xhci_trb  *trb, int *cycle_state)
 403 {
 404         struct xhci_segment *cur_seg = start_seg;
 405         struct xhci_generic_trb *generic_trb;
 406
 407         while (cur_seg->trbs > trb ||
 408                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 409                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 410                 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
 411                                 TRB_TYPE(TRB_LINK) &&
 412                                 (generic_trb->field[3] & LINK_TOGGLE))
 413                         *cycle_state = ~(*cycle_state) & 0x1;
 414                 cur_seg = cur_seg->next;
 415                 if (cur_seg == start_seg)
 416                         /* Looped over the entire list.  Oops! */
 417                         return NULL;
 418         }
 419         return cur_seg;
 420 }
 421
 422
 423 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 424                 unsigned int slot_id, unsigned int ep_index,
 425                 unsigned int stream_id)
 426 {
 427         struct xhci_virt_ep *ep;
 428
 429         ep = &xhci->devs[slot_id]->eps[ep_index];
 430         /* Common case: no streams */
 431         if (!(ep->ep_state & EP_HAS_STREAMS))
 432                 return ep->ring;
 433
 434         if (stream_id == 0) {
 435                 xhci_warn(xhci,
 436                                 "WARN: Slot ID %u, ep index %u has streams, "
 437                                 "but URB has no stream ID.\n",
 438                                 slot_id, ep_index);
 439                 return NULL;
 440         }
 441
 442         if (stream_id < ep->stream_info->num_streams)
 443                 return ep->stream_info->stream_rings[stream_id];
 444
 445         xhci_warn(xhci,
 446                         "WARN: Slot ID %u, ep index %u has "
 447                         "stream IDs 1 to %u allocated, "
 448                         "but stream ID %u is requested.\n",
 449                         slot_id, ep_index,
 450                         ep->stream_info->num_streams - 1,
 451                         stream_id);
 452         return NULL;
 453 }
 454
 455 /* Get the right ring for the given URB.
 456  * If the endpoint supports streams, boundary check the URB's stream ID.
 457  * If the endpoint doesn't support streams, return the singular endpoint ring.
 458  */
 459 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 460                 struct urb *urb)
 461 {
 462         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 463                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 464 }
 465
 466 /*
 467  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 468  * Record the new state of the xHC's endpoint ring dequeue segment,
 469  * dequeue pointer, and new consumer cycle state in state.
 470  * Update our internal representation of the ring's dequeue pointer.
 471  *
 472  * We do this in three jumps:
 473  *  - First we update our new ring state to be the same as when the xHC stopped.
 474  *  - Then we traverse the ring to find the segment that contains
 475  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 476  *    any link TRBs with the toggle cycle bit set.
 477  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 478  *    if we've moved it past a link TRB with the toggle cycle bit set.
 479  */
 480 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 481                 unsigned int slot_id, unsigned int ep_index,
 482                 unsigned int stream_id, struct xhci_td *cur_td,
 483                 struct xhci_dequeue_state *state)
 484 {
 485         struct xhci_virt_device *dev = xhci->devs[slot_id];
 486         struct xhci_ring *ep_ring;
 487         struct xhci_generic_trb *trb;
 488         struct xhci_ep_ctx *ep_ctx;
 489         dma_addr_t addr;
 490
 491         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 492                         ep_index, stream_id);
 493         if (!ep_ring) {
 494                 xhci_warn(xhci, "WARN can't find new dequeue state "
 495                                 "for invalid stream ID %u.\n",
 496                                 stream_id);
 497                 return;
 498         }
 499         state->new_cycle_state = 0;
 500         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 501         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 502                         dev->eps[ep_index].stopped_trb,
 503                         &state->new_cycle_state);
 504         if (!state->new_deq_seg)
 505                 BUG();
 506         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 507         xhci_dbg(xhci, "Finding endpoint context\n");
 508         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 509         state->new_cycle_state = 0x1 & ep_ctx->deq;
 510
 511         state->new_deq_ptr = cur_td->last_trb;
 512         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 513         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 514                         state->new_deq_ptr,
 515                         &state->new_cycle_state);
 516         if (!state->new_deq_seg)
 517                 BUG();
 518
 519         trb = &state->new_deq_ptr->generic;
 520         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 521                                 (trb->field[3] & LINK_TOGGLE))
 522                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 523         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 524
 525         /* Don't update the ring cycle state for the producer (us). */
 526         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 527                         state->new_deq_seg);
 528         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 529         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 530                         (unsigned long long) addr);
 531         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 532         ep_ring->dequeue = state->new_deq_ptr;
 533         ep_ring->deq_seg = state->new_deq_seg;
 534 }
 535
 536 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 537                 struct xhci_td *cur_td)
 538 {
 539         struct xhci_segment *cur_seg;
 540         union xhci_trb *cur_trb;
 541
 542         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 543                         true;
 544                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 545                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 546                                 TRB_TYPE(TRB_LINK)) {
 547                         /* Unchain any chained Link TRBs, but
 548                          * leave the pointers intact.
 549                          */
 550                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 551                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 552                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 553                                         "in seg %p (0x%llx dma)\n",
 554                                         cur_trb,
 555                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 556                                         cur_seg,
 557                                         (unsigned long long)cur_seg->dma);
 558                 } else {
 559                         cur_trb->generic.field[0] = 0;
 560                         cur_trb->generic.field[1] = 0;
 561                         cur_trb->generic.field[2] = 0;
 562                         /* Preserve only the cycle bit of this TRB */
 563                         cur_trb->generic.field[3] &= TRB_CYCLE;
 564                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 565                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 566                                         "in seg %p (0x%llx dma)\n",
 567                                         cur_trb,
 568                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 569                                         cur_seg,
 570                                         (unsigned long long)cur_seg->dma);
 571                 }
 572                 if (cur_trb == cur_td->last_trb)
 573                         break;
 574         }
 575 }
 576
 577 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 578                 unsigned int ep_index, unsigned int stream_id,
 579                 struct xhci_segment *deq_seg,
 580                 union xhci_trb *deq_ptr, u32 cycle_state);
 581
 582 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 583                 unsigned int slot_id, unsigned int ep_index,
 584                 unsigned int stream_id,
 585                 struct xhci_dequeue_state *deq_state)
 586 {
 587         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 588
 589         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 590                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 591                         deq_state->new_deq_seg,
 592                         (unsigned long long)deq_state->new_deq_seg->dma,
 593                         deq_state->new_deq_ptr,
 594                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 595                         deq_state->new_cycle_state);
 596         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 597                         deq_state->new_deq_seg,
 598                         deq_state->new_deq_ptr,
 599                         (u32) deq_state->new_cycle_state);
 600         /* Stop the TD queueing code from ringing the doorbell until
 601          * this command completes.  The HC won't set the dequeue pointer
 602          * if the ring is running, and ringing the doorbell starts the
 603          * ring running.
 604          */
 605         ep->ep_state |= SET_DEQ_PENDING;
 606 }
 607
 608 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 609                 struct xhci_virt_ep *ep)
 610 {
 611         ep->ep_state &= ~EP_HALT_PENDING;
 612         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 613          * timer is running on another CPU, we don't decrement stop_cmds_pending
 614          * (since we didn't successfully stop the watchdog timer).
 615          */
 616         if (del_timer(&ep->stop_cmd_timer))
 617                 ep->stop_cmds_pending--;
 618 }
 619
 620 /* Must be called with xhci->lock held in interrupt context */
 621 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 622                 struct xhci_td *cur_td, int status, char *adjective)
 623 {
 624         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 625         struct urb      *urb;
 626         struct urb_priv *urb_priv;
 627
 628         urb = cur_td->urb;
 629         urb_priv = urb->hcpriv;
 630         urb_priv->td_cnt++;
 631
 632         /* Only giveback urb when this is the last td in urb */
 633         if (urb_priv->td_cnt == urb_priv->length) {
 634                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 635                 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
 636
 637                 spin_unlock(&xhci->lock);
 638                 usb_hcd_giveback_urb(hcd, urb, status);
 639                 xhci_urb_free_priv(xhci, urb_priv);
 640                 spin_lock(&xhci->lock);
 641                 xhci_dbg(xhci, "%s URB given back\n", adjective);
 642         }
 643 }
 644
 645 /*
 646  * When we get a command completion for a Stop Endpoint Command, we need to
 647  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 648  *
 649  *  1. If the HW was in the middle of processing the TD that needs to be
 650  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 651  *     in the TD with a Set Dequeue Pointer Command.
 652  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 653  *     bit cleared) so that the HW will skip over them.
 654  */
 655 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 656                 union xhci_trb *trb)
 657 {
 658         unsigned int slot_id;
 659         unsigned int ep_index;
 660         struct xhci_ring *ep_ring;
 661         struct xhci_virt_ep *ep;
 662         struct list_head *entry;
 663         struct xhci_td *cur_td = NULL;
 664         struct xhci_td *last_unlinked_td;
 665
 666         struct xhci_dequeue_state deq_state;
 667
 668         memset(&deq_state, 0, sizeof(deq_state));
 669         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 670         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 671         ep = &xhci->devs[slot_id]->eps[ep_index];
 672
 673         if (list_empty(&ep->cancelled_td_list)) {
 674                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 675                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 676                 return;
 677         }
 678
 679         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 680          * We have the xHCI lock, so nothing can modify this list until we drop
 681          * it.  We're also in the event handler, so we can't get re-interrupted
 682          * if another Stop Endpoint command completes
 683          */
 684         list_for_each(entry, &ep->cancelled_td_list) {
 685                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 686                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 687                                 cur_td->first_trb,
 688                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 689                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 690                 if (!ep_ring) {
 691                         /* This shouldn't happen unless a driver is mucking
 692                          * with the stream ID after submission.  This will
 693                          * leave the TD on the hardware ring, and the hardware
 694                          * will try to execute it, and may access a buffer
 695                          * that has already been freed.  In the best case, the
 696                          * hardware will execute it, and the event handler will
 697                          * ignore the completion event for that TD, since it was
 698                          * removed from the td_list for that endpoint.  In
 699                          * short, don't muck with the stream ID after
 700                          * submission.
 701                          */
 702                         xhci_warn(xhci, "WARN Cancelled URB %p "
 703                                         "has invalid stream ID %u.\n",
 704                                         cur_td->urb,
 705                                         cur_td->urb->stream_id);
 706                         goto remove_finished_td;
 707                 }
 708                 /*
 709                  * If we stopped on the TD we need to cancel, then we have to
 710                  * move the xHC endpoint ring dequeue pointer past this TD.
 711                  */
 712                 if (cur_td == ep->stopped_td)
 713                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 714                                         cur_td->urb->stream_id,
 715                                         cur_td, &deq_state);
 716                 else
 717                         td_to_noop(xhci, ep_ring, cur_td);
 718 remove_finished_td:
 719                 /*
 720                  * The event handler won't see a completion for this TD anymore,
 721                  * so remove it from the endpoint ring's TD list.  Keep it in
 722                  * the cancelled TD list for URB completion later.
 723                  */
 724                 list_del(&cur_td->td_list);
 725         }
 726         last_unlinked_td = cur_td;
 727         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 728
 729         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 730         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 731                 xhci_queue_new_dequeue_state(xhci,
 732                                 slot_id, ep_index,
 733                                 ep->stopped_td->urb->stream_id,
 734                                 &deq_state);
 735                 xhci_ring_cmd_db(xhci);
 736         } else {
 737                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 738                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 739         }
 740         ep->stopped_td = NULL;
 741         ep->stopped_trb = NULL;
 742
 743         /*
 744          * Drop the lock and complete the URBs in the cancelled TD list.
 745          * New TDs to be cancelled might be added to the end of the list before
 746          * we can complete all the URBs for the TDs we already unlinked.
 747          * So stop when we've completed the URB for the last TD we unlinked.
 748          */
 749         do {
 750                 cur_td = list_entry(ep->cancelled_td_list.next,
 751                                 struct xhci_td, cancelled_td_list);
 752                 list_del(&cur_td->cancelled_td_list);
 753
 754                 /* Clean up the cancelled URB */
 755                 /* Doesn't matter what we pass for status, since the core will
 756                  * just overwrite it (because the URB has been unlinked).
 757                  */
 758                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 759
 760                 /* Stop processing the cancelled list if the watchdog timer is
 761                  * running.
 762                  */
 763                 if (xhci->xhc_state & XHCI_STATE_DYING)
 764                         return;
 765         } while (cur_td != last_unlinked_td);
 766
 767         /* Return to the event handler with xhci->lock re-acquired */
 768 }
 769
 770 /* Watchdog timer function for when a stop endpoint command fails to complete.
 771  * In this case, we assume the host controller is broken or dying or dead.  The
 772  * host may still be completing some other events, so we have to be careful to
 773  * let the event ring handler and the URB dequeueing/enqueueing functions know
 774  * through xhci->state.
 775  *
 776  * The timer may also fire if the host takes a very long time to respond to the
 777  * command, and the stop endpoint command completion handler cannot delete the
 778  * timer before the timer function is called.  Another endpoint cancellation may
 779  * sneak in before the timer function can grab the lock, and that may queue
 780  * another stop endpoint command and add the timer back.  So we cannot use a
 781  * simple flag to say whether there is a pending stop endpoint command for a
 782  * particular endpoint.
 783  *
 784  * Instead we use a combination of that flag and a counter for the number of
 785  * pending stop endpoint commands.  If the timer is the tail end of the last
 786  * stop endpoint command, and the endpoint's command is still pending, we assume
 787  * the host is dying.
 788  */
 789 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 790 {
 791         struct xhci_hcd *xhci;
 792         struct xhci_virt_ep *ep;
 793         struct xhci_virt_ep *temp_ep;
 794         struct xhci_ring *ring;
 795         struct xhci_td *cur_td;
 796         int ret, i, j;
 797
 798         ep = (struct xhci_virt_ep *) arg;
 799         xhci = ep->xhci;
 800
 801         spin_lock(&xhci->lock);
 802
 803         ep->stop_cmds_pending--;
 804         if (xhci->xhc_state & XHCI_STATE_DYING) {
 805                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 806                                 "xHCI as DYING, exiting.\n");
 807                 spin_unlock(&xhci->lock);
 808                 return;
 809         }
 810         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 811                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 812                                 "exiting.\n");
 813                 spin_unlock(&xhci->lock);
 814                 return;
 815         }
 816
 817         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 818         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 819         /* Oops, HC is dead or dying or at least not responding to the stop
 820          * endpoint command.
 821          */
 822         xhci->xhc_state |= XHCI_STATE_DYING;
 823         /* Disable interrupts from the host controller and start halting it */
 824         xhci_quiesce(xhci);
 825         spin_unlock(&xhci->lock);
 826
 827         ret = xhci_halt(xhci);
 828
 829         spin_lock(&xhci->lock);
 830         if (ret < 0) {
 831                 /* This is bad; the host is not responding to commands and it's
 832                  * not allowing itself to be halted.  At least interrupts are
 833                  * disabled, so we can set HC_STATE_HALT and notify the
 834                  * USB core.  But if we call usb_hc_died(), it will attempt to
 835                  * disconnect all device drivers under this host.  Those
 836                  * disconnect() methods will wait for all URBs to be unlinked,
 837                  * so we must complete them.
 838                  */
 839                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 840                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 841                 /* We could turn all TDs on the rings to no-ops.  This won't
 842                  * help if the host has cached part of the ring, and is slow if
 843                  * we want to preserve the cycle bit.  Skip it and hope the host
 844                  * doesn't touch the memory.
 845                  */
 846         }
 847         for (i = 0; i < MAX_HC_SLOTS; i++) {
 848                 if (!xhci->devs[i])
 849                         continue;
 850                 for (j = 0; j < 31; j++) {
 851                         temp_ep = &xhci->devs[i]->eps[j];
 852                         ring = temp_ep->ring;
 853                         if (!ring)
 854                                 continue;
 855                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 856                                         "ep index %u\n", i, j);
 857                         while (!list_empty(&ring->td_list)) {
 858                                 cur_td = list_first_entry(&ring->td_list,
 859                                                 struct xhci_td,
 860                                                 td_list);
 861                                 list_del(&cur_td->td_list);
 862                                 if (!list_empty(&cur_td->cancelled_td_list))
 863                                         list_del(&cur_td->cancelled_td_list);
 864                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 865                                                 -ESHUTDOWN, "killed");
 866                         }
 867                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 868                                 cur_td = list_first_entry(
 869                                                 &temp_ep->cancelled_td_list,
 870                                                 struct xhci_td,
 871                                                 cancelled_td_list);
 872                                 list_del(&cur_td->cancelled_td_list);
 873                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 874                                                 -ESHUTDOWN, "killed");
 875                         }
 876                 }
 877         }
 878         spin_unlock(&xhci->lock);
 879         xhci_to_hcd(xhci)->state = HC_STATE_HALT;
 880         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 881         usb_hc_died(xhci_to_hcd(xhci));
 882         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 883 }
 884
 885 /*
 886  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 887  * we need to clear the set deq pending flag in the endpoint ring state, so that
 888  * the TD queueing code can ring the doorbell again.  We also need to ring the
 889  * endpoint doorbell to restart the ring, but only if there aren't more
 890  * cancellations pending.
 891  */
 892 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 893                 struct xhci_event_cmd *event,
 894                 union xhci_trb *trb)
 895 {
 896         unsigned int slot_id;
 897         unsigned int ep_index;
 898         unsigned int stream_id;
 899         struct xhci_ring *ep_ring;
 900         struct xhci_virt_device *dev;
 901         struct xhci_ep_ctx *ep_ctx;
 902         struct xhci_slot_ctx *slot_ctx;
 903
 904         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 905         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 906         stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
 907         dev = xhci->devs[slot_id];
 908
 909         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 910         if (!ep_ring) {
 911                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 912                                 "freed stream ID %u\n",
 913                                 stream_id);
 914                 /* XXX: Harmless??? */
 915                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 916                 return;
 917         }
 918
 919         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 920         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 921
 922         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 923                 unsigned int ep_state;
 924                 unsigned int slot_state;
 925
 926                 switch (GET_COMP_CODE(event->status)) {
 927                 case COMP_TRB_ERR:
 928                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 929                                         "of stream ID configuration\n");
 930                         break;
 931                 case COMP_CTX_STATE:
 932                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 933                                         "to incorrect slot or ep state.\n");
 934                         ep_state = ep_ctx->ep_info;
 935                         ep_state &= EP_STATE_MASK;
 936                         slot_state = slot_ctx->dev_state;
 937                         slot_state = GET_SLOT_STATE(slot_state);
 938                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 939                                         slot_state, ep_state);
 940                         break;
 941                 case COMP_EBADSLT:
 942                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 943                                         "slot %u was not enabled.\n", slot_id);
 944                         break;
 945                 default:
 946                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 947                                         "completion code of %u.\n",
 948                                         GET_COMP_CODE(event->status));
 949                         break;
 950                 }
 951                 /* OK what do we do now?  The endpoint state is hosed, and we
 952                  * should never get to this point if the synchronization between
 953                  * queueing, and endpoint state are correct.  This might happen
 954                  * if the device gets disconnected after we've finished
 955                  * cancelling URBs, which might not be an error...
 956                  */
 957         } else {
 958                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 959                                 ep_ctx->deq);
 960         }
 961
 962         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 963         /* Restart any rings with pending URBs */
 964         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 965 }
 966
 967 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 968                 struct xhci_event_cmd *event,
 969                 union xhci_trb *trb)
 970 {
 971         int slot_id;
 972         unsigned int ep_index;
 973
 974         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 975         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 976         /* This command will only fail if the endpoint wasn't halted,
 977          * but we don't care.
 978          */
 979         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 980                         (unsigned int) GET_COMP_CODE(event->status));
 981
 982         /* HW with the reset endpoint quirk needs to have a configure endpoint
 983          * command complete before the endpoint can be used.  Queue that here
 984          * because the HW can't handle two commands being queued in a row.
 985          */
 986         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 987                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 988                 xhci_queue_configure_endpoint(xhci,
 989                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 990                                 false);
 991                 xhci_ring_cmd_db(xhci);
 992         } else {
 993                 /* Clear our internal halted state and restart the ring(s) */
 994                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 995                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 996         }
 997 }
 998
 999 /* Check to see if a command in the device's command queue matches this one.
1000  * Signal the completion or free the command, and return 1.  Return 0 if the
1001  * completed command isn't at the head of the command list.
1002  */
1003 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1004                 struct xhci_virt_device *virt_dev,
1005                 struct xhci_event_cmd *event)
1006 {
1007         struct xhci_command *command;
1008
1009         if (list_empty(&virt_dev->cmd_list))
1010                 return 0;
1011
1012         command = list_entry(virt_dev->cmd_list.next,
1013                         struct xhci_command, cmd_list);
1014         if (xhci->cmd_ring->dequeue != command->command_trb)
1015                 return 0;
1016
1017         command->status =
1018                 GET_COMP_CODE(event->status);
1019         list_del(&command->cmd_list);
1020         if (command->completion)
1021                 complete(command->completion);
1022         else
1023                 xhci_free_command(xhci, command);
1024         return 1;
1025 }
1026
1027 static void handle_cmd_completion(struct xhci_hcd *xhci,
1028                 struct xhci_event_cmd *event)
1029 {
1030         int slot_id = TRB_TO_SLOT_ID(event->flags);
1031         u64 cmd_dma;
1032         dma_addr_t cmd_dequeue_dma;
1033         struct xhci_input_control_ctx *ctrl_ctx;
1034         struct xhci_virt_device *virt_dev;
1035         unsigned int ep_index;
1036         struct xhci_ring *ep_ring;
1037         unsigned int ep_state;
1038
1039         cmd_dma = event->cmd_trb;
1040         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1041                         xhci->cmd_ring->dequeue);
1042         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1043         if (cmd_dequeue_dma == 0) {
1044                 xhci->error_bitmask |= 1 << 4;
1045                 return;
1046         }
1047         /* Does the DMA address match our internal dequeue pointer address? */
1048         if (cmd_dma != (u64) cmd_dequeue_dma) {
1049                 xhci->error_bitmask |= 1 << 5;
1050                 return;
1051         }
1052         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1053         case TRB_TYPE(TRB_ENABLE_SLOT):
1054                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1055                         xhci->slot_id = slot_id;
1056                 else
1057                         xhci->slot_id = 0;
1058                 complete(&xhci->addr_dev);
1059                 break;
1060         case TRB_TYPE(TRB_DISABLE_SLOT):
1061                 if (xhci->devs[slot_id])
1062                         xhci_free_virt_device(xhci, slot_id);
1063                 break;
1064         case TRB_TYPE(TRB_CONFIG_EP):
1065                 virt_dev = xhci->devs[slot_id];
1066                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1067                         break;
1068                 /*
1069                  * Configure endpoint commands can come from the USB core
1070                  * configuration or alt setting changes, or because the HW
1071                  * needed an extra configure endpoint command after a reset
1072                  * endpoint command or streams were being configured.
1073                  * If the command was for a halted endpoint, the xHCI driver
1074                  * is not waiting on the configure endpoint command.
1075                  */
1076                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1077                                 virt_dev->in_ctx);
1078                 /* Input ctx add_flags are the endpoint index plus one */
1079                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1080                 /* A usb_set_interface() call directly after clearing a halted
1081                  * condition may race on this quirky hardware.  Not worth
1082                  * worrying about, since this is prototype hardware.  Not sure
1083                  * if this will work for streams, but streams support was
1084                  * untested on this prototype.
1085                  */
1086                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1087                                 ep_index != (unsigned int) -1 &&
1088                                 ctrl_ctx->add_flags - SLOT_FLAG ==
1089                                         ctrl_ctx->drop_flags) {
1090                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1091                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1092                         if (!(ep_state & EP_HALTED))
1093                                 goto bandwidth_change;
1094                         xhci_dbg(xhci, "Completed config ep cmd - "
1095                                         "last ep index = %d, state = %d\n",
1096                                         ep_index, ep_state);
1097                         /* Clear internal halted state and restart ring(s) */
1098                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1099                                 ~EP_HALTED;
1100                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1101                         break;
1102                 }
1103 bandwidth_change:
1104                 xhci_dbg(xhci, "Completed config ep cmd\n");
1105                 xhci->devs[slot_id]->cmd_status =
1106                         GET_COMP_CODE(event->status);
1107                 complete(&xhci->devs[slot_id]->cmd_completion);
1108                 break;
1109         case TRB_TYPE(TRB_EVAL_CONTEXT):
1110                 virt_dev = xhci->devs[slot_id];
1111                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1112                         break;
1113                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1114                 complete(&xhci->devs[slot_id]->cmd_completion);
1115                 break;
1116         case TRB_TYPE(TRB_ADDR_DEV):
1117                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1118                 complete(&xhci->addr_dev);
1119                 break;
1120         case TRB_TYPE(TRB_STOP_RING):
1121                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
1122                 break;
1123         case TRB_TYPE(TRB_SET_DEQ):
1124                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1125                 break;
1126         case TRB_TYPE(TRB_CMD_NOOP):
1127                 ++xhci->noops_handled;
1128                 break;
1129         case TRB_TYPE(TRB_RESET_EP):
1130                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1131                 break;
1132         case TRB_TYPE(TRB_RESET_DEV):
1133                 xhci_dbg(xhci, "Completed reset device command.\n");
1134                 slot_id = TRB_TO_SLOT_ID(
1135                                 xhci->cmd_ring->dequeue->generic.field[3]);
1136                 virt_dev = xhci->devs[slot_id];
1137                 if (virt_dev)
1138                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1139                 else
1140                         xhci_warn(xhci, "Reset device command completion "
1141                                         "for disabled slot %u\n", slot_id);
1142                 break;
1143         case TRB_TYPE(TRB_NEC_GET_FW):
1144                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1145                         xhci->error_bitmask |= 1 << 6;
1146                         break;
1147                 }
1148                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1149                                 NEC_FW_MAJOR(event->status),
1150                                 NEC_FW_MINOR(event->status));
1151                 break;
1152         default:
1153                 /* Skip over unknown commands on the event ring */
1154                 xhci->error_bitmask |= 1 << 6;
1155                 break;
1156         }
1157         inc_deq(xhci, xhci->cmd_ring, false);
1158 }
1159
1160 static void handle_vendor_event(struct xhci_hcd *xhci,
1161                 union xhci_trb *event)
1162 {
1163         u32 trb_type;
1164
1165         trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1166         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1167         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1168                 handle_cmd_completion(xhci, &event->event_cmd);
1169 }
1170
1171 static void handle_port_status(struct xhci_hcd *xhci,
1172                 union xhci_trb *event)
1173 {
1174         u32 port_id;
1175
1176         /* Port status change events always have a successful completion code */
1177         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1178                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1179                 xhci->error_bitmask |= 1 << 8;
1180         }
1181         /* FIXME: core doesn't care about all port link state changes yet */
1182         port_id = GET_PORT_ID(event->generic.field[0]);
1183         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1184
1185         /* Update event ring dequeue pointer before dropping the lock */
1186         inc_deq(xhci, xhci->event_ring, true);
1187
1188         spin_unlock(&xhci->lock);
1189         /* Pass this up to the core */
1190         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1191         spin_lock(&xhci->lock);
1192 }
1193
1194 /*
1195  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1196  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1197  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1198  * returns 0.
1199  */
1200 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1201                 union xhci_trb  *start_trb,
1202                 union xhci_trb  *end_trb,
1203                 dma_addr_t      suspect_dma)
1204 {
1205         dma_addr_t start_dma;
1206         dma_addr_t end_seg_dma;
1207         dma_addr_t end_trb_dma;
1208         struct xhci_segment *cur_seg;
1209
1210         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1211         cur_seg = start_seg;
1212
1213         do {
1214                 if (start_dma == 0)
1215                         return NULL;
1216                 /* We may get an event for a Link TRB in the middle of a TD */
1217                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1218                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1219                 /* If the end TRB isn't in this segment, this is set to 0 */
1220                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1221
1222                 if (end_trb_dma > 0) {
1223                         /* The end TRB is in this segment, so suspect should be here */
1224                         if (start_dma <= end_trb_dma) {
1225                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1226                                         return cur_seg;
1227                         } else {
1228                                 /* Case for one segment with
1229                                  * a TD wrapped around to the top
1230                                  */
1231                                 if ((suspect_dma >= start_dma &&
1232                                                         suspect_dma <= end_seg_dma) ||
1233                                                 (suspect_dma >= cur_seg->dma &&
1234                                                  suspect_dma <= end_trb_dma))
1235                                         return cur_seg;
1236                         }
1237                         return NULL;
1238                 } else {
1239                         /* Might still be somewhere in this segment */
1240                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1241                                 return cur_seg;
1242                 }
1243                 cur_seg = cur_seg->next;
1244                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1245         } while (cur_seg != start_seg);
1246
1247         return NULL;
1248 }
1249
1250 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1251                 unsigned int slot_id, unsigned int ep_index,
1252                 unsigned int stream_id,
1253                 struct xhci_td *td, union xhci_trb *event_trb)
1254 {
1255         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1256         ep->ep_state |= EP_HALTED;
1257         ep->stopped_td = td;
1258         ep->stopped_trb = event_trb;
1259         ep->stopped_stream = stream_id;
1260
1261         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1262         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1263
1264         ep->stopped_td = NULL;
1265         ep->stopped_trb = NULL;
1266         ep->stopped_stream = 0;
1267
1268         xhci_ring_cmd_db(xhci);
1269 }
1270
1271 /* Check if an error has halted the endpoint ring.  The class driver will
1272  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1273  * However, a babble and other errors also halt the endpoint ring, and the class
1274  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1275  * Ring Dequeue Pointer command manually.
1276  */
1277 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1278                 struct xhci_ep_ctx *ep_ctx,
1279                 unsigned int trb_comp_code)
1280 {
1281         /* TRB completion codes that may require a manual halt cleanup */
1282         if (trb_comp_code == COMP_TX_ERR ||
1283                         trb_comp_code == COMP_BABBLE ||
1284                         trb_comp_code == COMP_SPLIT_ERR)
1285                 /* The 0.96 spec says a babbling control endpoint
1286                  * is not halted. The 0.96 spec says it is.  Some HW
1287                  * claims to be 0.95 compliant, but it halts the control
1288                  * endpoint anyway.  Check if a babble halted the
1289                  * endpoint.
1290                  */
1291                 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1292                         return 1;
1293
1294         return 0;
1295 }
1296
1297 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1298 {
1299         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1300                 /* Vendor defined "informational" completion code,
1301                  * treat as not-an-error.
1302                  */
1303                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1304                                 trb_comp_code);
1305                 xhci_dbg(xhci, "Treating code as success.\n");
1306                 return 1;
1307         }
1308         return 0;
1309 }
1310
1311 /*
1312  * Finish the td processing, remove the td from td list;
1313  * Return 1 if the urb can be given back.
1314  */
1315 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1316         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1317         struct xhci_virt_ep *ep, int *status, bool skip)
1318 {
1319         struct xhci_virt_device *xdev;
1320         struct xhci_ring *ep_ring;
1321         unsigned int slot_id;
1322         int ep_index;
1323         struct urb *urb = NULL;
1324         struct xhci_ep_ctx *ep_ctx;
1325         int ret = 0;
1326         struct urb_priv *urb_priv;
1327         u32 trb_comp_code;
1328
1329         slot_id = TRB_TO_SLOT_ID(event->flags);
1330         xdev = xhci->devs[slot_id];
1331         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1332         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1333         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1334         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1335
1336         if (skip)
1337                 goto td_cleanup;
1338
1339         if (trb_comp_code == COMP_STOP_INVAL ||
1340                         trb_comp_code == COMP_STOP) {
1341                 /* The Endpoint Stop Command completion will take care of any
1342                  * stopped TDs.  A stopped TD may be restarted, so don't update
1343                  * the ring dequeue pointer or take this TD off any lists yet.
1344                  */
1345                 ep->stopped_td = td;
1346                 ep->stopped_trb = event_trb;
1347                 return 0;
1348         } else {
1349                 if (trb_comp_code == COMP_STALL) {
1350                         /* The transfer is completed from the driver's
1351                          * perspective, but we need to issue a set dequeue
1352                          * command for this stalled endpoint to move the dequeue
1353                          * pointer past the TD.  We can't do that here because
1354                          * the halt condition must be cleared first.  Let the
1355                          * USB class driver clear the stall later.
1356                          */
1357                         ep->stopped_td = td;
1358                         ep->stopped_trb = event_trb;
1359                         ep->stopped_stream = ep_ring->stream_id;
1360                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1361                                         ep_ctx, trb_comp_code)) {
1362                         /* Other types of errors halt the endpoint, but the
1363                          * class driver doesn't call usb_reset_endpoint() unless
1364                          * the error is -EPIPE.  Clear the halted status in the
1365                          * xHCI hardware manually.
1366                          */
1367                         xhci_cleanup_halted_endpoint(xhci,
1368                                         slot_id, ep_index, ep_ring->stream_id,
1369                                         td, event_trb);
1370                 } else {
1371                         /* Update ring dequeue pointer */
1372                         while (ep_ring->dequeue != td->last_trb)
1373                                 inc_deq(xhci, ep_ring, false);
1374                         inc_deq(xhci, ep_ring, false);
1375                 }
1376
1377 td_cleanup:
1378                 /* Clean up the endpoint's TD list */
1379                 urb = td->urb;
1380                 urb_priv = urb->hcpriv;
1381
1382                 /* Do one last check of the actual transfer length.
1383                  * If the host controller said we transferred more data than
1384                  * the buffer length, urb->actual_length will be a very big
1385                  * number (since it's unsigned).  Play it safe and say we didn't
1386                  * transfer anything.
1387                  */
1388                 if (urb->actual_length > urb->transfer_buffer_length) {
1389                         xhci_warn(xhci, "URB transfer length is wrong, "
1390                                         "xHC issue? req. len = %u, "
1391                                         "act. len = %u\n",
1392                                         urb->transfer_buffer_length,
1393                                         urb->actual_length);
1394                         urb->actual_length = 0;
1395                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1396                                 *status = -EREMOTEIO;
1397                         else
1398                                 *status = 0;
1399                 }
1400                 list_del(&td->td_list);
1401                 /* Was this TD slated to be cancelled but completed anyway? */
1402                 if (!list_empty(&td->cancelled_td_list))
1403                         list_del(&td->cancelled_td_list);
1404
1405                 urb_priv->td_cnt++;
1406                 /* Giveback the urb when all the tds are completed */
1407                 if (urb_priv->td_cnt == urb_priv->length)
1408                         ret = 1;
1409         }
1410
1411         return ret;
1412 }
1413
1414 /*
1415  * Process control tds, update urb status and actual_length.
1416  */
1417 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1418         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1419         struct xhci_virt_ep *ep, int *status)
1420 {
1421         struct xhci_virt_device *xdev;
1422         struct xhci_ring *ep_ring;
1423         unsigned int slot_id;
1424         int ep_index;
1425         struct xhci_ep_ctx *ep_ctx;
1426         u32 trb_comp_code;
1427
1428         slot_id = TRB_TO_SLOT_ID(event->flags);
1429         xdev = xhci->devs[slot_id];
1430         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1431         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1432         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1433         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1434
1435         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1436         switch (trb_comp_code) {
1437         case COMP_SUCCESS:
1438                 if (event_trb == ep_ring->dequeue) {
1439                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1440                                         "without IOC set??\n");
1441                         *status = -ESHUTDOWN;
1442                 } else if (event_trb != td->last_trb) {
1443                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1444                                         "without IOC set??\n");
1445                         *status = -ESHUTDOWN;
1446                 } else {
1447                         xhci_dbg(xhci, "Successful control transfer!\n");
1448                         *status = 0;
1449                 }
1450                 break;
1451         case COMP_SHORT_TX:
1452                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1453                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1454                         *status = -EREMOTEIO;
1455                 else
1456                         *status = 0;
1457                 break;
1458         default:
1459                 if (!xhci_requires_manual_halt_cleanup(xhci,
1460                                         ep_ctx, trb_comp_code))
1461                         break;
1462                 xhci_dbg(xhci, "TRB error code %u, "
1463                                 "halted endpoint index = %u\n",
1464                                 trb_comp_code, ep_index);
1465                 /* else fall through */
1466         case COMP_STALL:
1467                 /* Did we transfer part of the data (middle) phase? */
1468                 if (event_trb != ep_ring->dequeue &&
1469                                 event_trb != td->last_trb)
1470                         td->urb->actual_length =
1471                                 td->urb->transfer_buffer_length
1472                                 - TRB_LEN(event->transfer_len);
1473                 else
1474                         td->urb->actual_length = 0;
1475
1476                 xhci_cleanup_halted_endpoint(xhci,
1477                         slot_id, ep_index, 0, td, event_trb);
1478                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1479         }
1480         /*
1481          * Did we transfer any data, despite the errors that might have
1482          * happened?  I.e. did we get past the setup stage?
1483          */
1484         if (event_trb != ep_ring->dequeue) {
1485                 /* The event was for the status stage */
1486                 if (event_trb == td->last_trb) {
1487                         if (td->urb->actual_length != 0) {
1488                                 /* Don't overwrite a previously set error code
1489                                  */
1490                                 if ((*status == -EINPROGRESS || *status == 0) &&
1491                                                 (td->urb->transfer_flags
1492                                                  & URB_SHORT_NOT_OK))
1493                                         /* Did we already see a short data
1494                                          * stage? */
1495                                         *status = -EREMOTEIO;
1496                         } else {
1497                                 td->urb->actual_length =
1498                                         td->urb->transfer_buffer_length;
1499                         }
1500                 } else {
1501                 /* Maybe the event was for the data stage? */
1502                         if (trb_comp_code != COMP_STOP_INVAL) {
1503                                 /* We didn't stop on a link TRB in the middle */
1504                                 td->urb->actual_length =
1505                                         td->urb->transfer_buffer_length -
1506                                         TRB_LEN(event->transfer_len);
1507                                 xhci_dbg(xhci, "Waiting for status "
1508                                                 "stage event\n");
1509                                 return 0;
1510                         }
1511                 }
1512         }
1513
1514         return finish_td(xhci, td, event_trb, event, ep, status, false);
1515 }
1516
1517 /*
1518  * Process isochronous tds, update urb packet status and actual_length.
1519  */
1520 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1521         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1522         struct xhci_virt_ep *ep, int *status)
1523 {
1524         struct xhci_ring *ep_ring;
1525         struct urb_priv *urb_priv;
1526         int idx;
1527         int len = 0;
1528         int skip_td = 0;
1529         union xhci_trb *cur_trb;
1530         struct xhci_segment *cur_seg;
1531         u32 trb_comp_code;
1532
1533         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1534         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1535         urb_priv = td->urb->hcpriv;
1536         idx = urb_priv->td_cnt;
1537
1538         if (ep->skip) {
1539                 /* The transfer is partly done */
1540                 *status = -EXDEV;
1541                 td->urb->iso_frame_desc[idx].status = -EXDEV;
1542         } else {
1543                 /* handle completion code */
1544                 switch (trb_comp_code) {
1545                 case COMP_SUCCESS:
1546                         td->urb->iso_frame_desc[idx].status = 0;
1547                         xhci_dbg(xhci, "Successful isoc transfer!\n");
1548                         break;
1549                 case COMP_SHORT_TX:
1550                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1551                                 td->urb->iso_frame_desc[idx].status =
1552                                          -EREMOTEIO;
1553                         else
1554                                 td->urb->iso_frame_desc[idx].status = 0;
1555                         break;
1556                 case COMP_BW_OVER:
1557                         td->urb->iso_frame_desc[idx].status = -ECOMM;
1558                         skip_td = 1;
1559                         break;
1560                 case COMP_BUFF_OVER:
1561                 case COMP_BABBLE:
1562                         td->urb->iso_frame_desc[idx].status = -EOVERFLOW;
1563                         skip_td = 1;
1564                         break;
1565                 case COMP_STALL:
1566                         td->urb->iso_frame_desc[idx].status = -EPROTO;
1567                         skip_td = 1;
1568                         break;
1569                 case COMP_STOP:
1570                 case COMP_STOP_INVAL:
1571                         break;
1572                 default:
1573                         td->urb->iso_frame_desc[idx].status = -1;
1574                         break;
1575                 }
1576         }
1577
1578         /* calc actual length */
1579         if (ep->skip) {
1580                 td->urb->iso_frame_desc[idx].actual_length = 0;
1581                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1582         }
1583
1584         if (trb_comp_code == COMP_SUCCESS || skip_td == 1) {
1585                 td->urb->iso_frame_desc[idx].actual_length =
1586                         td->urb->iso_frame_desc[idx].length;
1587                 td->urb->actual_length +=
1588                         td->urb->iso_frame_desc[idx].length;
1589         } else {
1590                 for (cur_trb = ep_ring->dequeue,
1591                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1592                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1593                         if ((cur_trb->generic.field[3] &
1594                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1595                             (cur_trb->generic.field[3] &
1596                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1597                                 len +=
1598                                     TRB_LEN(cur_trb->generic.field[2]);
1599                 }
1600                 len += TRB_LEN(cur_trb->generic.field[2]) -
1601                         TRB_LEN(event->transfer_len);
1602
1603                 if (trb_comp_code != COMP_STOP_INVAL) {
1604                         td->urb->iso_frame_desc[idx].actual_length = len;
1605                         td->urb->actual_length += len;
1606                 }
1607         }
1608
1609         if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1610                 *status = 0;
1611
1612         return finish_td(xhci, td, event_trb, event, ep, status, false);
1613 }
1614
1615 /*
1616  * Process bulk and interrupt tds, update urb status and actual_length.
1617  */
1618 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1619         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1620         struct xhci_virt_ep *ep, int *status)
1621 {
1622         struct xhci_ring *ep_ring;
1623         union xhci_trb *cur_trb;
1624         struct xhci_segment *cur_seg;
1625         u32 trb_comp_code;
1626
1627         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1628         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1629
1630         switch (trb_comp_code) {
1631         case COMP_SUCCESS:
1632                 /* Double check that the HW transferred everything. */
1633                 if (event_trb != td->last_trb) {
1634                         xhci_warn(xhci, "WARN Successful completion "
1635                                         "on short TX\n");
1636                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1637                                 *status = -EREMOTEIO;
1638                         else
1639                                 *status = 0;
1640                 } else {
1641                         if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1642                                 xhci_dbg(xhci, "Successful bulk "
1643                                                 "transfer!\n");
1644                         else
1645                                 xhci_dbg(xhci, "Successful interrupt "
1646                                                 "transfer!\n");
1647                         *status = 0;
1648                 }
1649                 break;
1650         case COMP_SHORT_TX:
1651                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1652                         *status = -EREMOTEIO;
1653                 else
1654                         *status = 0;
1655                 break;
1656         default:
1657                 /* Others already handled above */
1658                 break;
1659         }
1660         dev_dbg(&td->urb->dev->dev,
1661                         "ep %#x - asked for %d bytes, "
1662                         "%d bytes untransferred\n",
1663                         td->urb->ep->desc.bEndpointAddress,
1664                         td->urb->transfer_buffer_length,
1665                         TRB_LEN(event->transfer_len));
1666         /* Fast path - was this the last TRB in the TD for this URB? */
1667         if (event_trb == td->last_trb) {
1668                 if (TRB_LEN(event->transfer_len) != 0) {
1669                         td->urb->actual_length =
1670                                 td->urb->transfer_buffer_length -
1671                                 TRB_LEN(event->transfer_len);
1672                         if (td->urb->transfer_buffer_length <
1673                                         td->urb->actual_length) {
1674                                 xhci_warn(xhci, "HC gave bad length "
1675                                                 "of %d bytes left\n",
1676                                                 TRB_LEN(event->transfer_len));
1677                                 td->urb->actual_length = 0;
1678                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1679                                         *status = -EREMOTEIO;
1680                                 else
1681                                         *status = 0;
1682                         }
1683                         /* Don't overwrite a previously set error code */
1684                         if (*status == -EINPROGRESS) {
1685                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1686                                         *status = -EREMOTEIO;
1687                                 else
1688                                         *status = 0;
1689                         }
1690                 } else {
1691                         td->urb->actual_length =
1692                                 td->urb->transfer_buffer_length;
1693                         /* Ignore a short packet completion if the
1694                          * untransferred length was zero.
1695                          */
1696                         if (*status == -EREMOTEIO)
1697                                 *status = 0;
1698                 }
1699         } else {
1700                 /* Slow path - walk the list, starting from the dequeue
1701                  * pointer, to get the actual length transferred.
1702                  */
1703                 td->urb->actual_length = 0;
1704                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1705                                 cur_trb != event_trb;
1706                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1707                         if ((cur_trb->generic.field[3] &
1708                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1709                             (cur_trb->generic.field[3] &
1710                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1711                                 td->urb->actual_length +=
1712                                         TRB_LEN(cur_trb->generic.field[2]);
1713                 }
1714                 /* If the ring didn't stop on a Link or No-op TRB, add
1715                  * in the actual bytes transferred from the Normal TRB
1716                  */
1717                 if (trb_comp_code != COMP_STOP_INVAL)
1718                         td->urb->actual_length +=
1719                                 TRB_LEN(cur_trb->generic.field[2]) -
1720                                 TRB_LEN(event->transfer_len);
1721         }
1722
1723         return finish_td(xhci, td, event_trb, event, ep, status, false);
1724 }
1725
1726 /*
1727  * If this function returns an error condition, it means it got a Transfer
1728  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1729  * At this point, the host controller is probably hosed and should be reset.
1730  */
1731 static int handle_tx_event(struct xhci_hcd *xhci,
1732                 struct xhci_transfer_event *event)
1733 {
1734         struct xhci_virt_device *xdev;
1735         struct xhci_virt_ep *ep;
1736         struct xhci_ring *ep_ring;
1737         unsigned int slot_id;
1738         int ep_index;
1739         struct xhci_td *td = NULL;
1740         dma_addr_t event_dma;
1741         struct xhci_segment *event_seg;
1742         union xhci_trb *event_trb;
1743         struct urb *urb = NULL;
1744         int status = -EINPROGRESS;
1745         struct urb_priv *urb_priv;
1746         struct xhci_ep_ctx *ep_ctx;
1747         u32 trb_comp_code;
1748         int ret = 0;
1749
1750         slot_id = TRB_TO_SLOT_ID(event->flags);
1751         xdev = xhci->devs[slot_id];
1752         if (!xdev) {
1753                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1754                 return -ENODEV;
1755         }
1756
1757         /* Endpoint ID is 1 based, our index is zero based */
1758         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1759         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1760         ep = &xdev->eps[ep_index];
1761         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1762         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1763         if (!ep_ring ||
1764                 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1765                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1766                                 "or incorrect stream ring\n");
1767                 return -ENODEV;
1768         }
1769
1770         event_dma = event->buffer;
1771         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1772         /* Look for common error cases */
1773         switch (trb_comp_code) {
1774         /* Skip codes that require special handling depending on
1775          * transfer type
1776          */
1777         case COMP_SUCCESS:
1778         case COMP_SHORT_TX:
1779                 break;
1780         case COMP_STOP:
1781                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1782                 break;
1783         case COMP_STOP_INVAL:
1784                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1785                 break;
1786         case COMP_STALL:
1787                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1788                 ep->ep_state |= EP_HALTED;
1789                 status = -EPIPE;
1790                 break;
1791         case COMP_TRB_ERR:
1792                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1793                 status = -EILSEQ;
1794                 break;
1795         case COMP_SPLIT_ERR:
1796         case COMP_TX_ERR:
1797                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1798                 status = -EPROTO;
1799                 break;
1800         case COMP_BABBLE:
1801                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1802                 status = -EOVERFLOW;
1803                 break;
1804         case COMP_DB_ERR:
1805                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1806                 status = -ENOSR;
1807                 break;
1808         case COMP_BW_OVER:
1809                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1810                 break;
1811         case COMP_BUFF_OVER:
1812                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1813                 break;
1814         case COMP_UNDERRUN:
1815                 /*
1816                  * When the Isoch ring is empty, the xHC will generate
1817                  * a Ring Overrun Event for IN Isoch endpoint or Ring
1818                  * Underrun Event for OUT Isoch endpoint.
1819                  */
1820                 xhci_dbg(xhci, "underrun event on endpoint\n");
1821                 if (!list_empty(&ep_ring->td_list))
1822                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1823                                         "still with TDs queued?\n",
1824                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1825                 goto cleanup;
1826         case COMP_OVERRUN:
1827                 xhci_dbg(xhci, "overrun event on endpoint\n");
1828                 if (!list_empty(&ep_ring->td_list))
1829                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1830                                         "still with TDs queued?\n",
1831                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1832                 goto cleanup;
1833         case COMP_MISSED_INT:
1834                 /*
1835                  * When encounter missed service error, one or more isoc tds
1836                  * may be missed by xHC.
1837                  * Set skip flag of the ep_ring; Complete the missed tds as
1838                  * short transfer when process the ep_ring next time.
1839                  */
1840                 ep->skip = true;
1841                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1842                 goto cleanup;
1843         default:
1844                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1845                         status = 0;
1846                         break;
1847                 }
1848                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1849                                 "busted\n");
1850                 goto cleanup;
1851         }
1852
1853         do {
1854                 /* This TRB should be in the TD at the head of this ring's
1855                  * TD list.
1856                  */
1857                 if (list_empty(&ep_ring->td_list)) {
1858                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1859                                         "with no TDs queued?\n",
1860                                   TRB_TO_SLOT_ID(event->flags), ep_index);
1861                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1862                           (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1863                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1864                         if (ep->skip) {
1865                                 ep->skip = false;
1866                                 xhci_dbg(xhci, "td_list is empty while skip "
1867                                                 "flag set. Clear skip flag.\n");
1868                         }
1869                         ret = 0;
1870                         goto cleanup;
1871                 }
1872
1873                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1874                 /* Is this a TRB in the currently executing TD? */
1875                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1876                                 td->last_trb, event_dma);
1877                 if (event_seg && ep->skip) {
1878                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
1879                         ep->skip = false;
1880                 }
1881                 if (!event_seg &&
1882                    (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
1883                         /* HC is busted, give up! */
1884                         xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
1885                                         "part of current TD\n");
1886                         return -ESHUTDOWN;
1887                 }
1888
1889                 if (event_seg) {
1890                         event_trb = &event_seg->trbs[(event_dma -
1891                                          event_seg->dma) / sizeof(*event_trb)];
1892                         /*
1893                          * No-op TRB should not trigger interrupts.
1894                          * If event_trb is a no-op TRB, it means the
1895                          * corresponding TD has been cancelled. Just ignore
1896                          * the TD.
1897                          */
1898                         if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
1899                                          == TRB_TYPE(TRB_TR_NOOP)) {
1900                                 xhci_dbg(xhci, "event_trb is a no-op TRB. "
1901                                                 "Skip it\n");
1902                                 goto cleanup;
1903                         }
1904                 }
1905
1906                 /* Now update the urb's actual_length and give back to
1907                  * the core
1908                  */
1909                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
1910                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
1911                                                  &status);
1912                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
1913                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
1914                                                  &status);
1915                 else
1916                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
1917                                                  ep, &status);
1918
1919 cleanup:
1920                 /*
1921                  * Do not update event ring dequeue pointer if ep->skip is set.
1922                  * Will roll back to continue process missed tds.
1923                  */
1924                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
1925                         inc_deq(xhci, xhci->event_ring, true);
1926                 }
1927
1928                 if (ret) {
1929                         urb = td->urb;
1930                         urb_priv = urb->hcpriv;
1931                         /* Leave the TD around for the reset endpoint function
1932                          * to use(but only if it's not a control endpoint,
1933                          * since we already queued the Set TR dequeue pointer
1934                          * command for stalled control endpoints).
1935                          */
1936                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1937                                 (trb_comp_code != COMP_STALL &&
1938                                         trb_comp_code != COMP_BABBLE))
1939                                 xhci_urb_free_priv(xhci, urb_priv);
1940
1941                         usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1942                         xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1943                                         "status = %d\n",
1944                                         urb, urb->actual_length, status);
1945                         spin_unlock(&xhci->lock);
1946                         usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1947                         spin_lock(&xhci->lock);
1948                 }
1949
1950         /*
1951          * If ep->skip is set, it means there are missed tds on the
1952          * endpoint ring need to take care of.
1953          * Process them as short transfer until reach the td pointed by
1954          * the event.
1955          */
1956         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
1957
1958         return 0;
1959 }
1960
1961 /*
1962  * This function handles all OS-owned events on the event ring.  It may drop
1963  * xhci->lock between event processing (e.g. to pass up port status changes).
1964  */
1965 static void xhci_handle_event(struct xhci_hcd *xhci)
1966 {
1967         union xhci_trb *event;
1968         int update_ptrs = 1;
1969         int ret;
1970
1971         xhci_dbg(xhci, "In %s\n", __func__);
1972         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1973                 xhci->error_bitmask |= 1 << 1;
1974                 return;
1975         }
1976
1977         event = xhci->event_ring->dequeue;
1978         /* Does the HC or OS own the TRB? */
1979         if ((event->event_cmd.flags & TRB_CYCLE) !=
1980                         xhci->event_ring->cycle_state) {
1981                 xhci->error_bitmask |= 1 << 2;
1982                 return;
1983         }
1984         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1985
1986         /* FIXME: Handle more event types. */
1987         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1988         case TRB_TYPE(TRB_COMPLETION):
1989                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1990                 handle_cmd_completion(xhci, &event->event_cmd);
1991                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1992                 break;
1993         case TRB_TYPE(TRB_PORT_STATUS):
1994                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1995                 handle_port_status(xhci, event);
1996                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1997                 update_ptrs = 0;
1998                 break;
1999         case TRB_TYPE(TRB_TRANSFER):
2000                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
2001                 ret = handle_tx_event(xhci, &event->trans_event);
2002                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
2003                 if (ret < 0)
2004                         xhci->error_bitmask |= 1 << 9;
2005                 else
2006                         update_ptrs = 0;
2007                 break;
2008         default:
2009                 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
2010                         handle_vendor_event(xhci, event);
2011                 else
2012                         xhci->error_bitmask |= 1 << 3;
2013         }
2014         /* Any of the above functions may drop and re-acquire the lock, so check
2015          * to make sure a watchdog timer didn't mark the host as non-responsive.
2016          */
2017         if (xhci->xhc_state & XHCI_STATE_DYING) {
2018                 xhci_dbg(xhci, "xHCI host dying, returning from "
2019                                 "event handler.\n");
2020                 return;
2021         }
2022
2023         if (update_ptrs)
2024                 /* Update SW event ring dequeue pointer */
2025                 inc_deq(xhci, xhci->event_ring, true);
2026
2027         /* Are there more items on the event ring? */
2028         xhci_handle_event(xhci);
2029 }
2030
2031 /*
2032  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2033  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2034  * indicators of an event TRB error, but we check the status *first* to be safe.
2035  */
2036 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2037 {
2038         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2039         u32 status, irq_pending;
2040         union xhci_trb *trb;
2041         u64 temp_64;
2042         union xhci_trb *event_ring_deq;
2043         dma_addr_t deq;
2044
2045         spin_lock(&xhci->lock);
2046         trb = xhci->event_ring->dequeue;
2047         /* Check if the xHC generated the interrupt, or the irq is shared */
2048         status = xhci_readl(xhci, &xhci->op_regs->status);
2049         irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2050         if (status == 0xffffffff && irq_pending == 0xffffffff)
2051                 goto hw_died;
2052
2053         if (!(status & STS_EINT) && !ER_IRQ_PENDING(irq_pending)) {
2054                 spin_unlock(&xhci->lock);
2055                 xhci_warn(xhci, "Spurious interrupt.\n");
2056                 return IRQ_NONE;
2057         }
2058         xhci_dbg(xhci, "op reg status = %08x\n", status);
2059         xhci_dbg(xhci, "ir set irq_pending = %08x\n", irq_pending);
2060         xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2061         xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2062                         (unsigned long long)
2063                         xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2064                         lower_32_bits(trb->link.segment_ptr),
2065                         upper_32_bits(trb->link.segment_ptr),
2066                         (unsigned int) trb->link.intr_target,
2067                         (unsigned int) trb->link.control);
2068
2069         if (status & STS_FATAL) {
2070                 xhci_warn(xhci, "WARNING: Host System Error\n");
2071                 xhci_halt(xhci);
2072 hw_died:
2073                 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
2074                 spin_unlock(&xhci->lock);
2075                 return -ESHUTDOWN;
2076         }
2077
2078         /*
2079          * Clear the op reg interrupt status first,
2080          * so we can receive interrupts from other MSI-X interrupters.
2081          * Write 1 to clear the interrupt status.
2082          */
2083         status |= STS_EINT;
2084         xhci_writel(xhci, status, &xhci->op_regs->status);
2085         /* FIXME when MSI-X is supported and there are multiple vectors */
2086         /* Clear the MSI-X event interrupt status */
2087
2088         /* Acknowledge the interrupt */
2089         irq_pending |= 0x3;
2090         xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2091
2092         if (xhci->xhc_state & XHCI_STATE_DYING) {
2093                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2094                                 "Shouldn't IRQs be disabled?\n");
2095                 /* Clear the event handler busy flag (RW1C);
2096                  * the event ring should be empty.
2097                  */
2098                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2099                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2100                                 &xhci->ir_set->erst_dequeue);
2101                 spin_unlock(&xhci->lock);
2102
2103                 return IRQ_HANDLED;
2104         }
2105
2106         event_ring_deq = xhci->event_ring->dequeue;
2107         /* FIXME this should be a delayed service routine
2108          * that clears the EHB.
2109          */
2110         xhci_handle_event(xhci);
2111
2112         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2113         /* If necessary, update the HW's version of the event ring deq ptr. */
2114         if (event_ring_deq != xhci->event_ring->dequeue) {
2115                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2116                                 xhci->event_ring->dequeue);
2117                 if (deq == 0)
2118                         xhci_warn(xhci, "WARN something wrong with SW event "
2119                                         "ring dequeue ptr.\n");
2120                 /* Update HC event ring dequeue pointer */
2121                 temp_64 &= ERST_PTR_MASK;
2122                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2123         }
2124
2125         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2126         temp_64 |= ERST_EHB;
2127         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2128
2129         spin_unlock(&xhci->lock);
2130
2131         return IRQ_HANDLED;
2132 }
2133
2134 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2135 {
2136         irqreturn_t ret;
2137
2138         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2139
2140         ret = xhci_irq(hcd);
2141
2142         return ret;
2143 }
2144
2145 /****           Endpoint Ring Operations        ****/
2146
2147 /*
2148  * Generic function for queueing a TRB on a ring.
2149  * The caller must have checked to make sure there's room on the ring.
2150  *
2151  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2152  *                      prepare_transfer()?
2153  */
2154 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2155                 bool consumer, bool more_trbs_coming,
2156                 u32 field1, u32 field2, u32 field3, u32 field4)
2157 {
2158         struct xhci_generic_trb *trb;
2159
2160         trb = &ring->enqueue->generic;
2161         trb->field[0] = field1;
2162         trb->field[1] = field2;
2163         trb->field[2] = field3;
2164         trb->field[3] = field4;
2165         inc_enq(xhci, ring, consumer, more_trbs_coming);
2166 }
2167
2168 /*
2169  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2170  * FIXME allocate segments if the ring is full.
2171  */
2172 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2173                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2174 {
2175         /* Make sure the endpoint has been added to xHC schedule */
2176         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2177         switch (ep_state) {
2178         case EP_STATE_DISABLED:
2179                 /*
2180                  * USB core changed config/interfaces without notifying us,
2181                  * or hardware is reporting the wrong state.
2182                  */
2183                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2184                 return -ENOENT;
2185         case EP_STATE_ERROR:
2186                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2187                 /* FIXME event handling code for error needs to clear it */
2188                 /* XXX not sure if this should be -ENOENT or not */
2189                 return -EINVAL;
2190         case EP_STATE_HALTED:
2191                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2192         case EP_STATE_STOPPED:
2193         case EP_STATE_RUNNING:
2194                 break;
2195         default:
2196                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2197                 /*
2198                  * FIXME issue Configure Endpoint command to try to get the HC
2199                  * back into a known state.
2200                  */
2201                 return -EINVAL;
2202         }
2203         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2204                 /* FIXME allocate more room */
2205                 xhci_err(xhci, "ERROR no room on ep ring\n");
2206                 return -ENOMEM;
2207         }
2208
2209         if (enqueue_is_link_trb(ep_ring)) {
2210                 struct xhci_ring *ring = ep_ring;
2211                 union xhci_trb *next;
2212
2213                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2214                 next = ring->enqueue;
2215
2216                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2217
2218                         /* If we're not dealing with 0.95 hardware,
2219                          * clear the chain bit.
2220                          */
2221                         if (!xhci_link_trb_quirk(xhci))
2222                                 next->link.control &= ~TRB_CHAIN;
2223                         else
2224                                 next->link.control |= TRB_CHAIN;
2225
2226                         wmb();
2227                         next->link.control ^= (u32) TRB_CYCLE;
2228
2229                         /* Toggle the cycle bit after the last ring segment. */
2230                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2231                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2232                                 if (!in_interrupt()) {
2233                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2234                                                 "state for ring %p = %i\n",
2235                                                 ring, (unsigned int)ring->cycle_state);
2236                                 }
2237                         }
2238                         ring->enq_seg = ring->enq_seg->next;
2239                         ring->enqueue = ring->enq_seg->trbs;
2240                         next = ring->enqueue;
2241                 }
2242         }
2243
2244         return 0;
2245 }
2246
2247 static int prepare_transfer(struct xhci_hcd *xhci,
2248                 struct xhci_virt_device *xdev,
2249                 unsigned int ep_index,
2250                 unsigned int stream_id,
2251                 unsigned int num_trbs,
2252                 struct urb *urb,
2253                 unsigned int td_index,
2254                 gfp_t mem_flags)
2255 {
2256         int ret;
2257         struct urb_priv *urb_priv;
2258         struct xhci_td  *td;
2259         struct xhci_ring *ep_ring;
2260         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2261
2262         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2263         if (!ep_ring) {
2264                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2265                                 stream_id);
2266                 return -EINVAL;
2267         }
2268
2269         ret = prepare_ring(xhci, ep_ring,
2270                         ep_ctx->ep_info & EP_STATE_MASK,
2271                         num_trbs, mem_flags);
2272         if (ret)
2273                 return ret;
2274
2275         urb_priv = urb->hcpriv;
2276         td = urb_priv->td[td_index];
2277
2278         INIT_LIST_HEAD(&td->td_list);
2279         INIT_LIST_HEAD(&td->cancelled_td_list);
2280
2281         if (td_index == 0) {
2282                 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
2283                 if (unlikely(ret)) {
2284                         xhci_urb_free_priv(xhci, urb_priv);
2285                         urb->hcpriv = NULL;
2286                         return ret;
2287                 }
2288         }
2289
2290         td->urb = urb;
2291         /* Add this TD to the tail of the endpoint ring's TD list */
2292         list_add_tail(&td->td_list, &ep_ring->td_list);
2293         td->start_seg = ep_ring->enq_seg;
2294         td->first_trb = ep_ring->enqueue;
2295
2296         urb_priv->td[td_index] = td;
2297
2298         return 0;
2299 }
2300
2301 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2302 {
2303         int num_sgs, num_trbs, running_total, temp, i;
2304         struct scatterlist *sg;
2305
2306         sg = NULL;
2307         num_sgs = urb->num_sgs;
2308         temp = urb->transfer_buffer_length;
2309
2310         xhci_dbg(xhci, "count sg list trbs: \n");
2311         num_trbs = 0;
2312         for_each_sg(urb->sg, sg, num_sgs, i) {
2313                 unsigned int previous_total_trbs = num_trbs;
2314                 unsigned int len = sg_dma_len(sg);
2315
2316                 /* Scatter gather list entries may cross 64KB boundaries */
2317                 running_total = TRB_MAX_BUFF_SIZE -
2318                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2319                 if (running_total != 0)
2320                         num_trbs++;
2321
2322                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2323                 while (running_total < sg_dma_len(sg)) {
2324                         num_trbs++;
2325                         running_total += TRB_MAX_BUFF_SIZE;
2326                 }
2327                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2328                                 i, (unsigned long long)sg_dma_address(sg),
2329                                 len, len, num_trbs - previous_total_trbs);
2330
2331                 len = min_t(int, len, temp);
2332                 temp -= len;
2333                 if (temp == 0)
2334                         break;
2335         }
2336         xhci_dbg(xhci, "\n");
2337         if (!in_interrupt())
2338                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
2339                                 urb->ep->desc.bEndpointAddress,
2340                                 urb->transfer_buffer_length,
2341                                 num_trbs);
2342         return num_trbs;
2343 }
2344
2345 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2346 {
2347         if (num_trbs != 0)
2348                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2349                                 "TRBs, %d left\n", __func__,
2350                                 urb->ep->desc.bEndpointAddress, num_trbs);
2351         if (running_total != urb->transfer_buffer_length)
2352                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2353                                 "queued %#x (%d), asked for %#x (%d)\n",
2354                                 __func__,
2355                                 urb->ep->desc.bEndpointAddress,
2356                                 running_total, running_total,
2357                                 urb->transfer_buffer_length,
2358                                 urb->transfer_buffer_length);
2359 }
2360
2361 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2362                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2363                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
2364 {
2365         /*
2366          * Pass all the TRBs to the hardware at once and make sure this write
2367          * isn't reordered.
2368          */
2369         wmb();
2370         start_trb->field[3] |= start_cycle;
2371         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2372 }
2373
2374 /*
2375  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2376  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2377  * (comprised of sg list entries) can take several service intervals to
2378  * transmit.
2379  */
2380 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2381                 struct urb *urb, int slot_id, unsigned int ep_index)
2382 {
2383         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2384                         xhci->devs[slot_id]->out_ctx, ep_index);
2385         int xhci_interval;
2386         int ep_interval;
2387
2388         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2389         ep_interval = urb->interval;
2390         /* Convert to microframes */
2391         if (urb->dev->speed == USB_SPEED_LOW ||
2392                         urb->dev->speed == USB_SPEED_FULL)
2393                 ep_interval *= 8;
2394         /* FIXME change this to a warning and a suggestion to use the new API
2395          * to set the polling interval (once the API is added).
2396          */
2397         if (xhci_interval != ep_interval) {
2398                 if (!printk_ratelimit())
2399                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2400                                         " (%d microframe%s) than xHCI "
2401                                         "(%d microframe%s)\n",
2402                                         ep_interval,
2403                                         ep_interval == 1 ? "" : "s",
2404                                         xhci_interval,
2405                                         xhci_interval == 1 ? "" : "s");
2406                 urb->interval = xhci_interval;
2407                 /* Convert back to frames for LS/FS devices */
2408                 if (urb->dev->speed == USB_SPEED_LOW ||
2409                                 urb->dev->speed == USB_SPEED_FULL)
2410                         urb->interval /= 8;
2411         }
2412         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2413 }
2414
2415 /*
2416  * The TD size is the number of bytes remaining in the TD (including this TRB),
2417  * right shifted by 10.
2418  * It must fit in bits 21:17, so it can't be bigger than 31.
2419  */
2420 static u32 xhci_td_remainder(unsigned int remainder)
2421 {
2422         u32 max = (1 << (21 - 17 + 1)) - 1;
2423
2424         if ((remainder >> 10) >= max)
2425                 return max << 17;
2426         else
2427                 return (remainder >> 10) << 17;
2428 }
2429
2430 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2431                 struct urb *urb, int slot_id, unsigned int ep_index)
2432 {
2433         struct xhci_ring *ep_ring;
2434         unsigned int num_trbs;
2435         struct urb_priv *urb_priv;
2436         struct xhci_td *td;
2437         struct scatterlist *sg;
2438         int num_sgs;
2439         int trb_buff_len, this_sg_len, running_total;
2440         bool first_trb;
2441         u64 addr;
2442         bool more_trbs_coming;
2443
2444         struct xhci_generic_trb *start_trb;
2445         int start_cycle;
2446
2447         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2448         if (!ep_ring)
2449                 return -EINVAL;
2450
2451         num_trbs = count_sg_trbs_needed(xhci, urb);
2452         num_sgs = urb->num_sgs;
2453
2454         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2455                         ep_index, urb->stream_id,
2456                         num_trbs, urb, 0, mem_flags);
2457         if (trb_buff_len < 0)
2458                 return trb_buff_len;
2459
2460         urb_priv = urb->hcpriv;
2461         td = urb_priv->td[0];
2462
2463         /*
2464          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2465          * until we've finished creating all the other TRBs.  The ring's cycle
2466          * state may change as we enqueue the other TRBs, so save it too.
2467          */
2468         start_trb = &ep_ring->enqueue->generic;
2469         start_cycle = ep_ring->cycle_state;
2470
2471         running_total = 0;
2472         /*
2473          * How much data is in the first TRB?
2474          *
2475          * There are three forces at work for TRB buffer pointers and lengths:
2476          * 1. We don't want to walk off the end of this sg-list entry buffer.
2477          * 2. The transfer length that the driver requested may be smaller than
2478          *    the amount of memory allocated for this scatter-gather list.
2479          * 3. TRBs buffers can't cross 64KB boundaries.
2480          */
2481         sg = urb->sg;
2482         addr = (u64) sg_dma_address(sg);
2483         this_sg_len = sg_dma_len(sg);
2484         trb_buff_len = TRB_MAX_BUFF_SIZE -
2485                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2486         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2487         if (trb_buff_len > urb->transfer_buffer_length)
2488                 trb_buff_len = urb->transfer_buffer_length;
2489         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2490                         trb_buff_len);
2491
2492         first_trb = true;
2493         /* Queue the first TRB, even if it's zero-length */
2494         do {
2495                 u32 field = 0;
2496                 u32 length_field = 0;
2497                 u32 remainder = 0;
2498
2499                 /* Don't change the cycle bit of the first TRB until later */
2500                 if (first_trb)
2501                         first_trb = false;
2502                 else
2503                         field |= ep_ring->cycle_state;
2504
2505                 /* Chain all the TRBs together; clear the chain bit in the last
2506                  * TRB to indicate it's the last TRB in the chain.
2507                  */
2508                 if (num_trbs > 1) {
2509                         field |= TRB_CHAIN;
2510                 } else {
2511                         /* FIXME - add check for ZERO_PACKET flag before this */
2512                         td->last_trb = ep_ring->enqueue;
2513                         field |= TRB_IOC;
2514                 }
2515                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2516                                 "64KB boundary at %#x, end dma = %#x\n",
2517                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2518                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2519                                 (unsigned int) addr + trb_buff_len);
2520                 if (TRB_MAX_BUFF_SIZE -
2521                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
2522                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2523                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2524                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2525                                         (unsigned int) addr + trb_buff_len);
2526                 }
2527                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2528                                 running_total) ;
2529                 length_field = TRB_LEN(trb_buff_len) |
2530                         remainder |
2531                         TRB_INTR_TARGET(0);
2532                 if (num_trbs > 1)
2533                         more_trbs_coming = true;
2534                 else
2535                         more_trbs_coming = false;
2536                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2537                                 lower_32_bits(addr),
2538                                 upper_32_bits(addr),
2539                                 length_field,
2540                                 /* We always want to know if the TRB was short,
2541                                  * or we won't get an event when it completes.
2542                                  * (Unless we use event data TRBs, which are a
2543                                  * waste of space and HC resources.)
2544                                  */
2545                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2546                 --num_trbs;
2547                 running_total += trb_buff_len;
2548
2549                 /* Calculate length for next transfer --
2550                  * Are we done queueing all the TRBs for this sg entry?
2551                  */
2552                 this_sg_len -= trb_buff_len;
2553                 if (this_sg_len == 0) {
2554                         --num_sgs;
2555                         if (num_sgs == 0)
2556                                 break;
2557                         sg = sg_next(sg);
2558                         addr = (u64) sg_dma_address(sg);
2559                         this_sg_len = sg_dma_len(sg);
2560                 } else {
2561                         addr += trb_buff_len;
2562                 }
2563
2564                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2565                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2566                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2567                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2568                         trb_buff_len =
2569                                 urb->transfer_buffer_length - running_total;
2570         } while (running_total < urb->transfer_buffer_length);
2571
2572         check_trb_math(urb, num_trbs, running_total);
2573         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2574                         start_cycle, start_trb, td);
2575         return 0;
2576 }
2577
2578 /* This is very similar to what ehci-q.c qtd_fill() does */
2579 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2580                 struct urb *urb, int slot_id, unsigned int ep_index)
2581 {
2582         struct xhci_ring *ep_ring;
2583         struct urb_priv *urb_priv;
2584         struct xhci_td *td;
2585         int num_trbs;
2586         struct xhci_generic_trb *start_trb;
2587         bool first_trb;
2588         bool more_trbs_coming;
2589         int start_cycle;
2590         u32 field, length_field;
2591
2592         int running_total, trb_buff_len, ret;
2593         u64 addr;
2594
2595         if (urb->num_sgs)
2596                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2597
2598         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2599         if (!ep_ring)
2600                 return -EINVAL;
2601
2602         num_trbs = 0;
2603         /* How much data is (potentially) left before the 64KB boundary? */
2604         running_total = TRB_MAX_BUFF_SIZE -
2605                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2606
2607         /* If there's some data on this 64KB chunk, or we have to send a
2608          * zero-length transfer, we need at least one TRB
2609          */
2610         if (running_total != 0 || urb->transfer_buffer_length == 0)
2611                 num_trbs++;
2612         /* How many more 64KB chunks to transfer, how many more TRBs? */
2613         while (running_total < urb->transfer_buffer_length) {
2614                 num_trbs++;
2615                 running_total += TRB_MAX_BUFF_SIZE;
2616         }
2617         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2618
2619         if (!in_interrupt())
2620                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2621                                 urb->ep->desc.bEndpointAddress,
2622                                 urb->transfer_buffer_length,
2623                                 urb->transfer_buffer_length,
2624                                 (unsigned long long)urb->transfer_dma,
2625                                 num_trbs);
2626
2627         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2628                         ep_index, urb->stream_id,
2629                         num_trbs, urb, 0, mem_flags);
2630         if (ret < 0)
2631                 return ret;
2632
2633         urb_priv = urb->hcpriv;
2634         td = urb_priv->td[0];
2635
2636         /*
2637          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2638          * until we've finished creating all the other TRBs.  The ring's cycle
2639          * state may change as we enqueue the other TRBs, so save it too.
2640          */
2641         start_trb = &ep_ring->enqueue->generic;
2642         start_cycle = ep_ring->cycle_state;
2643
2644         running_total = 0;
2645         /* How much data is in the first TRB? */
2646         addr = (u64) urb->transfer_dma;
2647         trb_buff_len = TRB_MAX_BUFF_SIZE -
2648                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2649         if (urb->transfer_buffer_length < trb_buff_len)
2650                 trb_buff_len = urb->transfer_buffer_length;
2651
2652         first_trb = true;
2653
2654         /* Queue the first TRB, even if it's zero-length */
2655         do {
2656                 u32 remainder = 0;
2657                 field = 0;
2658
2659                 /* Don't change the cycle bit of the first TRB until later */
2660                 if (first_trb)
2661                         first_trb = false;
2662                 else
2663                         field |= ep_ring->cycle_state;
2664
2665                 /* Chain all the TRBs together; clear the chain bit in the last
2666                  * TRB to indicate it's the last TRB in the chain.
2667                  */
2668                 if (num_trbs > 1) {
2669                         field |= TRB_CHAIN;
2670                 } else {
2671                         /* FIXME - add check for ZERO_PACKET flag before this */
2672                         td->last_trb = ep_ring->enqueue;
2673                         field |= TRB_IOC;
2674                 }
2675                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2676                                 running_total);
2677                 length_field = TRB_LEN(trb_buff_len) |
2678                         remainder |
2679                         TRB_INTR_TARGET(0);
2680                 if (num_trbs > 1)
2681                         more_trbs_coming = true;
2682                 else
2683                         more_trbs_coming = false;
2684                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2685                                 lower_32_bits(addr),
2686                                 upper_32_bits(addr),
2687                                 length_field,
2688                                 /* We always want to know if the TRB was short,
2689                                  * or we won't get an event when it completes.
2690                                  * (Unless we use event data TRBs, which are a
2691                                  * waste of space and HC resources.)
2692                                  */
2693                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2694                 --num_trbs;
2695                 running_total += trb_buff_len;
2696
2697                 /* Calculate length for next transfer */
2698                 addr += trb_buff_len;
2699                 trb_buff_len = urb->transfer_buffer_length - running_total;
2700                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2701                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2702         } while (running_total < urb->transfer_buffer_length);
2703
2704         check_trb_math(urb, num_trbs, running_total);
2705         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2706                         start_cycle, start_trb, td);
2707         return 0;
2708 }
2709
2710 /* Caller must have locked xhci->lock */
2711 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2712                 struct urb *urb, int slot_id, unsigned int ep_index)
2713 {
2714         struct xhci_ring *ep_ring;
2715         int num_trbs;
2716         int ret;
2717         struct usb_ctrlrequest *setup;
2718         struct xhci_generic_trb *start_trb;
2719         int start_cycle;
2720         u32 field, length_field;
2721         struct urb_priv *urb_priv;
2722         struct xhci_td *td;
2723
2724         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2725         if (!ep_ring)
2726                 return -EINVAL;
2727
2728         /*
2729          * Need to copy setup packet into setup TRB, so we can't use the setup
2730          * DMA address.
2731          */
2732         if (!urb->setup_packet)
2733                 return -EINVAL;
2734
2735         if (!in_interrupt())
2736                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2737                                 slot_id, ep_index);
2738         /* 1 TRB for setup, 1 for status */
2739         num_trbs = 2;
2740         /*
2741          * Don't need to check if we need additional event data and normal TRBs,
2742          * since data in control transfers will never get bigger than 16MB
2743          * XXX: can we get a buffer that crosses 64KB boundaries?
2744          */
2745         if (urb->transfer_buffer_length > 0)
2746                 num_trbs++;
2747         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2748                         ep_index, urb->stream_id,
2749                         num_trbs, urb, 0, mem_flags);
2750         if (ret < 0)
2751                 return ret;
2752
2753         urb_priv = urb->hcpriv;
2754         td = urb_priv->td[0];
2755
2756         /*
2757          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2758          * until we've finished creating all the other TRBs.  The ring's cycle
2759          * state may change as we enqueue the other TRBs, so save it too.
2760          */
2761         start_trb = &ep_ring->enqueue->generic;
2762         start_cycle = ep_ring->cycle_state;
2763
2764         /* Queue setup TRB - see section 6.4.1.2.1 */
2765         /* FIXME better way to translate setup_packet into two u32 fields? */
2766         setup = (struct usb_ctrlrequest *) urb->setup_packet;
2767         queue_trb(xhci, ep_ring, false, true,
2768                         /* FIXME endianness is probably going to bite my ass here. */
2769                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2770                         setup->wIndex | setup->wLength << 16,
2771                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2772                         /* Immediate data in pointer */
2773                         TRB_IDT | TRB_TYPE(TRB_SETUP));
2774
2775         /* If there's data, queue data TRBs */
2776         field = 0;
2777         length_field = TRB_LEN(urb->transfer_buffer_length) |
2778                 xhci_td_remainder(urb->transfer_buffer_length) |
2779                 TRB_INTR_TARGET(0);
2780         if (urb->transfer_buffer_length > 0) {
2781                 if (setup->bRequestType & USB_DIR_IN)
2782                         field |= TRB_DIR_IN;
2783                 queue_trb(xhci, ep_ring, false, true,
2784                                 lower_32_bits(urb->transfer_dma),
2785                                 upper_32_bits(urb->transfer_dma),
2786                                 length_field,
2787                                 /* Event on short tx */
2788                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2789         }
2790
2791         /* Save the DMA address of the last TRB in the TD */
2792         td->last_trb = ep_ring->enqueue;
2793
2794         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2795         /* If the device sent data, the status stage is an OUT transfer */
2796         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2797                 field = 0;
2798         else
2799                 field = TRB_DIR_IN;
2800         queue_trb(xhci, ep_ring, false, false,
2801                         0,
2802                         0,
2803                         TRB_INTR_TARGET(0),
2804                         /* Event on completion */
2805                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2806
2807         giveback_first_trb(xhci, slot_id, ep_index, 0,
2808                         start_cycle, start_trb, td);
2809         return 0;
2810 }
2811
2812 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
2813                 struct urb *urb, int i)
2814 {
2815         int num_trbs = 0;
2816         u64 addr, td_len, running_total;
2817
2818         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2819         td_len = urb->iso_frame_desc[i].length;
2820
2821         running_total = TRB_MAX_BUFF_SIZE -
2822                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2823         if (running_total != 0)
2824                 num_trbs++;
2825
2826         while (running_total < td_len) {
2827                 num_trbs++;
2828                 running_total += TRB_MAX_BUFF_SIZE;
2829         }
2830
2831         return num_trbs;
2832 }
2833
2834 /* This is for isoc transfer */
2835 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2836                 struct urb *urb, int slot_id, unsigned int ep_index)
2837 {
2838         struct xhci_ring *ep_ring;
2839         struct urb_priv *urb_priv;
2840         struct xhci_td *td;
2841         int num_tds, trbs_per_td;
2842         struct xhci_generic_trb *start_trb;
2843         bool first_trb;
2844         int start_cycle;
2845         u32 field, length_field;
2846         int running_total, trb_buff_len, td_len, td_remain_len, ret;
2847         u64 start_addr, addr;
2848         int i, j;
2849
2850         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2851
2852         num_tds = urb->number_of_packets;
2853         if (num_tds < 1) {
2854                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
2855                 return -EINVAL;
2856         }
2857
2858         if (!in_interrupt())
2859                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d),"
2860                                 " addr = %#llx, num_tds = %d\n",
2861                                 urb->ep->desc.bEndpointAddress,
2862                                 urb->transfer_buffer_length,
2863                                 urb->transfer_buffer_length,
2864                                 (unsigned long long)urb->transfer_dma,
2865                                 num_tds);
2866
2867         start_addr = (u64) urb->transfer_dma;
2868         start_trb = &ep_ring->enqueue->generic;
2869         start_cycle = ep_ring->cycle_state;
2870
2871         /* Queue the first TRB, even if it's zero-length */
2872         for (i = 0; i < num_tds; i++) {
2873                 first_trb = true;
2874
2875                 running_total = 0;
2876                 addr = start_addr + urb->iso_frame_desc[i].offset;
2877                 td_len = urb->iso_frame_desc[i].length;
2878                 td_remain_len = td_len;
2879
2880                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
2881
2882                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
2883                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
2884                 if (ret < 0)
2885                         return ret;
2886
2887                 urb_priv = urb->hcpriv;
2888                 td = urb_priv->td[i];
2889
2890                 for (j = 0; j < trbs_per_td; j++) {
2891                         u32 remainder = 0;
2892                         field = 0;
2893
2894                         if (first_trb) {
2895                                 /* Queue the isoc TRB */
2896                                 field |= TRB_TYPE(TRB_ISOC);
2897                                 /* Assume URB_ISO_ASAP is set */
2898                                 field |= TRB_SIA;
2899                                 if (i > 0)
2900                                         field |= ep_ring->cycle_state;
2901                                 first_trb = false;
2902                         } else {
2903                                 /* Queue other normal TRBs */
2904                                 field |= TRB_TYPE(TRB_NORMAL);
2905                                 field |= ep_ring->cycle_state;
2906                         }
2907
2908                         /* Chain all the TRBs together; clear the chain bit in
2909                          * the last TRB to indicate it's the last TRB in the
2910                          * chain.
2911                          */
2912                         if (j < trbs_per_td - 1) {
2913                                 field |= TRB_CHAIN;
2914                         } else {
2915                                 td->last_trb = ep_ring->enqueue;
2916                                 field |= TRB_IOC;
2917                         }
2918
2919                         /* Calculate TRB length */
2920                         trb_buff_len = TRB_MAX_BUFF_SIZE -
2921                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2922                         if (trb_buff_len > td_remain_len)
2923                                 trb_buff_len = td_remain_len;
2924
2925                         remainder = xhci_td_remainder(td_len - running_total);
2926                         length_field = TRB_LEN(trb_buff_len) |
2927                                 remainder |
2928                                 TRB_INTR_TARGET(0);
2929                         queue_trb(xhci, ep_ring, false, false,
2930                                 lower_32_bits(addr),
2931                                 upper_32_bits(addr),
2932                                 length_field,
2933                                 /* We always want to know if the TRB was short,
2934                                  * or we won't get an event when it completes.
2935                                  * (Unless we use event data TRBs, which are a
2936                                  * waste of space and HC resources.)
2937                                  */
2938                                 field | TRB_ISP);
2939                         running_total += trb_buff_len;
2940
2941                         addr += trb_buff_len;
2942                         td_remain_len -= trb_buff_len;
2943                 }
2944
2945                 /* Check TD length */
2946                 if (running_total != td_len) {
2947                         xhci_err(xhci, "ISOC TD length unmatch\n");
2948                         return -EINVAL;
2949                 }
2950         }
2951
2952         wmb();
2953         start_trb->field[3] |= start_cycle;
2954
2955         ring_ep_doorbell(xhci, slot_id, ep_index, urb->stream_id);
2956         return 0;
2957 }
2958
2959 /*
2960  * Check transfer ring to guarantee there is enough room for the urb.
2961  * Update ISO URB start_frame and interval.
2962  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
2963  * update the urb->start_frame by now.
2964  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
2965  */
2966 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2967                 struct urb *urb, int slot_id, unsigned int ep_index)
2968 {
2969         struct xhci_virt_device *xdev;
2970         struct xhci_ring *ep_ring;
2971         struct xhci_ep_ctx *ep_ctx;
2972         int start_frame;
2973         int xhci_interval;
2974         int ep_interval;
2975         int num_tds, num_trbs, i;
2976         int ret;
2977
2978         xdev = xhci->devs[slot_id];
2979         ep_ring = xdev->eps[ep_index].ring;
2980         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2981
2982         num_trbs = 0;
2983         num_tds = urb->number_of_packets;
2984         for (i = 0; i < num_tds; i++)
2985                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
2986
2987         /* Check the ring to guarantee there is enough room for the whole urb.
2988          * Do not insert any td of the urb to the ring if the check failed.
2989          */
2990         ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
2991                                 num_trbs, mem_flags);
2992         if (ret)
2993                 return ret;
2994
2995         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
2996         start_frame &= 0x3fff;
2997
2998         urb->start_frame = start_frame;
2999         if (urb->dev->speed == USB_SPEED_LOW ||
3000                         urb->dev->speed == USB_SPEED_FULL)
3001                 urb->start_frame >>= 3;
3002
3003         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
3004         ep_interval = urb->interval;
3005         /* Convert to microframes */
3006         if (urb->dev->speed == USB_SPEED_LOW ||
3007                         urb->dev->speed == USB_SPEED_FULL)
3008                 ep_interval *= 8;
3009         /* FIXME change this to a warning and a suggestion to use the new API
3010          * to set the polling interval (once the API is added).
3011          */
3012         if (xhci_interval != ep_interval) {
3013                 if (!printk_ratelimit())
3014                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3015                                         " (%d microframe%s) than xHCI "
3016                                         "(%d microframe%s)\n",
3017                                         ep_interval,
3018                                         ep_interval == 1 ? "" : "s",
3019                                         xhci_interval,
3020                                         xhci_interval == 1 ? "" : "s");
3021                 urb->interval = xhci_interval;
3022                 /* Convert back to frames for LS/FS devices */
3023                 if (urb->dev->speed == USB_SPEED_LOW ||
3024                                 urb->dev->speed == USB_SPEED_FULL)
3025                         urb->interval /= 8;
3026         }
3027         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3028 }
3029
3030 /****           Command Ring Operations         ****/
3031
3032 /* Generic function for queueing a command TRB on the command ring.
3033  * Check to make sure there's room on the command ring for one command TRB.
3034  * Also check that there's room reserved for commands that must not fail.
3035  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3036  * then only check for the number of reserved spots.
3037  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3038  * because the command event handler may want to resubmit a failed command.
3039  */
3040 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3041                 u32 field3, u32 field4, bool command_must_succeed)
3042 {
3043         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3044         int ret;
3045
3046         if (!command_must_succeed)
3047                 reserved_trbs++;
3048
3049         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3050                         reserved_trbs, GFP_ATOMIC);
3051         if (ret < 0) {
3052                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3053                 if (command_must_succeed)
3054                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3055                                         "unfailable commands failed.\n");
3056                 return ret;
3057         }
3058         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3059                         field4 | xhci->cmd_ring->cycle_state);
3060         return 0;
3061 }
3062
3063 /* Queue a no-op command on the command ring */
3064 static int queue_cmd_noop(struct xhci_hcd *xhci)
3065 {
3066         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
3067 }
3068
3069 /*
3070  * Place a no-op command on the command ring to test the command and
3071  * event ring.
3072  */
3073 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
3074 {
3075         if (queue_cmd_noop(xhci) < 0)
3076                 return NULL;
3077         xhci->noops_submitted++;
3078         return xhci_ring_cmd_db;
3079 }
3080
3081 /* Queue a slot enable or disable request on the command ring */
3082 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3083 {
3084         return queue_command(xhci, 0, 0, 0,
3085                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3086 }
3087
3088 /* Queue an address device command TRB */
3089 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3090                 u32 slot_id)
3091 {
3092         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3093                         upper_32_bits(in_ctx_ptr), 0,
3094                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3095                         false);
3096 }
3097
3098 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3099                 u32 field1, u32 field2, u32 field3, u32 field4)
3100 {
3101         return queue_command(xhci, field1, field2, field3, field4, false);
3102 }
3103
3104 /* Queue a reset device command TRB */
3105 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3106 {
3107         return queue_command(xhci, 0, 0, 0,
3108                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3109                         false);
3110 }
3111
3112 /* Queue a configure endpoint command TRB */
3113 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3114                 u32 slot_id, bool command_must_succeed)
3115 {
3116         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3117                         upper_32_bits(in_ctx_ptr), 0,
3118                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3119                         command_must_succeed);
3120 }
3121
3122 /* Queue an evaluate context command TRB */
3123 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3124                 u32 slot_id)
3125 {
3126         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3127                         upper_32_bits(in_ctx_ptr), 0,
3128                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3129                         false);
3130 }
3131
3132 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3133                 unsigned int ep_index)
3134 {
3135         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3136         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3137         u32 type = TRB_TYPE(TRB_STOP_RING);
3138
3139         return queue_command(xhci, 0, 0, 0,
3140                         trb_slot_id | trb_ep_index | type, false);
3141 }
3142
3143 /* Set Transfer Ring Dequeue Pointer command.
3144  * This should not be used for endpoints that have streams enabled.
3145  */
3146 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3147                 unsigned int ep_index, unsigned int stream_id,
3148                 struct xhci_segment *deq_seg,
3149                 union xhci_trb *deq_ptr, u32 cycle_state)
3150 {
3151         dma_addr_t addr;
3152         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3153         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3154         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3155         u32 type = TRB_TYPE(TRB_SET_DEQ);
3156
3157         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3158         if (addr == 0) {
3159                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3160                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3161                                 deq_seg, deq_ptr);
3162                 return 0;
3163         }
3164         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3165                         upper_32_bits(addr), trb_stream_id,
3166                         trb_slot_id | trb_ep_index | type, false);
3167 }
3168
3169 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3170                 unsigned int ep_index)
3171 {
3172         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3173         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3174         u32 type = TRB_TYPE(TRB_RESET_EP);
3175
3176         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3177                         false);
3178 }