drivers/dma/ioat/dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/dmaengine.h>
  34 #include <linux/delay.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/prefetch.h>
  38 #include <linux/i7300_idle.h>
  39 #include "dma.h"
  40 #include "registers.h"
  41 #include "hw.h"
  42
  43 int ioat_pending_level = 4;
  44 module_param(ioat_pending_level, int, 0644);
  45 MODULE_PARM_DESC(ioat_pending_level,
  46                  "high-water mark for pushing ioat descriptors (default: 4)");
  47
  48 /* internal functions */
  49 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
  50 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
  51
  52 /**
  53  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  54  * @irq: interrupt id
  55  * @data: interrupt data
  56  */
  57 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  58 {
  59         struct ioatdma_device *instance = data;
  60         struct ioat_chan_common *chan;
  61         unsigned long attnstatus;
  62         int bit;
  63         u8 intrctrl;
  64
  65         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  66
  67         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  68                 return IRQ_NONE;
  69
  70         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  71                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  72                 return IRQ_NONE;
  73         }
  74
  75         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
  76         for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
  77                 chan = ioat_chan_by_index(instance, bit);
  78                 tasklet_schedule(&chan->cleanup_task);
  79         }
  80
  81         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  82         return IRQ_HANDLED;
  83 }
  84
  85 /**
  86  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
  87  * @irq: interrupt id
  88  * @data: interrupt data
  89  */
  90 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
  91 {
  92         struct ioat_chan_common *chan = data;
  93
  94         tasklet_schedule(&chan->cleanup_task);
  95
  96         return IRQ_HANDLED;
  97 }
  98
  99 /* common channel initialization */
 100 void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx)
 101 {
 102         struct dma_device *dma = &device->common;
 103         struct dma_chan *c = &chan->common;
 104         unsigned long data = (unsigned long) c;
 105
 106         chan->device = device;
 107         chan->reg_base = device->reg_base + (0x80 * (idx + 1));
 108         spin_lock_init(&chan->cleanup_lock);
 109         chan->common.device = dma;
 110         list_add_tail(&chan->common.device_node, &dma->channels);
 111         device->idx[idx] = chan;
 112         init_timer(&chan->timer);
 113         chan->timer.function = device->timer_fn;
 114         chan->timer.data = data;
 115         tasklet_init(&chan->cleanup_task, device->cleanup_fn, data);
 116         tasklet_disable(&chan->cleanup_task);
 117 }
 118
 119 /**
 120  * ioat1_dma_enumerate_channels - find and initialize the device's channels
 121  * @device: the device to be enumerated
 122  */
 123 static int ioat1_enumerate_channels(struct ioatdma_device *device)
 124 {
 125         u8 xfercap_scale;
 126         u32 xfercap;
 127         int i;
 128         struct ioat_dma_chan *ioat;
 129         struct device *dev = &device->pdev->dev;
 130         struct dma_device *dma = &device->common;
 131
 132         INIT_LIST_HEAD(&dma->channels);
 133         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 134         dma->chancnt &= 0x1f; /* bits [4:0] valid */
 135         if (dma->chancnt > ARRAY_SIZE(device->idx)) {
 136                 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
 137                          dma->chancnt, ARRAY_SIZE(device->idx));
 138                 dma->chancnt = ARRAY_SIZE(device->idx);
 139         }
 140         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 141         xfercap_scale &= 0x1f; /* bits [4:0] valid */
 142         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 143         dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
 144
 145 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
 146         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 147                 dma->chancnt--;
 148 #endif
 149         for (i = 0; i < dma->chancnt; i++) {
 150                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 151                 if (!ioat)
 152                         break;
 153
 154                 ioat_init_channel(device, &ioat->base, i);
 155                 ioat->xfercap = xfercap;
 156                 spin_lock_init(&ioat->desc_lock);
 157                 INIT_LIST_HEAD(&ioat->free_desc);
 158                 INIT_LIST_HEAD(&ioat->used_desc);
 159         }
 160         dma->chancnt = i;
 161         return i;
 162 }
 163
 164 /**
 165  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 166  *                                 descriptors to hw
 167  * @chan: DMA channel handle
 168  */
 169 static inline void
 170 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
 171 {
 172         void __iomem *reg_base = ioat->base.reg_base;
 173
 174         dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
 175                 __func__, ioat->pending);
 176         ioat->pending = 0;
 177         writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
 178 }
 179
 180 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 181 {
 182         struct ioat_dma_chan *ioat = to_ioat_chan(chan);
 183
 184         if (ioat->pending > 0) {
 185                 spin_lock_bh(&ioat->desc_lock);
 186                 __ioat1_dma_memcpy_issue_pending(ioat);
 187                 spin_unlock_bh(&ioat->desc_lock);
 188         }
 189 }
 190
 191 /**
 192  * ioat1_reset_channel - restart a channel
 193  * @ioat: IOAT DMA channel handle
 194  */
 195 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
 196 {
 197         struct ioat_chan_common *chan = &ioat->base;
 198         void __iomem *reg_base = chan->reg_base;
 199         u32 chansts, chanerr;
 200
 201         dev_warn(to_dev(chan), "reset\n");
 202         chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
 203         chansts = *chan->completion & IOAT_CHANSTS_STATUS;
 204         if (chanerr) {
 205                 dev_err(to_dev(chan),
 206                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 207                         chan_num(chan), chansts, chanerr);
 208                 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
 209         }
 210
 211         /*
 212          * whack it upside the head with a reset
 213          * and wait for things to settle out.
 214          * force the pending count to a really big negative
 215          * to make sure no one forces an issue_pending
 216          * while we're waiting.
 217          */
 218
 219         ioat->pending = INT_MIN;
 220         writeb(IOAT_CHANCMD_RESET,
 221                reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 222         set_bit(IOAT_RESET_PENDING, &chan->state);
 223         mod_timer(&chan->timer, jiffies + RESET_DELAY);
 224 }
 225
 226 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 227 {
 228         struct dma_chan *c = tx->chan;
 229         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 230         struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
 231         struct ioat_chan_common *chan = &ioat->base;
 232         struct ioat_desc_sw *first;
 233         struct ioat_desc_sw *chain_tail;
 234         dma_cookie_t cookie;
 235
 236         spin_lock_bh(&ioat->desc_lock);
 237         /* cookie incr and addition to used_list must be atomic */
 238         cookie = c->cookie;
 239         cookie++;
 240         if (cookie < 0)
 241                 cookie = 1;
 242         c->cookie = cookie;
 243         tx->cookie = cookie;
 244         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 245
 246         /* write address into NextDescriptor field of last desc in chain */
 247         first = to_ioat_desc(desc->tx_list.next);
 248         chain_tail = to_ioat_desc(ioat->used_desc.prev);
 249         /* make descriptor updates globally visible before chaining */
 250         wmb();
 251         chain_tail->hw->next = first->txd.phys;
 252         list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
 253         dump_desc_dbg(ioat, chain_tail);
 254         dump_desc_dbg(ioat, first);
 255
 256         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
 257                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 258
 259         ioat->active += desc->hw->tx_cnt;
 260         ioat->pending += desc->hw->tx_cnt;
 261         if (ioat->pending >= ioat_pending_level)
 262                 __ioat1_dma_memcpy_issue_pending(ioat);
 263         spin_unlock_bh(&ioat->desc_lock);
 264
 265         return cookie;
 266 }
 267
 268 /**
 269  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 270  * @ioat: the channel supplying the memory pool for the descriptors
 271  * @flags: allocation flags
 272  */
 273 static struct ioat_desc_sw *
 274 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
 275 {
 276         struct ioat_dma_descriptor *desc;
 277         struct ioat_desc_sw *desc_sw;
 278         struct ioatdma_device *ioatdma_device;
 279         dma_addr_t phys;
 280
 281         ioatdma_device = ioat->base.device;
 282         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 283         if (unlikely(!desc))
 284                 return NULL;
 285
 286         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 287         if (unlikely(!desc_sw)) {
 288                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 289                 return NULL;
 290         }
 291
 292         memset(desc, 0, sizeof(*desc));
 293
 294         INIT_LIST_HEAD(&desc_sw->tx_list);
 295         dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
 296         desc_sw->txd.tx_submit = ioat1_tx_submit;
 297         desc_sw->hw = desc;
 298         desc_sw->txd.phys = phys;
 299         set_desc_id(desc_sw, -1);
 300
 301         return desc_sw;
 302 }
 303
 304 static int ioat_initial_desc_count = 256;
 305 module_param(ioat_initial_desc_count, int, 0644);
 306 MODULE_PARM_DESC(ioat_initial_desc_count,
 307                  "ioat1: initial descriptors per channel (default: 256)");
 308 /**
 309  * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
 310  * @chan: the channel to be filled out
 311  */
 312 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
 313 {
 314         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 315         struct ioat_chan_common *chan = &ioat->base;
 316         struct ioat_desc_sw *desc;
 317         u32 chanerr;
 318         int i;
 319         LIST_HEAD(tmp_list);
 320
 321         /* have we already been set up? */
 322         if (!list_empty(&ioat->free_desc))
 323                 return ioat->desccount;
 324
 325         /* Setup register to interrupt and write completion status on error */
 326         writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 327
 328         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 329         if (chanerr) {
 330                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
 331                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 332         }
 333
 334         /* Allocate descriptors */
 335         for (i = 0; i < ioat_initial_desc_count; i++) {
 336                 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
 337                 if (!desc) {
 338                         dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
 339                         break;
 340                 }
 341                 set_desc_id(desc, i);
 342                 list_add_tail(&desc->node, &tmp_list);
 343         }
 344         spin_lock_bh(&ioat->desc_lock);
 345         ioat->desccount = i;
 346         list_splice(&tmp_list, &ioat->free_desc);
 347         spin_unlock_bh(&ioat->desc_lock);
 348
 349         /* allocate a completion writeback area */
 350         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 351         chan->completion = pci_pool_alloc(chan->device->completion_pool,
 352                                           GFP_KERNEL, &chan->completion_dma);
 353         memset(chan->completion, 0, sizeof(*chan->completion));
 354         writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
 355                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 356         writel(((u64) chan->completion_dma) >> 32,
 357                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 358
 359         tasklet_enable(&chan->cleanup_task);
 360         ioat1_dma_start_null_desc(ioat);  /* give chain to dma device */
 361         dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
 362                 __func__, ioat->desccount);
 363         return ioat->desccount;
 364 }
 365
 366 /**
 367  * ioat1_dma_free_chan_resources - release all the descriptors
 368  * @chan: the channel to be cleaned
 369  */
 370 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
 371 {
 372         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 373         struct ioat_chan_common *chan = &ioat->base;
 374         struct ioatdma_device *ioatdma_device = chan->device;
 375         struct ioat_desc_sw *desc, *_desc;
 376         int in_use_descs = 0;
 377
 378         /* Before freeing channel resources first check
 379          * if they have been previously allocated for this channel.
 380          */
 381         if (ioat->desccount == 0)
 382                 return;
 383
 384         tasklet_disable(&chan->cleanup_task);
 385         del_timer_sync(&chan->timer);
 386         ioat1_cleanup(ioat);
 387
 388         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 389          * before removing DMA descriptor resources.
 390          */
 391         writeb(IOAT_CHANCMD_RESET,
 392                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 393         mdelay(100);
 394
 395         spin_lock_bh(&ioat->desc_lock);
 396         list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
 397                 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
 398                         __func__, desc_id(desc));
 399                 dump_desc_dbg(ioat, desc);
 400                 in_use_descs++;
 401                 list_del(&desc->node);
 402                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 403                               desc->txd.phys);
 404                 kfree(desc);
 405         }
 406         list_for_each_entry_safe(desc, _desc,
 407                                  &ioat->free_desc, node) {
 408                 list_del(&desc->node);
 409                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 410                               desc->txd.phys);
 411                 kfree(desc);
 412         }
 413         spin_unlock_bh(&ioat->desc_lock);
 414
 415         pci_pool_free(ioatdma_device->completion_pool,
 416                       chan->completion,
 417                       chan->completion_dma);
 418
 419         /* one is ok since we left it on there on purpose */
 420         if (in_use_descs > 1)
 421                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 422                         in_use_descs - 1);
 423
 424         chan->last_completion = 0;
 425         chan->completion_dma = 0;
 426         ioat->pending = 0;
 427         ioat->desccount = 0;
 428 }
 429
 430 /**
 431  * ioat1_dma_get_next_descriptor - return the next available descriptor
 432  * @ioat: IOAT DMA channel handle
 433  *
 434  * Gets the next descriptor from the chain, and must be called with the
 435  * channel's desc_lock held.  Allocates more descriptors if the channel
 436  * has run out.
 437  */
 438 static struct ioat_desc_sw *
 439 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
 440 {
 441         struct ioat_desc_sw *new;
 442
 443         if (!list_empty(&ioat->free_desc)) {
 444                 new = to_ioat_desc(ioat->free_desc.next);
 445                 list_del(&new->node);
 446         } else {
 447                 /* try to get another desc */
 448                 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
 449                 if (!new) {
 450                         dev_err(to_dev(&ioat->base), "alloc failed\n");
 451                         return NULL;
 452                 }
 453         }
 454         dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
 455                 __func__, desc_id(new));
 456         prefetch(new->hw);
 457         return new;
 458 }
 459
 460 static struct dma_async_tx_descriptor *
 461 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
 462                       dma_addr_t dma_src, size_t len, unsigned long flags)
 463 {
 464         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 465         struct ioat_desc_sw *desc;
 466         size_t copy;
 467         LIST_HEAD(chain);
 468         dma_addr_t src = dma_src;
 469         dma_addr_t dest = dma_dest;
 470         size_t total_len = len;
 471         struct ioat_dma_descriptor *hw = NULL;
 472         int tx_cnt = 0;
 473
 474         spin_lock_bh(&ioat->desc_lock);
 475         desc = ioat1_dma_get_next_descriptor(ioat);
 476         do {
 477                 if (!desc)
 478                         break;
 479
 480                 tx_cnt++;
 481                 copy = min_t(size_t, len, ioat->xfercap);
 482
 483                 hw = desc->hw;
 484                 hw->size = copy;
 485                 hw->ctl = 0;
 486                 hw->src_addr = src;
 487                 hw->dst_addr = dest;
 488
 489                 list_add_tail(&desc->node, &chain);
 490
 491                 len -= copy;
 492                 dest += copy;
 493                 src += copy;
 494                 if (len) {
 495                         struct ioat_desc_sw *next;
 496
 497                         async_tx_ack(&desc->txd);
 498                         next = ioat1_dma_get_next_descriptor(ioat);
 499                         hw->next = next ? next->txd.phys : 0;
 500                         dump_desc_dbg(ioat, desc);
 501                         desc = next;
 502                 } else
 503                         hw->next = 0;
 504         } while (len);
 505
 506         if (!desc) {
 507                 struct ioat_chan_common *chan = &ioat->base;
 508
 509                 dev_err(to_dev(chan),
 510                         "chan%d - get_next_desc failed\n", chan_num(chan));
 511                 list_splice(&chain, &ioat->free_desc);
 512                 spin_unlock_bh(&ioat->desc_lock);
 513                 return NULL;
 514         }
 515         spin_unlock_bh(&ioat->desc_lock);
 516
 517         desc->txd.flags = flags;
 518         desc->len = total_len;
 519         list_splice(&chain, &desc->tx_list);
 520         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 521         hw->ctl_f.compl_write = 1;
 522         hw->tx_cnt = tx_cnt;
 523         dump_desc_dbg(ioat, desc);
 524
 525         return &desc->txd;
 526 }
 527
 528 static void ioat1_cleanup_event(unsigned long data)
 529 {
 530         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 531
 532         ioat1_cleanup(ioat);
 533         writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
 534 }
 535
 536 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 537                     size_t len, struct ioat_dma_descriptor *hw)
 538 {
 539         struct pci_dev *pdev = chan->device->pdev;
 540         size_t offset = len - hw->size;
 541
 542         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
 543                 ioat_unmap(pdev, hw->dst_addr - offset, len,
 544                            PCI_DMA_FROMDEVICE, flags, 1);
 545
 546         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
 547                 ioat_unmap(pdev, hw->src_addr - offset, len,
 548                            PCI_DMA_TODEVICE, flags, 0);
 549 }
 550
 551 dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan)
 552 {
 553         dma_addr_t phys_complete;
 554         u64 completion;
 555
 556         completion = *chan->completion;
 557         phys_complete = ioat_chansts_to_addr(completion);
 558
 559         dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
 560                 (unsigned long long) phys_complete);
 561
 562         if (is_ioat_halted(completion)) {
 563                 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 564                 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
 565                         chanerr);
 566
 567                 /* TODO do something to salvage the situation */
 568         }
 569
 570         return phys_complete;
 571 }
 572
 573 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
 574                            dma_addr_t *phys_complete)
 575 {
 576         *phys_complete = ioat_get_current_completion(chan);
 577         if (*phys_complete == chan->last_completion)
 578                 return false;
 579         clear_bit(IOAT_COMPLETION_ACK, &chan->state);
 580         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 581
 582         return true;
 583 }
 584
 585 static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete)
 586 {
 587         struct ioat_chan_common *chan = &ioat->base;
 588         struct list_head *_desc, *n;
 589         struct dma_async_tx_descriptor *tx;
 590
 591         dev_dbg(to_dev(chan), "%s: phys_complete: %llx\n",
 592                  __func__, (unsigned long long) phys_complete);
 593         list_for_each_safe(_desc, n, &ioat->used_desc) {
 594                 struct ioat_desc_sw *desc;
 595
 596                 prefetch(n);
 597                 desc = list_entry(_desc, typeof(*desc), node);
 598                 tx = &desc->txd;
 599                 /*
 600                  * Incoming DMA requests may use multiple descriptors,
 601                  * due to exceeding xfercap, perhaps. If so, only the
 602                  * last one will have a cookie, and require unmapping.
 603                  */
 604                 dump_desc_dbg(ioat, desc);
 605                 if (tx->cookie) {
 606                         chan->completed_cookie = tx->cookie;
 607                         tx->cookie = 0;
 608                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 609                         ioat->active -= desc->hw->tx_cnt;
 610                         if (tx->callback) {
 611                                 tx->callback(tx->callback_param);
 612                                 tx->callback = NULL;
 613                         }
 614                 }
 615
 616                 if (tx->phys != phys_complete) {
 617                         /*
 618                          * a completed entry, but not the last, so clean
 619                          * up if the client is done with the descriptor
 620                          */
 621                         if (async_tx_test_ack(tx))
 622                                 list_move_tail(&desc->node, &ioat->free_desc);
 623                 } else {
 624                         /*
 625                          * last used desc. Do not remove, so we can
 626                          * append from it.
 627                          */
 628
 629                         /* if nothing else is pending, cancel the
 630                          * completion timeout
 631                          */
 632                         if (n == &ioat->used_desc) {
 633                                 dev_dbg(to_dev(chan),
 634                                         "%s cancel completion timeout\n",
 635                                         __func__);
 636                                 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
 637                         }
 638
 639                         /* TODO check status bits? */
 640                         break;
 641                 }
 642         }
 643
 644         chan->last_completion = phys_complete;
 645 }
 646
 647 /**
 648  * ioat1_cleanup - cleanup up finished descriptors
 649  * @chan: ioat channel to be cleaned up
 650  *
 651  * To prevent lock contention we defer cleanup when the locks are
 652  * contended with a terminal timeout that forces cleanup and catches
 653  * completion notification errors.
 654  */
 655 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
 656 {
 657         struct ioat_chan_common *chan = &ioat->base;
 658         dma_addr_t phys_complete;
 659
 660         prefetch(chan->completion);
 661
 662         if (!spin_trylock_bh(&chan->cleanup_lock))
 663                 return;
 664
 665         if (!ioat_cleanup_preamble(chan, &phys_complete)) {
 666                 spin_unlock_bh(&chan->cleanup_lock);
 667                 return;
 668         }
 669
 670         if (!spin_trylock_bh(&ioat->desc_lock)) {
 671                 spin_unlock_bh(&chan->cleanup_lock);
 672                 return;
 673         }
 674
 675         __cleanup(ioat, phys_complete);
 676
 677         spin_unlock_bh(&ioat->desc_lock);
 678         spin_unlock_bh(&chan->cleanup_lock);
 679 }
 680
 681 static void ioat1_timer_event(unsigned long data)
 682 {
 683         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 684         struct ioat_chan_common *chan = &ioat->base;
 685
 686         dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
 687
 688         spin_lock_bh(&chan->cleanup_lock);
 689         if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
 690                 struct ioat_desc_sw *desc;
 691
 692                 spin_lock_bh(&ioat->desc_lock);
 693
 694                 /* restart active descriptors */
 695                 desc = to_ioat_desc(ioat->used_desc.prev);
 696                 ioat_set_chainaddr(ioat, desc->txd.phys);
 697                 ioat_start(chan);
 698
 699                 ioat->pending = 0;
 700                 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
 701                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 702                 spin_unlock_bh(&ioat->desc_lock);
 703         } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
 704                 dma_addr_t phys_complete;
 705
 706                 spin_lock_bh(&ioat->desc_lock);
 707                 /* if we haven't made progress and we have already
 708                  * acknowledged a pending completion once, then be more
 709                  * forceful with a restart
 710                  */
 711                 if (ioat_cleanup_preamble(chan, &phys_complete))
 712                         __cleanup(ioat, phys_complete);
 713                 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
 714                         ioat1_reset_channel(ioat);
 715                 else {
 716                         u64 status = ioat_chansts(chan);
 717
 718                         /* manually update the last completion address */
 719                         if (ioat_chansts_to_addr(status) != 0)
 720                                 *chan->completion = status;
 721
 722                         set_bit(IOAT_COMPLETION_ACK, &chan->state);
 723                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 724                 }
 725                 spin_unlock_bh(&ioat->desc_lock);
 726         }
 727         spin_unlock_bh(&chan->cleanup_lock);
 728 }
 729
 730 enum dma_status
 731 ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 732                    struct dma_tx_state *txstate)
 733 {
 734         struct ioat_chan_common *chan = to_chan_common(c);
 735         struct ioatdma_device *device = chan->device;
 736
 737         if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
 738                 return DMA_SUCCESS;
 739
 740         device->cleanup_fn((unsigned long) c);
 741
 742         return ioat_tx_status(c, cookie, txstate);
 743 }
 744
 745 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
 746 {
 747         struct ioat_chan_common *chan = &ioat->base;
 748         struct ioat_desc_sw *desc;
 749         struct ioat_dma_descriptor *hw;
 750
 751         spin_lock_bh(&ioat->desc_lock);
 752
 753         desc = ioat1_dma_get_next_descriptor(ioat);
 754
 755         if (!desc) {
 756                 dev_err(to_dev(chan),
 757                         "Unable to start null desc - get next desc failed\n");
 758                 spin_unlock_bh(&ioat->desc_lock);
 759                 return;
 760         }
 761
 762         hw = desc->hw;
 763         hw->ctl = 0;
 764         hw->ctl_f.null = 1;
 765         hw->ctl_f.int_en = 1;
 766         hw->ctl_f.compl_write = 1;
 767         /* set size to non-zero value (channel returns error when size is 0) */
 768         hw->size = NULL_DESC_BUFFER_SIZE;
 769         hw->src_addr = 0;
 770         hw->dst_addr = 0;
 771         async_tx_ack(&desc->txd);
 772         hw->next = 0;
 773         list_add_tail(&desc->node, &ioat->used_desc);
 774         dump_desc_dbg(ioat, desc);
 775
 776         ioat_set_chainaddr(ioat, desc->txd.phys);
 777         ioat_start(chan);
 778         spin_unlock_bh(&ioat->desc_lock);
 779 }
 780
 781 /*
 782  * Perform a IOAT transaction to verify the HW works.
 783  */
 784 #define IOAT_TEST_SIZE 2000
 785
 786 static void __devinit ioat_dma_test_callback(void *dma_async_param)
 787 {
 788         struct completion *cmp = dma_async_param;
 789
 790         complete(cmp);
 791 }
 792
 793 /**
 794  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
 795  * @device: device to be tested
 796  */
 797 int __devinit ioat_dma_self_test(struct ioatdma_device *device)
 798 {
 799         int i;
 800         u8 *src;
 801         u8 *dest;
 802         struct dma_device *dma = &device->common;
 803         struct device *dev = &device->pdev->dev;
 804         struct dma_chan *dma_chan;
 805         struct dma_async_tx_descriptor *tx;
 806         dma_addr_t dma_dest, dma_src;
 807         dma_cookie_t cookie;
 808         int err = 0;
 809         struct completion cmp;
 810         unsigned long tmo;
 811         unsigned long flags;
 812
 813         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 814         if (!src)
 815                 return -ENOMEM;
 816         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 817         if (!dest) {
 818                 kfree(src);
 819                 return -ENOMEM;
 820         }
 821
 822         /* Fill in src buffer */
 823         for (i = 0; i < IOAT_TEST_SIZE; i++)
 824                 src[i] = (u8)i;
 825
 826         /* Start copy, using first DMA channel */
 827         dma_chan = container_of(dma->channels.next, struct dma_chan,
 828                                 device_node);
 829         if (dma->device_alloc_chan_resources(dma_chan) < 1) {
 830                 dev_err(dev, "selftest cannot allocate chan resource\n");
 831                 err = -ENODEV;
 832                 goto out;
 833         }
 834
 835         dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
 836         dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
 837         flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
 838                 DMA_PREP_INTERRUPT;
 839         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
 840                                                    IOAT_TEST_SIZE, flags);
 841         if (!tx) {
 842                 dev_err(dev, "Self-test prep failed, disabling\n");
 843                 err = -ENODEV;
 844                 goto free_resources;
 845         }
 846
 847         async_tx_ack(tx);
 848         init_completion(&cmp);
 849         tx->callback = ioat_dma_test_callback;
 850         tx->callback_param = &cmp;
 851         cookie = tx->tx_submit(tx);
 852         if (cookie < 0) {
 853                 dev_err(dev, "Self-test setup failed, disabling\n");
 854                 err = -ENODEV;
 855                 goto free_resources;
 856         }
 857         dma->device_issue_pending(dma_chan);
 858
 859         tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
 860
 861         if (tmo == 0 ||
 862             dma->device_tx_status(dma_chan, cookie, NULL)
 863                                         != DMA_SUCCESS) {
 864                 dev_err(dev, "Self-test copy timed out, disabling\n");
 865                 err = -ENODEV;
 866                 goto free_resources;
 867         }
 868         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
 869                 dev_err(dev, "Self-test copy failed compare, disabling\n");
 870                 err = -ENODEV;
 871                 goto free_resources;
 872         }
 873
 874 free_resources:
 875         dma->device_free_chan_resources(dma_chan);
 876 out:
 877         kfree(src);
 878         kfree(dest);
 879         return err;
 880 }
 881
 882 static char ioat_interrupt_style[32] = "msix";
 883 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
 884                     sizeof(ioat_interrupt_style), 0644);
 885 MODULE_PARM_DESC(ioat_interrupt_style,
 886                  "set ioat interrupt style: msix (default), "
 887                  "msix-single-vector, msi, intx)");
 888
 889 /**
 890  * ioat_dma_setup_interrupts - setup interrupt handler
 891  * @device: ioat device
 892  */
 893 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
 894 {
 895         struct ioat_chan_common *chan;
 896         struct pci_dev *pdev = device->pdev;
 897         struct device *dev = &pdev->dev;
 898         struct msix_entry *msix;
 899         int i, j, msixcnt;
 900         int err = -EINVAL;
 901         u8 intrctrl = 0;
 902
 903         if (!strcmp(ioat_interrupt_style, "msix"))
 904                 goto msix;
 905         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
 906                 goto msix_single_vector;
 907         if (!strcmp(ioat_interrupt_style, "msi"))
 908                 goto msi;
 909         if (!strcmp(ioat_interrupt_style, "intx"))
 910                 goto intx;
 911         dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
 912         goto err_no_irq;
 913
 914 msix:
 915         /* The number of MSI-X vectors should equal the number of channels */
 916         msixcnt = device->common.chancnt;
 917         for (i = 0; i < msixcnt; i++)
 918                 device->msix_entries[i].entry = i;
 919
 920         err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
 921         if (err < 0)
 922                 goto msi;
 923         if (err > 0)
 924                 goto msix_single_vector;
 925
 926         for (i = 0; i < msixcnt; i++) {
 927                 msix = &device->msix_entries[i];
 928                 chan = ioat_chan_by_index(device, i);
 929                 err = devm_request_irq(dev, msix->vector,
 930                                        ioat_dma_do_interrupt_msix, 0,
 931                                        "ioat-msix", chan);
 932                 if (err) {
 933                         for (j = 0; j < i; j++) {
 934                                 msix = &device->msix_entries[j];
 935                                 chan = ioat_chan_by_index(device, j);
 936                                 devm_free_irq(dev, msix->vector, chan);
 937                         }
 938                         goto msix_single_vector;
 939                 }
 940         }
 941         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
 942         goto done;
 943
 944 msix_single_vector:
 945         msix = &device->msix_entries[0];
 946         msix->entry = 0;
 947         err = pci_enable_msix(pdev, device->msix_entries, 1);
 948         if (err)
 949                 goto msi;
 950
 951         err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
 952                                "ioat-msix", device);
 953         if (err) {
 954                 pci_disable_msix(pdev);
 955                 goto msi;
 956         }
 957         goto done;
 958
 959 msi:
 960         err = pci_enable_msi(pdev);
 961         if (err)
 962                 goto intx;
 963
 964         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
 965                                "ioat-msi", device);
 966         if (err) {
 967                 pci_disable_msi(pdev);
 968                 goto intx;
 969         }
 970         goto done;
 971
 972 intx:
 973         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
 974                                IRQF_SHARED, "ioat-intx", device);
 975         if (err)
 976                 goto err_no_irq;
 977
 978 done:
 979         if (device->intr_quirk)
 980                 device->intr_quirk(device);
 981         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
 982         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
 983         return 0;
 984
 985 err_no_irq:
 986         /* Disable all interrupt generation */
 987         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
 988         dev_err(dev, "no usable interrupts\n");
 989         return err;
 990 }
 991
 992 static void ioat_disable_interrupts(struct ioatdma_device *device)
 993 {
 994         /* Disable all interrupt generation */
 995         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
 996 }
 997
 998 int __devinit ioat_probe(struct ioatdma_device *device)
 999 {
1000         int err = -ENODEV;
1001         struct dma_device *dma = &device->common;
1002         struct pci_dev *pdev = device->pdev;
1003         struct device *dev = &pdev->dev;
1004
1005         /* DMA coherent memory pool for DMA descriptor allocations */
1006         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1007                                            sizeof(struct ioat_dma_descriptor),
1008                                            64, 0);
1009         if (!device->dma_pool) {
1010                 err = -ENOMEM;
1011                 goto err_dma_pool;
1012         }
1013
1014         device->completion_pool = pci_pool_create("completion_pool", pdev,
1015                                                   sizeof(u64), SMP_CACHE_BYTES,
1016                                                   SMP_CACHE_BYTES);
1017
1018         if (!device->completion_pool) {
1019                 err = -ENOMEM;
1020                 goto err_completion_pool;
1021         }
1022
1023         device->enumerate_channels(device);
1024
1025         dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1026         dma->dev = &pdev->dev;
1027
1028         if (!dma->chancnt) {
1029                 dev_err(dev, "channel enumeration error\n");
1030                 goto err_setup_interrupts;
1031         }
1032
1033         err = ioat_dma_setup_interrupts(device);
1034         if (err)
1035                 goto err_setup_interrupts;
1036
1037         err = device->self_test(device);
1038         if (err)
1039                 goto err_self_test;
1040
1041         return 0;
1042
1043 err_self_test:
1044         ioat_disable_interrupts(device);
1045 err_setup_interrupts:
1046         pci_pool_destroy(device->completion_pool);
1047 err_completion_pool:
1048         pci_pool_destroy(device->dma_pool);
1049 err_dma_pool:
1050         return err;
1051 }
1052
1053 int __devinit ioat_register(struct ioatdma_device *device)
1054 {
1055         int err = dma_async_device_register(&device->common);
1056
1057         if (err) {
1058                 ioat_disable_interrupts(device);
1059                 pci_pool_destroy(device->completion_pool);
1060                 pci_pool_destroy(device->dma_pool);
1061         }
1062
1063         return err;
1064 }
1065
1066 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1067 static void ioat1_intr_quirk(struct ioatdma_device *device)
1068 {
1069         struct pci_dev *pdev = device->pdev;
1070         u32 dmactrl;
1071
1072         pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1073         if (pdev->msi_enabled)
1074                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1075         else
1076                 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1077         pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1078 }
1079
1080 static ssize_t ring_size_show(struct dma_chan *c, char *page)
1081 {
1082         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1083
1084         return sprintf(page, "%d\n", ioat->desccount);
1085 }
1086 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1087
1088 static ssize_t ring_active_show(struct dma_chan *c, char *page)
1089 {
1090         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1091
1092         return sprintf(page, "%d\n", ioat->active);
1093 }
1094 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1095
1096 static ssize_t cap_show(struct dma_chan *c, char *page)
1097 {
1098         struct dma_device *dma = c->device;
1099
1100         return sprintf(page, "copy%s%s%s%s%s%s\n",
1101                        dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1102                        dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1103                        dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1104                        dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
1105                        dma_has_cap(DMA_MEMSET, dma->cap_mask)  ? " fill" : "",
1106                        dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1107
1108 }
1109 struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1110
1111 static ssize_t version_show(struct dma_chan *c, char *page)
1112 {
1113         struct dma_device *dma = c->device;
1114         struct ioatdma_device *device = to_ioatdma_device(dma);
1115
1116         return sprintf(page, "%d.%d\n",
1117                        device->version >> 4, device->version & 0xf);
1118 }
1119 struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1120
1121 static struct attribute *ioat1_attrs[] = {
1122         &ring_size_attr.attr,
1123         &ring_active_attr.attr,
1124         &ioat_cap_attr.attr,
1125         &ioat_version_attr.attr,
1126         NULL,
1127 };
1128
1129 static ssize_t
1130 ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1131 {
1132         struct ioat_sysfs_entry *entry;
1133         struct ioat_chan_common *chan;
1134
1135         entry = container_of(attr, struct ioat_sysfs_entry, attr);
1136         chan = container_of(kobj, struct ioat_chan_common, kobj);
1137
1138         if (!entry->show)
1139                 return -EIO;
1140         return entry->show(&chan->common, page);
1141 }
1142
1143 const struct sysfs_ops ioat_sysfs_ops = {
1144         .show   = ioat_attr_show,
1145 };
1146
1147 static struct kobj_type ioat1_ktype = {
1148         .sysfs_ops = &ioat_sysfs_ops,
1149         .default_attrs = ioat1_attrs,
1150 };
1151
1152 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1153 {
1154         struct dma_device *dma = &device->common;
1155         struct dma_chan *c;
1156
1157         list_for_each_entry(c, &dma->channels, device_node) {
1158                 struct ioat_chan_common *chan = to_chan_common(c);
1159                 struct kobject *parent = &c->dev->device.kobj;
1160                 int err;
1161
1162                 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1163                 if (err) {
1164                         dev_warn(to_dev(chan),
1165                                  "sysfs init error (%d), continuing...\n", err);
1166                         kobject_put(&chan->kobj);
1167                         set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1168                 }
1169         }
1170 }
1171
1172 void ioat_kobject_del(struct ioatdma_device *device)
1173 {
1174         struct dma_device *dma = &device->common;
1175         struct dma_chan *c;
1176
1177         list_for_each_entry(c, &dma->channels, device_node) {
1178                 struct ioat_chan_common *chan = to_chan_common(c);
1179
1180                 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1181                         kobject_del(&chan->kobj);
1182                         kobject_put(&chan->kobj);
1183                 }
1184         }
1185 }
1186
1187 int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1188 {
1189         struct pci_dev *pdev = device->pdev;
1190         struct dma_device *dma;
1191         int err;
1192
1193         device->intr_quirk = ioat1_intr_quirk;
1194         device->enumerate_channels = ioat1_enumerate_channels;
1195         device->self_test = ioat_dma_self_test;
1196         device->timer_fn = ioat1_timer_event;
1197         device->cleanup_fn = ioat1_cleanup_event;
1198         dma = &device->common;
1199         dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1200         dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1201         dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1202         dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1203         dma->device_tx_status = ioat_dma_tx_status;
1204
1205         err = ioat_probe(device);
1206         if (err)
1207                 return err;
1208         ioat_set_tcp_copy_break(4096);
1209         err = ioat_register(device);
1210         if (err)
1211                 return err;
1212         ioat_kobject_add(device, &ioat1_ktype);
1213
1214         if (dca)
1215                 device->dca = ioat_dca_init(pdev, device->reg_base);
1216
1217         return err;
1218 }
1219
1220 void __devexit ioat_dma_remove(struct ioatdma_device *device)
1221 {
1222         struct dma_device *dma = &device->common;
1223
1224         ioat_disable_interrupts(device);
1225
1226         ioat_kobject_del(device);
1227
1228         dma_async_device_unregister(dma);
1229
1230         pci_pool_destroy(device->dma_pool);
1231         pci_pool_destroy(device->completion_pool);
1232
1233         INIT_LIST_HEAD(&dma->channels);
1234 }