drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/serial_reg.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/dmi.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/pch_dma.h>
  31
  32 enum {
  33         PCH_UART_HANDLED_RX_INT_SHIFT,
  34         PCH_UART_HANDLED_TX_INT_SHIFT,
  35         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  36         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  37         PCH_UART_HANDLED_MS_INT_SHIFT,
  38 };
  39
  40 enum {
  41         PCH_UART_8LINE,
  42         PCH_UART_2LINE,
  43 };
  44
  45 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  46
  47 /* Set the max number of UART port
  48  * Intel EG20T PCH: 4 port
  49  * OKI SEMICONDUCTOR ML7213 IOH: 3 port
  50  * OKI SEMICONDUCTOR ML7223 IOH: 2 port
  51 */
  52 #define PCH_UART_NR     4
  53
  54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  56 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  57                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  58 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  59                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  61
  62 #define PCH_UART_RBR            0x00
  63 #define PCH_UART_THR            0x00
  64
  65 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  66                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  67 #define PCH_UART_IER_ERBFI      0x00000001
  68 #define PCH_UART_IER_ETBEI      0x00000002
  69 #define PCH_UART_IER_ELSI       0x00000004
  70 #define PCH_UART_IER_EDSSI      0x00000008
  71
  72 #define PCH_UART_IIR_IP                 0x00000001
  73 #define PCH_UART_IIR_IID                0x00000006
  74 #define PCH_UART_IIR_MSI                0x00000000
  75 #define PCH_UART_IIR_TRI                0x00000002
  76 #define PCH_UART_IIR_RRI                0x00000004
  77 #define PCH_UART_IIR_REI                0x00000006
  78 #define PCH_UART_IIR_TOI                0x00000008
  79 #define PCH_UART_IIR_FIFO256            0x00000020
  80 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  81 #define PCH_UART_IIR_FE                 0x000000C0
  82
  83 #define PCH_UART_FCR_FIFOE              0x00000001
  84 #define PCH_UART_FCR_RFR                0x00000002
  85 #define PCH_UART_FCR_TFR                0x00000004
  86 #define PCH_UART_FCR_DMS                0x00000008
  87 #define PCH_UART_FCR_FIFO256            0x00000020
  88 #define PCH_UART_FCR_RFTL               0x000000C0
  89
  90 #define PCH_UART_FCR_RFTL1              0x00000000
  91 #define PCH_UART_FCR_RFTL64             0x00000040
  92 #define PCH_UART_FCR_RFTL128            0x00000080
  93 #define PCH_UART_FCR_RFTL224            0x000000C0
  94 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  95 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  96 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  97 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  98 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  99 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 100 #define PCH_UART_FCR_RFTL_SHIFT         6
 101
 102 #define PCH_UART_LCR_WLS        0x00000003
 103 #define PCH_UART_LCR_STB        0x00000004
 104 #define PCH_UART_LCR_PEN        0x00000008
 105 #define PCH_UART_LCR_EPS        0x00000010
 106 #define PCH_UART_LCR_SP         0x00000020
 107 #define PCH_UART_LCR_SB         0x00000040
 108 #define PCH_UART_LCR_DLAB       0x00000080
 109 #define PCH_UART_LCR_NP         0x00000000
 110 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 111 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 112 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 113 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 114                                 PCH_UART_LCR_SP)
 115
 116 #define PCH_UART_LCR_5BIT       0x00000000
 117 #define PCH_UART_LCR_6BIT       0x00000001
 118 #define PCH_UART_LCR_7BIT       0x00000002
 119 #define PCH_UART_LCR_8BIT       0x00000003
 120
 121 #define PCH_UART_MCR_DTR        0x00000001
 122 #define PCH_UART_MCR_RTS        0x00000002
 123 #define PCH_UART_MCR_OUT        0x0000000C
 124 #define PCH_UART_MCR_LOOP       0x00000010
 125 #define PCH_UART_MCR_AFE        0x00000020
 126
 127 #define PCH_UART_LSR_DR         0x00000001
 128 #define PCH_UART_LSR_ERR        (1<<7)
 129
 130 #define PCH_UART_MSR_DCTS       0x00000001
 131 #define PCH_UART_MSR_DDSR       0x00000002
 132 #define PCH_UART_MSR_TERI       0x00000004
 133 #define PCH_UART_MSR_DDCD       0x00000008
 134 #define PCH_UART_MSR_CTS        0x00000010
 135 #define PCH_UART_MSR_DSR        0x00000020
 136 #define PCH_UART_MSR_RI         0x00000040
 137 #define PCH_UART_MSR_DCD        0x00000080
 138 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 139                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 140
 141 #define PCH_UART_DLL            0x00
 142 #define PCH_UART_DLM            0x01
 143
 144 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 145 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 146 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 147 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 148 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 149
 150 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 151 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 152 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 153 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 154 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 155 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 156 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 157 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 158 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 159 #define PCH_UART_HAL_STB1               0
 160 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 161
 162 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 163 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 164 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 165                                         PCH_UART_HAL_CLR_RX_FIFO)
 166
 167 #define PCH_UART_HAL_DMA_MODE0          0
 168 #define PCH_UART_HAL_FIFO_DIS           0
 169 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 170 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 171                                         PCH_UART_FCR_FIFO256)
 172 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 173 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 174 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 175 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 176 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 177 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 178 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 179 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 180 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 181 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 182 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 183 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 184 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 185 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 186
 187 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 188 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 189 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 190 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 191 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 192
 193 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 194 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 195 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 196 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 197 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 198
 199 #define PCI_VENDOR_ID_ROHM              0x10DB
 200
 201 struct pch_uart_buffer {
 202         unsigned char *buf;
 203         int size;
 204 };
 205
 206 struct eg20t_port {
 207         struct uart_port port;
 208         int port_type;
 209         void __iomem *membase;
 210         resource_size_t mapbase;
 211         unsigned int iobase;
 212         struct pci_dev *pdev;
 213         int fifo_size;
 214         int base_baud;
 215         int start_tx;
 216         int start_rx;
 217         int tx_empty;
 218         int int_dis_flag;
 219         int trigger;
 220         int trigger_level;
 221         struct pch_uart_buffer rxbuf;
 222         unsigned int dmsr;
 223         unsigned int fcr;
 224         unsigned int mcr;
 225         unsigned int use_dma;
 226         unsigned int use_dma_flag;
 227         struct dma_async_tx_descriptor  *desc_tx;
 228         struct dma_async_tx_descriptor  *desc_rx;
 229         struct pch_dma_slave            param_tx;
 230         struct pch_dma_slave            param_rx;
 231         struct dma_chan                 *chan_tx;
 232         struct dma_chan                 *chan_rx;
 233         struct scatterlist              *sg_tx_p;
 234         int                             nent;
 235         struct scatterlist              sg_rx;
 236         int                             tx_dma_use;
 237         void                            *rx_buf_virt;
 238         dma_addr_t                      rx_buf_dma;
 239 };
 240
 241 /**
 242  * struct pch_uart_driver_data - private data structure for UART-DMA
 243  * @port_type:                  The number of DMA channel
 244  * @line_no:                    UART port line number (0, 1, 2...)
 245  */
 246 struct pch_uart_driver_data {
 247         int port_type;
 248         int line_no;
 249 };
 250
 251 enum pch_uart_num_t {
 252         pch_et20t_uart0 = 0,
 253         pch_et20t_uart1,
 254         pch_et20t_uart2,
 255         pch_et20t_uart3,
 256         pch_ml7213_uart0,
 257         pch_ml7213_uart1,
 258         pch_ml7213_uart2,
 259         pch_ml7223_uart0,
 260         pch_ml7223_uart1,
 261 };
 262
 263 static struct pch_uart_driver_data drv_dat[] = {
 264         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 265         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 266         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 267         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 268         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 269         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 270         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 271         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 272         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 273 };
 274
 275 static unsigned int default_baud = 9600;
 276 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 277 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 278 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 279 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 280
 281 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 282                                  int base_baud)
 283 {
 284         struct eg20t_port *priv = pci_get_drvdata(pdev);
 285
 286         priv->trigger_level = 1;
 287         priv->fcr = 0;
 288 }
 289
 290 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 291 {
 292         unsigned int msr = ioread8(base + UART_MSR);
 293         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 294
 295         return msr;
 296 }
 297
 298 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 299                                           unsigned int flag)
 300 {
 301         u8 ier = ioread8(priv->membase + UART_IER);
 302         ier |= flag & PCH_UART_IER_MASK;
 303         iowrite8(ier, priv->membase + UART_IER);
 304 }
 305
 306 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 307                                            unsigned int flag)
 308 {
 309         u8 ier = ioread8(priv->membase + UART_IER);
 310         ier &= ~(flag & PCH_UART_IER_MASK);
 311         iowrite8(ier, priv->membase + UART_IER);
 312 }
 313
 314 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 315                                  unsigned int parity, unsigned int bits,
 316                                  unsigned int stb)
 317 {
 318         unsigned int dll, dlm, lcr;
 319         int div;
 320
 321         div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
 322         if (div < 0 || USHRT_MAX <= div) {
 323                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 324                 return -EINVAL;
 325         }
 326
 327         dll = (unsigned int)div & 0x00FFU;
 328         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 329
 330         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 331                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 332                 return -EINVAL;
 333         }
 334
 335         if (bits & ~PCH_UART_LCR_WLS) {
 336                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 337                 return -EINVAL;
 338         }
 339
 340         if (stb & ~PCH_UART_LCR_STB) {
 341                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 342                 return -EINVAL;
 343         }
 344
 345         lcr = parity;
 346         lcr |= bits;
 347         lcr |= stb;
 348
 349         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 350                  __func__, baud, div, lcr, jiffies);
 351         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 352         iowrite8(dll, priv->membase + PCH_UART_DLL);
 353         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 354         iowrite8(lcr, priv->membase + UART_LCR);
 355
 356         return 0;
 357 }
 358
 359 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 360                                     unsigned int flag)
 361 {
 362         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 363                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 364                         __func__, flag);
 365                 return -EINVAL;
 366         }
 367
 368         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 369         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 370                  priv->membase + UART_FCR);
 371         iowrite8(priv->fcr, priv->membase + UART_FCR);
 372
 373         return 0;
 374 }
 375
 376 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 377                                  unsigned int dmamode,
 378                                  unsigned int fifo_size, unsigned int trigger)
 379 {
 380         u8 fcr;
 381
 382         if (dmamode & ~PCH_UART_FCR_DMS) {
 383                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 384                         __func__, dmamode);
 385                 return -EINVAL;
 386         }
 387
 388         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 389                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 390                         __func__, fifo_size);
 391                 return -EINVAL;
 392         }
 393
 394         if (trigger & ~PCH_UART_FCR_RFTL) {
 395                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 396                         __func__, trigger);
 397                 return -EINVAL;
 398         }
 399
 400         switch (priv->fifo_size) {
 401         case 256:
 402                 priv->trigger_level =
 403                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 404                 break;
 405         case 64:
 406                 priv->trigger_level =
 407                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 408                 break;
 409         case 16:
 410                 priv->trigger_level =
 411                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 412                 break;
 413         default:
 414                 priv->trigger_level =
 415                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 416                 break;
 417         }
 418         fcr =
 419             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 420         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 421         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 422                  priv->membase + UART_FCR);
 423         iowrite8(fcr, priv->membase + UART_FCR);
 424         priv->fcr = fcr;
 425
 426         return 0;
 427 }
 428
 429 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 430 {
 431         priv->dmsr = 0;
 432         return get_msr(priv, priv->membase);
 433 }
 434
 435 static void pch_uart_hal_write(struct eg20t_port *priv,
 436                               const unsigned char *buf, int tx_size)
 437 {
 438         int i;
 439         unsigned int thr;
 440
 441         for (i = 0; i < tx_size;) {
 442                 thr = buf[i++];
 443                 iowrite8(thr, priv->membase + PCH_UART_THR);
 444         }
 445 }
 446
 447 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 448                              int rx_size)
 449 {
 450         int i;
 451         u8 rbr, lsr;
 452
 453         lsr = ioread8(priv->membase + UART_LSR);
 454         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 455              i < rx_size && lsr & UART_LSR_DR;
 456              lsr = ioread8(priv->membase + UART_LSR)) {
 457                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 458                 buf[i++] = rbr;
 459         }
 460         return i;
 461 }
 462
 463 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 464 {
 465         unsigned int iir;
 466         int ret;
 467
 468         iir = ioread8(priv->membase + UART_IIR);
 469         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 470         return ret;
 471 }
 472
 473 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 474 {
 475         return ioread8(priv->membase + UART_LSR);
 476 }
 477
 478 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 479 {
 480         unsigned int lcr;
 481
 482         lcr = ioread8(priv->membase + UART_LCR);
 483         if (on)
 484                 lcr |= PCH_UART_LCR_SB;
 485         else
 486                 lcr &= ~PCH_UART_LCR_SB;
 487
 488         iowrite8(lcr, priv->membase + UART_LCR);
 489 }
 490
 491 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 492                    int size)
 493 {
 494         struct uart_port *port;
 495         struct tty_struct *tty;
 496
 497         port = &priv->port;
 498         tty = tty_port_tty_get(&port->state->port);
 499         if (!tty) {
 500                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 501                 return -EBUSY;
 502         }
 503
 504         tty_insert_flip_string(tty, buf, size);
 505         tty_flip_buffer_push(tty);
 506         tty_kref_put(tty);
 507
 508         return 0;
 509 }
 510
 511 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 512 {
 513         int ret;
 514         struct uart_port *port = &priv->port;
 515
 516         if (port->x_char) {
 517                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 518                         __func__, port->x_char, jiffies);
 519                 buf[0] = port->x_char;
 520                 port->x_char = 0;
 521                 ret = 1;
 522         } else {
 523                 ret = 0;
 524         }
 525
 526         return ret;
 527 }
 528
 529 static int dma_push_rx(struct eg20t_port *priv, int size)
 530 {
 531         struct tty_struct *tty;
 532         int room;
 533         struct uart_port *port = &priv->port;
 534
 535         port = &priv->port;
 536         tty = tty_port_tty_get(&port->state->port);
 537         if (!tty) {
 538                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 539                 return 0;
 540         }
 541
 542         room = tty_buffer_request_room(tty, size);
 543
 544         if (room < size)
 545                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 546                          size - room);
 547         if (!room)
 548                 return room;
 549
 550         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 551
 552         port->icount.rx += room;
 553         tty_kref_put(tty);
 554
 555         return room;
 556 }
 557
 558 static void pch_free_dma(struct uart_port *port)
 559 {
 560         struct eg20t_port *priv;
 561         priv = container_of(port, struct eg20t_port, port);
 562
 563         if (priv->chan_tx) {
 564                 dma_release_channel(priv->chan_tx);
 565                 priv->chan_tx = NULL;
 566         }
 567         if (priv->chan_rx) {
 568                 dma_release_channel(priv->chan_rx);
 569                 priv->chan_rx = NULL;
 570         }
 571         if (sg_dma_address(&priv->sg_rx))
 572                 dma_free_coherent(port->dev, port->fifosize,
 573                                   sg_virt(&priv->sg_rx),
 574                                   sg_dma_address(&priv->sg_rx));
 575
 576         return;
 577 }
 578
 579 static bool filter(struct dma_chan *chan, void *slave)
 580 {
 581         struct pch_dma_slave *param = slave;
 582
 583         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 584                                                   chan->device->dev)) {
 585                 chan->private = param;
 586                 return true;
 587         } else {
 588                 return false;
 589         }
 590 }
 591
 592 static void pch_request_dma(struct uart_port *port)
 593 {
 594         dma_cap_mask_t mask;
 595         struct dma_chan *chan;
 596         struct pci_dev *dma_dev;
 597         struct pch_dma_slave *param;
 598         struct eg20t_port *priv =
 599                                 container_of(port, struct eg20t_port, port);
 600         dma_cap_zero(mask);
 601         dma_cap_set(DMA_SLAVE, mask);
 602
 603         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 604                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 605                                                                 information */
 606         /* Set Tx DMA */
 607         param = &priv->param_tx;
 608         param->dma_dev = &dma_dev->dev;
 609         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 610
 611         param->tx_reg = port->mapbase + UART_TX;
 612         chan = dma_request_channel(mask, filter, param);
 613         if (!chan) {
 614                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 615                         __func__);
 616                 return;
 617         }
 618         priv->chan_tx = chan;
 619
 620         /* Set Rx DMA */
 621         param = &priv->param_rx;
 622         param->dma_dev = &dma_dev->dev;
 623         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 624
 625         param->rx_reg = port->mapbase + UART_RX;
 626         chan = dma_request_channel(mask, filter, param);
 627         if (!chan) {
 628                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 629                         __func__);
 630                 dma_release_channel(priv->chan_tx);
 631                 return;
 632         }
 633
 634         /* Get Consistent memory for DMA */
 635         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 636                                     &priv->rx_buf_dma, GFP_KERNEL);
 637         priv->chan_rx = chan;
 638 }
 639
 640 static void pch_dma_rx_complete(void *arg)
 641 {
 642         struct eg20t_port *priv = arg;
 643         struct uart_port *port = &priv->port;
 644         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 645         int count;
 646
 647         if (!tty) {
 648                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 649                 return;
 650         }
 651
 652         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 653         count = dma_push_rx(priv, priv->trigger_level);
 654         if (count)
 655                 tty_flip_buffer_push(tty);
 656         tty_kref_put(tty);
 657         async_tx_ack(priv->desc_rx);
 658         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
 659 }
 660
 661 static void pch_dma_tx_complete(void *arg)
 662 {
 663         struct eg20t_port *priv = arg;
 664         struct uart_port *port = &priv->port;
 665         struct circ_buf *xmit = &port->state->xmit;
 666         struct scatterlist *sg = priv->sg_tx_p;
 667         int i;
 668
 669         for (i = 0; i < priv->nent; i++, sg++) {
 670                 xmit->tail += sg_dma_len(sg);
 671                 port->icount.tx += sg_dma_len(sg);
 672         }
 673         xmit->tail &= UART_XMIT_SIZE - 1;
 674         async_tx_ack(priv->desc_tx);
 675         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 676         priv->tx_dma_use = 0;
 677         priv->nent = 0;
 678         kfree(priv->sg_tx_p);
 679         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 680 }
 681
 682 static int pop_tx(struct eg20t_port *priv, int size)
 683 {
 684         int count = 0;
 685         struct uart_port *port = &priv->port;
 686         struct circ_buf *xmit = &port->state->xmit;
 687
 688         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 689                 goto pop_tx_end;
 690
 691         do {
 692                 int cnt_to_end =
 693                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 694                 int sz = min(size - count, cnt_to_end);
 695                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 696                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 697                 count += sz;
 698         } while (!uart_circ_empty(xmit) && count < size);
 699
 700 pop_tx_end:
 701         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 702                  count, size - count, jiffies);
 703
 704         return count;
 705 }
 706
 707 static int handle_rx_to(struct eg20t_port *priv)
 708 {
 709         struct pch_uart_buffer *buf;
 710         int rx_size;
 711         int ret;
 712         if (!priv->start_rx) {
 713                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 714                 return 0;
 715         }
 716         buf = &priv->rxbuf;
 717         do {
 718                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 719                 ret = push_rx(priv, buf->buf, rx_size);
 720                 if (ret)
 721                         return 0;
 722         } while (rx_size == buf->size);
 723
 724         return PCH_UART_HANDLED_RX_INT;
 725 }
 726
 727 static int handle_rx(struct eg20t_port *priv)
 728 {
 729         return handle_rx_to(priv);
 730 }
 731
 732 static int dma_handle_rx(struct eg20t_port *priv)
 733 {
 734         struct uart_port *port = &priv->port;
 735         struct dma_async_tx_descriptor *desc;
 736         struct scatterlist *sg;
 737
 738         priv = container_of(port, struct eg20t_port, port);
 739         sg = &priv->sg_rx;
 740
 741         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 742
 743         sg_dma_len(sg) = priv->trigger_level;
 744
 745         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 746                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 747                      ~PAGE_MASK);
 748
 749         sg_dma_address(sg) = priv->rx_buf_dma;
 750
 751         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 752                         sg, 1, DMA_FROM_DEVICE,
 753                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 754
 755         if (!desc)
 756                 return 0;
 757
 758         priv->desc_rx = desc;
 759         desc->callback = pch_dma_rx_complete;
 760         desc->callback_param = priv;
 761         desc->tx_submit(desc);
 762         dma_async_issue_pending(priv->chan_rx);
 763
 764         return PCH_UART_HANDLED_RX_INT;
 765 }
 766
 767 static unsigned int handle_tx(struct eg20t_port *priv)
 768 {
 769         struct uart_port *port = &priv->port;
 770         struct circ_buf *xmit = &port->state->xmit;
 771         int fifo_size;
 772         int tx_size;
 773         int size;
 774         int tx_empty;
 775
 776         if (!priv->start_tx) {
 777                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 778                         __func__, jiffies);
 779                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 780                 priv->tx_empty = 1;
 781                 return 0;
 782         }
 783
 784         fifo_size = max(priv->fifo_size, 1);
 785         tx_empty = 1;
 786         if (pop_tx_x(priv, xmit->buf)) {
 787                 pch_uart_hal_write(priv, xmit->buf, 1);
 788                 port->icount.tx++;
 789                 tx_empty = 0;
 790                 fifo_size--;
 791         }
 792         size = min(xmit->head - xmit->tail, fifo_size);
 793         if (size < 0)
 794                 size = fifo_size;
 795
 796         tx_size = pop_tx(priv, size);
 797         if (tx_size > 0) {
 798                 port->icount.tx += tx_size;
 799                 tx_empty = 0;
 800         }
 801
 802         priv->tx_empty = tx_empty;
 803
 804         if (tx_empty) {
 805                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 806                 uart_write_wakeup(port);
 807         }
 808
 809         return PCH_UART_HANDLED_TX_INT;
 810 }
 811
 812 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 813 {
 814         struct uart_port *port = &priv->port;
 815         struct circ_buf *xmit = &port->state->xmit;
 816         struct scatterlist *sg;
 817         int nent;
 818         int fifo_size;
 819         int tx_empty;
 820         struct dma_async_tx_descriptor *desc;
 821         int num;
 822         int i;
 823         int bytes;
 824         int size;
 825         int rem;
 826
 827         if (!priv->start_tx) {
 828                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 829                         __func__, jiffies);
 830                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 831                 priv->tx_empty = 1;
 832                 return 0;
 833         }
 834
 835         if (priv->tx_dma_use) {
 836                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 837                         __func__, jiffies);
 838                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 839                 priv->tx_empty = 1;
 840                 return 0;
 841         }
 842
 843         fifo_size = max(priv->fifo_size, 1);
 844         tx_empty = 1;
 845         if (pop_tx_x(priv, xmit->buf)) {
 846                 pch_uart_hal_write(priv, xmit->buf, 1);
 847                 port->icount.tx++;
 848                 tx_empty = 0;
 849                 fifo_size--;
 850         }
 851
 852         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 853                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 854                              xmit->tail, UART_XMIT_SIZE));
 855         if (!bytes) {
 856                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 857                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 858                 uart_write_wakeup(port);
 859                 return 0;
 860         }
 861
 862         if (bytes > fifo_size) {
 863                 num = bytes / fifo_size + 1;
 864                 size = fifo_size;
 865                 rem = bytes % fifo_size;
 866         } else {
 867                 num = 1;
 868                 size = bytes;
 869                 rem = bytes;
 870         }
 871
 872         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 873                 __func__, num, size, rem);
 874
 875         priv->tx_dma_use = 1;
 876
 877         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 878
 879         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 880         sg = priv->sg_tx_p;
 881
 882         for (i = 0; i < num; i++, sg++) {
 883                 if (i == (num - 1))
 884                         sg_set_page(sg, virt_to_page(xmit->buf),
 885                                     rem, fifo_size * i);
 886                 else
 887                         sg_set_page(sg, virt_to_page(xmit->buf),
 888                                     size, fifo_size * i);
 889         }
 890
 891         sg = priv->sg_tx_p;
 892         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 893         if (!nent) {
 894                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 895                 return 0;
 896         }
 897         priv->nent = nent;
 898
 899         for (i = 0; i < nent; i++, sg++) {
 900                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 901                               fifo_size * i;
 902                 sg_dma_address(sg) = (sg_dma_address(sg) &
 903                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 904                 if (i == (nent - 1))
 905                         sg_dma_len(sg) = rem;
 906                 else
 907                         sg_dma_len(sg) = size;
 908         }
 909
 910         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 911                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 912                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 913         if (!desc) {
 914                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
 915                         __func__);
 916                 return 0;
 917         }
 918         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 919         priv->desc_tx = desc;
 920         desc->callback = pch_dma_tx_complete;
 921         desc->callback_param = priv;
 922
 923         desc->tx_submit(desc);
 924
 925         dma_async_issue_pending(priv->chan_tx);
 926
 927         return PCH_UART_HANDLED_TX_INT;
 928 }
 929
 930 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 931 {
 932         u8 fcr = ioread8(priv->membase + UART_FCR);
 933
 934         /* Reset FIFO */
 935         fcr |= UART_FCR_CLEAR_RCVR;
 936         iowrite8(fcr, priv->membase + UART_FCR);
 937
 938         if (lsr & PCH_UART_LSR_ERR)
 939                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 940
 941         if (lsr & UART_LSR_FE)
 942                 dev_err(&priv->pdev->dev, "Framing Error\n");
 943
 944         if (lsr & UART_LSR_PE)
 945                 dev_err(&priv->pdev->dev, "Parity Error\n");
 946
 947         if (lsr & UART_LSR_OE)
 948                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 949 }
 950
 951 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 952 {
 953         struct eg20t_port *priv = dev_id;
 954         unsigned int handled;
 955         u8 lsr;
 956         int ret = 0;
 957         unsigned int iid;
 958         unsigned long flags;
 959
 960         spin_lock_irqsave(&priv->port.lock, flags);
 961         handled = 0;
 962         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 963                 switch (iid) {
 964                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 965                         lsr = pch_uart_hal_get_line_status(priv);
 966                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 967                                                 UART_LSR_PE | UART_LSR_OE)) {
 968                                 pch_uart_err_ir(priv, lsr);
 969                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 970                         }
 971                         break;
 972                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 973                         if (priv->use_dma) {
 974                                 pch_uart_hal_disable_interrupt(priv,
 975                                                         PCH_UART_HAL_RX_INT);
 976                                 ret = dma_handle_rx(priv);
 977                                 if (!ret)
 978                                         pch_uart_hal_enable_interrupt(priv,
 979                                                         PCH_UART_HAL_RX_INT);
 980                         } else {
 981                                 ret = handle_rx(priv);
 982                         }
 983                         break;
 984                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 985                                                    (FIFO Timeout) */
 986                         ret = handle_rx_to(priv);
 987                         break;
 988                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
 989                                                    Empty */
 990                         if (priv->use_dma)
 991                                 ret = dma_handle_tx(priv);
 992                         else
 993                                 ret = handle_tx(priv);
 994                         break;
 995                 case PCH_UART_IID_MS:   /* Modem Status */
 996                         ret = PCH_UART_HANDLED_MS_INT;
 997                         break;
 998                 default:        /* Never junp to this label */
 999                         dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1000                                 iid, jiffies);
1001                         ret = -1;
1002                         break;
1003                 }
1004                 handled |= (unsigned int)ret;
1005         }
1006         if (handled == 0 && iid <= 1) {
1007                 if (priv->int_dis_flag)
1008                         priv->int_dis_flag = 0;
1009         }
1010
1011         spin_unlock_irqrestore(&priv->port.lock, flags);
1012         return IRQ_RETVAL(handled);
1013 }
1014
1015 /* This function tests whether the transmitter fifo and shifter for the port
1016                                                 described by 'port' is empty. */
1017 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1018 {
1019         struct eg20t_port *priv;
1020         int ret;
1021         priv = container_of(port, struct eg20t_port, port);
1022         if (priv->tx_empty)
1023                 ret = TIOCSER_TEMT;
1024         else
1025                 ret = 0;
1026
1027         return ret;
1028 }
1029
1030 /* Returns the current state of modem control inputs. */
1031 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1032 {
1033         struct eg20t_port *priv;
1034         u8 modem;
1035         unsigned int ret = 0;
1036
1037         priv = container_of(port, struct eg20t_port, port);
1038         modem = pch_uart_hal_get_modem(priv);
1039
1040         if (modem & UART_MSR_DCD)
1041                 ret |= TIOCM_CAR;
1042
1043         if (modem & UART_MSR_RI)
1044                 ret |= TIOCM_RNG;
1045
1046         if (modem & UART_MSR_DSR)
1047                 ret |= TIOCM_DSR;
1048
1049         if (modem & UART_MSR_CTS)
1050                 ret |= TIOCM_CTS;
1051
1052         return ret;
1053 }
1054
1055 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1056 {
1057         u32 mcr = 0;
1058         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1059
1060         if (mctrl & TIOCM_DTR)
1061                 mcr |= UART_MCR_DTR;
1062         if (mctrl & TIOCM_RTS)
1063                 mcr |= UART_MCR_RTS;
1064         if (mctrl & TIOCM_LOOP)
1065                 mcr |= UART_MCR_LOOP;
1066
1067         if (priv->mcr & UART_MCR_AFE)
1068                 mcr |= UART_MCR_AFE;
1069
1070         if (mctrl)
1071                 iowrite8(mcr, priv->membase + UART_MCR);
1072 }
1073
1074 static void pch_uart_stop_tx(struct uart_port *port)
1075 {
1076         struct eg20t_port *priv;
1077         priv = container_of(port, struct eg20t_port, port);
1078         priv->start_tx = 0;
1079         priv->tx_dma_use = 0;
1080 }
1081
1082 static void pch_uart_start_tx(struct uart_port *port)
1083 {
1084         struct eg20t_port *priv;
1085
1086         priv = container_of(port, struct eg20t_port, port);
1087
1088         if (priv->use_dma) {
1089                 if (priv->tx_dma_use) {
1090                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1091                                 __func__);
1092                         return;
1093                 }
1094         }
1095
1096         priv->start_tx = 1;
1097         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1098 }
1099
1100 static void pch_uart_stop_rx(struct uart_port *port)
1101 {
1102         struct eg20t_port *priv;
1103         priv = container_of(port, struct eg20t_port, port);
1104         priv->start_rx = 0;
1105         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1106         priv->int_dis_flag = 1;
1107 }
1108
1109 /* Enable the modem status interrupts. */
1110 static void pch_uart_enable_ms(struct uart_port *port)
1111 {
1112         struct eg20t_port *priv;
1113         priv = container_of(port, struct eg20t_port, port);
1114         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1115 }
1116
1117 /* Control the transmission of a break signal. */
1118 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1119 {
1120         struct eg20t_port *priv;
1121         unsigned long flags;
1122
1123         priv = container_of(port, struct eg20t_port, port);
1124         spin_lock_irqsave(&port->lock, flags);
1125         pch_uart_hal_set_break(priv, ctl);
1126         spin_unlock_irqrestore(&port->lock, flags);
1127 }
1128
1129 /* Grab any interrupt resources and initialise any low level driver state. */
1130 static int pch_uart_startup(struct uart_port *port)
1131 {
1132         struct eg20t_port *priv;
1133         int ret;
1134         int fifo_size;
1135         int trigger_level;
1136
1137         priv = container_of(port, struct eg20t_port, port);
1138         priv->tx_empty = 1;
1139
1140         if (port->uartclk)
1141                 priv->base_baud = port->uartclk;
1142         else
1143                 port->uartclk = priv->base_baud;
1144
1145         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1146         ret = pch_uart_hal_set_line(priv, default_baud,
1147                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1148                               PCH_UART_HAL_STB1);
1149         if (ret)
1150                 return ret;
1151
1152         switch (priv->fifo_size) {
1153         case 256:
1154                 fifo_size = PCH_UART_HAL_FIFO256;
1155                 break;
1156         case 64:
1157                 fifo_size = PCH_UART_HAL_FIFO64;
1158                 break;
1159         case 16:
1160                 fifo_size = PCH_UART_HAL_FIFO16;
1161         case 1:
1162         default:
1163                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1164                 break;
1165         }
1166
1167         switch (priv->trigger) {
1168         case PCH_UART_HAL_TRIGGER1:
1169                 trigger_level = 1;
1170                 break;
1171         case PCH_UART_HAL_TRIGGER_L:
1172                 trigger_level = priv->fifo_size / 4;
1173                 break;
1174         case PCH_UART_HAL_TRIGGER_M:
1175                 trigger_level = priv->fifo_size / 2;
1176                 break;
1177         case PCH_UART_HAL_TRIGGER_H:
1178         default:
1179                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1180                 break;
1181         }
1182
1183         priv->trigger_level = trigger_level;
1184         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1185                                     fifo_size, priv->trigger);
1186         if (ret < 0)
1187                 return ret;
1188
1189         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1190                         KBUILD_MODNAME, priv);
1191         if (ret < 0)
1192                 return ret;
1193
1194         if (priv->use_dma)
1195                 pch_request_dma(port);
1196
1197         priv->start_rx = 1;
1198         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1199         uart_update_timeout(port, CS8, default_baud);
1200
1201         return 0;
1202 }
1203
1204 static void pch_uart_shutdown(struct uart_port *port)
1205 {
1206         struct eg20t_port *priv;
1207         int ret;
1208
1209         priv = container_of(port, struct eg20t_port, port);
1210         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1211         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1212         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1213                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1214         if (ret)
1215                 dev_err(priv->port.dev,
1216                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1217
1218         if (priv->use_dma_flag)
1219                 pch_free_dma(port);
1220
1221         free_irq(priv->port.irq, priv);
1222 }
1223
1224 /* Change the port parameters, including word length, parity, stop
1225  *bits.  Update read_status_mask and ignore_status_mask to indicate
1226  *the types of events we are interested in receiving.  */
1227 static void pch_uart_set_termios(struct uart_port *port,
1228                                  struct ktermios *termios, struct ktermios *old)
1229 {
1230         int baud;
1231         int rtn;
1232         unsigned int parity, bits, stb;
1233         struct eg20t_port *priv;
1234         unsigned long flags;
1235
1236         priv = container_of(port, struct eg20t_port, port);
1237         switch (termios->c_cflag & CSIZE) {
1238         case CS5:
1239                 bits = PCH_UART_HAL_5BIT;
1240                 break;
1241         case CS6:
1242                 bits = PCH_UART_HAL_6BIT;
1243                 break;
1244         case CS7:
1245                 bits = PCH_UART_HAL_7BIT;
1246                 break;
1247         default:                /* CS8 */
1248                 bits = PCH_UART_HAL_8BIT;
1249                 break;
1250         }
1251         if (termios->c_cflag & CSTOPB)
1252                 stb = PCH_UART_HAL_STB2;
1253         else
1254                 stb = PCH_UART_HAL_STB1;
1255
1256         if (termios->c_cflag & PARENB) {
1257                 if (!(termios->c_cflag & PARODD))
1258                         parity = PCH_UART_HAL_PARITY_ODD;
1259                 else
1260                         parity = PCH_UART_HAL_PARITY_EVEN;
1261
1262         } else {
1263                 parity = PCH_UART_HAL_PARITY_NONE;
1264         }
1265
1266         /* Only UART0 has auto hardware flow function */
1267         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1268                 priv->mcr |= UART_MCR_AFE;
1269         else
1270                 priv->mcr &= ~UART_MCR_AFE;
1271
1272         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1273
1274         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1275
1276         spin_lock_irqsave(&port->lock, flags);
1277
1278         uart_update_timeout(port, termios->c_cflag, baud);
1279         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1280         if (rtn)
1281                 goto out;
1282
1283         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1284         /* Don't rewrite B0 */
1285         if (tty_termios_baud_rate(termios))
1286                 tty_termios_encode_baud_rate(termios, baud, baud);
1287
1288 out:
1289         spin_unlock_irqrestore(&port->lock, flags);
1290 }
1291
1292 static const char *pch_uart_type(struct uart_port *port)
1293 {
1294         return KBUILD_MODNAME;
1295 }
1296
1297 static void pch_uart_release_port(struct uart_port *port)
1298 {
1299         struct eg20t_port *priv;
1300
1301         priv = container_of(port, struct eg20t_port, port);
1302         pci_iounmap(priv->pdev, priv->membase);
1303         pci_release_regions(priv->pdev);
1304 }
1305
1306 static int pch_uart_request_port(struct uart_port *port)
1307 {
1308         struct eg20t_port *priv;
1309         int ret;
1310         void __iomem *membase;
1311
1312         priv = container_of(port, struct eg20t_port, port);
1313         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1314         if (ret < 0)
1315                 return -EBUSY;
1316
1317         membase = pci_iomap(priv->pdev, 1, 0);
1318         if (!membase) {
1319                 pci_release_regions(priv->pdev);
1320                 return -EBUSY;
1321         }
1322         priv->membase = port->membase = membase;
1323
1324         return 0;
1325 }
1326
1327 static void pch_uart_config_port(struct uart_port *port, int type)
1328 {
1329         struct eg20t_port *priv;
1330
1331         priv = container_of(port, struct eg20t_port, port);
1332         if (type & UART_CONFIG_TYPE) {
1333                 port->type = priv->port_type;
1334                 pch_uart_request_port(port);
1335         }
1336 }
1337
1338 static int pch_uart_verify_port(struct uart_port *port,
1339                                 struct serial_struct *serinfo)
1340 {
1341         struct eg20t_port *priv;
1342
1343         priv = container_of(port, struct eg20t_port, port);
1344         if (serinfo->flags & UPF_LOW_LATENCY) {
1345                 dev_info(priv->port.dev,
1346                         "PCH UART : Use PIO Mode (without DMA)\n");
1347                 priv->use_dma = 0;
1348                 serinfo->flags &= ~UPF_LOW_LATENCY;
1349         } else {
1350 #ifndef CONFIG_PCH_DMA
1351                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1352                         __func__);
1353                 return -EOPNOTSUPP;
1354 #endif
1355                 priv->use_dma = 1;
1356                 priv->use_dma_flag = 1;
1357                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1358         }
1359
1360         return 0;
1361 }
1362
1363 static struct uart_ops pch_uart_ops = {
1364         .tx_empty = pch_uart_tx_empty,
1365         .set_mctrl = pch_uart_set_mctrl,
1366         .get_mctrl = pch_uart_get_mctrl,
1367         .stop_tx = pch_uart_stop_tx,
1368         .start_tx = pch_uart_start_tx,
1369         .stop_rx = pch_uart_stop_rx,
1370         .enable_ms = pch_uart_enable_ms,
1371         .break_ctl = pch_uart_break_ctl,
1372         .startup = pch_uart_startup,
1373         .shutdown = pch_uart_shutdown,
1374         .set_termios = pch_uart_set_termios,
1375 /*      .pm             = pch_uart_pm,          Not supported yet */
1376 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1377         .type = pch_uart_type,
1378         .release_port = pch_uart_release_port,
1379         .request_port = pch_uart_request_port,
1380         .config_port = pch_uart_config_port,
1381         .verify_port = pch_uart_verify_port
1382 };
1383
1384 static struct uart_driver pch_uart_driver = {
1385         .owner = THIS_MODULE,
1386         .driver_name = KBUILD_MODNAME,
1387         .dev_name = PCH_UART_DRIVER_DEVICE,
1388         .major = 0,
1389         .minor = 0,
1390         .nr = PCH_UART_NR,
1391 };
1392
1393 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1394                                              const struct pci_device_id *id)
1395 {
1396         struct eg20t_port *priv;
1397         int ret;
1398         unsigned int iobase;
1399         unsigned int mapbase;
1400         unsigned char *rxbuf;
1401         int fifosize, base_baud;
1402         int port_type;
1403         struct pch_uart_driver_data *board;
1404         const char *board_name;
1405
1406         board = &drv_dat[id->driver_data];
1407         port_type = board->port_type;
1408
1409         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1410         if (priv == NULL)
1411                 goto init_port_alloc_err;
1412
1413         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1414         if (!rxbuf)
1415                 goto init_port_free_txbuf;
1416
1417         base_baud = 1843200; /* 1.8432MHz */
1418
1419         /* quirk for CM-iTC board */
1420         board_name = dmi_get_system_info(DMI_BOARD_NAME);
1421         if (board_name && strstr(board_name, "CM-iTC"))
1422                 base_baud = 192000000; /* 192.0MHz */
1423
1424         switch (port_type) {
1425         case PORT_UNKNOWN:
1426                 fifosize = 256; /* EG20T/ML7213: UART0 */
1427                 break;
1428         case PORT_8250:
1429                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1430                 break;
1431         default:
1432                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1433                 goto init_port_hal_free;
1434         }
1435
1436         pci_enable_msi(pdev);
1437
1438         iobase = pci_resource_start(pdev, 0);
1439         mapbase = pci_resource_start(pdev, 1);
1440         priv->mapbase = mapbase;
1441         priv->iobase = iobase;
1442         priv->pdev = pdev;
1443         priv->tx_empty = 1;
1444         priv->rxbuf.buf = rxbuf;
1445         priv->rxbuf.size = PAGE_SIZE;
1446
1447         priv->fifo_size = fifosize;
1448         priv->base_baud = base_baud;
1449         priv->port_type = PORT_MAX_8250 + port_type + 1;
1450         priv->port.dev = &pdev->dev;
1451         priv->port.iobase = iobase;
1452         priv->port.membase = NULL;
1453         priv->port.mapbase = mapbase;
1454         priv->port.irq = pdev->irq;
1455         priv->port.iotype = UPIO_PORT;
1456         priv->port.ops = &pch_uart_ops;
1457         priv->port.flags = UPF_BOOT_AUTOCONF;
1458         priv->port.fifosize = fifosize;
1459         priv->port.line = board->line_no;
1460         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1461
1462         spin_lock_init(&priv->port.lock);
1463
1464         pci_set_drvdata(pdev, priv);
1465         pch_uart_hal_request(pdev, fifosize, base_baud);
1466
1467         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1468         if (ret < 0)
1469                 goto init_port_hal_free;
1470
1471         return priv;
1472
1473 init_port_hal_free:
1474         free_page((unsigned long)rxbuf);
1475 init_port_free_txbuf:
1476         kfree(priv);
1477 init_port_alloc_err:
1478
1479         return NULL;
1480 }
1481
1482 static void pch_uart_exit_port(struct eg20t_port *priv)
1483 {
1484         uart_remove_one_port(&pch_uart_driver, &priv->port);
1485         pci_set_drvdata(priv->pdev, NULL);
1486         free_page((unsigned long)priv->rxbuf.buf);
1487 }
1488
1489 static void pch_uart_pci_remove(struct pci_dev *pdev)
1490 {
1491         struct eg20t_port *priv;
1492
1493         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1494
1495         pci_disable_msi(pdev);
1496         pch_uart_exit_port(priv);
1497         pci_disable_device(pdev);
1498         kfree(priv);
1499         return;
1500 }
1501 #ifdef CONFIG_PM
1502 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1503 {
1504         struct eg20t_port *priv = pci_get_drvdata(pdev);
1505
1506         uart_suspend_port(&pch_uart_driver, &priv->port);
1507
1508         pci_save_state(pdev);
1509         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1510         return 0;
1511 }
1512
1513 static int pch_uart_pci_resume(struct pci_dev *pdev)
1514 {
1515         struct eg20t_port *priv = pci_get_drvdata(pdev);
1516         int ret;
1517
1518         pci_set_power_state(pdev, PCI_D0);
1519         pci_restore_state(pdev);
1520
1521         ret = pci_enable_device(pdev);
1522         if (ret) {
1523                 dev_err(&pdev->dev,
1524                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1525                 return ret;
1526         }
1527
1528         uart_resume_port(&pch_uart_driver, &priv->port);
1529
1530         return 0;
1531 }
1532 #else
1533 #define pch_uart_pci_suspend NULL
1534 #define pch_uart_pci_resume NULL
1535 #endif
1536
1537 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1538         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1539          .driver_data = pch_et20t_uart0},
1540         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1541          .driver_data = pch_et20t_uart1},
1542         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1543          .driver_data = pch_et20t_uart2},
1544         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1545          .driver_data = pch_et20t_uart3},
1546         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1547          .driver_data = pch_ml7213_uart0},
1548         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1549          .driver_data = pch_ml7213_uart1},
1550         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1551          .driver_data = pch_ml7213_uart2},
1552         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1553          .driver_data = pch_ml7223_uart0},
1554         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1555          .driver_data = pch_ml7223_uart1},
1556         {0,},
1557 };
1558
1559 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1560                                         const struct pci_device_id *id)
1561 {
1562         int ret;
1563         struct eg20t_port *priv;
1564
1565         ret = pci_enable_device(pdev);
1566         if (ret < 0)
1567                 goto probe_error;
1568
1569         priv = pch_uart_init_port(pdev, id);
1570         if (!priv) {
1571                 ret = -EBUSY;
1572                 goto probe_disable_device;
1573         }
1574         pci_set_drvdata(pdev, priv);
1575
1576         return ret;
1577
1578 probe_disable_device:
1579         pci_disable_msi(pdev);
1580         pci_disable_device(pdev);
1581 probe_error:
1582         return ret;
1583 }
1584
1585 static struct pci_driver pch_uart_pci_driver = {
1586         .name = "pch_uart",
1587         .id_table = pch_uart_pci_id,
1588         .probe = pch_uart_pci_probe,
1589         .remove = __devexit_p(pch_uart_pci_remove),
1590         .suspend = pch_uart_pci_suspend,
1591         .resume = pch_uart_pci_resume,
1592 };
1593
1594 static int __init pch_uart_module_init(void)
1595 {
1596         int ret;
1597
1598         /* register as UART driver */
1599         ret = uart_register_driver(&pch_uart_driver);
1600         if (ret < 0)
1601                 return ret;
1602
1603         /* register as PCI driver */
1604         ret = pci_register_driver(&pch_uart_pci_driver);
1605         if (ret < 0)
1606                 uart_unregister_driver(&pch_uart_driver);
1607
1608         return ret;
1609 }
1610 module_init(pch_uart_module_init);
1611
1612 static void __exit pch_uart_module_exit(void)
1613 {
1614         pci_unregister_driver(&pch_uart_pci_driver);
1615         uart_unregister_driver(&pch_uart_driver);
1616 }
1617 module_exit(pch_uart_module_exit);
1618
1619 MODULE_LICENSE("GPL v2");
1620 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1621 module_param(default_baud, uint, S_IRUGO);