drivers/net/wireless/rtlwifi/pci.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "core.h"
  31 #include "wifi.h"
  32 #include "pci.h"
  33 #include "base.h"
  34 #include "ps.h"
  35 #include "efuse.h"
  36
  37 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
  38         INTEL_VENDOR_ID,
  39         ATI_VENDOR_ID,
  40         AMD_VENDOR_ID,
  41         SIS_VENDOR_ID
  42 };
  43
  44 static const u8 ac_to_hwq[] = {
  45         VO_QUEUE,
  46         VI_QUEUE,
  47         BE_QUEUE,
  48         BK_QUEUE
  49 };
  50
  51 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
  52                        struct sk_buff *skb)
  53 {
  54         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  55         __le16 fc = rtl_get_fc(skb);
  56         u8 queue_index = skb_get_queue_mapping(skb);
  57
  58         if (unlikely(ieee80211_is_beacon(fc)))
  59                 return BEACON_QUEUE;
  60         if (ieee80211_is_mgmt(fc))
  61                 return MGNT_QUEUE;
  62         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
  63                 if (ieee80211_is_nullfunc(fc))
  64                         return HIGH_QUEUE;
  65
  66         return ac_to_hwq[queue_index];
  67 }
  68
  69 /* Update PCI dependent default settings*/
  70 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  74         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  75         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  76         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
  77         u8 init_aspm;
  78
  79         ppsc->reg_rfps_level = 0;
  80         ppsc->support_aspm = 0;
  81
  82         /*Update PCI ASPM setting */
  83         ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
  84         switch (rtlpci->const_pci_aspm) {
  85         case 0:
  86                 /*No ASPM */
  87                 break;
  88
  89         case 1:
  90                 /*ASPM dynamically enabled/disable. */
  91                 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
  92                 break;
  93
  94         case 2:
  95                 /*ASPM with Clock Req dynamically enabled/disable. */
  96                 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
  97                                          RT_RF_OFF_LEVL_CLK_REQ);
  98                 break;
  99
 100         case 3:
 101                 /*
 102                  * Always enable ASPM and Clock Req
 103                  * from initialization to halt.
 104                  * */
 105                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
 106                 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
 107                                          RT_RF_OFF_LEVL_CLK_REQ);
 108                 break;
 109
 110         case 4:
 111                 /*
 112                  * Always enable ASPM without Clock Req
 113                  * from initialization to halt.
 114                  * */
 115                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
 116                                           RT_RF_OFF_LEVL_CLK_REQ);
 117                 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
 118                 break;
 119         }
 120
 121         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
 122
 123         /*Update Radio OFF setting */
 124         switch (rtlpci->const_hwsw_rfoff_d3) {
 125         case 1:
 126                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 127                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 128                 break;
 129
 130         case 2:
 131                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 132                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 133                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
 134                 break;
 135
 136         case 3:
 137                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
 138                 break;
 139         }
 140
 141         /*Set HW definition to determine if it supports ASPM. */
 142         switch (rtlpci->const_support_pciaspm) {
 143         case 0:{
 144                         /*Not support ASPM. */
 145                         bool support_aspm = false;
 146                         ppsc->support_aspm = support_aspm;
 147                         break;
 148                 }
 149         case 1:{
 150                         /*Support ASPM. */
 151                         bool support_aspm = true;
 152                         bool support_backdoor = true;
 153                         ppsc->support_aspm = support_aspm;
 154
 155                         /*if (priv->oem_id == RT_CID_TOSHIBA &&
 156                            !priv->ndis_adapter.amd_l1_patch)
 157                            support_backdoor = false; */
 158
 159                         ppsc->support_backdoor = support_backdoor;
 160
 161                         break;
 162                 }
 163         case 2:
 164                 /*ASPM value set by chipset. */
 165                 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
 166                         bool support_aspm = true;
 167                         ppsc->support_aspm = support_aspm;
 168                 }
 169                 break;
 170         default:
 171                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 172                          ("switch case not process\n"));
 173                 break;
 174         }
 175
 176         /* toshiba aspm issue, toshiba will set aspm selfly
 177          * so we should not set aspm in driver */
 178         pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
 179         if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
 180                 init_aspm == 0x43)
 181                 ppsc->support_aspm = false;
 182 }
 183
 184 static bool _rtl_pci_platform_switch_device_pci_aspm(
 185                         struct ieee80211_hw *hw,
 186                         u8 value)
 187 {
 188         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 189         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 190
 191         if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
 192                 value |= 0x40;
 193
 194         pci_write_config_byte(rtlpci->pdev, 0x80, value);
 195
 196         return false;
 197 }
 198
 199 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
 200 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
 201 {
 202         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 203         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 204
 205         pci_write_config_byte(rtlpci->pdev, 0x81, value);
 206
 207         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 208                 udelay(100);
 209
 210         return true;
 211 }
 212
 213 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
 214 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
 215 {
 216         struct rtl_priv *rtlpriv = rtl_priv(hw);
 217         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 218         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 219         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 220         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 221         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 222         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 223         /*Retrieve original configuration settings. */
 224         u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
 225         u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
 226                                 pcibridge_linkctrlreg;
 227         u16 aspmlevel = 0;
 228         u8 tmp_u1b = 0;
 229
 230         if (!ppsc->support_aspm)
 231                 return;
 232
 233         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 234                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 235                          ("PCI(Bridge) UNKNOWN.\n"));
 236
 237                 return;
 238         }
 239
 240         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 241                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 242                 _rtl_pci_switch_clk_req(hw, 0x0);
 243         }
 244
 245         /*for promising device will in L0 state after an I/O. */
 246         pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
 247
 248         /*Set corresponding value. */
 249         aspmlevel |= BIT(0) | BIT(1);
 250         linkctrl_reg &= ~aspmlevel;
 251         pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
 252
 253         _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
 254         udelay(50);
 255
 256         /*4 Disable Pci Bridge ASPM */
 257         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 258                                      pcicfg_addrport + (num4bytes << 2));
 259         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
 260
 261         udelay(50);
 262 }
 263
 264 /*
 265  *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
 266  *power saving We should follow the sequence to enable
 267  *RTL8192SE first then enable Pci Bridge ASPM
 268  *or the system will show bluescreen.
 269  */
 270 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
 271 {
 272         struct rtl_priv *rtlpriv = rtl_priv(hw);
 273         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 274         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 275         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 276         u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
 277         u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
 278         u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
 279         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 280         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 281         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 282         u16 aspmlevel;
 283         u8 u_pcibridge_aspmsetting;
 284         u8 u_device_aspmsetting;
 285
 286         if (!ppsc->support_aspm)
 287                 return;
 288
 289         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 290                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 291                          ("PCI(Bridge) UNKNOWN.\n"));
 292                 return;
 293         }
 294
 295         /*4 Enable Pci Bridge ASPM */
 296         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 297                                      pcicfg_addrport + (num4bytes << 2));
 298
 299         u_pcibridge_aspmsetting =
 300             pcipriv->ndis_adapter.pcibridge_linkctrlreg |
 301             rtlpci->const_hostpci_aspm_setting;
 302
 303         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
 304                 u_pcibridge_aspmsetting &= ~BIT(0);
 305
 306         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
 307
 308         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 309                  ("PlatformEnableASPM():PciBridge busnumber[%x], "
 310                   "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 311                   pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
 312                   (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
 313                   u_pcibridge_aspmsetting));
 314
 315         udelay(50);
 316
 317         /*Get ASPM level (with/without Clock Req) */
 318         aspmlevel = rtlpci->const_devicepci_aspm_setting;
 319         u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
 320
 321         /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
 322         /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
 323
 324         u_device_aspmsetting |= aspmlevel;
 325
 326         _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
 327
 328         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 329                 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
 330                                              RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
 331                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 332         }
 333         udelay(100);
 334 }
 335
 336 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
 337 {
 338         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 339         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 340
 341         bool status = false;
 342         u8 offset_e0;
 343         unsigned offset_e4;
 344
 345         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 346                         pcicfg_addrport + 0xE0);
 347         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
 348
 349         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 350                         pcicfg_addrport + 0xE0);
 351         rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
 352
 353         if (offset_e0 == 0xA0) {
 354                 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 355                                              pcicfg_addrport + 0xE4);
 356                 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
 357                 if (offset_e4 & BIT(23))
 358                         status = true;
 359         }
 360
 361         return status;
 362 }
 363
 364 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
 365 {
 366         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 367         u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
 368         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 369         u8 linkctrl_reg;
 370         u8 num4bbytes;
 371
 372         num4bbytes = (capabilityoffset + 0x10) / 4;
 373
 374         /*Read  Link Control Register */
 375         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 376                                      pcicfg_addrport + (num4bbytes << 2));
 377         rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
 378
 379         pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
 380 }
 381
 382 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
 383                 struct ieee80211_hw *hw)
 384 {
 385         struct rtl_priv *rtlpriv = rtl_priv(hw);
 386         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 387
 388         u8 tmp;
 389         int pos;
 390         u8 linkctrl_reg;
 391
 392         /*Link Control Register */
 393         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 394         pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
 395         pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
 396
 397         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 398                  ("Link Control Register =%x\n",
 399                   pcipriv->ndis_adapter.linkctrl_reg));
 400
 401         pci_read_config_byte(pdev, 0x98, &tmp);
 402         tmp |= BIT(4);
 403         pci_write_config_byte(pdev, 0x98, tmp);
 404
 405         tmp = 0x17;
 406         pci_write_config_byte(pdev, 0x70f, tmp);
 407 }
 408
 409 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
 410 {
 411         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 412
 413         _rtl_pci_update_default_setting(hw);
 414
 415         if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
 416                 /*Always enable ASPM & Clock Req. */
 417                 rtl_pci_enable_aspm(hw);
 418                 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
 419         }
 420
 421 }
 422
 423 static void _rtl_pci_io_handler_init(struct device *dev,
 424                                      struct ieee80211_hw *hw)
 425 {
 426         struct rtl_priv *rtlpriv = rtl_priv(hw);
 427
 428         rtlpriv->io.dev = dev;
 429
 430         rtlpriv->io.write8_async = pci_write8_async;
 431         rtlpriv->io.write16_async = pci_write16_async;
 432         rtlpriv->io.write32_async = pci_write32_async;
 433
 434         rtlpriv->io.read8_sync = pci_read8_sync;
 435         rtlpriv->io.read16_sync = pci_read16_sync;
 436         rtlpriv->io.read32_sync = pci_read32_sync;
 437
 438 }
 439
 440 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
 441 {
 442 }
 443
 444 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
 445                 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
 446 {
 447         struct rtl_priv *rtlpriv = rtl_priv(hw);
 448         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 449         u8 additionlen = FCS_LEN;
 450         struct sk_buff *next_skb;
 451
 452         /* here open is 4, wep/tkip is 8, aes is 12*/
 453         if (info->control.hw_key)
 454                 additionlen += info->control.hw_key->icv_len;
 455
 456         /* The most skb num is 6 */
 457         tcb_desc->empkt_num = 0;
 458         spin_lock_bh(&rtlpriv->locks.waitq_lock);
 459         skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
 460                 struct ieee80211_tx_info *next_info;
 461
 462                 next_info = IEEE80211_SKB_CB(next_skb);
 463                 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
 464                         tcb_desc->empkt_len[tcb_desc->empkt_num] =
 465                                 next_skb->len + additionlen;
 466                         tcb_desc->empkt_num++;
 467                 } else {
 468                         break;
 469                 }
 470
 471                 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
 472                                       next_skb))
 473                         break;
 474
 475                 if (tcb_desc->empkt_num >= 5)
 476                         break;
 477         }
 478         spin_unlock_bh(&rtlpriv->locks.waitq_lock);
 479
 480         return true;
 481 }
 482
 483 /* just for early mode now */
 484 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
 485 {
 486         struct rtl_priv *rtlpriv = rtl_priv(hw);
 487         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 488         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 489         struct sk_buff *skb = NULL;
 490         struct ieee80211_tx_info *info = NULL;
 491         int tid; /* should be int */
 492
 493         if (!rtlpriv->rtlhal.earlymode_enable)
 494                 return;
 495
 496         /* we juse use em for BE/BK/VI/VO */
 497         for (tid = 7; tid >= 0; tid--) {
 498                 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
 499                 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
 500                 while (!mac->act_scanning &&
 501                        rtlpriv->psc.rfpwr_state == ERFON) {
 502                         struct rtl_tcb_desc tcb_desc;
 503                         memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
 504
 505                         spin_lock_bh(&rtlpriv->locks.waitq_lock);
 506                         if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
 507                            (ring->entries - skb_queue_len(&ring->queue) > 5)) {
 508                                 skb = skb_dequeue(&mac->skb_waitq[tid]);
 509                         } else {
 510                                 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
 511                                 break;
 512                         }
 513                         spin_unlock_bh(&rtlpriv->locks.waitq_lock);
 514
 515                         /* Some macaddr can't do early mode. like
 516                          * multicast/broadcast/no_qos data */
 517                         info = IEEE80211_SKB_CB(skb);
 518                         if (info->flags & IEEE80211_TX_CTL_AMPDU)
 519                                 _rtl_update_earlymode_info(hw, skb,
 520                                                            &tcb_desc, tid);
 521
 522                         rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
 523                 }
 524         }
 525 }
 526
 527
 528 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
 529 {
 530         struct rtl_priv *rtlpriv = rtl_priv(hw);
 531         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 532
 533         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
 534
 535         while (skb_queue_len(&ring->queue)) {
 536                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
 537                 struct sk_buff *skb;
 538                 struct ieee80211_tx_info *info;
 539                 __le16 fc;
 540                 u8 tid;
 541
 542                 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
 543                                                           HW_DESC_OWN);
 544
 545                 /*
 546                  *beacon packet will only use the first
 547                  *descriptor defautly,and the own may not
 548                  *be cleared by the hardware
 549                  */
 550                 if (own)
 551                         return;
 552                 ring->idx = (ring->idx + 1) % ring->entries;
 553
 554                 skb = __skb_dequeue(&ring->queue);
 555                 pci_unmap_single(rtlpci->pdev,
 556                                  rtlpriv->cfg->ops->
 557                                              get_desc((u8 *) entry, true,
 558                                                       HW_DESC_TXBUFF_ADDR),
 559                                  skb->len, PCI_DMA_TODEVICE);
 560
 561                 /* remove early mode header */
 562                 if (rtlpriv->rtlhal.earlymode_enable)
 563                         skb_pull(skb, EM_HDR_LEN);
 564
 565                 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
 566                          ("new ring->idx:%d, "
 567                           "free: skb_queue_len:%d, free: seq:%x\n",
 568                           ring->idx,
 569                           skb_queue_len(&ring->queue),
 570                           *(u16 *) (skb->data + 22)));
 571
 572                 if (prio == TXCMD_QUEUE) {
 573                         dev_kfree_skb(skb);
 574                         goto tx_status_ok;
 575
 576                 }
 577
 578                 /* for sw LPS, just after NULL skb send out, we can
 579                  * sure AP kown we are sleeped, our we should not let
 580                  * rf to sleep*/
 581                 fc = rtl_get_fc(skb);
 582                 if (ieee80211_is_nullfunc(fc)) {
 583                         if (ieee80211_has_pm(fc)) {
 584                                 rtlpriv->mac80211.offchan_deley = true;
 585                                 rtlpriv->psc.state_inap = 1;
 586                         } else {
 587                                 rtlpriv->psc.state_inap = 0;
 588                         }
 589                 }
 590
 591                 /* update tid tx pkt num */
 592                 tid = rtl_get_tid(skb);
 593                 if (tid <= 7)
 594                         rtlpriv->link_info.tidtx_inperiod[tid]++;
 595
 596                 info = IEEE80211_SKB_CB(skb);
 597                 ieee80211_tx_info_clear_status(info);
 598
 599                 info->flags |= IEEE80211_TX_STAT_ACK;
 600                 /*info->status.rates[0].count = 1; */
 601
 602                 ieee80211_tx_status_irqsafe(hw, skb);
 603
 604                 if ((ring->entries - skb_queue_len(&ring->queue))
 605                                 == 2) {
 606
 607                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 608                                         ("more desc left, wake"
 609                                          "skb_queue@%d,ring->idx = %d,"
 610                                          "skb_queue_len = 0x%d\n",
 611                                          prio, ring->idx,
 612                                          skb_queue_len(&ring->queue)));
 613
 614                         ieee80211_wake_queue(hw,
 615                                         skb_get_queue_mapping
 616                                         (skb));
 617                 }
 618 tx_status_ok:
 619                 skb = NULL;
 620         }
 621
 622         if (((rtlpriv->link_info.num_rx_inperiod +
 623                 rtlpriv->link_info.num_tx_inperiod) > 8) ||
 624                 (rtlpriv->link_info.num_rx_inperiod > 2)) {
 625                 tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
 626         }
 627 }
 628
 629 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
 630 {
 631         struct rtl_priv *rtlpriv = rtl_priv(hw);
 632         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 633         int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
 634
 635         struct ieee80211_rx_status rx_status = { 0 };
 636         unsigned int count = rtlpci->rxringcount;
 637         u8 own;
 638         u8 tmp_one;
 639         u32 bufferaddress;
 640         bool unicast = false;
 641
 642         struct rtl_stats stats = {
 643                 .signal = 0,
 644                 .noise = -98,
 645                 .rate = 0,
 646         };
 647         int index = rtlpci->rx_ring[rx_queue_idx].idx;
 648
 649         /*RX NORMAL PKT */
 650         while (count--) {
 651                 /*rx descriptor */
 652                 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
 653                                 index];
 654                 /*rx pkt */
 655                 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
 656                                 index];
 657
 658                 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
 659                                                        false, HW_DESC_OWN);
 660
 661                 if (own) {
 662                         /*wait data to be filled by hardware */
 663                         break;
 664                 } else {
 665                         struct ieee80211_hdr *hdr;
 666                         __le16 fc;
 667                         struct sk_buff *new_skb = NULL;
 668
 669                         rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
 670                                                          &rx_status,
 671                                                          (u8 *) pdesc, skb);
 672
 673                         new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
 674                         if (unlikely(!new_skb)) {
 675                                 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
 676                                          DBG_DMESG,
 677                                          ("can't alloc skb for rx\n"));
 678                                 goto done;
 679                         }
 680
 681                         pci_unmap_single(rtlpci->pdev,
 682                                          *((dma_addr_t *) skb->cb),
 683                                          rtlpci->rxbuffersize,
 684                                          PCI_DMA_FROMDEVICE);
 685
 686                         skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
 687                                                          false,
 688                                                          HW_DESC_RXPKT_LEN));
 689                         skb_reserve(skb,
 690                                     stats.rx_drvinfo_size + stats.rx_bufshift);
 691
 692                         /*
 693                          *NOTICE This can not be use for mac80211,
 694                          *this is done in mac80211 code,
 695                          *if you done here sec DHCP will fail
 696                          *skb_trim(skb, skb->len - 4);
 697                          */
 698
 699                         hdr = rtl_get_hdr(skb);
 700                         fc = rtl_get_fc(skb);
 701
 702                         if (!stats.crc && !stats.hwerror) {
 703                                 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
 704                                        sizeof(rx_status));
 705
 706                                 if (is_broadcast_ether_addr(hdr->addr1)) {
 707                                         ;/*TODO*/
 708                                 } else if (is_multicast_ether_addr(hdr->addr1)) {
 709                                         ;/*TODO*/
 710                                 } else {
 711                                         unicast = true;
 712                                         rtlpriv->stats.rxbytesunicast +=
 713                                             skb->len;
 714                                 }
 715
 716                                 rtl_is_special_data(hw, skb, false);
 717
 718                                 if (ieee80211_is_data(fc)) {
 719                                         rtlpriv->cfg->ops->led_control(hw,
 720                                                                LED_CTL_RX);
 721
 722                                         if (unicast)
 723                                                 rtlpriv->link_info.
 724                                                     num_rx_inperiod++;
 725                                 }
 726
 727                                 /* for sw lps */
 728                                 rtl_swlps_beacon(hw, (void *)skb->data,
 729                                                  skb->len);
 730                                 rtl_recognize_peer(hw, (void *)skb->data,
 731                                                    skb->len);
 732                                 if ((rtlpriv->mac80211.opmode ==
 733                                      NL80211_IFTYPE_AP) &&
 734                                     (rtlpriv->rtlhal.current_bandtype ==
 735                                      BAND_ON_2_4G) &&
 736                                      (ieee80211_is_beacon(fc) ||
 737                                      ieee80211_is_probe_resp(fc))) {
 738                                         dev_kfree_skb_any(skb);
 739                                 } else {
 740                                         if (unlikely(!rtl_action_proc(hw, skb,
 741                                             false))) {
 742                                                 dev_kfree_skb_any(skb);
 743                                         } else {
 744                                                 struct sk_buff *uskb = NULL;
 745                                                 u8 *pdata;
 746                                                 uskb = dev_alloc_skb(skb->len
 747                                                                      + 128);
 748                                                 memcpy(IEEE80211_SKB_RXCB(uskb),
 749                                                        &rx_status,
 750                                                        sizeof(rx_status));
 751                                                 pdata = (u8 *)skb_put(uskb,
 752                                                         skb->len);
 753                                                 memcpy(pdata, skb->data,
 754                                                        skb->len);
 755                                                 dev_kfree_skb_any(skb);
 756
 757                                                 ieee80211_rx_irqsafe(hw, uskb);
 758                                         }
 759                                 }
 760                         } else {
 761                                 dev_kfree_skb_any(skb);
 762                         }
 763
 764                         if (((rtlpriv->link_info.num_rx_inperiod +
 765                                 rtlpriv->link_info.num_tx_inperiod) > 8) ||
 766                                 (rtlpriv->link_info.num_rx_inperiod > 2)) {
 767                                 tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
 768                         }
 769
 770                         skb = new_skb;
 771
 772                         rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
 773                         *((dma_addr_t *) skb->cb) =
 774                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
 775                                            rtlpci->rxbuffersize,
 776                                            PCI_DMA_FROMDEVICE);
 777
 778                 }
 779 done:
 780                 bufferaddress = (*((dma_addr_t *)skb->cb));
 781                 tmp_one = 1;
 782                 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
 783                                             HW_DESC_RXBUFF_ADDR,
 784                                             (u8 *)&bufferaddress);
 785                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 786                                             HW_DESC_RXPKT_LEN,
 787                                             (u8 *)&rtlpci->rxbuffersize);
 788
 789                 if (index == rtlpci->rxringcount - 1)
 790                         rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 791                                                     HW_DESC_RXERO,
 792                                                     (u8 *)&tmp_one);
 793
 794                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
 795                                             (u8 *)&tmp_one);
 796
 797                 index = (index + 1) % rtlpci->rxringcount;
 798         }
 799
 800         rtlpci->rx_ring[rx_queue_idx].idx = index;
 801 }
 802
 803 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
 804 {
 805         struct ieee80211_hw *hw = dev_id;
 806         struct rtl_priv *rtlpriv = rtl_priv(hw);
 807         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 808         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 809         unsigned long flags;
 810         u32 inta = 0;
 811         u32 intb = 0;
 812
 813         if (rtlpci->irq_enabled == 0)
 814                 return IRQ_HANDLED;
 815
 816         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
 817
 818         /*read ISR: 4/8bytes */
 819         rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
 820
 821         /*Shared IRQ or HW disappared */
 822         if (!inta || inta == 0xffff)
 823                 goto done;
 824
 825         /*<1> beacon related */
 826         if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
 827                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 828                          ("beacon ok interrupt!\n"));
 829         }
 830
 831         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
 832                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 833                          ("beacon err interrupt!\n"));
 834         }
 835
 836         if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
 837                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 838                          ("beacon interrupt!\n"));
 839         }
 840
 841         if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
 842                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 843                          ("prepare beacon for interrupt!\n"));
 844                 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
 845         }
 846
 847         /*<3> Tx related */
 848         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
 849                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
 850
 851         if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
 852                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 853                          ("Manage ok interrupt!\n"));
 854                 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
 855         }
 856
 857         if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
 858                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 859                          ("HIGH_QUEUE ok interrupt!\n"));
 860                 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
 861         }
 862
 863         if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
 864                 rtlpriv->link_info.num_tx_inperiod++;
 865
 866                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 867                          ("BK Tx OK interrupt!\n"));
 868                 _rtl_pci_tx_isr(hw, BK_QUEUE);
 869         }
 870
 871         if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
 872                 rtlpriv->link_info.num_tx_inperiod++;
 873
 874                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 875                          ("BE TX OK interrupt!\n"));
 876                 _rtl_pci_tx_isr(hw, BE_QUEUE);
 877         }
 878
 879         if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
 880                 rtlpriv->link_info.num_tx_inperiod++;
 881
 882                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 883                          ("VI TX OK interrupt!\n"));
 884                 _rtl_pci_tx_isr(hw, VI_QUEUE);
 885         }
 886
 887         if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
 888                 rtlpriv->link_info.num_tx_inperiod++;
 889
 890                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 891                          ("Vo TX OK interrupt!\n"));
 892                 _rtl_pci_tx_isr(hw, VO_QUEUE);
 893         }
 894
 895         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
 896                 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
 897                         rtlpriv->link_info.num_tx_inperiod++;
 898
 899                         RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 900                                         ("CMD TX OK interrupt!\n"));
 901                         _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
 902                 }
 903         }
 904
 905         /*<2> Rx related */
 906         if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
 907                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
 908                 _rtl_pci_rx_interrupt(hw);
 909         }
 910
 911         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
 912                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 913                          ("rx descriptor unavailable!\n"));
 914                 _rtl_pci_rx_interrupt(hw);
 915         }
 916
 917         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
 918                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
 919                 _rtl_pci_rx_interrupt(hw);
 920         }
 921
 922         if (rtlpriv->rtlhal.earlymode_enable)
 923                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 924
 925         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 926         return IRQ_HANDLED;
 927
 928 done:
 929         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 930         return IRQ_HANDLED;
 931 }
 932
 933 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
 934 {
 935         _rtl_pci_tx_chk_waitq(hw);
 936 }
 937
 938 static void _rtl_pci_ips_leave_tasklet(struct ieee80211_hw *hw)
 939 {
 940         rtl_lps_leave(hw);
 941 }
 942
 943 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
 944 {
 945         struct rtl_priv *rtlpriv = rtl_priv(hw);
 946         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 947         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 948         struct rtl8192_tx_ring *ring = NULL;
 949         struct ieee80211_hdr *hdr = NULL;
 950         struct ieee80211_tx_info *info = NULL;
 951         struct sk_buff *pskb = NULL;
 952         struct rtl_tx_desc *pdesc = NULL;
 953         struct rtl_tcb_desc tcb_desc;
 954         u8 temp_one = 1;
 955
 956         memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
 957         ring = &rtlpci->tx_ring[BEACON_QUEUE];
 958         pskb = __skb_dequeue(&ring->queue);
 959         if (pskb)
 960                 kfree_skb(pskb);
 961
 962         /*NB: the beacon data buffer must be 32-bit aligned. */
 963         pskb = ieee80211_beacon_get(hw, mac->vif);
 964         if (pskb == NULL)
 965                 return;
 966         hdr = rtl_get_hdr(pskb);
 967         info = IEEE80211_SKB_CB(pskb);
 968         pdesc = &ring->desc[0];
 969         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
 970                 info, pskb, BEACON_QUEUE, &tcb_desc);
 971
 972         __skb_queue_tail(&ring->queue, pskb);
 973
 974         rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
 975                                     (u8 *)&temp_one);
 976
 977         return;
 978 }
 979
 980 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
 981 {
 982         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 983         u8 i;
 984
 985         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
 986                 rtlpci->txringcount[i] = RT_TXDESC_NUM;
 987
 988         /*
 989          *we just alloc 2 desc for beacon queue,
 990          *because we just need first desc in hw beacon.
 991          */
 992         rtlpci->txringcount[BEACON_QUEUE] = 2;
 993
 994         /*
 995          *BE queue need more descriptor for performance
 996          *consideration or, No more tx desc will happen,
 997          *and may cause mac80211 mem leakage.
 998          */
 999         rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1000
1001         rtlpci->rxbuffersize = 9100;    /*2048/1024; */
1002         rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;     /*64; */
1003 }
1004
1005 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1006                 struct pci_dev *pdev)
1007 {
1008         struct rtl_priv *rtlpriv = rtl_priv(hw);
1009         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1010         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1011         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1012
1013         rtlpci->up_first_time = true;
1014         rtlpci->being_init_adapter = false;
1015
1016         rtlhal->hw = hw;
1017         rtlpci->pdev = pdev;
1018
1019         /*Tx/Rx related var */
1020         _rtl_pci_init_trx_var(hw);
1021
1022         /*IBSS*/ mac->beacon_interval = 100;
1023
1024         /*AMPDU*/
1025         mac->min_space_cfg = 0;
1026         mac->max_mss_density = 0;
1027         /*set sane AMPDU defaults */
1028         mac->current_ampdu_density = 7;
1029         mac->current_ampdu_factor = 3;
1030
1031         /*QOS*/
1032         rtlpci->acm_method = eAcmWay2_SW;
1033
1034         /*task */
1035         tasklet_init(&rtlpriv->works.irq_tasklet,
1036                      (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1037                      (unsigned long)hw);
1038         tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1039                      (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1040                      (unsigned long)hw);
1041         tasklet_init(&rtlpriv->works.ips_leave_tasklet,
1042                      (void (*)(unsigned long))_rtl_pci_ips_leave_tasklet,
1043                      (unsigned long)hw);
1044 }
1045
1046 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1047                                  unsigned int prio, unsigned int entries)
1048 {
1049         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1050         struct rtl_priv *rtlpriv = rtl_priv(hw);
1051         struct rtl_tx_desc *ring;
1052         dma_addr_t dma;
1053         u32 nextdescaddress;
1054         int i;
1055
1056         ring = pci_alloc_consistent(rtlpci->pdev,
1057                                     sizeof(*ring) * entries, &dma);
1058
1059         if (!ring || (unsigned long)ring & 0xFF) {
1060                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1061                          ("Cannot allocate TX ring (prio = %d)\n", prio));
1062                 return -ENOMEM;
1063         }
1064
1065         memset(ring, 0, sizeof(*ring) * entries);
1066         rtlpci->tx_ring[prio].desc = ring;
1067         rtlpci->tx_ring[prio].dma = dma;
1068         rtlpci->tx_ring[prio].idx = 0;
1069         rtlpci->tx_ring[prio].entries = entries;
1070         skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1071
1072         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1073                  ("queue:%d, ring_addr:%p\n", prio, ring));
1074
1075         for (i = 0; i < entries; i++) {
1076                 nextdescaddress = (u32) dma +
1077                                               ((i + 1) % entries) *
1078                                               sizeof(*ring);
1079
1080                 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1081                                             true, HW_DESC_TX_NEXTDESC_ADDR,
1082                                             (u8 *)&nextdescaddress);
1083         }
1084
1085         return 0;
1086 }
1087
1088 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1089 {
1090         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1091         struct rtl_priv *rtlpriv = rtl_priv(hw);
1092         struct rtl_rx_desc *entry = NULL;
1093         int i, rx_queue_idx;
1094         u8 tmp_one = 1;
1095
1096         /*
1097          *rx_queue_idx 0:RX_MPDU_QUEUE
1098          *rx_queue_idx 1:RX_CMD_QUEUE
1099          */
1100         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1101              rx_queue_idx++) {
1102                 rtlpci->rx_ring[rx_queue_idx].desc =
1103                     pci_alloc_consistent(rtlpci->pdev,
1104                                          sizeof(*rtlpci->rx_ring[rx_queue_idx].
1105                                                 desc) * rtlpci->rxringcount,
1106                                          &rtlpci->rx_ring[rx_queue_idx].dma);
1107
1108                 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1109                     (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1110                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1111                                  ("Cannot allocate RX ring\n"));
1112                         return -ENOMEM;
1113                 }
1114
1115                 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1116                        sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1117                        rtlpci->rxringcount);
1118
1119                 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1120
1121                 /* If amsdu_8k is disabled, set buffersize to 4096. This
1122                  * change will reduce memory fragmentation.
1123                  */
1124                 if (rtlpci->rxbuffersize > 4096 &&
1125                     rtlpriv->rtlhal.disable_amsdu_8k)
1126                         rtlpci->rxbuffersize = 4096;
1127
1128                 for (i = 0; i < rtlpci->rxringcount; i++) {
1129                         struct sk_buff *skb =
1130                             dev_alloc_skb(rtlpci->rxbuffersize);
1131                         u32 bufferaddress;
1132                         if (!skb)
1133                                 return 0;
1134                         entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1135
1136                         /*skb->dev = dev; */
1137
1138                         rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1139
1140                         /*
1141                          *just set skb->cb to mapping addr
1142                          *for pci_unmap_single use
1143                          */
1144                         *((dma_addr_t *) skb->cb) =
1145                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1146                                            rtlpci->rxbuffersize,
1147                                            PCI_DMA_FROMDEVICE);
1148
1149                         bufferaddress = (*((dma_addr_t *)skb->cb));
1150                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1151                                                     HW_DESC_RXBUFF_ADDR,
1152                                                     (u8 *)&bufferaddress);
1153                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1154                                                     HW_DESC_RXPKT_LEN,
1155                                                     (u8 *)&rtlpci->
1156                                                     rxbuffersize);
1157                         rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1158                                                     HW_DESC_RXOWN,
1159                                                     (u8 *)&tmp_one);
1160                 }
1161
1162                 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1163                                             HW_DESC_RXERO, (u8 *)&tmp_one);
1164         }
1165         return 0;
1166 }
1167
1168 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1169                 unsigned int prio)
1170 {
1171         struct rtl_priv *rtlpriv = rtl_priv(hw);
1172         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1173         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1174
1175         while (skb_queue_len(&ring->queue)) {
1176                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1177                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1178
1179                 pci_unmap_single(rtlpci->pdev,
1180                                  rtlpriv->cfg->
1181                                              ops->get_desc((u8 *) entry, true,
1182                                                    HW_DESC_TXBUFF_ADDR),
1183                                  skb->len, PCI_DMA_TODEVICE);
1184                 kfree_skb(skb);
1185                 ring->idx = (ring->idx + 1) % ring->entries;
1186         }
1187
1188         pci_free_consistent(rtlpci->pdev,
1189                             sizeof(*ring->desc) * ring->entries,
1190                             ring->desc, ring->dma);
1191         ring->desc = NULL;
1192 }
1193
1194 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1195 {
1196         int i, rx_queue_idx;
1197
1198         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1199         /*rx_queue_idx 1:RX_CMD_QUEUE */
1200         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1201              rx_queue_idx++) {
1202                 for (i = 0; i < rtlpci->rxringcount; i++) {
1203                         struct sk_buff *skb =
1204                             rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1205                         if (!skb)
1206                                 continue;
1207
1208                         pci_unmap_single(rtlpci->pdev,
1209                                          *((dma_addr_t *) skb->cb),
1210                                          rtlpci->rxbuffersize,
1211                                          PCI_DMA_FROMDEVICE);
1212                         kfree_skb(skb);
1213                 }
1214
1215                 pci_free_consistent(rtlpci->pdev,
1216                                     sizeof(*rtlpci->rx_ring[rx_queue_idx].
1217                                            desc) * rtlpci->rxringcount,
1218                                     rtlpci->rx_ring[rx_queue_idx].desc,
1219                                     rtlpci->rx_ring[rx_queue_idx].dma);
1220                 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1221         }
1222 }
1223
1224 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1225 {
1226         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1227         int ret;
1228         int i;
1229
1230         ret = _rtl_pci_init_rx_ring(hw);
1231         if (ret)
1232                 return ret;
1233
1234         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1235                 ret = _rtl_pci_init_tx_ring(hw, i,
1236                                  rtlpci->txringcount[i]);
1237                 if (ret)
1238                         goto err_free_rings;
1239         }
1240
1241         return 0;
1242
1243 err_free_rings:
1244         _rtl_pci_free_rx_ring(rtlpci);
1245
1246         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1247                 if (rtlpci->tx_ring[i].desc)
1248                         _rtl_pci_free_tx_ring(hw, i);
1249
1250         return 1;
1251 }
1252
1253 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1254 {
1255         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1256         u32 i;
1257
1258         /*free rx rings */
1259         _rtl_pci_free_rx_ring(rtlpci);
1260
1261         /*free tx rings */
1262         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1263                 _rtl_pci_free_tx_ring(hw, i);
1264
1265         return 0;
1266 }
1267
1268 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1269 {
1270         struct rtl_priv *rtlpriv = rtl_priv(hw);
1271         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1272         int i, rx_queue_idx;
1273         unsigned long flags;
1274         u8 tmp_one = 1;
1275
1276         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1277         /*rx_queue_idx 1:RX_CMD_QUEUE */
1278         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1279              rx_queue_idx++) {
1280                 /*
1281                  *force the rx_ring[RX_MPDU_QUEUE/
1282                  *RX_CMD_QUEUE].idx to the first one
1283                  */
1284                 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1285                         struct rtl_rx_desc *entry = NULL;
1286
1287                         for (i = 0; i < rtlpci->rxringcount; i++) {
1288                                 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1289                                 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1290                                                             false,
1291                                                             HW_DESC_RXOWN,
1292                                                             (u8 *)&tmp_one);
1293                         }
1294                         rtlpci->rx_ring[rx_queue_idx].idx = 0;
1295                 }
1296         }
1297
1298         /*
1299          *after reset, release previous pending packet,
1300          *and force the  tx idx to the first one
1301          */
1302         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1303         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1304                 if (rtlpci->tx_ring[i].desc) {
1305                         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1306
1307                         while (skb_queue_len(&ring->queue)) {
1308                                 struct rtl_tx_desc *entry =
1309                                     &ring->desc[ring->idx];
1310                                 struct sk_buff *skb =
1311                                     __skb_dequeue(&ring->queue);
1312
1313                                 pci_unmap_single(rtlpci->pdev,
1314                                                  rtlpriv->cfg->ops->
1315                                                          get_desc((u8 *)
1316                                                          entry,
1317                                                          true,
1318                                                          HW_DESC_TXBUFF_ADDR),
1319                                                  skb->len, PCI_DMA_TODEVICE);
1320                                 kfree_skb(skb);
1321                                 ring->idx = (ring->idx + 1) % ring->entries;
1322                         }
1323                         ring->idx = 0;
1324                 }
1325         }
1326
1327         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1328
1329         return 0;
1330 }
1331
1332 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1333                                         struct sk_buff *skb)
1334 {
1335         struct rtl_priv *rtlpriv = rtl_priv(hw);
1336         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1337         struct ieee80211_sta *sta = info->control.sta;
1338         struct rtl_sta_info *sta_entry = NULL;
1339         u8 tid = rtl_get_tid(skb);
1340
1341         if (!sta)
1342                 return false;
1343         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1344
1345         if (!rtlpriv->rtlhal.earlymode_enable)
1346                 return false;
1347         if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1348                 return false;
1349         if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1350                 return false;
1351         if (tid > 7)
1352                 return false;
1353
1354         /* maybe every tid should be checked */
1355         if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1356                 return false;
1357
1358         spin_lock_bh(&rtlpriv->locks.waitq_lock);
1359         skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1360         spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1361
1362         return true;
1363 }
1364
1365 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1366                 struct rtl_tcb_desc *ptcb_desc)
1367 {
1368         struct rtl_priv *rtlpriv = rtl_priv(hw);
1369         struct rtl_sta_info *sta_entry = NULL;
1370         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1371         struct ieee80211_sta *sta = info->control.sta;
1372         struct rtl8192_tx_ring *ring;
1373         struct rtl_tx_desc *pdesc;
1374         u8 idx;
1375         u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1376         unsigned long flags;
1377         struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1378         __le16 fc = rtl_get_fc(skb);
1379         u8 *pda_addr = hdr->addr1;
1380         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1381         /*ssn */
1382         u8 tid = 0;
1383         u16 seq_number = 0;
1384         u8 own;
1385         u8 temp_one = 1;
1386
1387         if (ieee80211_is_auth(fc)) {
1388                 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1389                 rtl_ips_nic_on(hw);
1390         }
1391
1392         if (rtlpriv->psc.sw_ps_enabled) {
1393                 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1394                         !ieee80211_has_pm(fc))
1395                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1396         }
1397
1398         rtl_action_proc(hw, skb, true);
1399
1400         if (is_multicast_ether_addr(pda_addr))
1401                 rtlpriv->stats.txbytesmulticast += skb->len;
1402         else if (is_broadcast_ether_addr(pda_addr))
1403                 rtlpriv->stats.txbytesbroadcast += skb->len;
1404         else
1405                 rtlpriv->stats.txbytesunicast += skb->len;
1406
1407         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1408         ring = &rtlpci->tx_ring[hw_queue];
1409         if (hw_queue != BEACON_QUEUE)
1410                 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1411                                 ring->entries;
1412         else
1413                 idx = 0;
1414
1415         pdesc = &ring->desc[idx];
1416         own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1417                         true, HW_DESC_OWN);
1418
1419         if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1420                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1421                          ("No more TX desc@%d, ring->idx = %d,"
1422                           "idx = %d, skb_queue_len = 0x%d\n",
1423                           hw_queue, ring->idx, idx,
1424                           skb_queue_len(&ring->queue)));
1425
1426                 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1427                 return skb->len;
1428         }
1429
1430         if (ieee80211_is_data_qos(fc)) {
1431                 tid = rtl_get_tid(skb);
1432                 if (sta) {
1433                         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1434                         seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1435                                       IEEE80211_SCTL_SEQ) >> 4;
1436                         seq_number += 1;
1437
1438                         if (!ieee80211_has_morefrags(hdr->frame_control))
1439                                 sta_entry->tids[tid].seq_number = seq_number;
1440                 }
1441         }
1442
1443         if (ieee80211_is_data(fc))
1444                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1445
1446         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1447                         info, skb, hw_queue, ptcb_desc);
1448
1449         __skb_queue_tail(&ring->queue, skb);
1450
1451         rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1452                                     HW_DESC_OWN, (u8 *)&temp_one);
1453
1454
1455         if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1456             hw_queue != BEACON_QUEUE) {
1457
1458                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1459                          ("less desc left, stop skb_queue@%d, "
1460                           "ring->idx = %d,"
1461                           "idx = %d, skb_queue_len = 0x%d\n",
1462                           hw_queue, ring->idx, idx,
1463                           skb_queue_len(&ring->queue)));
1464
1465                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1466         }
1467
1468         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1469
1470         rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1471
1472         return 0;
1473 }
1474
1475 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1476 {
1477         struct rtl_priv *rtlpriv = rtl_priv(hw);
1478         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1479         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1480         u16 i = 0;
1481         int queue_id;
1482         struct rtl8192_tx_ring *ring;
1483
1484         for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1485                 u32 queue_len;
1486                 ring = &pcipriv->dev.tx_ring[queue_id];
1487                 queue_len = skb_queue_len(&ring->queue);
1488                 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1489                         queue_id == TXCMD_QUEUE) {
1490                         queue_id--;
1491                         continue;
1492                 } else {
1493                         msleep(20);
1494                         i++;
1495                 }
1496
1497                 /* we just wait 1s for all queues */
1498                 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1499                         is_hal_stop(rtlhal) || i >= 200)
1500                         return;
1501         }
1502 }
1503
1504 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1505 {
1506         struct rtl_priv *rtlpriv = rtl_priv(hw);
1507         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1508
1509         _rtl_pci_deinit_trx_ring(hw);
1510
1511         synchronize_irq(rtlpci->pdev->irq);
1512         tasklet_kill(&rtlpriv->works.irq_tasklet);
1513         tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
1514
1515         flush_workqueue(rtlpriv->works.rtl_wq);
1516         destroy_workqueue(rtlpriv->works.rtl_wq);
1517
1518 }
1519
1520 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1521 {
1522         struct rtl_priv *rtlpriv = rtl_priv(hw);
1523         int err;
1524
1525         _rtl_pci_init_struct(hw, pdev);
1526
1527         err = _rtl_pci_init_trx_ring(hw);
1528         if (err) {
1529                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1530                          ("tx ring initialization failed"));
1531                 return err;
1532         }
1533
1534         return 1;
1535 }
1536
1537 static int rtl_pci_start(struct ieee80211_hw *hw)
1538 {
1539         struct rtl_priv *rtlpriv = rtl_priv(hw);
1540         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1541         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1542         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1543
1544         int err;
1545
1546         rtl_pci_reset_trx_ring(hw);
1547
1548         rtlpci->driver_is_goingto_unload = false;
1549         err = rtlpriv->cfg->ops->hw_init(hw);
1550         if (err) {
1551                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1552                          ("Failed to config hardware!\n"));
1553                 return err;
1554         }
1555
1556         rtlpriv->cfg->ops->enable_interrupt(hw);
1557         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1558
1559         rtl_init_rx_config(hw);
1560
1561         /*should after adapter start and interrupt enable. */
1562         set_hal_start(rtlhal);
1563
1564         RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1565
1566         rtlpci->up_first_time = false;
1567
1568         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1569         return 0;
1570 }
1571
1572 static void rtl_pci_stop(struct ieee80211_hw *hw)
1573 {
1574         struct rtl_priv *rtlpriv = rtl_priv(hw);
1575         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1576         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1577         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1578         unsigned long flags;
1579         u8 RFInProgressTimeOut = 0;
1580
1581         /*
1582          *should before disable interrrupt&adapter
1583          *and will do it immediately.
1584          */
1585         set_hal_stop(rtlhal);
1586
1587         rtlpriv->cfg->ops->disable_interrupt(hw);
1588         tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
1589
1590         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1591         while (ppsc->rfchange_inprogress) {
1592                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1593                 if (RFInProgressTimeOut > 100) {
1594                         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1595                         break;
1596                 }
1597                 mdelay(1);
1598                 RFInProgressTimeOut++;
1599                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1600         }
1601         ppsc->rfchange_inprogress = true;
1602         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1603
1604         rtlpci->driver_is_goingto_unload = true;
1605         rtlpriv->cfg->ops->hw_disable(hw);
1606         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1607
1608         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1609         ppsc->rfchange_inprogress = false;
1610         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1611
1612         rtl_pci_enable_aspm(hw);
1613 }
1614
1615 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1616                 struct ieee80211_hw *hw)
1617 {
1618         struct rtl_priv *rtlpriv = rtl_priv(hw);
1619         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1620         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1621         struct pci_dev *bridge_pdev = pdev->bus->self;
1622         u16 venderid;
1623         u16 deviceid;
1624         u8 revisionid;
1625         u16 irqline;
1626         u8 tmp;
1627
1628         pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1629         venderid = pdev->vendor;
1630         deviceid = pdev->device;
1631         pci_read_config_byte(pdev, 0x8, &revisionid);
1632         pci_read_config_word(pdev, 0x3C, &irqline);
1633
1634         if (deviceid == RTL_PCI_8192_DID ||
1635             deviceid == RTL_PCI_0044_DID ||
1636             deviceid == RTL_PCI_0047_DID ||
1637             deviceid == RTL_PCI_8192SE_DID ||
1638             deviceid == RTL_PCI_8174_DID ||
1639             deviceid == RTL_PCI_8173_DID ||
1640             deviceid == RTL_PCI_8172_DID ||
1641             deviceid == RTL_PCI_8171_DID) {
1642                 switch (revisionid) {
1643                 case RTL_PCI_REVISION_ID_8192PCIE:
1644                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1645                                  ("8192 PCI-E is found - "
1646                                   "vid/did=%x/%x\n", venderid, deviceid));
1647                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1648                         break;
1649                 case RTL_PCI_REVISION_ID_8192SE:
1650                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1651                                  ("8192SE is found - "
1652                                   "vid/did=%x/%x\n", venderid, deviceid));
1653                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1654                         break;
1655                 default:
1656                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1657                                  ("Err: Unknown device - "
1658                                   "vid/did=%x/%x\n", venderid, deviceid));
1659                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1660                         break;
1661
1662                 }
1663         } else if (deviceid == RTL_PCI_8192CET_DID ||
1664                    deviceid == RTL_PCI_8192CE_DID ||
1665                    deviceid == RTL_PCI_8191CE_DID ||
1666                    deviceid == RTL_PCI_8188CE_DID) {
1667                 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1668                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1669                          ("8192C PCI-E is found - "
1670                           "vid/did=%x/%x\n", venderid, deviceid));
1671         } else if (deviceid == RTL_PCI_8192DE_DID ||
1672                    deviceid == RTL_PCI_8192DE_DID2) {
1673                 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1674                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1675                          ("8192D PCI-E is found - "
1676                           "vid/did=%x/%x\n", venderid, deviceid));
1677         } else {
1678                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1679                          ("Err: Unknown device -"
1680                           " vid/did=%x/%x\n", venderid, deviceid));
1681
1682                 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1683         }
1684
1685         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1686                 if (revisionid == 0 || revisionid == 1) {
1687                         if (revisionid == 0) {
1688                                 RT_TRACE(rtlpriv, COMP_INIT,
1689                                          DBG_LOUD, ("Find 92DE MAC0.\n"));
1690                                 rtlhal->interfaceindex = 0;
1691                         } else if (revisionid == 1) {
1692                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1693                                         ("Find 92DE MAC1.\n"));
1694                                 rtlhal->interfaceindex = 1;
1695                         }
1696                 } else {
1697                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1698                                 ("Unknown device - "
1699                                 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1700                                 venderid, deviceid, revisionid));
1701                         rtlhal->interfaceindex = 0;
1702                 }
1703         }
1704         /*find bus info */
1705         pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1706         pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1707         pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1708
1709         /*find bridge info */
1710         pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1711         for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1712                 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1713                         pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1714                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1715                                  ("Pci Bridge Vendor is found index: %d\n",
1716                                   tmp));
1717                         break;
1718                 }
1719         }
1720
1721         if (pcipriv->ndis_adapter.pcibridge_vendor !=
1722                 PCI_BRIDGE_VENDOR_UNKNOWN) {
1723                 pcipriv->ndis_adapter.pcibridge_busnum =
1724                     bridge_pdev->bus->number;
1725                 pcipriv->ndis_adapter.pcibridge_devnum =
1726                     PCI_SLOT(bridge_pdev->devfn);
1727                 pcipriv->ndis_adapter.pcibridge_funcnum =
1728                     PCI_FUNC(bridge_pdev->devfn);
1729                 pcipriv->ndis_adapter.pcicfg_addrport =
1730                     (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1731                     (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1732                     (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1733                 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1734                     pci_pcie_cap(bridge_pdev);
1735                 pcipriv->ndis_adapter.num4bytes =
1736                     (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1737
1738                 rtl_pci_get_linkcontrol_field(hw);
1739
1740                 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1741                     PCI_BRIDGE_VENDOR_AMD) {
1742                         pcipriv->ndis_adapter.amd_l1_patch =
1743                             rtl_pci_get_amd_l1_patch(hw);
1744                 }
1745         }
1746
1747         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1748                  ("pcidev busnumber:devnumber:funcnumber:"
1749                   "vendor:link_ctl %d:%d:%d:%x:%x\n",
1750                   pcipriv->ndis_adapter.busnumber,
1751                   pcipriv->ndis_adapter.devnumber,
1752                   pcipriv->ndis_adapter.funcnumber,
1753                   pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1754
1755         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1756                  ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1757                   "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1758                   pcipriv->ndis_adapter.pcibridge_busnum,
1759                   pcipriv->ndis_adapter.pcibridge_devnum,
1760                   pcipriv->ndis_adapter.pcibridge_funcnum,
1761                   pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1762                   pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1763                   pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1764                   pcipriv->ndis_adapter.amd_l1_patch));
1765
1766         rtl_pci_parse_configuration(pdev, hw);
1767
1768         return true;
1769 }
1770
1771 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1772                             const struct pci_device_id *id)
1773 {
1774         struct ieee80211_hw *hw = NULL;
1775
1776         struct rtl_priv *rtlpriv = NULL;
1777         struct rtl_pci_priv *pcipriv = NULL;
1778         struct rtl_pci *rtlpci;
1779         unsigned long pmem_start, pmem_len, pmem_flags;
1780         int err;
1781
1782         err = pci_enable_device(pdev);
1783         if (err) {
1784                 RT_ASSERT(false,
1785                           ("%s : Cannot enable new PCI device\n",
1786                            pci_name(pdev)));
1787                 return err;
1788         }
1789
1790         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1791                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1792                         RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1793                                           "for consistent allocations\n"));
1794                         pci_disable_device(pdev);
1795                         return -ENOMEM;
1796                 }
1797         }
1798
1799         pci_set_master(pdev);
1800
1801         hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1802                                 sizeof(struct rtl_priv), &rtl_ops);
1803         if (!hw) {
1804                 RT_ASSERT(false,
1805                           ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1806                 err = -ENOMEM;
1807                 goto fail1;
1808         }
1809
1810         SET_IEEE80211_DEV(hw, &pdev->dev);
1811         pci_set_drvdata(pdev, hw);
1812
1813         rtlpriv = hw->priv;
1814         pcipriv = (void *)rtlpriv->priv;
1815         pcipriv->dev.pdev = pdev;
1816
1817         /* init cfg & intf_ops */
1818         rtlpriv->rtlhal.interface = INTF_PCI;
1819         rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1820         rtlpriv->intf_ops = &rtl_pci_ops;
1821
1822         /*
1823          *init dbgp flags before all
1824          *other functions, because we will
1825          *use it in other funtions like
1826          *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1827          *you can not use these macro
1828          *before this
1829          */
1830         rtl_dbgp_flag_init(hw);
1831
1832         /* MEM map */
1833         err = pci_request_regions(pdev, KBUILD_MODNAME);
1834         if (err) {
1835                 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1836                 return err;
1837         }
1838
1839         pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1840         pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1841         pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1842
1843         /*shared mem start */
1844         rtlpriv->io.pci_mem_start =
1845                         (unsigned long)pci_iomap(pdev,
1846                         rtlpriv->cfg->bar_id, pmem_len);
1847         if (rtlpriv->io.pci_mem_start == 0) {
1848                 RT_ASSERT(false, ("Can't map PCI mem\n"));
1849                 goto fail2;
1850         }
1851
1852         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1853                  ("mem mapped space: start: 0x%08lx len:%08lx "
1854                   "flags:%08lx, after map:0x%08lx\n",
1855                   pmem_start, pmem_len, pmem_flags,
1856                   rtlpriv->io.pci_mem_start));
1857
1858         /* Disable Clk Request */
1859         pci_write_config_byte(pdev, 0x81, 0);
1860         /* leave D3 mode */
1861         pci_write_config_byte(pdev, 0x44, 0);
1862         pci_write_config_byte(pdev, 0x04, 0x06);
1863         pci_write_config_byte(pdev, 0x04, 0x07);
1864
1865         /* find adapter */
1866         _rtl_pci_find_adapter(pdev, hw);
1867
1868         /* Init IO handler */
1869         _rtl_pci_io_handler_init(&pdev->dev, hw);
1870
1871         /*like read eeprom and so on */
1872         rtlpriv->cfg->ops->read_eeprom_info(hw);
1873
1874         if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1875                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1876                          ("Can't init_sw_vars.\n"));
1877                 goto fail3;
1878         }
1879
1880         rtlpriv->cfg->ops->init_sw_leds(hw);
1881
1882         /*aspm */
1883         rtl_pci_init_aspm(hw);
1884
1885         /* Init mac80211 sw */
1886         err = rtl_init_core(hw);
1887         if (err) {
1888                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1889                          ("Can't allocate sw for mac80211.\n"));
1890                 goto fail3;
1891         }
1892
1893         /* Init PCI sw */
1894         err = !rtl_pci_init(hw, pdev);
1895         if (err) {
1896                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1897                          ("Failed to init PCI.\n"));
1898                 goto fail3;
1899         }
1900
1901         err = ieee80211_register_hw(hw);
1902         if (err) {
1903                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1904                          ("Can't register mac80211 hw.\n"));
1905                 goto fail3;
1906         } else {
1907                 rtlpriv->mac80211.mac80211_registered = 1;
1908         }
1909
1910         err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1911         if (err) {
1912                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1913                          ("failed to create sysfs device attributes\n"));
1914                 goto fail3;
1915         }
1916
1917         /*init rfkill */
1918         rtl_init_rfkill(hw);
1919
1920         rtlpci = rtl_pcidev(pcipriv);
1921         err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1922                           IRQF_SHARED, KBUILD_MODNAME, hw);
1923         if (err) {
1924                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1925                          ("%s: failed to register IRQ handler\n",
1926                           wiphy_name(hw->wiphy)));
1927                 goto fail3;
1928         } else {
1929                 rtlpci->irq_alloc = 1;
1930         }
1931
1932         set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1933         return 0;
1934
1935 fail3:
1936         pci_set_drvdata(pdev, NULL);
1937         rtl_deinit_core(hw);
1938         _rtl_pci_io_handler_release(hw);
1939         ieee80211_free_hw(hw);
1940
1941         if (rtlpriv->io.pci_mem_start != 0)
1942                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1943
1944 fail2:
1945         pci_release_regions(pdev);
1946
1947 fail1:
1948
1949         pci_disable_device(pdev);
1950
1951         return -ENODEV;
1952
1953 }
1954 EXPORT_SYMBOL(rtl_pci_probe);
1955
1956 void rtl_pci_disconnect(struct pci_dev *pdev)
1957 {
1958         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1959         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1960         struct rtl_priv *rtlpriv = rtl_priv(hw);
1961         struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1962         struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1963
1964         clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1965
1966         sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1967
1968         /*ieee80211_unregister_hw will call ops_stop */
1969         if (rtlmac->mac80211_registered == 1) {
1970                 ieee80211_unregister_hw(hw);
1971                 rtlmac->mac80211_registered = 0;
1972         } else {
1973                 rtl_deinit_deferred_work(hw);
1974                 rtlpriv->intf_ops->adapter_stop(hw);
1975         }
1976
1977         /*deinit rfkill */
1978         rtl_deinit_rfkill(hw);
1979
1980         rtl_pci_deinit(hw);
1981         rtl_deinit_core(hw);
1982         _rtl_pci_io_handler_release(hw);
1983         rtlpriv->cfg->ops->deinit_sw_vars(hw);
1984
1985         if (rtlpci->irq_alloc) {
1986                 free_irq(rtlpci->pdev->irq, hw);
1987                 rtlpci->irq_alloc = 0;
1988         }
1989
1990         if (rtlpriv->io.pci_mem_start != 0) {
1991                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1992                 pci_release_regions(pdev);
1993         }
1994
1995         pci_disable_device(pdev);
1996
1997         rtl_pci_disable_aspm(hw);
1998
1999         pci_set_drvdata(pdev, NULL);
2000
2001         ieee80211_free_hw(hw);
2002 }
2003 EXPORT_SYMBOL(rtl_pci_disconnect);
2004
2005 /***************************************
2006 kernel pci power state define:
2007 PCI_D0         ((pci_power_t __force) 0)
2008 PCI_D1         ((pci_power_t __force) 1)
2009 PCI_D2         ((pci_power_t __force) 2)
2010 PCI_D3hot      ((pci_power_t __force) 3)
2011 PCI_D3cold     ((pci_power_t __force) 4)
2012 PCI_UNKNOWN    ((pci_power_t __force) 5)
2013
2014 This function is called when system
2015 goes into suspend state mac80211 will
2016 call rtl_mac_stop() from the mac80211
2017 suspend function first, So there is
2018 no need to call hw_disable here.
2019 ****************************************/
2020 int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2021 {
2022         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2023         struct rtl_priv *rtlpriv = rtl_priv(hw);
2024
2025         rtlpriv->cfg->ops->hw_suspend(hw);
2026         rtl_deinit_rfkill(hw);
2027
2028         pci_save_state(pdev);
2029         pci_disable_device(pdev);
2030         pci_set_power_state(pdev, PCI_D3hot);
2031         return 0;
2032 }
2033 EXPORT_SYMBOL(rtl_pci_suspend);
2034
2035 int rtl_pci_resume(struct pci_dev *pdev)
2036 {
2037         int ret;
2038         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2039         struct rtl_priv *rtlpriv = rtl_priv(hw);
2040
2041         pci_set_power_state(pdev, PCI_D0);
2042         ret = pci_enable_device(pdev);
2043         if (ret) {
2044                 RT_ASSERT(false, ("ERR: <======\n"));
2045                 return ret;
2046         }
2047
2048         pci_restore_state(pdev);
2049
2050         rtlpriv->cfg->ops->hw_resume(hw);
2051         rtl_init_rfkill(hw);
2052         return 0;
2053 }
2054 EXPORT_SYMBOL(rtl_pci_resume);
2055
2056 struct rtl_intf_ops rtl_pci_ops = {
2057         .read_efuse_byte = read_efuse_byte,
2058         .adapter_start = rtl_pci_start,
2059         .adapter_stop = rtl_pci_stop,
2060         .adapter_tx = rtl_pci_tx,
2061         .flush = rtl_pci_flush,
2062         .reset_trx_ring = rtl_pci_reset_trx_ring,
2063         .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2064
2065         .disable_aspm = rtl_pci_disable_aspm,
2066         .enable_aspm = rtl_pci_enable_aspm,
2067 };