2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 static inline int ring_space(struct intel_ring_buffer *ring)
39 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
45 static u32 i915_gem_get_seqno(struct drm_device *dev)
47 drm_i915_private_t *dev_priv = dev->dev_private;
50 seqno = dev_priv->next_seqno;
52 /* reserve 0 for non-seqno */
53 if (++dev_priv->next_seqno == 0)
54 dev_priv->next_seqno = 1;
60 render_ring_flush(struct intel_ring_buffer *ring,
61 u32 invalidate_domains,
64 struct drm_device *dev = ring->dev;
71 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
72 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
73 * also flushed at 2d versus 3d pipeline switches.
77 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
78 * MI_READ_FLUSH is set, and is always flushed on 965.
80 * I915_GEM_DOMAIN_COMMAND may not exist?
82 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
83 * invalidated when MI_EXE_FLUSH is set.
85 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
86 * invalidated with every MI_FLUSH.
90 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
91 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
92 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
93 * are flushed at any MI_FLUSH.
96 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
97 if ((invalidate_domains|flush_domains) &
98 I915_GEM_DOMAIN_RENDER)
99 cmd &= ~MI_NO_WRITE_FLUSH;
100 if (INTEL_INFO(dev)->gen < 4) {
102 * On the 965, the sampler cache always gets flushed
103 * and this bit is reserved.
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
108 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
111 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
112 (IS_G4X(dev) || IS_GEN5(dev)))
113 cmd |= MI_INVALIDATE_ISP;
115 ret = intel_ring_begin(ring, 2);
119 intel_ring_emit(ring, cmd);
120 intel_ring_emit(ring, MI_NOOP);
121 intel_ring_advance(ring);
126 static void ring_write_tail(struct intel_ring_buffer *ring,
129 drm_i915_private_t *dev_priv = ring->dev->dev_private;
130 I915_WRITE_TAIL(ring, value);
133 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
135 drm_i915_private_t *dev_priv = ring->dev->dev_private;
136 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
137 RING_ACTHD(ring->mmio_base) : ACTHD;
139 return I915_READ(acthd_reg);
142 static int init_ring_common(struct intel_ring_buffer *ring)
144 drm_i915_private_t *dev_priv = ring->dev->dev_private;
145 struct drm_i915_gem_object *obj = ring->obj;
148 /* Stop the ring if it's running. */
149 I915_WRITE_CTL(ring, 0);
150 I915_WRITE_HEAD(ring, 0);
151 ring->write_tail(ring, 0);
153 /* Initialize the ring. */
154 I915_WRITE_START(ring, obj->gtt_offset);
155 head = I915_READ_HEAD(ring) & HEAD_ADDR;
157 /* G45 ring initialization fails to reset head to zero */
159 DRM_DEBUG_KMS("%s head not reset to zero "
160 "ctl %08x head %08x tail %08x start %08x\n",
163 I915_READ_HEAD(ring),
164 I915_READ_TAIL(ring),
165 I915_READ_START(ring));
167 I915_WRITE_HEAD(ring, 0);
169 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
170 DRM_ERROR("failed to set %s head to zero "
171 "ctl %08x head %08x tail %08x start %08x\n",
174 I915_READ_HEAD(ring),
175 I915_READ_TAIL(ring),
176 I915_READ_START(ring));
181 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
182 | RING_REPORT_64K | RING_VALID);
184 /* If the head is still not zero, the ring is dead */
185 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
186 I915_READ_START(ring) != obj->gtt_offset ||
187 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
188 DRM_ERROR("%s initialization failed "
189 "ctl %08x head %08x tail %08x start %08x\n",
192 I915_READ_HEAD(ring),
193 I915_READ_TAIL(ring),
194 I915_READ_START(ring));
198 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
199 i915_kernel_lost_context(ring->dev);
201 ring->head = I915_READ_HEAD(ring);
202 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
203 ring->space = ring_space(ring);
210 * 965+ support PIPE_CONTROL commands, which provide finer grained control
211 * over cache flushing.
213 struct pipe_control {
214 struct drm_i915_gem_object *obj;
215 volatile u32 *cpu_page;
220 init_pipe_control(struct intel_ring_buffer *ring)
222 struct pipe_control *pc;
223 struct drm_i915_gem_object *obj;
229 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
233 obj = i915_gem_alloc_object(ring->dev, 4096);
235 DRM_ERROR("Failed to allocate seqno page\n");
239 obj->cache_level = I915_CACHE_LLC;
241 ret = i915_gem_object_pin(obj, 4096, true);
245 pc->gtt_offset = obj->gtt_offset;
246 pc->cpu_page = kmap(obj->pages[0]);
247 if (pc->cpu_page == NULL)
255 i915_gem_object_unpin(obj);
257 drm_gem_object_unreference(&obj->base);
264 cleanup_pipe_control(struct intel_ring_buffer *ring)
266 struct pipe_control *pc = ring->private;
267 struct drm_i915_gem_object *obj;
273 kunmap(obj->pages[0]);
274 i915_gem_object_unpin(obj);
275 drm_gem_object_unreference(&obj->base);
278 ring->private = NULL;
281 static int init_render_ring(struct intel_ring_buffer *ring)
283 struct drm_device *dev = ring->dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 int ret = init_ring_common(ring);
287 if (INTEL_INFO(dev)->gen > 3) {
288 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
290 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
291 I915_WRITE(MI_MODE, mode);
294 if (INTEL_INFO(dev)->gen >= 6) {
295 } else if (IS_GEN5(dev)) {
296 ret = init_pipe_control(ring);
304 static void render_ring_cleanup(struct intel_ring_buffer *ring)
309 cleanup_pipe_control(ring);
313 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
315 struct drm_device *dev = ring->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
320 * cs -> 1 = vcs, 0 = bcs
321 * vcs -> 1 = bcs, 0 = cs,
322 * bcs -> 1 = cs, 0 = vcs.
324 id = ring - dev_priv->ring;
328 intel_ring_emit(ring,
330 MI_SEMAPHORE_REGISTER |
331 MI_SEMAPHORE_UPDATE);
332 intel_ring_emit(ring, seqno);
333 intel_ring_emit(ring,
334 RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
338 gen6_add_request(struct intel_ring_buffer *ring,
344 ret = intel_ring_begin(ring, 10);
348 seqno = i915_gem_get_seqno(ring->dev);
349 update_semaphore(ring, 0, seqno);
350 update_semaphore(ring, 1, seqno);
352 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
353 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
354 intel_ring_emit(ring, seqno);
355 intel_ring_emit(ring, MI_USER_INTERRUPT);
356 intel_ring_advance(ring);
363 intel_ring_sync(struct intel_ring_buffer *ring,
364 struct intel_ring_buffer *to,
369 ret = intel_ring_begin(ring, 4);
373 intel_ring_emit(ring,
375 MI_SEMAPHORE_REGISTER |
376 intel_ring_sync_index(ring, to) << 17 |
377 MI_SEMAPHORE_COMPARE);
378 intel_ring_emit(ring, seqno);
379 intel_ring_emit(ring, 0);
380 intel_ring_emit(ring, MI_NOOP);
381 intel_ring_advance(ring);
386 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
388 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
389 PIPE_CONTROL_DEPTH_STALL | 2); \
390 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
391 intel_ring_emit(ring__, 0); \
392 intel_ring_emit(ring__, 0); \
396 pc_render_add_request(struct intel_ring_buffer *ring,
399 struct drm_device *dev = ring->dev;
400 u32 seqno = i915_gem_get_seqno(dev);
401 struct pipe_control *pc = ring->private;
402 u32 scratch_addr = pc->gtt_offset + 128;
405 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
406 * incoherent with writes to memory, i.e. completely fubar,
407 * so we need to use PIPE_NOTIFY instead.
409 * However, we also need to workaround the qword write
410 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
411 * memory before requesting an interrupt.
413 ret = intel_ring_begin(ring, 32);
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
418 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
419 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
420 intel_ring_emit(ring, seqno);
421 intel_ring_emit(ring, 0);
422 PIPE_CONTROL_FLUSH(ring, scratch_addr);
423 scratch_addr += 128; /* write to separate cachelines */
424 PIPE_CONTROL_FLUSH(ring, scratch_addr);
426 PIPE_CONTROL_FLUSH(ring, scratch_addr);
428 PIPE_CONTROL_FLUSH(ring, scratch_addr);
430 PIPE_CONTROL_FLUSH(ring, scratch_addr);
432 PIPE_CONTROL_FLUSH(ring, scratch_addr);
433 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
434 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
435 PIPE_CONTROL_NOTIFY);
436 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
437 intel_ring_emit(ring, seqno);
438 intel_ring_emit(ring, 0);
439 intel_ring_advance(ring);
446 render_ring_add_request(struct intel_ring_buffer *ring,
449 struct drm_device *dev = ring->dev;
450 u32 seqno = i915_gem_get_seqno(dev);
453 ret = intel_ring_begin(ring, 4);
457 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
458 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
459 intel_ring_emit(ring, seqno);
460 intel_ring_emit(ring, MI_USER_INTERRUPT);
461 intel_ring_advance(ring);
468 ring_get_seqno(struct intel_ring_buffer *ring)
470 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
474 pc_render_get_seqno(struct intel_ring_buffer *ring)
476 struct pipe_control *pc = ring->private;
477 return pc->cpu_page[0];
481 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
483 dev_priv->gt_irq_mask &= ~mask;
484 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
489 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
491 dev_priv->gt_irq_mask |= mask;
492 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
497 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
499 dev_priv->irq_mask &= ~mask;
500 I915_WRITE(IMR, dev_priv->irq_mask);
505 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
507 dev_priv->irq_mask |= mask;
508 I915_WRITE(IMR, dev_priv->irq_mask);
513 render_ring_get_irq(struct intel_ring_buffer *ring)
515 struct drm_device *dev = ring->dev;
516 drm_i915_private_t *dev_priv = dev->dev_private;
518 if (!dev->irq_enabled)
521 spin_lock(&ring->irq_lock);
522 if (ring->irq_refcount++ == 0) {
523 if (HAS_PCH_SPLIT(dev))
524 ironlake_enable_irq(dev_priv,
525 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
527 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
529 spin_unlock(&ring->irq_lock);
535 render_ring_put_irq(struct intel_ring_buffer *ring)
537 struct drm_device *dev = ring->dev;
538 drm_i915_private_t *dev_priv = dev->dev_private;
540 spin_lock(&ring->irq_lock);
541 if (--ring->irq_refcount == 0) {
542 if (HAS_PCH_SPLIT(dev))
543 ironlake_disable_irq(dev_priv,
547 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
549 spin_unlock(&ring->irq_lock);
552 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
554 drm_i915_private_t *dev_priv = ring->dev->dev_private;
555 u32 mmio = IS_GEN6(ring->dev) ?
556 RING_HWS_PGA_GEN6(ring->mmio_base) :
557 RING_HWS_PGA(ring->mmio_base);
558 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
563 bsd_ring_flush(struct intel_ring_buffer *ring,
564 u32 invalidate_domains,
569 ret = intel_ring_begin(ring, 2);
573 intel_ring_emit(ring, MI_FLUSH);
574 intel_ring_emit(ring, MI_NOOP);
575 intel_ring_advance(ring);
580 ring_add_request(struct intel_ring_buffer *ring,
586 ret = intel_ring_begin(ring, 4);
590 seqno = i915_gem_get_seqno(ring->dev);
592 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
593 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
594 intel_ring_emit(ring, seqno);
595 intel_ring_emit(ring, MI_USER_INTERRUPT);
596 intel_ring_advance(ring);
603 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
605 struct drm_device *dev = ring->dev;
606 drm_i915_private_t *dev_priv = dev->dev_private;
608 if (!dev->irq_enabled)
611 spin_lock(&ring->irq_lock);
612 if (ring->irq_refcount++ == 0)
613 ironlake_enable_irq(dev_priv, flag);
614 spin_unlock(&ring->irq_lock);
620 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
622 struct drm_device *dev = ring->dev;
623 drm_i915_private_t *dev_priv = dev->dev_private;
625 spin_lock(&ring->irq_lock);
626 if (--ring->irq_refcount == 0)
627 ironlake_disable_irq(dev_priv, flag);
628 spin_unlock(&ring->irq_lock);
632 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
634 struct drm_device *dev = ring->dev;
635 drm_i915_private_t *dev_priv = dev->dev_private;
637 if (!dev->irq_enabled)
640 spin_lock(&ring->irq_lock);
641 if (ring->irq_refcount++ == 0) {
642 ring->irq_mask &= ~rflag;
643 I915_WRITE_IMR(ring, ring->irq_mask);
644 ironlake_enable_irq(dev_priv, gflag);
646 spin_unlock(&ring->irq_lock);
652 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
654 struct drm_device *dev = ring->dev;
655 drm_i915_private_t *dev_priv = dev->dev_private;
657 spin_lock(&ring->irq_lock);
658 if (--ring->irq_refcount == 0) {
659 ring->irq_mask |= rflag;
660 I915_WRITE_IMR(ring, ring->irq_mask);
661 ironlake_disable_irq(dev_priv, gflag);
663 spin_unlock(&ring->irq_lock);
667 bsd_ring_get_irq(struct intel_ring_buffer *ring)
669 return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
672 bsd_ring_put_irq(struct intel_ring_buffer *ring)
674 ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
678 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
682 ret = intel_ring_begin(ring, 2);
686 intel_ring_emit(ring,
687 MI_BATCH_BUFFER_START | (2 << 6) |
688 MI_BATCH_NON_SECURE_I965);
689 intel_ring_emit(ring, offset);
690 intel_ring_advance(ring);
696 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
699 struct drm_device *dev = ring->dev;
702 if (IS_I830(dev) || IS_845G(dev)) {
703 ret = intel_ring_begin(ring, 4);
707 intel_ring_emit(ring, MI_BATCH_BUFFER);
708 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
709 intel_ring_emit(ring, offset + len - 8);
710 intel_ring_emit(ring, 0);
712 ret = intel_ring_begin(ring, 2);
716 if (INTEL_INFO(dev)->gen >= 4) {
717 intel_ring_emit(ring,
718 MI_BATCH_BUFFER_START | (2 << 6) |
719 MI_BATCH_NON_SECURE_I965);
720 intel_ring_emit(ring, offset);
722 intel_ring_emit(ring,
723 MI_BATCH_BUFFER_START | (2 << 6));
724 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
727 intel_ring_advance(ring);
732 static void cleanup_status_page(struct intel_ring_buffer *ring)
734 drm_i915_private_t *dev_priv = ring->dev->dev_private;
735 struct drm_i915_gem_object *obj;
737 obj = ring->status_page.obj;
741 kunmap(obj->pages[0]);
742 i915_gem_object_unpin(obj);
743 drm_gem_object_unreference(&obj->base);
744 ring->status_page.obj = NULL;
746 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
749 static int init_status_page(struct intel_ring_buffer *ring)
751 struct drm_device *dev = ring->dev;
752 drm_i915_private_t *dev_priv = dev->dev_private;
753 struct drm_i915_gem_object *obj;
756 obj = i915_gem_alloc_object(dev, 4096);
758 DRM_ERROR("Failed to allocate status page\n");
762 obj->cache_level = I915_CACHE_LLC;
764 ret = i915_gem_object_pin(obj, 4096, true);
769 ring->status_page.gfx_addr = obj->gtt_offset;
770 ring->status_page.page_addr = kmap(obj->pages[0]);
771 if (ring->status_page.page_addr == NULL) {
772 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
775 ring->status_page.obj = obj;
776 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
778 intel_ring_setup_status_page(ring);
779 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
780 ring->name, ring->status_page.gfx_addr);
785 i915_gem_object_unpin(obj);
787 drm_gem_object_unreference(&obj->base);
792 int intel_init_ring_buffer(struct drm_device *dev,
793 struct intel_ring_buffer *ring)
795 struct drm_i915_gem_object *obj;
799 INIT_LIST_HEAD(&ring->active_list);
800 INIT_LIST_HEAD(&ring->request_list);
801 INIT_LIST_HEAD(&ring->gpu_write_list);
803 init_waitqueue_head(&ring->irq_queue);
804 spin_lock_init(&ring->irq_lock);
807 if (I915_NEED_GFX_HWS(dev)) {
808 ret = init_status_page(ring);
813 obj = i915_gem_alloc_object(dev, ring->size);
815 DRM_ERROR("Failed to allocate ringbuffer\n");
822 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
826 ring->map.size = ring->size;
827 ring->map.offset = dev->agp->base + obj->gtt_offset;
832 drm_core_ioremap_wc(&ring->map, dev);
833 if (ring->map.handle == NULL) {
834 DRM_ERROR("Failed to map ringbuffer.\n");
839 ring->virtual_start = ring->map.handle;
840 ret = ring->init(ring);
844 /* Workaround an erratum on the i830 which causes a hang if
845 * the TAIL pointer points to within the last 2 cachelines
848 ring->effective_size = ring->size;
849 if (IS_I830(ring->dev))
850 ring->effective_size -= 128;
855 drm_core_ioremapfree(&ring->map, dev);
857 i915_gem_object_unpin(obj);
859 drm_gem_object_unreference(&obj->base);
862 cleanup_status_page(ring);
866 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
868 struct drm_i915_private *dev_priv;
871 if (ring->obj == NULL)
874 /* Disable the ring buffer. The ring must be idle at this point */
875 dev_priv = ring->dev->dev_private;
876 ret = intel_wait_ring_idle(ring);
878 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
881 I915_WRITE_CTL(ring, 0);
883 drm_core_ioremapfree(&ring->map, ring->dev);
885 i915_gem_object_unpin(ring->obj);
886 drm_gem_object_unreference(&ring->obj->base);
892 cleanup_status_page(ring);
895 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
898 int rem = ring->size - ring->tail;
900 if (ring->space < rem) {
901 int ret = intel_wait_ring_buffer(ring, rem);
906 virt = (unsigned int *)(ring->virtual_start + ring->tail);
914 ring->space = ring_space(ring);
919 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
921 struct drm_device *dev = ring->dev;
922 struct drm_i915_private *dev_priv = dev->dev_private;
926 /* If the reported head position has wrapped or hasn't advanced,
927 * fallback to the slow and accurate path.
929 head = intel_read_status_page(ring, 4);
930 if (head > ring->head) {
932 ring->space = ring_space(ring);
933 if (ring->space >= n)
937 trace_i915_ring_wait_begin(ring);
938 end = jiffies + 3 * HZ;
940 ring->head = I915_READ_HEAD(ring);
941 ring->space = ring_space(ring);
942 if (ring->space >= n) {
943 trace_i915_ring_wait_end(ring);
947 if (dev->primary->master) {
948 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
949 if (master_priv->sarea_priv)
950 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
954 if (atomic_read(&dev_priv->mm.wedged))
956 } while (!time_after(jiffies, end));
957 trace_i915_ring_wait_end(ring);
961 int intel_ring_begin(struct intel_ring_buffer *ring,
964 struct drm_i915_private *dev_priv = ring->dev->dev_private;
965 int n = 4*num_dwords;
968 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
971 if (unlikely(ring->tail + n > ring->effective_size)) {
972 ret = intel_wrap_ring_buffer(ring);
977 if (unlikely(ring->space < n)) {
978 ret = intel_wait_ring_buffer(ring, n);
987 void intel_ring_advance(struct intel_ring_buffer *ring)
989 ring->tail &= ring->size - 1;
990 ring->write_tail(ring, ring->tail);
993 static const struct intel_ring_buffer render_ring = {
994 .name = "render ring",
996 .mmio_base = RENDER_RING_BASE,
997 .size = 32 * PAGE_SIZE,
998 .init = init_render_ring,
999 .write_tail = ring_write_tail,
1000 .flush = render_ring_flush,
1001 .add_request = render_ring_add_request,
1002 .get_seqno = ring_get_seqno,
1003 .irq_get = render_ring_get_irq,
1004 .irq_put = render_ring_put_irq,
1005 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1006 .cleanup = render_ring_cleanup,
1009 /* ring buffer for bit-stream decoder */
1011 static const struct intel_ring_buffer bsd_ring = {
1014 .mmio_base = BSD_RING_BASE,
1015 .size = 32 * PAGE_SIZE,
1016 .init = init_ring_common,
1017 .write_tail = ring_write_tail,
1018 .flush = bsd_ring_flush,
1019 .add_request = ring_add_request,
1020 .get_seqno = ring_get_seqno,
1021 .irq_get = bsd_ring_get_irq,
1022 .irq_put = bsd_ring_put_irq,
1023 .dispatch_execbuffer = ring_dispatch_execbuffer,
1027 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1030 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1032 /* Every tail move must follow the sequence below */
1033 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1034 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1035 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1036 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1038 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1039 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1041 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1043 I915_WRITE_TAIL(ring, value);
1044 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1045 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1046 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1049 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1050 u32 invalidate, u32 flush)
1055 ret = intel_ring_begin(ring, 4);
1060 if (invalidate & I915_GEM_GPU_DOMAINS)
1061 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1062 intel_ring_emit(ring, cmd);
1063 intel_ring_emit(ring, 0);
1064 intel_ring_emit(ring, 0);
1065 intel_ring_emit(ring, MI_NOOP);
1066 intel_ring_advance(ring);
1071 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1072 u32 offset, u32 len)
1076 ret = intel_ring_begin(ring, 2);
1080 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1081 /* bit0-7 is the length on GEN6+ */
1082 intel_ring_emit(ring, offset);
1083 intel_ring_advance(ring);
1089 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1091 return gen6_ring_get_irq(ring,
1093 GEN6_RENDER_USER_INTERRUPT);
1097 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1099 return gen6_ring_put_irq(ring,
1101 GEN6_RENDER_USER_INTERRUPT);
1105 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1107 return gen6_ring_get_irq(ring,
1108 GT_GEN6_BSD_USER_INTERRUPT,
1109 GEN6_BSD_USER_INTERRUPT);
1113 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1115 return gen6_ring_put_irq(ring,
1116 GT_GEN6_BSD_USER_INTERRUPT,
1117 GEN6_BSD_USER_INTERRUPT);
1120 /* ring buffer for Video Codec for Gen6+ */
1121 static const struct intel_ring_buffer gen6_bsd_ring = {
1122 .name = "gen6 bsd ring",
1124 .mmio_base = GEN6_BSD_RING_BASE,
1125 .size = 32 * PAGE_SIZE,
1126 .init = init_ring_common,
1127 .write_tail = gen6_bsd_ring_write_tail,
1128 .flush = gen6_ring_flush,
1129 .add_request = gen6_add_request,
1130 .get_seqno = ring_get_seqno,
1131 .irq_get = gen6_bsd_ring_get_irq,
1132 .irq_put = gen6_bsd_ring_put_irq,
1133 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1136 /* Blitter support (SandyBridge+) */
1139 blt_ring_get_irq(struct intel_ring_buffer *ring)
1141 return gen6_ring_get_irq(ring,
1142 GT_BLT_USER_INTERRUPT,
1143 GEN6_BLITTER_USER_INTERRUPT);
1147 blt_ring_put_irq(struct intel_ring_buffer *ring)
1149 gen6_ring_put_irq(ring,
1150 GT_BLT_USER_INTERRUPT,
1151 GEN6_BLITTER_USER_INTERRUPT);
1155 /* Workaround for some stepping of SNB,
1156 * each time when BLT engine ring tail moved,
1157 * the first command in the ring to be parsed
1158 * should be MI_BATCH_BUFFER_START
1160 #define NEED_BLT_WORKAROUND(dev) \
1161 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1163 static inline struct drm_i915_gem_object *
1164 to_blt_workaround(struct intel_ring_buffer *ring)
1166 return ring->private;
1169 static int blt_ring_init(struct intel_ring_buffer *ring)
1171 if (NEED_BLT_WORKAROUND(ring->dev)) {
1172 struct drm_i915_gem_object *obj;
1176 obj = i915_gem_alloc_object(ring->dev, 4096);
1180 ret = i915_gem_object_pin(obj, 4096, true);
1182 drm_gem_object_unreference(&obj->base);
1186 ptr = kmap(obj->pages[0]);
1187 *ptr++ = MI_BATCH_BUFFER_END;
1189 kunmap(obj->pages[0]);
1191 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1193 i915_gem_object_unpin(obj);
1194 drm_gem_object_unreference(&obj->base);
1198 ring->private = obj;
1201 return init_ring_common(ring);
1204 static int blt_ring_begin(struct intel_ring_buffer *ring,
1207 if (ring->private) {
1208 int ret = intel_ring_begin(ring, num_dwords+2);
1212 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1213 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1217 return intel_ring_begin(ring, 4);
1220 static int blt_ring_flush(struct intel_ring_buffer *ring,
1221 u32 invalidate, u32 flush)
1226 ret = blt_ring_begin(ring, 4);
1231 if (invalidate & I915_GEM_DOMAIN_RENDER)
1232 cmd |= MI_INVALIDATE_TLB;
1233 intel_ring_emit(ring, cmd);
1234 intel_ring_emit(ring, 0);
1235 intel_ring_emit(ring, 0);
1236 intel_ring_emit(ring, MI_NOOP);
1237 intel_ring_advance(ring);
1241 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1246 i915_gem_object_unpin(ring->private);
1247 drm_gem_object_unreference(ring->private);
1248 ring->private = NULL;
1251 static const struct intel_ring_buffer gen6_blt_ring = {
1254 .mmio_base = BLT_RING_BASE,
1255 .size = 32 * PAGE_SIZE,
1256 .init = blt_ring_init,
1257 .write_tail = ring_write_tail,
1258 .flush = blt_ring_flush,
1259 .add_request = gen6_add_request,
1260 .get_seqno = ring_get_seqno,
1261 .irq_get = blt_ring_get_irq,
1262 .irq_put = blt_ring_put_irq,
1263 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1264 .cleanup = blt_ring_cleanup,
1267 int intel_init_render_ring_buffer(struct drm_device *dev)
1269 drm_i915_private_t *dev_priv = dev->dev_private;
1270 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1272 *ring = render_ring;
1273 if (INTEL_INFO(dev)->gen >= 6) {
1274 ring->add_request = gen6_add_request;
1275 ring->irq_get = gen6_render_ring_get_irq;
1276 ring->irq_put = gen6_render_ring_put_irq;
1277 } else if (IS_GEN5(dev)) {
1278 ring->add_request = pc_render_add_request;
1279 ring->get_seqno = pc_render_get_seqno;
1282 if (!I915_NEED_GFX_HWS(dev)) {
1283 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1284 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1287 return intel_init_ring_buffer(dev, ring);
1290 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1292 drm_i915_private_t *dev_priv = dev->dev_private;
1293 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1295 *ring = render_ring;
1296 if (INTEL_INFO(dev)->gen >= 6) {
1297 ring->add_request = gen6_add_request;
1298 ring->irq_get = gen6_render_ring_get_irq;
1299 ring->irq_put = gen6_render_ring_put_irq;
1300 } else if (IS_GEN5(dev)) {
1301 ring->add_request = pc_render_add_request;
1302 ring->get_seqno = pc_render_get_seqno;
1306 INIT_LIST_HEAD(&ring->active_list);
1307 INIT_LIST_HEAD(&ring->request_list);
1308 INIT_LIST_HEAD(&ring->gpu_write_list);
1311 ring->effective_size = ring->size;
1312 if (IS_I830(ring->dev))
1313 ring->effective_size -= 128;
1315 ring->map.offset = start;
1316 ring->map.size = size;
1318 ring->map.flags = 0;
1321 drm_core_ioremap_wc(&ring->map, dev);
1322 if (ring->map.handle == NULL) {
1323 DRM_ERROR("can not ioremap virtual address for"
1328 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1332 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1334 drm_i915_private_t *dev_priv = dev->dev_private;
1335 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1338 *ring = gen6_bsd_ring;
1342 return intel_init_ring_buffer(dev, ring);
1345 int intel_init_blt_ring_buffer(struct drm_device *dev)
1347 drm_i915_private_t *dev_priv = dev->dev_private;
1348 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1350 *ring = gen6_blt_ring;
1352 return intel_init_ring_buffer(dev, ring);