drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 /*
  72  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  73  * address of the TRB.
  74  */
  75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  76                 union xhci_trb *trb)
  77 {
  78         unsigned long segment_offset;
  79
  80         if (!seg || !trb || trb < seg->trbs)
  81                 return 0;
  82         /* offset in TRBs */
  83         segment_offset = trb - seg->trbs;
  84         if (segment_offset > TRBS_PER_SEGMENT)
  85                 return 0;
  86         return seg->dma + (segment_offset * sizeof(*trb));
  87 }
  88
  89 /* Does this link TRB point to the first segment in a ring,
  90  * or was the previous TRB the last TRB on the last segment in the ERST?
  91  */
  92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  93                 struct xhci_segment *seg, union xhci_trb *trb)
  94 {
  95         if (ring == xhci->event_ring)
  96                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  97                         (seg->next == xhci->event_ring->first_seg);
  98         else
  99                 return trb->link.control & LINK_TOGGLE;
 100 }
 101
 102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 103  * segment?  I.e. would the updated event TRB pointer step off the end of the
 104  * event seg?
 105  */
 106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 107                 struct xhci_segment *seg, union xhci_trb *trb)
 108 {
 109         if (ring == xhci->event_ring)
 110                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 111         else
 112                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 113 }
 114
 115 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
 116 {
 117         struct xhci_link_trb *link = &ring->enqueue->link;
 118         return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
 119 }
 120
 121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 122  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 123  * effect the ring dequeue or enqueue pointers.
 124  */
 125 static void next_trb(struct xhci_hcd *xhci,
 126                 struct xhci_ring *ring,
 127                 struct xhci_segment **seg,
 128                 union xhci_trb **trb)
 129 {
 130         if (last_trb(xhci, ring, *seg, *trb)) {
 131                 *seg = (*seg)->next;
 132                 *trb = ((*seg)->trbs);
 133         } else {
 134                 *trb = (*trb)++;
 135         }
 136 }
 137
 138 /*
 139  * See Cycle bit rules. SW is the consumer for the event ring only.
 140  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 141  */
 142 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 143 {
 144         union xhci_trb *next = ++(ring->dequeue);
 145         unsigned long long addr;
 146
 147         ring->deq_updates++;
 148         /* Update the dequeue pointer further if that was a link TRB or we're at
 149          * the end of an event ring segment (which doesn't have link TRBS)
 150          */
 151         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 152                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 153                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 154                         if (!in_interrupt())
 155                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 156                                                 ring,
 157                                                 (unsigned int) ring->cycle_state);
 158                 }
 159                 ring->deq_seg = ring->deq_seg->next;
 160                 ring->dequeue = ring->deq_seg->trbs;
 161                 next = ring->dequeue;
 162         }
 163         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 164         if (ring == xhci->event_ring)
 165                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 166         else if (ring == xhci->cmd_ring)
 167                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 168         else
 169                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 170 }
 171
 172 /*
 173  * See Cycle bit rules. SW is the consumer for the event ring only.
 174  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 175  *
 176  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 177  * chain bit is set), then set the chain bit in all the following link TRBs.
 178  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 179  * have their chain bit cleared (so that each Link TRB is a separate TD).
 180  *
 181  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 182  * set, but other sections talk about dealing with the chain bit set.  This was
 183  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 184  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 185  *
 186  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 187  *                      prepare_transfer()?
 188  */
 189 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 190                 bool consumer, bool more_trbs_coming)
 191 {
 192         u32 chain;
 193         union xhci_trb *next;
 194         unsigned long long addr;
 195
 196         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 197         next = ++(ring->enqueue);
 198
 199         ring->enq_updates++;
 200         /* Update the dequeue pointer further if that was a link TRB or we're at
 201          * the end of an event ring segment (which doesn't have link TRBS)
 202          */
 203         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 204                 if (!consumer) {
 205                         if (ring != xhci->event_ring) {
 206                                 /*
 207                                  * If the caller doesn't plan on enqueueing more
 208                                  * TDs before ringing the doorbell, then we
 209                                  * don't want to give the link TRB to the
 210                                  * hardware just yet.  We'll give the link TRB
 211                                  * back in prepare_ring() just before we enqueue
 212                                  * the TD at the top of the ring.
 213                                  */
 214                                 if (!chain && !more_trbs_coming)
 215                                         break;
 216
 217                                 /* If we're not dealing with 0.95 hardware,
 218                                  * carry over the chain bit of the previous TRB
 219                                  * (which may mean the chain bit is cleared).
 220                                  */
 221                                 if (!xhci_link_trb_quirk(xhci)) {
 222                                         next->link.control &= ~TRB_CHAIN;
 223                                         next->link.control |= chain;
 224                                 }
 225                                 /* Give this link TRB to the hardware */
 226                                 wmb();
 227                                 next->link.control ^= TRB_CYCLE;
 228                         }
 229                         /* Toggle the cycle bit after the last ring segment. */
 230                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 231                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 232                                 if (!in_interrupt())
 233                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 234                                                         ring,
 235                                                         (unsigned int) ring->cycle_state);
 236                         }
 237                 }
 238                 ring->enq_seg = ring->enq_seg->next;
 239                 ring->enqueue = ring->enq_seg->trbs;
 240                 next = ring->enqueue;
 241         }
 242         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 243         if (ring == xhci->event_ring)
 244                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 245         else if (ring == xhci->cmd_ring)
 246                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 247         else
 248                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 249 }
 250
 251 /*
 252  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 253  * above.
 254  * FIXME: this would be simpler and faster if we just kept track of the number
 255  * of free TRBs in a ring.
 256  */
 257 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 258                 unsigned int num_trbs)
 259 {
 260         int i;
 261         union xhci_trb *enq = ring->enqueue;
 262         struct xhci_segment *enq_seg = ring->enq_seg;
 263         struct xhci_segment *cur_seg;
 264         unsigned int left_on_ring;
 265
 266         /* If we are currently pointing to a link TRB, advance the
 267          * enqueue pointer before checking for space */
 268         while (last_trb(xhci, ring, enq_seg, enq)) {
 269                 enq_seg = enq_seg->next;
 270                 enq = enq_seg->trbs;
 271         }
 272
 273         /* Check if ring is empty */
 274         if (enq == ring->dequeue) {
 275                 /* Can't use link trbs */
 276                 left_on_ring = TRBS_PER_SEGMENT - 1;
 277                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 278                                 cur_seg = cur_seg->next)
 279                         left_on_ring += TRBS_PER_SEGMENT - 1;
 280
 281                 /* Always need one TRB free in the ring. */
 282                 left_on_ring -= 1;
 283                 if (num_trbs > left_on_ring) {
 284                         xhci_warn(xhci, "Not enough room on ring; "
 285                                         "need %u TRBs, %u TRBs left\n",
 286                                         num_trbs, left_on_ring);
 287                         return 0;
 288                 }
 289                 return 1;
 290         }
 291         /* Make sure there's an extra empty TRB available */
 292         for (i = 0; i <= num_trbs; ++i) {
 293                 if (enq == ring->dequeue)
 294                         return 0;
 295                 enq++;
 296                 while (last_trb(xhci, ring, enq_seg, enq)) {
 297                         enq_seg = enq_seg->next;
 298                         enq = enq_seg->trbs;
 299                 }
 300         }
 301         return 1;
 302 }
 303
 304 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 305 {
 306         u64 temp;
 307         dma_addr_t deq;
 308
 309         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 310                         xhci->event_ring->dequeue);
 311         if (deq == 0 && !in_interrupt())
 312                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 313                                 "dequeue ptr.\n");
 314         /* Update HC event ring dequeue pointer */
 315         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 316         temp &= ERST_PTR_MASK;
 317         /* Don't clear the EHB bit (which is RW1C) because
 318          * there might be more events to service.
 319          */
 320         temp &= ~ERST_EHB;
 321         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 322         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 323                         &xhci->ir_set->erst_dequeue);
 324 }
 325
 326 /* Ring the host controller doorbell after placing a command on the ring */
 327 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 328 {
 329         u32 temp;
 330
 331         xhci_dbg(xhci, "// Ding dong!\n");
 332         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 333         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 334         /* Flush PCI posted writes */
 335         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 336 }
 337
 338 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 339                 unsigned int slot_id,
 340                 unsigned int ep_index,
 341                 unsigned int stream_id)
 342 {
 343         struct xhci_virt_ep *ep;
 344         unsigned int ep_state;
 345         u32 field;
 346         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 347
 348         ep = &xhci->devs[slot_id]->eps[ep_index];
 349         ep_state = ep->ep_state;
 350         /* Don't ring the doorbell for this endpoint if there are pending
 351          * cancellations because the we don't want to interrupt processing.
 352          * We don't want to restart any stream rings if there's a set dequeue
 353          * pointer command pending because the device can choose to start any
 354          * stream once the endpoint is on the HW schedule.
 355          * FIXME - check all the stream rings for pending cancellations.
 356          */
 357         if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
 358                         && !(ep_state & EP_HALTED)) {
 359                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 360                 field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id);
 361                 xhci_writel(xhci, field, db_addr);
 362                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 363                  * isn't time-critical and we shouldn't make the CPU wait for
 364                  * the flush.
 365                  */
 366                 xhci_readl(xhci, db_addr);
 367         }
 368 }
 369
 370 /* Ring the doorbell for any rings with pending URBs */
 371 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 372                 unsigned int slot_id,
 373                 unsigned int ep_index)
 374 {
 375         unsigned int stream_id;
 376         struct xhci_virt_ep *ep;
 377
 378         ep = &xhci->devs[slot_id]->eps[ep_index];
 379
 380         /* A ring has pending URBs if its TD list is not empty */
 381         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 382                 if (!(list_empty(&ep->ring->td_list)))
 383                         ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 384                 return;
 385         }
 386
 387         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 388                         stream_id++) {
 389                 struct xhci_stream_info *stream_info = ep->stream_info;
 390                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 391                         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
 392         }
 393 }
 394
 395 /*
 396  * Find the segment that trb is in.  Start searching in start_seg.
 397  * If we must move past a segment that has a link TRB with a toggle cycle state
 398  * bit set, then we will toggle the value pointed at by cycle_state.
 399  */
 400 static struct xhci_segment *find_trb_seg(
 401                 struct xhci_segment *start_seg,
 402                 union xhci_trb  *trb, int *cycle_state)
 403 {
 404         struct xhci_segment *cur_seg = start_seg;
 405         struct xhci_generic_trb *generic_trb;
 406
 407         while (cur_seg->trbs > trb ||
 408                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 409                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 410                 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
 411                                 TRB_TYPE(TRB_LINK) &&
 412                                 (generic_trb->field[3] & LINK_TOGGLE))
 413                         *cycle_state = ~(*cycle_state) & 0x1;
 414                 cur_seg = cur_seg->next;
 415                 if (cur_seg == start_seg)
 416                         /* Looped over the entire list.  Oops! */
 417                         return NULL;
 418         }
 419         return cur_seg;
 420 }
 421
 422 /*
 423  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 424  * Record the new state of the xHC's endpoint ring dequeue segment,
 425  * dequeue pointer, and new consumer cycle state in state.
 426  * Update our internal representation of the ring's dequeue pointer.
 427  *
 428  * We do this in three jumps:
 429  *  - First we update our new ring state to be the same as when the xHC stopped.
 430  *  - Then we traverse the ring to find the segment that contains
 431  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 432  *    any link TRBs with the toggle cycle bit set.
 433  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 434  *    if we've moved it past a link TRB with the toggle cycle bit set.
 435  */
 436 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 437                 unsigned int slot_id, unsigned int ep_index,
 438                 unsigned int stream_id, struct xhci_td *cur_td,
 439                 struct xhci_dequeue_state *state)
 440 {
 441         struct xhci_virt_device *dev = xhci->devs[slot_id];
 442         struct xhci_ring *ep_ring;
 443         struct xhci_generic_trb *trb;
 444         struct xhci_ep_ctx *ep_ctx;
 445         dma_addr_t addr;
 446
 447         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 448                         ep_index, stream_id);
 449         if (!ep_ring) {
 450                 xhci_warn(xhci, "WARN can't find new dequeue state "
 451                                 "for invalid stream ID %u.\n",
 452                                 stream_id);
 453                 return;
 454         }
 455         state->new_cycle_state = 0;
 456         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 457         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 458                         dev->eps[ep_index].stopped_trb,
 459                         &state->new_cycle_state);
 460         if (!state->new_deq_seg)
 461                 BUG();
 462         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 463         xhci_dbg(xhci, "Finding endpoint context\n");
 464         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 465         state->new_cycle_state = 0x1 & ep_ctx->deq;
 466
 467         state->new_deq_ptr = cur_td->last_trb;
 468         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 469         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 470                         state->new_deq_ptr,
 471                         &state->new_cycle_state);
 472         if (!state->new_deq_seg)
 473                 BUG();
 474
 475         trb = &state->new_deq_ptr->generic;
 476         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 477                                 (trb->field[3] & LINK_TOGGLE))
 478                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 479         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 480
 481         /* Don't update the ring cycle state for the producer (us). */
 482         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 483                         state->new_deq_seg);
 484         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 485         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 486                         (unsigned long long) addr);
 487         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 488         ep_ring->dequeue = state->new_deq_ptr;
 489         ep_ring->deq_seg = state->new_deq_seg;
 490 }
 491
 492 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 493                 struct xhci_td *cur_td)
 494 {
 495         struct xhci_segment *cur_seg;
 496         union xhci_trb *cur_trb;
 497
 498         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 499                         true;
 500                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 501                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 502                                 TRB_TYPE(TRB_LINK)) {
 503                         /* Unchain any chained Link TRBs, but
 504                          * leave the pointers intact.
 505                          */
 506                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 507                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 508                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 509                                         "in seg %p (0x%llx dma)\n",
 510                                         cur_trb,
 511                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 512                                         cur_seg,
 513                                         (unsigned long long)cur_seg->dma);
 514                 } else {
 515                         cur_trb->generic.field[0] = 0;
 516                         cur_trb->generic.field[1] = 0;
 517                         cur_trb->generic.field[2] = 0;
 518                         /* Preserve only the cycle bit of this TRB */
 519                         cur_trb->generic.field[3] &= TRB_CYCLE;
 520                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 521                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 522                                         "in seg %p (0x%llx dma)\n",
 523                                         cur_trb,
 524                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 525                                         cur_seg,
 526                                         (unsigned long long)cur_seg->dma);
 527                 }
 528                 if (cur_trb == cur_td->last_trb)
 529                         break;
 530         }
 531 }
 532
 533 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 534                 unsigned int ep_index, unsigned int stream_id,
 535                 struct xhci_segment *deq_seg,
 536                 union xhci_trb *deq_ptr, u32 cycle_state);
 537
 538 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 539                 unsigned int slot_id, unsigned int ep_index,
 540                 unsigned int stream_id,
 541                 struct xhci_dequeue_state *deq_state)
 542 {
 543         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 544
 545         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 546                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 547                         deq_state->new_deq_seg,
 548                         (unsigned long long)deq_state->new_deq_seg->dma,
 549                         deq_state->new_deq_ptr,
 550                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 551                         deq_state->new_cycle_state);
 552         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 553                         deq_state->new_deq_seg,
 554                         deq_state->new_deq_ptr,
 555                         (u32) deq_state->new_cycle_state);
 556         /* Stop the TD queueing code from ringing the doorbell until
 557          * this command completes.  The HC won't set the dequeue pointer
 558          * if the ring is running, and ringing the doorbell starts the
 559          * ring running.
 560          */
 561         ep->ep_state |= SET_DEQ_PENDING;
 562 }
 563
 564 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 565                 struct xhci_virt_ep *ep)
 566 {
 567         ep->ep_state &= ~EP_HALT_PENDING;
 568         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 569          * timer is running on another CPU, we don't decrement stop_cmds_pending
 570          * (since we didn't successfully stop the watchdog timer).
 571          */
 572         if (del_timer(&ep->stop_cmd_timer))
 573                 ep->stop_cmds_pending--;
 574 }
 575
 576 /* Must be called with xhci->lock held in interrupt context */
 577 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 578                 struct xhci_td *cur_td, int status, char *adjective)
 579 {
 580         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 581         struct urb      *urb;
 582         struct urb_priv *urb_priv;
 583
 584         urb = cur_td->urb;
 585         urb_priv = urb->hcpriv;
 586         urb_priv->td_cnt++;
 587
 588         /* Only giveback urb when this is the last td in urb */
 589         if (urb_priv->td_cnt == urb_priv->length) {
 590                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 591                 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
 592
 593                 spin_unlock(&xhci->lock);
 594                 usb_hcd_giveback_urb(hcd, urb, status);
 595                 xhci_urb_free_priv(xhci, urb_priv);
 596                 spin_lock(&xhci->lock);
 597                 xhci_dbg(xhci, "%s URB given back\n", adjective);
 598         }
 599 }
 600
 601 /*
 602  * When we get a command completion for a Stop Endpoint Command, we need to
 603  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 604  *
 605  *  1. If the HW was in the middle of processing the TD that needs to be
 606  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 607  *     in the TD with a Set Dequeue Pointer Command.
 608  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 609  *     bit cleared) so that the HW will skip over them.
 610  */
 611 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 612                 union xhci_trb *trb)
 613 {
 614         unsigned int slot_id;
 615         unsigned int ep_index;
 616         struct xhci_ring *ep_ring;
 617         struct xhci_virt_ep *ep;
 618         struct list_head *entry;
 619         struct xhci_td *cur_td = NULL;
 620         struct xhci_td *last_unlinked_td;
 621
 622         struct xhci_dequeue_state deq_state;
 623
 624         memset(&deq_state, 0, sizeof(deq_state));
 625         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 626         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 627         ep = &xhci->devs[slot_id]->eps[ep_index];
 628
 629         if (list_empty(&ep->cancelled_td_list)) {
 630                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 631                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 632                 return;
 633         }
 634
 635         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 636          * We have the xHCI lock, so nothing can modify this list until we drop
 637          * it.  We're also in the event handler, so we can't get re-interrupted
 638          * if another Stop Endpoint command completes
 639          */
 640         list_for_each(entry, &ep->cancelled_td_list) {
 641                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 642                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 643                                 cur_td->first_trb,
 644                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 645                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 646                 if (!ep_ring) {
 647                         /* This shouldn't happen unless a driver is mucking
 648                          * with the stream ID after submission.  This will
 649                          * leave the TD on the hardware ring, and the hardware
 650                          * will try to execute it, and may access a buffer
 651                          * that has already been freed.  In the best case, the
 652                          * hardware will execute it, and the event handler will
 653                          * ignore the completion event for that TD, since it was
 654                          * removed from the td_list for that endpoint.  In
 655                          * short, don't muck with the stream ID after
 656                          * submission.
 657                          */
 658                         xhci_warn(xhci, "WARN Cancelled URB %p "
 659                                         "has invalid stream ID %u.\n",
 660                                         cur_td->urb,
 661                                         cur_td->urb->stream_id);
 662                         goto remove_finished_td;
 663                 }
 664                 /*
 665                  * If we stopped on the TD we need to cancel, then we have to
 666                  * move the xHC endpoint ring dequeue pointer past this TD.
 667                  */
 668                 if (cur_td == ep->stopped_td)
 669                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 670                                         cur_td->urb->stream_id,
 671                                         cur_td, &deq_state);
 672                 else
 673                         td_to_noop(xhci, ep_ring, cur_td);
 674 remove_finished_td:
 675                 /*
 676                  * The event handler won't see a completion for this TD anymore,
 677                  * so remove it from the endpoint ring's TD list.  Keep it in
 678                  * the cancelled TD list for URB completion later.
 679                  */
 680                 list_del(&cur_td->td_list);
 681         }
 682         last_unlinked_td = cur_td;
 683         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 684
 685         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 686         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 687                 xhci_queue_new_dequeue_state(xhci,
 688                                 slot_id, ep_index,
 689                                 ep->stopped_td->urb->stream_id,
 690                                 &deq_state);
 691                 xhci_ring_cmd_db(xhci);
 692         } else {
 693                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 694                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 695         }
 696         ep->stopped_td = NULL;
 697         ep->stopped_trb = NULL;
 698
 699         /*
 700          * Drop the lock and complete the URBs in the cancelled TD list.
 701          * New TDs to be cancelled might be added to the end of the list before
 702          * we can complete all the URBs for the TDs we already unlinked.
 703          * So stop when we've completed the URB for the last TD we unlinked.
 704          */
 705         do {
 706                 cur_td = list_entry(ep->cancelled_td_list.next,
 707                                 struct xhci_td, cancelled_td_list);
 708                 list_del(&cur_td->cancelled_td_list);
 709
 710                 /* Clean up the cancelled URB */
 711                 /* Doesn't matter what we pass for status, since the core will
 712                  * just overwrite it (because the URB has been unlinked).
 713                  */
 714                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 715
 716                 /* Stop processing the cancelled list if the watchdog timer is
 717                  * running.
 718                  */
 719                 if (xhci->xhc_state & XHCI_STATE_DYING)
 720                         return;
 721         } while (cur_td != last_unlinked_td);
 722
 723         /* Return to the event handler with xhci->lock re-acquired */
 724 }
 725
 726 /* Watchdog timer function for when a stop endpoint command fails to complete.
 727  * In this case, we assume the host controller is broken or dying or dead.  The
 728  * host may still be completing some other events, so we have to be careful to
 729  * let the event ring handler and the URB dequeueing/enqueueing functions know
 730  * through xhci->state.
 731  *
 732  * The timer may also fire if the host takes a very long time to respond to the
 733  * command, and the stop endpoint command completion handler cannot delete the
 734  * timer before the timer function is called.  Another endpoint cancellation may
 735  * sneak in before the timer function can grab the lock, and that may queue
 736  * another stop endpoint command and add the timer back.  So we cannot use a
 737  * simple flag to say whether there is a pending stop endpoint command for a
 738  * particular endpoint.
 739  *
 740  * Instead we use a combination of that flag and a counter for the number of
 741  * pending stop endpoint commands.  If the timer is the tail end of the last
 742  * stop endpoint command, and the endpoint's command is still pending, we assume
 743  * the host is dying.
 744  */
 745 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 746 {
 747         struct xhci_hcd *xhci;
 748         struct xhci_virt_ep *ep;
 749         struct xhci_virt_ep *temp_ep;
 750         struct xhci_ring *ring;
 751         struct xhci_td *cur_td;
 752         int ret, i, j;
 753
 754         ep = (struct xhci_virt_ep *) arg;
 755         xhci = ep->xhci;
 756
 757         spin_lock(&xhci->lock);
 758
 759         ep->stop_cmds_pending--;
 760         if (xhci->xhc_state & XHCI_STATE_DYING) {
 761                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 762                                 "xHCI as DYING, exiting.\n");
 763                 spin_unlock(&xhci->lock);
 764                 return;
 765         }
 766         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 767                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 768                                 "exiting.\n");
 769                 spin_unlock(&xhci->lock);
 770                 return;
 771         }
 772
 773         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 774         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 775         /* Oops, HC is dead or dying or at least not responding to the stop
 776          * endpoint command.
 777          */
 778         xhci->xhc_state |= XHCI_STATE_DYING;
 779         /* Disable interrupts from the host controller and start halting it */
 780         xhci_quiesce(xhci);
 781         spin_unlock(&xhci->lock);
 782
 783         ret = xhci_halt(xhci);
 784
 785         spin_lock(&xhci->lock);
 786         if (ret < 0) {
 787                 /* This is bad; the host is not responding to commands and it's
 788                  * not allowing itself to be halted.  At least interrupts are
 789                  * disabled, so we can set HC_STATE_HALT and notify the
 790                  * USB core.  But if we call usb_hc_died(), it will attempt to
 791                  * disconnect all device drivers under this host.  Those
 792                  * disconnect() methods will wait for all URBs to be unlinked,
 793                  * so we must complete them.
 794                  */
 795                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 796                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 797                 /* We could turn all TDs on the rings to no-ops.  This won't
 798                  * help if the host has cached part of the ring, and is slow if
 799                  * we want to preserve the cycle bit.  Skip it and hope the host
 800                  * doesn't touch the memory.
 801                  */
 802         }
 803         for (i = 0; i < MAX_HC_SLOTS; i++) {
 804                 if (!xhci->devs[i])
 805                         continue;
 806                 for (j = 0; j < 31; j++) {
 807                         temp_ep = &xhci->devs[i]->eps[j];
 808                         ring = temp_ep->ring;
 809                         if (!ring)
 810                                 continue;
 811                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 812                                         "ep index %u\n", i, j);
 813                         while (!list_empty(&ring->td_list)) {
 814                                 cur_td = list_first_entry(&ring->td_list,
 815                                                 struct xhci_td,
 816                                                 td_list);
 817                                 list_del(&cur_td->td_list);
 818                                 if (!list_empty(&cur_td->cancelled_td_list))
 819                                         list_del(&cur_td->cancelled_td_list);
 820                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 821                                                 -ESHUTDOWN, "killed");
 822                         }
 823                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 824                                 cur_td = list_first_entry(
 825                                                 &temp_ep->cancelled_td_list,
 826                                                 struct xhci_td,
 827                                                 cancelled_td_list);
 828                                 list_del(&cur_td->cancelled_td_list);
 829                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 830                                                 -ESHUTDOWN, "killed");
 831                         }
 832                 }
 833         }
 834         spin_unlock(&xhci->lock);
 835         xhci_to_hcd(xhci)->state = HC_STATE_HALT;
 836         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 837         usb_hc_died(xhci_to_hcd(xhci));
 838         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 839 }
 840
 841 /*
 842  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 843  * we need to clear the set deq pending flag in the endpoint ring state, so that
 844  * the TD queueing code can ring the doorbell again.  We also need to ring the
 845  * endpoint doorbell to restart the ring, but only if there aren't more
 846  * cancellations pending.
 847  */
 848 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 849                 struct xhci_event_cmd *event,
 850                 union xhci_trb *trb)
 851 {
 852         unsigned int slot_id;
 853         unsigned int ep_index;
 854         unsigned int stream_id;
 855         struct xhci_ring *ep_ring;
 856         struct xhci_virt_device *dev;
 857         struct xhci_ep_ctx *ep_ctx;
 858         struct xhci_slot_ctx *slot_ctx;
 859
 860         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 861         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 862         stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
 863         dev = xhci->devs[slot_id];
 864
 865         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 866         if (!ep_ring) {
 867                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 868                                 "freed stream ID %u\n",
 869                                 stream_id);
 870                 /* XXX: Harmless??? */
 871                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 872                 return;
 873         }
 874
 875         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 876         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 877
 878         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 879                 unsigned int ep_state;
 880                 unsigned int slot_state;
 881
 882                 switch (GET_COMP_CODE(event->status)) {
 883                 case COMP_TRB_ERR:
 884                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 885                                         "of stream ID configuration\n");
 886                         break;
 887                 case COMP_CTX_STATE:
 888                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 889                                         "to incorrect slot or ep state.\n");
 890                         ep_state = ep_ctx->ep_info;
 891                         ep_state &= EP_STATE_MASK;
 892                         slot_state = slot_ctx->dev_state;
 893                         slot_state = GET_SLOT_STATE(slot_state);
 894                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 895                                         slot_state, ep_state);
 896                         break;
 897                 case COMP_EBADSLT:
 898                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 899                                         "slot %u was not enabled.\n", slot_id);
 900                         break;
 901                 default:
 902                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 903                                         "completion code of %u.\n",
 904                                         GET_COMP_CODE(event->status));
 905                         break;
 906                 }
 907                 /* OK what do we do now?  The endpoint state is hosed, and we
 908                  * should never get to this point if the synchronization between
 909                  * queueing, and endpoint state are correct.  This might happen
 910                  * if the device gets disconnected after we've finished
 911                  * cancelling URBs, which might not be an error...
 912                  */
 913         } else {
 914                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 915                                 ep_ctx->deq);
 916         }
 917
 918         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 919         /* Restart any rings with pending URBs */
 920         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 921 }
 922
 923 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 924                 struct xhci_event_cmd *event,
 925                 union xhci_trb *trb)
 926 {
 927         int slot_id;
 928         unsigned int ep_index;
 929
 930         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 931         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 932         /* This command will only fail if the endpoint wasn't halted,
 933          * but we don't care.
 934          */
 935         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 936                         (unsigned int) GET_COMP_CODE(event->status));
 937
 938         /* HW with the reset endpoint quirk needs to have a configure endpoint
 939          * command complete before the endpoint can be used.  Queue that here
 940          * because the HW can't handle two commands being queued in a row.
 941          */
 942         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 943                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 944                 xhci_queue_configure_endpoint(xhci,
 945                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 946                                 false);
 947                 xhci_ring_cmd_db(xhci);
 948         } else {
 949                 /* Clear our internal halted state and restart the ring(s) */
 950                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 951                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 952         }
 953 }
 954
 955 /* Check to see if a command in the device's command queue matches this one.
 956  * Signal the completion or free the command, and return 1.  Return 0 if the
 957  * completed command isn't at the head of the command list.
 958  */
 959 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
 960                 struct xhci_virt_device *virt_dev,
 961                 struct xhci_event_cmd *event)
 962 {
 963         struct xhci_command *command;
 964
 965         if (list_empty(&virt_dev->cmd_list))
 966                 return 0;
 967
 968         command = list_entry(virt_dev->cmd_list.next,
 969                         struct xhci_command, cmd_list);
 970         if (xhci->cmd_ring->dequeue != command->command_trb)
 971                 return 0;
 972
 973         command->status =
 974                 GET_COMP_CODE(event->status);
 975         list_del(&command->cmd_list);
 976         if (command->completion)
 977                 complete(command->completion);
 978         else
 979                 xhci_free_command(xhci, command);
 980         return 1;
 981 }
 982
 983 static void handle_cmd_completion(struct xhci_hcd *xhci,
 984                 struct xhci_event_cmd *event)
 985 {
 986         int slot_id = TRB_TO_SLOT_ID(event->flags);
 987         u64 cmd_dma;
 988         dma_addr_t cmd_dequeue_dma;
 989         struct xhci_input_control_ctx *ctrl_ctx;
 990         struct xhci_virt_device *virt_dev;
 991         unsigned int ep_index;
 992         struct xhci_ring *ep_ring;
 993         unsigned int ep_state;
 994
 995         cmd_dma = event->cmd_trb;
 996         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 997                         xhci->cmd_ring->dequeue);
 998         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 999         if (cmd_dequeue_dma == 0) {
1000                 xhci->error_bitmask |= 1 << 4;
1001                 return;
1002         }
1003         /* Does the DMA address match our internal dequeue pointer address? */
1004         if (cmd_dma != (u64) cmd_dequeue_dma) {
1005                 xhci->error_bitmask |= 1 << 5;
1006                 return;
1007         }
1008         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1009         case TRB_TYPE(TRB_ENABLE_SLOT):
1010                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1011                         xhci->slot_id = slot_id;
1012                 else
1013                         xhci->slot_id = 0;
1014                 complete(&xhci->addr_dev);
1015                 break;
1016         case TRB_TYPE(TRB_DISABLE_SLOT):
1017                 if (xhci->devs[slot_id])
1018                         xhci_free_virt_device(xhci, slot_id);
1019                 break;
1020         case TRB_TYPE(TRB_CONFIG_EP):
1021                 virt_dev = xhci->devs[slot_id];
1022                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1023                         break;
1024                 /*
1025                  * Configure endpoint commands can come from the USB core
1026                  * configuration or alt setting changes, or because the HW
1027                  * needed an extra configure endpoint command after a reset
1028                  * endpoint command or streams were being configured.
1029                  * If the command was for a halted endpoint, the xHCI driver
1030                  * is not waiting on the configure endpoint command.
1031                  */
1032                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1033                                 virt_dev->in_ctx);
1034                 /* Input ctx add_flags are the endpoint index plus one */
1035                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1036                 /* A usb_set_interface() call directly after clearing a halted
1037                  * condition may race on this quirky hardware.  Not worth
1038                  * worrying about, since this is prototype hardware.  Not sure
1039                  * if this will work for streams, but streams support was
1040                  * untested on this prototype.
1041                  */
1042                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1043                                 ep_index != (unsigned int) -1 &&
1044                                 ctrl_ctx->add_flags - SLOT_FLAG ==
1045                                         ctrl_ctx->drop_flags) {
1046                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1047                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1048                         if (!(ep_state & EP_HALTED))
1049                                 goto bandwidth_change;
1050                         xhci_dbg(xhci, "Completed config ep cmd - "
1051                                         "last ep index = %d, state = %d\n",
1052                                         ep_index, ep_state);
1053                         /* Clear internal halted state and restart ring(s) */
1054                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1055                                 ~EP_HALTED;
1056                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1057                         break;
1058                 }
1059 bandwidth_change:
1060                 xhci_dbg(xhci, "Completed config ep cmd\n");
1061                 xhci->devs[slot_id]->cmd_status =
1062                         GET_COMP_CODE(event->status);
1063                 complete(&xhci->devs[slot_id]->cmd_completion);
1064                 break;
1065         case TRB_TYPE(TRB_EVAL_CONTEXT):
1066                 virt_dev = xhci->devs[slot_id];
1067                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1068                         break;
1069                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1070                 complete(&xhci->devs[slot_id]->cmd_completion);
1071                 break;
1072         case TRB_TYPE(TRB_ADDR_DEV):
1073                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1074                 complete(&xhci->addr_dev);
1075                 break;
1076         case TRB_TYPE(TRB_STOP_RING):
1077                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
1078                 break;
1079         case TRB_TYPE(TRB_SET_DEQ):
1080                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1081                 break;
1082         case TRB_TYPE(TRB_CMD_NOOP):
1083                 ++xhci->noops_handled;
1084                 break;
1085         case TRB_TYPE(TRB_RESET_EP):
1086                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1087                 break;
1088         case TRB_TYPE(TRB_RESET_DEV):
1089                 xhci_dbg(xhci, "Completed reset device command.\n");
1090                 slot_id = TRB_TO_SLOT_ID(
1091                                 xhci->cmd_ring->dequeue->generic.field[3]);
1092                 virt_dev = xhci->devs[slot_id];
1093                 if (virt_dev)
1094                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1095                 else
1096                         xhci_warn(xhci, "Reset device command completion "
1097                                         "for disabled slot %u\n", slot_id);
1098                 break;
1099         case TRB_TYPE(TRB_NEC_GET_FW):
1100                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1101                         xhci->error_bitmask |= 1 << 6;
1102                         break;
1103                 }
1104                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1105                                 NEC_FW_MAJOR(event->status),
1106                                 NEC_FW_MINOR(event->status));
1107                 break;
1108         default:
1109                 /* Skip over unknown commands on the event ring */
1110                 xhci->error_bitmask |= 1 << 6;
1111                 break;
1112         }
1113         inc_deq(xhci, xhci->cmd_ring, false);
1114 }
1115
1116 static void handle_vendor_event(struct xhci_hcd *xhci,
1117                 union xhci_trb *event)
1118 {
1119         u32 trb_type;
1120
1121         trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1122         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1123         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1124                 handle_cmd_completion(xhci, &event->event_cmd);
1125 }
1126
1127 static void handle_port_status(struct xhci_hcd *xhci,
1128                 union xhci_trb *event)
1129 {
1130         u32 port_id;
1131
1132         /* Port status change events always have a successful completion code */
1133         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1134                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1135                 xhci->error_bitmask |= 1 << 8;
1136         }
1137         /* FIXME: core doesn't care about all port link state changes yet */
1138         port_id = GET_PORT_ID(event->generic.field[0]);
1139         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1140
1141         /* Update event ring dequeue pointer before dropping the lock */
1142         inc_deq(xhci, xhci->event_ring, true);
1143         xhci_set_hc_event_deq(xhci);
1144
1145         spin_unlock(&xhci->lock);
1146         /* Pass this up to the core */
1147         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1148         spin_lock(&xhci->lock);
1149 }
1150
1151 /*
1152  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1153  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1154  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1155  * returns 0.
1156  */
1157 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1158                 union xhci_trb  *start_trb,
1159                 union xhci_trb  *end_trb,
1160                 dma_addr_t      suspect_dma)
1161 {
1162         dma_addr_t start_dma;
1163         dma_addr_t end_seg_dma;
1164         dma_addr_t end_trb_dma;
1165         struct xhci_segment *cur_seg;
1166
1167         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1168         cur_seg = start_seg;
1169
1170         do {
1171                 if (start_dma == 0)
1172                         return NULL;
1173                 /* We may get an event for a Link TRB in the middle of a TD */
1174                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1175                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1176                 /* If the end TRB isn't in this segment, this is set to 0 */
1177                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1178
1179                 if (end_trb_dma > 0) {
1180                         /* The end TRB is in this segment, so suspect should be here */
1181                         if (start_dma <= end_trb_dma) {
1182                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1183                                         return cur_seg;
1184                         } else {
1185                                 /* Case for one segment with
1186                                  * a TD wrapped around to the top
1187                                  */
1188                                 if ((suspect_dma >= start_dma &&
1189                                                         suspect_dma <= end_seg_dma) ||
1190                                                 (suspect_dma >= cur_seg->dma &&
1191                                                  suspect_dma <= end_trb_dma))
1192                                         return cur_seg;
1193                         }
1194                         return NULL;
1195                 } else {
1196                         /* Might still be somewhere in this segment */
1197                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1198                                 return cur_seg;
1199                 }
1200                 cur_seg = cur_seg->next;
1201                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1202         } while (cur_seg != start_seg);
1203
1204         return NULL;
1205 }
1206
1207 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1208                 unsigned int slot_id, unsigned int ep_index,
1209                 unsigned int stream_id,
1210                 struct xhci_td *td, union xhci_trb *event_trb)
1211 {
1212         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1213         ep->ep_state |= EP_HALTED;
1214         ep->stopped_td = td;
1215         ep->stopped_trb = event_trb;
1216         ep->stopped_stream = stream_id;
1217
1218         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1219         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1220
1221         ep->stopped_td = NULL;
1222         ep->stopped_trb = NULL;
1223         ep->stopped_stream = 0;
1224
1225         xhci_ring_cmd_db(xhci);
1226 }
1227
1228 /* Check if an error has halted the endpoint ring.  The class driver will
1229  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1230  * However, a babble and other errors also halt the endpoint ring, and the class
1231  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1232  * Ring Dequeue Pointer command manually.
1233  */
1234 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1235                 struct xhci_ep_ctx *ep_ctx,
1236                 unsigned int trb_comp_code)
1237 {
1238         /* TRB completion codes that may require a manual halt cleanup */
1239         if (trb_comp_code == COMP_TX_ERR ||
1240                         trb_comp_code == COMP_BABBLE ||
1241                         trb_comp_code == COMP_SPLIT_ERR)
1242                 /* The 0.96 spec says a babbling control endpoint
1243                  * is not halted. The 0.96 spec says it is.  Some HW
1244                  * claims to be 0.95 compliant, but it halts the control
1245                  * endpoint anyway.  Check if a babble halted the
1246                  * endpoint.
1247                  */
1248                 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1249                         return 1;
1250
1251         return 0;
1252 }
1253
1254 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1255 {
1256         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1257                 /* Vendor defined "informational" completion code,
1258                  * treat as not-an-error.
1259                  */
1260                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1261                                 trb_comp_code);
1262                 xhci_dbg(xhci, "Treating code as success.\n");
1263                 return 1;
1264         }
1265         return 0;
1266 }
1267
1268 /*
1269  * Finish the td processing, remove the td from td list;
1270  * Return 1 if the urb can be given back.
1271  */
1272 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1273         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1274         struct xhci_virt_ep *ep, int *status, bool skip)
1275 {
1276         struct xhci_virt_device *xdev;
1277         struct xhci_ring *ep_ring;
1278         unsigned int slot_id;
1279         int ep_index;
1280         struct urb *urb = NULL;
1281         struct xhci_ep_ctx *ep_ctx;
1282         int ret = 0;
1283         struct urb_priv *urb_priv;
1284         u32 trb_comp_code;
1285
1286         slot_id = TRB_TO_SLOT_ID(event->flags);
1287         xdev = xhci->devs[slot_id];
1288         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1289         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1290         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1291         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1292
1293         if (skip)
1294                 goto td_cleanup;
1295
1296         if (trb_comp_code == COMP_STOP_INVAL ||
1297                         trb_comp_code == COMP_STOP) {
1298                 /* The Endpoint Stop Command completion will take care of any
1299                  * stopped TDs.  A stopped TD may be restarted, so don't update
1300                  * the ring dequeue pointer or take this TD off any lists yet.
1301                  */
1302                 ep->stopped_td = td;
1303                 ep->stopped_trb = event_trb;
1304                 return 0;
1305         } else {
1306                 if (trb_comp_code == COMP_STALL) {
1307                         /* The transfer is completed from the driver's
1308                          * perspective, but we need to issue a set dequeue
1309                          * command for this stalled endpoint to move the dequeue
1310                          * pointer past the TD.  We can't do that here because
1311                          * the halt condition must be cleared first.  Let the
1312                          * USB class driver clear the stall later.
1313                          */
1314                         ep->stopped_td = td;
1315                         ep->stopped_trb = event_trb;
1316                         ep->stopped_stream = ep_ring->stream_id;
1317                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1318                                         ep_ctx, trb_comp_code)) {
1319                         /* Other types of errors halt the endpoint, but the
1320                          * class driver doesn't call usb_reset_endpoint() unless
1321                          * the error is -EPIPE.  Clear the halted status in the
1322                          * xHCI hardware manually.
1323                          */
1324                         xhci_cleanup_halted_endpoint(xhci,
1325                                         slot_id, ep_index, ep_ring->stream_id,
1326                                         td, event_trb);
1327                 } else {
1328                         /* Update ring dequeue pointer */
1329                         while (ep_ring->dequeue != td->last_trb)
1330                                 inc_deq(xhci, ep_ring, false);
1331                         inc_deq(xhci, ep_ring, false);
1332                 }
1333
1334 td_cleanup:
1335                 /* Clean up the endpoint's TD list */
1336                 urb = td->urb;
1337                 urb_priv = urb->hcpriv;
1338
1339                 /* Do one last check of the actual transfer length.
1340                  * If the host controller said we transferred more data than
1341                  * the buffer length, urb->actual_length will be a very big
1342                  * number (since it's unsigned).  Play it safe and say we didn't
1343                  * transfer anything.
1344                  */
1345                 if (urb->actual_length > urb->transfer_buffer_length) {
1346                         xhci_warn(xhci, "URB transfer length is wrong, "
1347                                         "xHC issue? req. len = %u, "
1348                                         "act. len = %u\n",
1349                                         urb->transfer_buffer_length,
1350                                         urb->actual_length);
1351                         urb->actual_length = 0;
1352                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1353                                 *status = -EREMOTEIO;
1354                         else
1355                                 *status = 0;
1356                 }
1357                 list_del(&td->td_list);
1358                 /* Was this TD slated to be cancelled but completed anyway? */
1359                 if (!list_empty(&td->cancelled_td_list))
1360                         list_del(&td->cancelled_td_list);
1361
1362                 urb_priv->td_cnt++;
1363                 /* Giveback the urb when all the tds are completed */
1364                 if (urb_priv->td_cnt == urb_priv->length)
1365                         ret = 1;
1366         }
1367
1368         return ret;
1369 }
1370
1371 /*
1372  * Process control tds, update urb status and actual_length.
1373  */
1374 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1375         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1376         struct xhci_virt_ep *ep, int *status)
1377 {
1378         struct xhci_virt_device *xdev;
1379         struct xhci_ring *ep_ring;
1380         unsigned int slot_id;
1381         int ep_index;
1382         struct xhci_ep_ctx *ep_ctx;
1383         u32 trb_comp_code;
1384
1385         slot_id = TRB_TO_SLOT_ID(event->flags);
1386         xdev = xhci->devs[slot_id];
1387         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1388         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1389         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1390         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1391
1392         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1393         switch (trb_comp_code) {
1394         case COMP_SUCCESS:
1395                 if (event_trb == ep_ring->dequeue) {
1396                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1397                                         "without IOC set??\n");
1398                         *status = -ESHUTDOWN;
1399                 } else if (event_trb != td->last_trb) {
1400                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1401                                         "without IOC set??\n");
1402                         *status = -ESHUTDOWN;
1403                 } else {
1404                         xhci_dbg(xhci, "Successful control transfer!\n");
1405                         *status = 0;
1406                 }
1407                 break;
1408         case COMP_SHORT_TX:
1409                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1410                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1411                         *status = -EREMOTEIO;
1412                 else
1413                         *status = 0;
1414                 break;
1415         default:
1416                 if (!xhci_requires_manual_halt_cleanup(xhci,
1417                                         ep_ctx, trb_comp_code))
1418                         break;
1419                 xhci_dbg(xhci, "TRB error code %u, "
1420                                 "halted endpoint index = %u\n",
1421                                 trb_comp_code, ep_index);
1422                 /* else fall through */
1423         case COMP_STALL:
1424                 /* Did we transfer part of the data (middle) phase? */
1425                 if (event_trb != ep_ring->dequeue &&
1426                                 event_trb != td->last_trb)
1427                         td->urb->actual_length =
1428                                 td->urb->transfer_buffer_length
1429                                 - TRB_LEN(event->transfer_len);
1430                 else
1431                         td->urb->actual_length = 0;
1432
1433                 xhci_cleanup_halted_endpoint(xhci,
1434                         slot_id, ep_index, 0, td, event_trb);
1435                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1436         }
1437         /*
1438          * Did we transfer any data, despite the errors that might have
1439          * happened?  I.e. did we get past the setup stage?
1440          */
1441         if (event_trb != ep_ring->dequeue) {
1442                 /* The event was for the status stage */
1443                 if (event_trb == td->last_trb) {
1444                         if (td->urb->actual_length != 0) {
1445                                 /* Don't overwrite a previously set error code
1446                                  */
1447                                 if ((*status == -EINPROGRESS || *status == 0) &&
1448                                                 (td->urb->transfer_flags
1449                                                  & URB_SHORT_NOT_OK))
1450                                         /* Did we already see a short data
1451                                          * stage? */
1452                                         *status = -EREMOTEIO;
1453                         } else {
1454                                 td->urb->actual_length =
1455                                         td->urb->transfer_buffer_length;
1456                         }
1457                 } else {
1458                 /* Maybe the event was for the data stage? */
1459                         if (trb_comp_code != COMP_STOP_INVAL) {
1460                                 /* We didn't stop on a link TRB in the middle */
1461                                 td->urb->actual_length =
1462                                         td->urb->transfer_buffer_length -
1463                                         TRB_LEN(event->transfer_len);
1464                                 xhci_dbg(xhci, "Waiting for status "
1465                                                 "stage event\n");
1466                                 return 0;
1467                         }
1468                 }
1469         }
1470
1471         return finish_td(xhci, td, event_trb, event, ep, status, false);
1472 }
1473
1474 /*
1475  * Process bulk and interrupt tds, update urb status and actual_length.
1476  */
1477 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1478         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1479         struct xhci_virt_ep *ep, int *status)
1480 {
1481         struct xhci_ring *ep_ring;
1482         union xhci_trb *cur_trb;
1483         struct xhci_segment *cur_seg;
1484         u32 trb_comp_code;
1485
1486         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1487         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1488
1489         switch (trb_comp_code) {
1490         case COMP_SUCCESS:
1491                 /* Double check that the HW transferred everything. */
1492                 if (event_trb != td->last_trb) {
1493                         xhci_warn(xhci, "WARN Successful completion "
1494                                         "on short TX\n");
1495                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1496                                 *status = -EREMOTEIO;
1497                         else
1498                                 *status = 0;
1499                 } else {
1500                         if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1501                                 xhci_dbg(xhci, "Successful bulk "
1502                                                 "transfer!\n");
1503                         else
1504                                 xhci_dbg(xhci, "Successful interrupt "
1505                                                 "transfer!\n");
1506                         *status = 0;
1507                 }
1508                 break;
1509         case COMP_SHORT_TX:
1510                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1511                         *status = -EREMOTEIO;
1512                 else
1513                         *status = 0;
1514                 break;
1515         default:
1516                 /* Others already handled above */
1517                 break;
1518         }
1519         dev_dbg(&td->urb->dev->dev,
1520                         "ep %#x - asked for %d bytes, "
1521                         "%d bytes untransferred\n",
1522                         td->urb->ep->desc.bEndpointAddress,
1523                         td->urb->transfer_buffer_length,
1524                         TRB_LEN(event->transfer_len));
1525         /* Fast path - was this the last TRB in the TD for this URB? */
1526         if (event_trb == td->last_trb) {
1527                 if (TRB_LEN(event->transfer_len) != 0) {
1528                         td->urb->actual_length =
1529                                 td->urb->transfer_buffer_length -
1530                                 TRB_LEN(event->transfer_len);
1531                         if (td->urb->transfer_buffer_length <
1532                                         td->urb->actual_length) {
1533                                 xhci_warn(xhci, "HC gave bad length "
1534                                                 "of %d bytes left\n",
1535                                                 TRB_LEN(event->transfer_len));
1536                                 td->urb->actual_length = 0;
1537                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1538                                         *status = -EREMOTEIO;
1539                                 else
1540                                         *status = 0;
1541                         }
1542                         /* Don't overwrite a previously set error code */
1543                         if (*status == -EINPROGRESS) {
1544                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1545                                         *status = -EREMOTEIO;
1546                                 else
1547                                         *status = 0;
1548                         }
1549                 } else {
1550                         td->urb->actual_length =
1551                                 td->urb->transfer_buffer_length;
1552                         /* Ignore a short packet completion if the
1553                          * untransferred length was zero.
1554                          */
1555                         if (*status == -EREMOTEIO)
1556                                 *status = 0;
1557                 }
1558         } else {
1559                 /* Slow path - walk the list, starting from the dequeue
1560                  * pointer, to get the actual length transferred.
1561                  */
1562                 td->urb->actual_length = 0;
1563                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1564                                 cur_trb != event_trb;
1565                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1566                         if ((cur_trb->generic.field[3] &
1567                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1568                             (cur_trb->generic.field[3] &
1569                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1570                                 td->urb->actual_length +=
1571                                         TRB_LEN(cur_trb->generic.field[2]);
1572                 }
1573                 /* If the ring didn't stop on a Link or No-op TRB, add
1574                  * in the actual bytes transferred from the Normal TRB
1575                  */
1576                 if (trb_comp_code != COMP_STOP_INVAL)
1577                         td->urb->actual_length +=
1578                                 TRB_LEN(cur_trb->generic.field[2]) -
1579                                 TRB_LEN(event->transfer_len);
1580         }
1581
1582         return finish_td(xhci, td, event_trb, event, ep, status, false);
1583 }
1584
1585 /*
1586  * If this function returns an error condition, it means it got a Transfer
1587  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1588  * At this point, the host controller is probably hosed and should be reset.
1589  */
1590 static int handle_tx_event(struct xhci_hcd *xhci,
1591                 struct xhci_transfer_event *event)
1592 {
1593         struct xhci_virt_device *xdev;
1594         struct xhci_virt_ep *ep;
1595         struct xhci_ring *ep_ring;
1596         unsigned int slot_id;
1597         int ep_index;
1598         struct xhci_td *td = NULL;
1599         dma_addr_t event_dma;
1600         struct xhci_segment *event_seg;
1601         union xhci_trb *event_trb;
1602         struct urb *urb = NULL;
1603         int status = -EINPROGRESS;
1604         struct urb_priv *urb_priv;
1605         struct xhci_ep_ctx *ep_ctx;
1606         u32 trb_comp_code;
1607         int ret = 0;
1608
1609         slot_id = TRB_TO_SLOT_ID(event->flags);
1610         xdev = xhci->devs[slot_id];
1611         if (!xdev) {
1612                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1613                 return -ENODEV;
1614         }
1615
1616         /* Endpoint ID is 1 based, our index is zero based */
1617         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1618         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1619         ep = &xdev->eps[ep_index];
1620         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1621         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1622         if (!ep_ring ||
1623                 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1624                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1625                                 "or incorrect stream ring\n");
1626                 return -ENODEV;
1627         }
1628
1629         event_dma = event->buffer;
1630         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1631         /* Look for common error cases */
1632         switch (trb_comp_code) {
1633         /* Skip codes that require special handling depending on
1634          * transfer type
1635          */
1636         case COMP_SUCCESS:
1637         case COMP_SHORT_TX:
1638                 break;
1639         case COMP_STOP:
1640                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1641                 break;
1642         case COMP_STOP_INVAL:
1643                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1644                 break;
1645         case COMP_STALL:
1646                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1647                 ep->ep_state |= EP_HALTED;
1648                 status = -EPIPE;
1649                 break;
1650         case COMP_TRB_ERR:
1651                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1652                 status = -EILSEQ;
1653                 break;
1654         case COMP_SPLIT_ERR:
1655         case COMP_TX_ERR:
1656                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1657                 status = -EPROTO;
1658                 break;
1659         case COMP_BABBLE:
1660                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1661                 status = -EOVERFLOW;
1662                 break;
1663         case COMP_DB_ERR:
1664                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1665                 status = -ENOSR;
1666                 break;
1667         case COMP_BW_OVER:
1668                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1669                 break;
1670         case COMP_BUFF_OVER:
1671                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1672                 break;
1673         case COMP_UNDERRUN:
1674                 /*
1675                  * When the Isoch ring is empty, the xHC will generate
1676                  * a Ring Overrun Event for IN Isoch endpoint or Ring
1677                  * Underrun Event for OUT Isoch endpoint.
1678                  */
1679                 xhci_dbg(xhci, "underrun event on endpoint\n");
1680                 if (!list_empty(&ep_ring->td_list))
1681                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1682                                         "still with TDs queued?\n",
1683                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1684                 goto cleanup;
1685         case COMP_OVERRUN:
1686                 xhci_dbg(xhci, "overrun event on endpoint\n");
1687                 if (!list_empty(&ep_ring->td_list))
1688                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1689                                         "still with TDs queued?\n",
1690                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1691                 goto cleanup;
1692         case COMP_MISSED_INT:
1693                 /*
1694                  * When encounter missed service error, one or more isoc tds
1695                  * may be missed by xHC.
1696                  * Set skip flag of the ep_ring; Complete the missed tds as
1697                  * short transfer when process the ep_ring next time.
1698                  */
1699                 ep->skip = true;
1700                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1701                 goto cleanup;
1702         default:
1703                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1704                         status = 0;
1705                         break;
1706                 }
1707                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1708                                 "busted\n");
1709                 goto cleanup;
1710         }
1711
1712         do {
1713                 /* This TRB should be in the TD at the head of this ring's
1714                  * TD list.
1715                  */
1716                 if (list_empty(&ep_ring->td_list)) {
1717                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1718                                         "with no TDs queued?\n",
1719                                   TRB_TO_SLOT_ID(event->flags), ep_index);
1720                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1721                           (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1722                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1723                         if (ep->skip) {
1724                                 ep->skip = false;
1725                                 xhci_dbg(xhci, "td_list is empty while skip "
1726                                                 "flag set. Clear skip flag.\n");
1727                         }
1728                         ret = 0;
1729                         goto cleanup;
1730                 }
1731
1732                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1733                 /* Is this a TRB in the currently executing TD? */
1734                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1735                                 td->last_trb, event_dma);
1736                 if (event_seg && ep->skip) {
1737                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
1738                         ep->skip = false;
1739                 }
1740                 if (!event_seg &&
1741                    (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
1742                         /* HC is busted, give up! */
1743                         xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
1744                                         "part of current TD\n");
1745                         return -ESHUTDOWN;
1746                 }
1747
1748                 if (event_seg) {
1749                         event_trb = &event_seg->trbs[(event_dma -
1750                                          event_seg->dma) / sizeof(*event_trb)];
1751                         /*
1752                          * No-op TRB should not trigger interrupts.
1753                          * If event_trb is a no-op TRB, it means the
1754                          * corresponding TD has been cancelled. Just ignore
1755                          * the TD.
1756                          */
1757                         if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
1758                                          == TRB_TYPE(TRB_TR_NOOP)) {
1759                                 xhci_dbg(xhci, "event_trb is a no-op TRB. "
1760                                                 "Skip it\n");
1761                                 goto cleanup;
1762                         }
1763                 }
1764
1765                 /* Now update the urb's actual_length and give back to
1766                  * the core
1767                  */
1768                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
1769                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
1770                                                  &status);
1771                 else
1772                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
1773                                                  ep, &status);
1774
1775 cleanup:
1776                 /*
1777                  * Do not update event ring dequeue pointer if ep->skip is set.
1778                  * Will roll back to continue process missed tds.
1779                  */
1780                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
1781                         inc_deq(xhci, xhci->event_ring, true);
1782                         xhci_set_hc_event_deq(xhci);
1783                 }
1784
1785                 if (ret) {
1786                         urb = td->urb;
1787                         urb_priv = urb->hcpriv;
1788                         /* Leave the TD around for the reset endpoint function
1789                          * to use(but only if it's not a control endpoint,
1790                          * since we already queued the Set TR dequeue pointer
1791                          * command for stalled control endpoints).
1792                          */
1793                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1794                                 (trb_comp_code != COMP_STALL &&
1795                                         trb_comp_code != COMP_BABBLE))
1796                                 xhci_urb_free_priv(xhci, urb_priv);
1797
1798                         usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1799                         xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1800                                         "status = %d\n",
1801                                         urb, urb->actual_length, status);
1802                         spin_unlock(&xhci->lock);
1803                         usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1804                         spin_lock(&xhci->lock);
1805                 }
1806
1807         /*
1808          * If ep->skip is set, it means there are missed tds on the
1809          * endpoint ring need to take care of.
1810          * Process them as short transfer until reach the td pointed by
1811          * the event.
1812          */
1813         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
1814
1815         return 0;
1816 }
1817
1818 /*
1819  * This function handles all OS-owned events on the event ring.  It may drop
1820  * xhci->lock between event processing (e.g. to pass up port status changes).
1821  */
1822 void xhci_handle_event(struct xhci_hcd *xhci)
1823 {
1824         union xhci_trb *event;
1825         int update_ptrs = 1;
1826         int ret;
1827
1828         xhci_dbg(xhci, "In %s\n", __func__);
1829         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1830                 xhci->error_bitmask |= 1 << 1;
1831                 return;
1832         }
1833
1834         event = xhci->event_ring->dequeue;
1835         /* Does the HC or OS own the TRB? */
1836         if ((event->event_cmd.flags & TRB_CYCLE) !=
1837                         xhci->event_ring->cycle_state) {
1838                 xhci->error_bitmask |= 1 << 2;
1839                 return;
1840         }
1841         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1842
1843         /* FIXME: Handle more event types. */
1844         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1845         case TRB_TYPE(TRB_COMPLETION):
1846                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1847                 handle_cmd_completion(xhci, &event->event_cmd);
1848                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1849                 break;
1850         case TRB_TYPE(TRB_PORT_STATUS):
1851                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1852                 handle_port_status(xhci, event);
1853                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1854                 update_ptrs = 0;
1855                 break;
1856         case TRB_TYPE(TRB_TRANSFER):
1857                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1858                 ret = handle_tx_event(xhci, &event->trans_event);
1859                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1860                 if (ret < 0)
1861                         xhci->error_bitmask |= 1 << 9;
1862                 else
1863                         update_ptrs = 0;
1864                 break;
1865         default:
1866                 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
1867                         handle_vendor_event(xhci, event);
1868                 else
1869                         xhci->error_bitmask |= 1 << 3;
1870         }
1871         /* Any of the above functions may drop and re-acquire the lock, so check
1872          * to make sure a watchdog timer didn't mark the host as non-responsive.
1873          */
1874         if (xhci->xhc_state & XHCI_STATE_DYING) {
1875                 xhci_dbg(xhci, "xHCI host dying, returning from "
1876                                 "event handler.\n");
1877                 return;
1878         }
1879
1880         if (update_ptrs) {
1881                 /* Update SW and HC event ring dequeue pointer */
1882                 inc_deq(xhci, xhci->event_ring, true);
1883                 xhci_set_hc_event_deq(xhci);
1884         }
1885         /* Are there more items on the event ring? */
1886         xhci_handle_event(xhci);
1887 }
1888
1889 /****           Endpoint Ring Operations        ****/
1890
1891 /*
1892  * Generic function for queueing a TRB on a ring.
1893  * The caller must have checked to make sure there's room on the ring.
1894  *
1895  * @more_trbs_coming:   Will you enqueue more TRBs before calling
1896  *                      prepare_transfer()?
1897  */
1898 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1899                 bool consumer, bool more_trbs_coming,
1900                 u32 field1, u32 field2, u32 field3, u32 field4)
1901 {
1902         struct xhci_generic_trb *trb;
1903
1904         trb = &ring->enqueue->generic;
1905         trb->field[0] = field1;
1906         trb->field[1] = field2;
1907         trb->field[2] = field3;
1908         trb->field[3] = field4;
1909         inc_enq(xhci, ring, consumer, more_trbs_coming);
1910 }
1911
1912 /*
1913  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1914  * FIXME allocate segments if the ring is full.
1915  */
1916 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1917                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1918 {
1919         /* Make sure the endpoint has been added to xHC schedule */
1920         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1921         switch (ep_state) {
1922         case EP_STATE_DISABLED:
1923                 /*
1924                  * USB core changed config/interfaces without notifying us,
1925                  * or hardware is reporting the wrong state.
1926                  */
1927                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1928                 return -ENOENT;
1929         case EP_STATE_ERROR:
1930                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1931                 /* FIXME event handling code for error needs to clear it */
1932                 /* XXX not sure if this should be -ENOENT or not */
1933                 return -EINVAL;
1934         case EP_STATE_HALTED:
1935                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1936         case EP_STATE_STOPPED:
1937         case EP_STATE_RUNNING:
1938                 break;
1939         default:
1940                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1941                 /*
1942                  * FIXME issue Configure Endpoint command to try to get the HC
1943                  * back into a known state.
1944                  */
1945                 return -EINVAL;
1946         }
1947         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1948                 /* FIXME allocate more room */
1949                 xhci_err(xhci, "ERROR no room on ep ring\n");
1950                 return -ENOMEM;
1951         }
1952
1953         if (enqueue_is_link_trb(ep_ring)) {
1954                 struct xhci_ring *ring = ep_ring;
1955                 union xhci_trb *next;
1956
1957                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
1958                 next = ring->enqueue;
1959
1960                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
1961
1962                         /* If we're not dealing with 0.95 hardware,
1963                          * clear the chain bit.
1964                          */
1965                         if (!xhci_link_trb_quirk(xhci))
1966                                 next->link.control &= ~TRB_CHAIN;
1967                         else
1968                                 next->link.control |= TRB_CHAIN;
1969
1970                         wmb();
1971                         next->link.control ^= (u32) TRB_CYCLE;
1972
1973                         /* Toggle the cycle bit after the last ring segment. */
1974                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
1975                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
1976                                 if (!in_interrupt()) {
1977                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
1978                                                 "state for ring %p = %i\n",
1979                                                 ring, (unsigned int)ring->cycle_state);
1980                                 }
1981                         }
1982                         ring->enq_seg = ring->enq_seg->next;
1983                         ring->enqueue = ring->enq_seg->trbs;
1984                         next = ring->enqueue;
1985                 }
1986         }
1987
1988         return 0;
1989 }
1990
1991 static int prepare_transfer(struct xhci_hcd *xhci,
1992                 struct xhci_virt_device *xdev,
1993                 unsigned int ep_index,
1994                 unsigned int stream_id,
1995                 unsigned int num_trbs,
1996                 struct urb *urb,
1997                 unsigned int td_index,
1998                 gfp_t mem_flags)
1999 {
2000         int ret;
2001         struct urb_priv *urb_priv;
2002         struct xhci_td  *td;
2003         struct xhci_ring *ep_ring;
2004         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2005
2006         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2007         if (!ep_ring) {
2008                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2009                                 stream_id);
2010                 return -EINVAL;
2011         }
2012
2013         ret = prepare_ring(xhci, ep_ring,
2014                         ep_ctx->ep_info & EP_STATE_MASK,
2015                         num_trbs, mem_flags);
2016         if (ret)
2017                 return ret;
2018
2019         urb_priv = urb->hcpriv;
2020         td = urb_priv->td[td_index];
2021
2022         INIT_LIST_HEAD(&td->td_list);
2023         INIT_LIST_HEAD(&td->cancelled_td_list);
2024
2025         if (td_index == 0) {
2026                 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
2027                 if (unlikely(ret)) {
2028                         xhci_urb_free_priv(xhci, urb_priv);
2029                         urb->hcpriv = NULL;
2030                         return ret;
2031                 }
2032         }
2033
2034         td->urb = urb;
2035         /* Add this TD to the tail of the endpoint ring's TD list */
2036         list_add_tail(&td->td_list, &ep_ring->td_list);
2037         td->start_seg = ep_ring->enq_seg;
2038         td->first_trb = ep_ring->enqueue;
2039
2040         urb_priv->td[td_index] = td;
2041
2042         return 0;
2043 }
2044
2045 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2046 {
2047         int num_sgs, num_trbs, running_total, temp, i;
2048         struct scatterlist *sg;
2049
2050         sg = NULL;
2051         num_sgs = urb->num_sgs;
2052         temp = urb->transfer_buffer_length;
2053
2054         xhci_dbg(xhci, "count sg list trbs: \n");
2055         num_trbs = 0;
2056         for_each_sg(urb->sg, sg, num_sgs, i) {
2057                 unsigned int previous_total_trbs = num_trbs;
2058                 unsigned int len = sg_dma_len(sg);
2059
2060                 /* Scatter gather list entries may cross 64KB boundaries */
2061                 running_total = TRB_MAX_BUFF_SIZE -
2062                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2063                 if (running_total != 0)
2064                         num_trbs++;
2065
2066                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2067                 while (running_total < sg_dma_len(sg)) {
2068                         num_trbs++;
2069                         running_total += TRB_MAX_BUFF_SIZE;
2070                 }
2071                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2072                                 i, (unsigned long long)sg_dma_address(sg),
2073                                 len, len, num_trbs - previous_total_trbs);
2074
2075                 len = min_t(int, len, temp);
2076                 temp -= len;
2077                 if (temp == 0)
2078                         break;
2079         }
2080         xhci_dbg(xhci, "\n");
2081         if (!in_interrupt())
2082                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
2083                                 urb->ep->desc.bEndpointAddress,
2084                                 urb->transfer_buffer_length,
2085                                 num_trbs);
2086         return num_trbs;
2087 }
2088
2089 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2090 {
2091         if (num_trbs != 0)
2092                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2093                                 "TRBs, %d left\n", __func__,
2094                                 urb->ep->desc.bEndpointAddress, num_trbs);
2095         if (running_total != urb->transfer_buffer_length)
2096                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2097                                 "queued %#x (%d), asked for %#x (%d)\n",
2098                                 __func__,
2099                                 urb->ep->desc.bEndpointAddress,
2100                                 running_total, running_total,
2101                                 urb->transfer_buffer_length,
2102                                 urb->transfer_buffer_length);
2103 }
2104
2105 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2106                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2107                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
2108 {
2109         /*
2110          * Pass all the TRBs to the hardware at once and make sure this write
2111          * isn't reordered.
2112          */
2113         wmb();
2114         start_trb->field[3] |= start_cycle;
2115         ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2116 }
2117
2118 /*
2119  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2120  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2121  * (comprised of sg list entries) can take several service intervals to
2122  * transmit.
2123  */
2124 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2125                 struct urb *urb, int slot_id, unsigned int ep_index)
2126 {
2127         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2128                         xhci->devs[slot_id]->out_ctx, ep_index);
2129         int xhci_interval;
2130         int ep_interval;
2131
2132         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2133         ep_interval = urb->interval;
2134         /* Convert to microframes */
2135         if (urb->dev->speed == USB_SPEED_LOW ||
2136                         urb->dev->speed == USB_SPEED_FULL)
2137                 ep_interval *= 8;
2138         /* FIXME change this to a warning and a suggestion to use the new API
2139          * to set the polling interval (once the API is added).
2140          */
2141         if (xhci_interval != ep_interval) {
2142                 if (!printk_ratelimit())
2143                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2144                                         " (%d microframe%s) than xHCI "
2145                                         "(%d microframe%s)\n",
2146                                         ep_interval,
2147                                         ep_interval == 1 ? "" : "s",
2148                                         xhci_interval,
2149                                         xhci_interval == 1 ? "" : "s");
2150                 urb->interval = xhci_interval;
2151                 /* Convert back to frames for LS/FS devices */
2152                 if (urb->dev->speed == USB_SPEED_LOW ||
2153                                 urb->dev->speed == USB_SPEED_FULL)
2154                         urb->interval /= 8;
2155         }
2156         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2157 }
2158
2159 /*
2160  * The TD size is the number of bytes remaining in the TD (including this TRB),
2161  * right shifted by 10.
2162  * It must fit in bits 21:17, so it can't be bigger than 31.
2163  */
2164 static u32 xhci_td_remainder(unsigned int remainder)
2165 {
2166         u32 max = (1 << (21 - 17 + 1)) - 1;
2167
2168         if ((remainder >> 10) >= max)
2169                 return max << 17;
2170         else
2171                 return (remainder >> 10) << 17;
2172 }
2173
2174 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2175                 struct urb *urb, int slot_id, unsigned int ep_index)
2176 {
2177         struct xhci_ring *ep_ring;
2178         unsigned int num_trbs;
2179         struct urb_priv *urb_priv;
2180         struct xhci_td *td;
2181         struct scatterlist *sg;
2182         int num_sgs;
2183         int trb_buff_len, this_sg_len, running_total;
2184         bool first_trb;
2185         u64 addr;
2186         bool more_trbs_coming;
2187
2188         struct xhci_generic_trb *start_trb;
2189         int start_cycle;
2190
2191         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2192         if (!ep_ring)
2193                 return -EINVAL;
2194
2195         num_trbs = count_sg_trbs_needed(xhci, urb);
2196         num_sgs = urb->num_sgs;
2197
2198         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2199                         ep_index, urb->stream_id,
2200                         num_trbs, urb, 0, mem_flags);
2201         if (trb_buff_len < 0)
2202                 return trb_buff_len;
2203
2204         urb_priv = urb->hcpriv;
2205         td = urb_priv->td[0];
2206
2207         /*
2208          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2209          * until we've finished creating all the other TRBs.  The ring's cycle
2210          * state may change as we enqueue the other TRBs, so save it too.
2211          */
2212         start_trb = &ep_ring->enqueue->generic;
2213         start_cycle = ep_ring->cycle_state;
2214
2215         running_total = 0;
2216         /*
2217          * How much data is in the first TRB?
2218          *
2219          * There are three forces at work for TRB buffer pointers and lengths:
2220          * 1. We don't want to walk off the end of this sg-list entry buffer.
2221          * 2. The transfer length that the driver requested may be smaller than
2222          *    the amount of memory allocated for this scatter-gather list.
2223          * 3. TRBs buffers can't cross 64KB boundaries.
2224          */
2225         sg = urb->sg;
2226         addr = (u64) sg_dma_address(sg);
2227         this_sg_len = sg_dma_len(sg);
2228         trb_buff_len = TRB_MAX_BUFF_SIZE -
2229                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2230         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2231         if (trb_buff_len > urb->transfer_buffer_length)
2232                 trb_buff_len = urb->transfer_buffer_length;
2233         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2234                         trb_buff_len);
2235
2236         first_trb = true;
2237         /* Queue the first TRB, even if it's zero-length */
2238         do {
2239                 u32 field = 0;
2240                 u32 length_field = 0;
2241                 u32 remainder = 0;
2242
2243                 /* Don't change the cycle bit of the first TRB until later */
2244                 if (first_trb)
2245                         first_trb = false;
2246                 else
2247                         field |= ep_ring->cycle_state;
2248
2249                 /* Chain all the TRBs together; clear the chain bit in the last
2250                  * TRB to indicate it's the last TRB in the chain.
2251                  */
2252                 if (num_trbs > 1) {
2253                         field |= TRB_CHAIN;
2254                 } else {
2255                         /* FIXME - add check for ZERO_PACKET flag before this */
2256                         td->last_trb = ep_ring->enqueue;
2257                         field |= TRB_IOC;
2258                 }
2259                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2260                                 "64KB boundary at %#x, end dma = %#x\n",
2261                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2262                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2263                                 (unsigned int) addr + trb_buff_len);
2264                 if (TRB_MAX_BUFF_SIZE -
2265                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
2266                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2267                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2268                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2269                                         (unsigned int) addr + trb_buff_len);
2270                 }
2271                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2272                                 running_total) ;
2273                 length_field = TRB_LEN(trb_buff_len) |
2274                         remainder |
2275                         TRB_INTR_TARGET(0);
2276                 if (num_trbs > 1)
2277                         more_trbs_coming = true;
2278                 else
2279                         more_trbs_coming = false;
2280                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2281                                 lower_32_bits(addr),
2282                                 upper_32_bits(addr),
2283                                 length_field,
2284                                 /* We always want to know if the TRB was short,
2285                                  * or we won't get an event when it completes.
2286                                  * (Unless we use event data TRBs, which are a
2287                                  * waste of space and HC resources.)
2288                                  */
2289                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2290                 --num_trbs;
2291                 running_total += trb_buff_len;
2292
2293                 /* Calculate length for next transfer --
2294                  * Are we done queueing all the TRBs for this sg entry?
2295                  */
2296                 this_sg_len -= trb_buff_len;
2297                 if (this_sg_len == 0) {
2298                         --num_sgs;
2299                         if (num_sgs == 0)
2300                                 break;
2301                         sg = sg_next(sg);
2302                         addr = (u64) sg_dma_address(sg);
2303                         this_sg_len = sg_dma_len(sg);
2304                 } else {
2305                         addr += trb_buff_len;
2306                 }
2307
2308                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2309                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2310                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2311                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2312                         trb_buff_len =
2313                                 urb->transfer_buffer_length - running_total;
2314         } while (running_total < urb->transfer_buffer_length);
2315
2316         check_trb_math(urb, num_trbs, running_total);
2317         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2318                         start_cycle, start_trb, td);
2319         return 0;
2320 }
2321
2322 /* This is very similar to what ehci-q.c qtd_fill() does */
2323 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2324                 struct urb *urb, int slot_id, unsigned int ep_index)
2325 {
2326         struct xhci_ring *ep_ring;
2327         struct urb_priv *urb_priv;
2328         struct xhci_td *td;
2329         int num_trbs;
2330         struct xhci_generic_trb *start_trb;
2331         bool first_trb;
2332         bool more_trbs_coming;
2333         int start_cycle;
2334         u32 field, length_field;
2335
2336         int running_total, trb_buff_len, ret;
2337         u64 addr;
2338
2339         if (urb->num_sgs)
2340                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2341
2342         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2343         if (!ep_ring)
2344                 return -EINVAL;
2345
2346         num_trbs = 0;
2347         /* How much data is (potentially) left before the 64KB boundary? */
2348         running_total = TRB_MAX_BUFF_SIZE -
2349                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2350
2351         /* If there's some data on this 64KB chunk, or we have to send a
2352          * zero-length transfer, we need at least one TRB
2353          */
2354         if (running_total != 0 || urb->transfer_buffer_length == 0)
2355                 num_trbs++;
2356         /* How many more 64KB chunks to transfer, how many more TRBs? */
2357         while (running_total < urb->transfer_buffer_length) {
2358                 num_trbs++;
2359                 running_total += TRB_MAX_BUFF_SIZE;
2360         }
2361         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2362
2363         if (!in_interrupt())
2364                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2365                                 urb->ep->desc.bEndpointAddress,
2366                                 urb->transfer_buffer_length,
2367                                 urb->transfer_buffer_length,
2368                                 (unsigned long long)urb->transfer_dma,
2369                                 num_trbs);
2370
2371         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2372                         ep_index, urb->stream_id,
2373                         num_trbs, urb, 0, mem_flags);
2374         if (ret < 0)
2375                 return ret;
2376
2377         urb_priv = urb->hcpriv;
2378         td = urb_priv->td[0];
2379
2380         /*
2381          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2382          * until we've finished creating all the other TRBs.  The ring's cycle
2383          * state may change as we enqueue the other TRBs, so save it too.
2384          */
2385         start_trb = &ep_ring->enqueue->generic;
2386         start_cycle = ep_ring->cycle_state;
2387
2388         running_total = 0;
2389         /* How much data is in the first TRB? */
2390         addr = (u64) urb->transfer_dma;
2391         trb_buff_len = TRB_MAX_BUFF_SIZE -
2392                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2393         if (urb->transfer_buffer_length < trb_buff_len)
2394                 trb_buff_len = urb->transfer_buffer_length;
2395
2396         first_trb = true;
2397
2398         /* Queue the first TRB, even if it's zero-length */
2399         do {
2400                 u32 remainder = 0;
2401                 field = 0;
2402
2403                 /* Don't change the cycle bit of the first TRB until later */
2404                 if (first_trb)
2405                         first_trb = false;
2406                 else
2407                         field |= ep_ring->cycle_state;
2408
2409                 /* Chain all the TRBs together; clear the chain bit in the last
2410                  * TRB to indicate it's the last TRB in the chain.
2411                  */
2412                 if (num_trbs > 1) {
2413                         field |= TRB_CHAIN;
2414                 } else {
2415                         /* FIXME - add check for ZERO_PACKET flag before this */
2416                         td->last_trb = ep_ring->enqueue;
2417                         field |= TRB_IOC;
2418                 }
2419                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2420                                 running_total);
2421                 length_field = TRB_LEN(trb_buff_len) |
2422                         remainder |
2423                         TRB_INTR_TARGET(0);
2424                 if (num_trbs > 1)
2425                         more_trbs_coming = true;
2426                 else
2427                         more_trbs_coming = false;
2428                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2429                                 lower_32_bits(addr),
2430                                 upper_32_bits(addr),
2431                                 length_field,
2432                                 /* We always want to know if the TRB was short,
2433                                  * or we won't get an event when it completes.
2434                                  * (Unless we use event data TRBs, which are a
2435                                  * waste of space and HC resources.)
2436                                  */
2437                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2438                 --num_trbs;
2439                 running_total += trb_buff_len;
2440
2441                 /* Calculate length for next transfer */
2442                 addr += trb_buff_len;
2443                 trb_buff_len = urb->transfer_buffer_length - running_total;
2444                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2445                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2446         } while (running_total < urb->transfer_buffer_length);
2447
2448         check_trb_math(urb, num_trbs, running_total);
2449         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2450                         start_cycle, start_trb, td);
2451         return 0;
2452 }
2453
2454 /* Caller must have locked xhci->lock */
2455 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2456                 struct urb *urb, int slot_id, unsigned int ep_index)
2457 {
2458         struct xhci_ring *ep_ring;
2459         int num_trbs;
2460         int ret;
2461         struct usb_ctrlrequest *setup;
2462         struct xhci_generic_trb *start_trb;
2463         int start_cycle;
2464         u32 field, length_field;
2465         struct urb_priv *urb_priv;
2466         struct xhci_td *td;
2467
2468         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2469         if (!ep_ring)
2470                 return -EINVAL;
2471
2472         /*
2473          * Need to copy setup packet into setup TRB, so we can't use the setup
2474          * DMA address.
2475          */
2476         if (!urb->setup_packet)
2477                 return -EINVAL;
2478
2479         if (!in_interrupt())
2480                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2481                                 slot_id, ep_index);
2482         /* 1 TRB for setup, 1 for status */
2483         num_trbs = 2;
2484         /*
2485          * Don't need to check if we need additional event data and normal TRBs,
2486          * since data in control transfers will never get bigger than 16MB
2487          * XXX: can we get a buffer that crosses 64KB boundaries?
2488          */
2489         if (urb->transfer_buffer_length > 0)
2490                 num_trbs++;
2491         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2492                         ep_index, urb->stream_id,
2493                         num_trbs, urb, 0, mem_flags);
2494         if (ret < 0)
2495                 return ret;
2496
2497         urb_priv = urb->hcpriv;
2498         td = urb_priv->td[0];
2499
2500         /*
2501          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2502          * until we've finished creating all the other TRBs.  The ring's cycle
2503          * state may change as we enqueue the other TRBs, so save it too.
2504          */
2505         start_trb = &ep_ring->enqueue->generic;
2506         start_cycle = ep_ring->cycle_state;
2507
2508         /* Queue setup TRB - see section 6.4.1.2.1 */
2509         /* FIXME better way to translate setup_packet into two u32 fields? */
2510         setup = (struct usb_ctrlrequest *) urb->setup_packet;
2511         queue_trb(xhci, ep_ring, false, true,
2512                         /* FIXME endianness is probably going to bite my ass here. */
2513                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2514                         setup->wIndex | setup->wLength << 16,
2515                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2516                         /* Immediate data in pointer */
2517                         TRB_IDT | TRB_TYPE(TRB_SETUP));
2518
2519         /* If there's data, queue data TRBs */
2520         field = 0;
2521         length_field = TRB_LEN(urb->transfer_buffer_length) |
2522                 xhci_td_remainder(urb->transfer_buffer_length) |
2523                 TRB_INTR_TARGET(0);
2524         if (urb->transfer_buffer_length > 0) {
2525                 if (setup->bRequestType & USB_DIR_IN)
2526                         field |= TRB_DIR_IN;
2527                 queue_trb(xhci, ep_ring, false, true,
2528                                 lower_32_bits(urb->transfer_dma),
2529                                 upper_32_bits(urb->transfer_dma),
2530                                 length_field,
2531                                 /* Event on short tx */
2532                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2533         }
2534
2535         /* Save the DMA address of the last TRB in the TD */
2536         td->last_trb = ep_ring->enqueue;
2537
2538         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2539         /* If the device sent data, the status stage is an OUT transfer */
2540         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2541                 field = 0;
2542         else
2543                 field = TRB_DIR_IN;
2544         queue_trb(xhci, ep_ring, false, false,
2545                         0,
2546                         0,
2547                         TRB_INTR_TARGET(0),
2548                         /* Event on completion */
2549                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2550
2551         giveback_first_trb(xhci, slot_id, ep_index, 0,
2552                         start_cycle, start_trb, td);
2553         return 0;
2554 }
2555
2556 /****           Command Ring Operations         ****/
2557
2558 /* Generic function for queueing a command TRB on the command ring.
2559  * Check to make sure there's room on the command ring for one command TRB.
2560  * Also check that there's room reserved for commands that must not fail.
2561  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2562  * then only check for the number of reserved spots.
2563  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2564  * because the command event handler may want to resubmit a failed command.
2565  */
2566 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2567                 u32 field3, u32 field4, bool command_must_succeed)
2568 {
2569         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2570         int ret;
2571
2572         if (!command_must_succeed)
2573                 reserved_trbs++;
2574
2575         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
2576                         reserved_trbs, GFP_ATOMIC);
2577         if (ret < 0) {
2578                 xhci_err(xhci, "ERR: No room for command on command ring\n");
2579                 if (command_must_succeed)
2580                         xhci_err(xhci, "ERR: Reserved TRB counting for "
2581                                         "unfailable commands failed.\n");
2582                 return ret;
2583         }
2584         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
2585                         field4 | xhci->cmd_ring->cycle_state);
2586         return 0;
2587 }
2588
2589 /* Queue a no-op command on the command ring */
2590 static int queue_cmd_noop(struct xhci_hcd *xhci)
2591 {
2592         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2593 }
2594
2595 /*
2596  * Place a no-op command on the command ring to test the command and
2597  * event ring.
2598  */
2599 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2600 {
2601         if (queue_cmd_noop(xhci) < 0)
2602                 return NULL;
2603         xhci->noops_submitted++;
2604         return xhci_ring_cmd_db;
2605 }
2606
2607 /* Queue a slot enable or disable request on the command ring */
2608 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2609 {
2610         return queue_command(xhci, 0, 0, 0,
2611                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2612 }
2613
2614 /* Queue an address device command TRB */
2615 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2616                 u32 slot_id)
2617 {
2618         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2619                         upper_32_bits(in_ctx_ptr), 0,
2620                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2621                         false);
2622 }
2623
2624 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
2625                 u32 field1, u32 field2, u32 field3, u32 field4)
2626 {
2627         return queue_command(xhci, field1, field2, field3, field4, false);
2628 }
2629
2630 /* Queue a reset device command TRB */
2631 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
2632 {
2633         return queue_command(xhci, 0, 0, 0,
2634                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
2635                         false);
2636 }
2637
2638 /* Queue a configure endpoint command TRB */
2639 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2640                 u32 slot_id, bool command_must_succeed)
2641 {
2642         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2643                         upper_32_bits(in_ctx_ptr), 0,
2644                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2645                         command_must_succeed);
2646 }
2647
2648 /* Queue an evaluate context command TRB */
2649 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2650                 u32 slot_id)
2651 {
2652         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2653                         upper_32_bits(in_ctx_ptr), 0,
2654                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2655                         false);
2656 }
2657
2658 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2659                 unsigned int ep_index)
2660 {
2661         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2662         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2663         u32 type = TRB_TYPE(TRB_STOP_RING);
2664
2665         return queue_command(xhci, 0, 0, 0,
2666                         trb_slot_id | trb_ep_index | type, false);
2667 }
2668
2669 /* Set Transfer Ring Dequeue Pointer command.
2670  * This should not be used for endpoints that have streams enabled.
2671  */
2672 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2673                 unsigned int ep_index, unsigned int stream_id,
2674                 struct xhci_segment *deq_seg,
2675                 union xhci_trb *deq_ptr, u32 cycle_state)
2676 {
2677         dma_addr_t addr;
2678         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2679         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2680         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
2681         u32 type = TRB_TYPE(TRB_SET_DEQ);
2682
2683         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2684         if (addr == 0) {
2685                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2686                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2687                                 deq_seg, deq_ptr);
2688                 return 0;
2689         }
2690         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2691                         upper_32_bits(addr), trb_stream_id,
2692                         trb_slot_id | trb_ep_index | type, false);
2693 }
2694
2695 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2696                 unsigned int ep_index)
2697 {
2698         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2699         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2700         u32 type = TRB_TYPE(TRB_RESET_EP);
2701
2702         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
2703                         false);
2704 }