2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
72 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
78 unsigned long segment_offset;
80 if (!seg || !trb || trb < seg->trbs)
83 segment_offset = trb - seg->trbs;
84 if (segment_offset > TRBS_PER_SEGMENT)
86 return seg->dma + (segment_offset * sizeof(*trb));
89 /* Does this link TRB point to the first segment in a ring,
90 * or was the previous TRB the last TRB on the last segment in the ERST?
92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
93 struct xhci_segment *seg, union xhci_trb *trb)
95 if (ring == xhci->event_ring)
96 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
97 (seg->next == xhci->event_ring->first_seg);
99 return trb->link.control & LINK_TOGGLE;
102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
103 * segment? I.e. would the updated event TRB pointer step off the end of the
106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
107 struct xhci_segment *seg, union xhci_trb *trb)
109 if (ring == xhci->event_ring)
110 return trb == &seg->trbs[TRBS_PER_SEGMENT];
112 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
115 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
116 * TRB is in a new segment. This does not skip over link TRBs, and it does not
117 * effect the ring dequeue or enqueue pointers.
119 static void next_trb(struct xhci_hcd *xhci,
120 struct xhci_ring *ring,
121 struct xhci_segment **seg,
122 union xhci_trb **trb)
124 if (last_trb(xhci, ring, *seg, *trb)) {
126 *trb = ((*seg)->trbs);
133 * See Cycle bit rules. SW is the consumer for the event ring only.
134 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
136 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
138 union xhci_trb *next = ++(ring->dequeue);
139 unsigned long long addr;
142 /* Update the dequeue pointer further if that was a link TRB or we're at
143 * the end of an event ring segment (which doesn't have link TRBS)
145 while (last_trb(xhci, ring, ring->deq_seg, next)) {
146 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
147 ring->cycle_state = (ring->cycle_state ? 0 : 1);
149 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
151 (unsigned int) ring->cycle_state);
153 ring->deq_seg = ring->deq_seg->next;
154 ring->dequeue = ring->deq_seg->trbs;
155 next = ring->dequeue;
157 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
158 if (ring == xhci->event_ring)
159 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
160 else if (ring == xhci->cmd_ring)
161 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
163 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
167 * See Cycle bit rules. SW is the consumer for the event ring only.
168 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
170 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
171 * chain bit is set), then set the chain bit in all the following link TRBs.
172 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
173 * have their chain bit cleared (so that each Link TRB is a separate TD).
175 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
176 * set, but other sections talk about dealing with the chain bit set. This was
177 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
178 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
180 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
183 union xhci_trb *next;
184 unsigned long long addr;
186 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
187 next = ++(ring->enqueue);
190 /* Update the dequeue pointer further if that was a link TRB or we're at
191 * the end of an event ring segment (which doesn't have link TRBS)
193 while (last_trb(xhci, ring, ring->enq_seg, next)) {
195 if (ring != xhci->event_ring) {
196 /* If we're not dealing with 0.95 hardware,
197 * carry over the chain bit of the previous TRB
198 * (which may mean the chain bit is cleared).
200 if (!xhci_link_trb_quirk(xhci)) {
201 next->link.control &= ~TRB_CHAIN;
202 next->link.control |= chain;
204 /* Give this link TRB to the hardware */
206 if (next->link.control & TRB_CYCLE)
207 next->link.control &= (u32) ~TRB_CYCLE;
209 next->link.control |= (u32) TRB_CYCLE;
211 /* Toggle the cycle bit after the last ring segment. */
212 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
213 ring->cycle_state = (ring->cycle_state ? 0 : 1);
215 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
217 (unsigned int) ring->cycle_state);
220 ring->enq_seg = ring->enq_seg->next;
221 ring->enqueue = ring->enq_seg->trbs;
222 next = ring->enqueue;
224 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
225 if (ring == xhci->event_ring)
226 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
227 else if (ring == xhci->cmd_ring)
228 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
230 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
234 * Check to see if there's room to enqueue num_trbs on the ring. See rules
236 * FIXME: this would be simpler and faster if we just kept track of the number
237 * of free TRBs in a ring.
239 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
240 unsigned int num_trbs)
243 union xhci_trb *enq = ring->enqueue;
244 struct xhci_segment *enq_seg = ring->enq_seg;
245 struct xhci_segment *cur_seg;
246 unsigned int left_on_ring;
248 /* Check if ring is empty */
249 if (enq == ring->dequeue) {
250 /* Can't use link trbs */
251 left_on_ring = TRBS_PER_SEGMENT - 1;
252 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
253 cur_seg = cur_seg->next)
254 left_on_ring += TRBS_PER_SEGMENT - 1;
256 /* Always need one TRB free in the ring. */
258 if (num_trbs > left_on_ring) {
259 xhci_warn(xhci, "Not enough room on ring; "
260 "need %u TRBs, %u TRBs left\n",
261 num_trbs, left_on_ring);
266 /* Make sure there's an extra empty TRB available */
267 for (i = 0; i <= num_trbs; ++i) {
268 if (enq == ring->dequeue)
271 while (last_trb(xhci, ring, enq_seg, enq)) {
272 enq_seg = enq_seg->next;
279 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
284 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
285 xhci->event_ring->dequeue);
286 if (deq == 0 && !in_interrupt())
287 xhci_warn(xhci, "WARN something wrong with SW event ring "
289 /* Update HC event ring dequeue pointer */
290 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
291 temp &= ERST_PTR_MASK;
292 /* Don't clear the EHB bit (which is RW1C) because
293 * there might be more events to service.
296 xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
297 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
298 &xhci->ir_set->erst_dequeue);
301 /* Ring the host controller doorbell after placing a command on the ring */
302 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
306 xhci_dbg(xhci, "// Ding dong!\n");
307 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
308 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
309 /* Flush PCI posted writes */
310 xhci_readl(xhci, &xhci->dba->doorbell[0]);
313 static void ring_ep_doorbell(struct xhci_hcd *xhci,
314 unsigned int slot_id,
315 unsigned int ep_index)
317 struct xhci_virt_ep *ep;
318 unsigned int ep_state;
320 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
322 ep = &xhci->devs[slot_id]->eps[ep_index];
323 ep_state = ep->ep_state;
324 /* Don't ring the doorbell for this endpoint if there are pending
325 * cancellations because the we don't want to interrupt processing.
326 * We don't want to restart any stream rings if there's a set dequeue
327 * pointer command pending because the device can choose to start any
328 * stream once the endpoint is on the HW schedule.
329 * FIXME - check all the stream rings for pending cancellations.
331 if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
332 && !(ep_state & EP_HALTED)) {
333 field = xhci_readl(xhci, db_addr) & DB_MASK;
334 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
335 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
336 * isn't time-critical and we shouldn't make the CPU wait for
339 xhci_readl(xhci, db_addr);
344 * Find the segment that trb is in. Start searching in start_seg.
345 * If we must move past a segment that has a link TRB with a toggle cycle state
346 * bit set, then we will toggle the value pointed at by cycle_state.
348 static struct xhci_segment *find_trb_seg(
349 struct xhci_segment *start_seg,
350 union xhci_trb *trb, int *cycle_state)
352 struct xhci_segment *cur_seg = start_seg;
353 struct xhci_generic_trb *generic_trb;
355 while (cur_seg->trbs > trb ||
356 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
357 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
358 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
359 (generic_trb->field[3] & LINK_TOGGLE))
360 *cycle_state = ~(*cycle_state) & 0x1;
361 cur_seg = cur_seg->next;
362 if (cur_seg == start_seg)
363 /* Looped over the entire list. Oops! */
370 * Move the xHC's endpoint ring dequeue pointer past cur_td.
371 * Record the new state of the xHC's endpoint ring dequeue segment,
372 * dequeue pointer, and new consumer cycle state in state.
373 * Update our internal representation of the ring's dequeue pointer.
375 * We do this in three jumps:
376 * - First we update our new ring state to be the same as when the xHC stopped.
377 * - Then we traverse the ring to find the segment that contains
378 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
379 * any link TRBs with the toggle cycle bit set.
380 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
381 * if we've moved it past a link TRB with the toggle cycle bit set.
383 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
384 unsigned int slot_id, unsigned int ep_index,
385 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
387 struct xhci_virt_device *dev = xhci->devs[slot_id];
388 struct xhci_ring *ep_ring = dev->eps[ep_index].ring;
389 struct xhci_generic_trb *trb;
390 struct xhci_ep_ctx *ep_ctx;
393 state->new_cycle_state = 0;
394 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
395 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
396 dev->eps[ep_index].stopped_trb,
397 &state->new_cycle_state);
398 if (!state->new_deq_seg)
400 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
401 xhci_dbg(xhci, "Finding endpoint context\n");
402 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
403 state->new_cycle_state = 0x1 & ep_ctx->deq;
405 state->new_deq_ptr = cur_td->last_trb;
406 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
407 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
409 &state->new_cycle_state);
410 if (!state->new_deq_seg)
413 trb = &state->new_deq_ptr->generic;
414 if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
415 (trb->field[3] & LINK_TOGGLE))
416 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
417 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
419 /* Don't update the ring cycle state for the producer (us). */
420 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
422 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
423 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
424 (unsigned long long) addr);
425 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
426 ep_ring->dequeue = state->new_deq_ptr;
427 ep_ring->deq_seg = state->new_deq_seg;
430 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
431 struct xhci_td *cur_td)
433 struct xhci_segment *cur_seg;
434 union xhci_trb *cur_trb;
436 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
438 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
439 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
440 TRB_TYPE(TRB_LINK)) {
441 /* Unchain any chained Link TRBs, but
442 * leave the pointers intact.
444 cur_trb->generic.field[3] &= ~TRB_CHAIN;
445 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
446 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
447 "in seg %p (0x%llx dma)\n",
449 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
451 (unsigned long long)cur_seg->dma);
453 cur_trb->generic.field[0] = 0;
454 cur_trb->generic.field[1] = 0;
455 cur_trb->generic.field[2] = 0;
456 /* Preserve only the cycle bit of this TRB */
457 cur_trb->generic.field[3] &= TRB_CYCLE;
458 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
459 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
460 "in seg %p (0x%llx dma)\n",
462 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
464 (unsigned long long)cur_seg->dma);
466 if (cur_trb == cur_td->last_trb)
471 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
472 unsigned int ep_index, struct xhci_segment *deq_seg,
473 union xhci_trb *deq_ptr, u32 cycle_state);
475 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
476 unsigned int slot_id, unsigned int ep_index,
477 struct xhci_dequeue_state *deq_state)
479 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
481 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
482 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
483 deq_state->new_deq_seg,
484 (unsigned long long)deq_state->new_deq_seg->dma,
485 deq_state->new_deq_ptr,
486 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
487 deq_state->new_cycle_state);
488 queue_set_tr_deq(xhci, slot_id, ep_index,
489 deq_state->new_deq_seg,
490 deq_state->new_deq_ptr,
491 (u32) deq_state->new_cycle_state);
492 /* Stop the TD queueing code from ringing the doorbell until
493 * this command completes. The HC won't set the dequeue pointer
494 * if the ring is running, and ringing the doorbell starts the
497 ep->ep_state |= SET_DEQ_PENDING;
500 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
501 struct xhci_virt_ep *ep)
503 ep->ep_state &= ~EP_HALT_PENDING;
504 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
505 * timer is running on another CPU, we don't decrement stop_cmds_pending
506 * (since we didn't successfully stop the watchdog timer).
508 if (del_timer(&ep->stop_cmd_timer))
509 ep->stop_cmds_pending--;
512 /* Must be called with xhci->lock held in interrupt context */
513 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
514 struct xhci_td *cur_td, int status, char *adjective)
516 struct usb_hcd *hcd = xhci_to_hcd(xhci);
518 cur_td->urb->hcpriv = NULL;
519 usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb);
520 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb);
522 spin_unlock(&xhci->lock);
523 usb_hcd_giveback_urb(hcd, cur_td->urb, status);
525 spin_lock(&xhci->lock);
526 xhci_dbg(xhci, "%s URB given back\n", adjective);
530 * When we get a command completion for a Stop Endpoint Command, we need to
531 * unlink any cancelled TDs from the ring. There are two ways to do that:
533 * 1. If the HW was in the middle of processing the TD that needs to be
534 * cancelled, then we must move the ring's dequeue pointer past the last TRB
535 * in the TD with a Set Dequeue Pointer Command.
536 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
537 * bit cleared) so that the HW will skip over them.
539 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
542 unsigned int slot_id;
543 unsigned int ep_index;
544 struct xhci_ring *ep_ring;
545 struct xhci_virt_ep *ep;
546 struct list_head *entry;
547 struct xhci_td *cur_td = 0;
548 struct xhci_td *last_unlinked_td;
550 struct xhci_dequeue_state deq_state;
552 memset(&deq_state, 0, sizeof(deq_state));
553 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
554 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
555 ep = &xhci->devs[slot_id]->eps[ep_index];
558 if (list_empty(&ep->cancelled_td_list)) {
559 xhci_stop_watchdog_timer_in_irq(xhci, ep);
560 ring_ep_doorbell(xhci, slot_id, ep_index);
564 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
565 * We have the xHCI lock, so nothing can modify this list until we drop
566 * it. We're also in the event handler, so we can't get re-interrupted
567 * if another Stop Endpoint command completes
569 list_for_each(entry, &ep->cancelled_td_list) {
570 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
571 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
573 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
575 * If we stopped on the TD we need to cancel, then we have to
576 * move the xHC endpoint ring dequeue pointer past this TD.
578 if (cur_td == ep->stopped_td)
579 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
582 td_to_noop(xhci, ep_ring, cur_td);
584 * The event handler won't see a completion for this TD anymore,
585 * so remove it from the endpoint ring's TD list. Keep it in
586 * the cancelled TD list for URB completion later.
588 list_del(&cur_td->td_list);
590 last_unlinked_td = cur_td;
591 xhci_stop_watchdog_timer_in_irq(xhci, ep);
593 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
594 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
595 xhci_queue_new_dequeue_state(xhci,
596 slot_id, ep_index, &deq_state);
597 xhci_ring_cmd_db(xhci);
599 /* Otherwise just ring the doorbell to restart the ring */
600 ring_ep_doorbell(xhci, slot_id, ep_index);
602 ep->stopped_td = NULL;
603 ep->stopped_trb = NULL;
606 * Drop the lock and complete the URBs in the cancelled TD list.
607 * New TDs to be cancelled might be added to the end of the list before
608 * we can complete all the URBs for the TDs we already unlinked.
609 * So stop when we've completed the URB for the last TD we unlinked.
612 cur_td = list_entry(ep->cancelled_td_list.next,
613 struct xhci_td, cancelled_td_list);
614 list_del(&cur_td->cancelled_td_list);
616 /* Clean up the cancelled URB */
617 /* Doesn't matter what we pass for status, since the core will
618 * just overwrite it (because the URB has been unlinked).
620 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
622 /* Stop processing the cancelled list if the watchdog timer is
625 if (xhci->xhc_state & XHCI_STATE_DYING)
627 } while (cur_td != last_unlinked_td);
629 /* Return to the event handler with xhci->lock re-acquired */
632 /* Watchdog timer function for when a stop endpoint command fails to complete.
633 * In this case, we assume the host controller is broken or dying or dead. The
634 * host may still be completing some other events, so we have to be careful to
635 * let the event ring handler and the URB dequeueing/enqueueing functions know
636 * through xhci->state.
638 * The timer may also fire if the host takes a very long time to respond to the
639 * command, and the stop endpoint command completion handler cannot delete the
640 * timer before the timer function is called. Another endpoint cancellation may
641 * sneak in before the timer function can grab the lock, and that may queue
642 * another stop endpoint command and add the timer back. So we cannot use a
643 * simple flag to say whether there is a pending stop endpoint command for a
644 * particular endpoint.
646 * Instead we use a combination of that flag and a counter for the number of
647 * pending stop endpoint commands. If the timer is the tail end of the last
648 * stop endpoint command, and the endpoint's command is still pending, we assume
651 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
653 struct xhci_hcd *xhci;
654 struct xhci_virt_ep *ep;
655 struct xhci_virt_ep *temp_ep;
656 struct xhci_ring *ring;
657 struct xhci_td *cur_td;
660 ep = (struct xhci_virt_ep *) arg;
663 spin_lock(&xhci->lock);
665 ep->stop_cmds_pending--;
666 if (xhci->xhc_state & XHCI_STATE_DYING) {
667 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
668 "xHCI as DYING, exiting.\n");
669 spin_unlock(&xhci->lock);
672 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
673 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
675 spin_unlock(&xhci->lock);
679 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
680 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
681 /* Oops, HC is dead or dying or at least not responding to the stop
684 xhci->xhc_state |= XHCI_STATE_DYING;
685 /* Disable interrupts from the host controller and start halting it */
687 spin_unlock(&xhci->lock);
689 ret = xhci_halt(xhci);
691 spin_lock(&xhci->lock);
693 /* This is bad; the host is not responding to commands and it's
694 * not allowing itself to be halted. At least interrupts are
695 * disabled, so we can set HC_STATE_HALT and notify the
696 * USB core. But if we call usb_hc_died(), it will attempt to
697 * disconnect all device drivers under this host. Those
698 * disconnect() methods will wait for all URBs to be unlinked,
699 * so we must complete them.
701 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
702 xhci_warn(xhci, "Completing active URBs anyway.\n");
703 /* We could turn all TDs on the rings to no-ops. This won't
704 * help if the host has cached part of the ring, and is slow if
705 * we want to preserve the cycle bit. Skip it and hope the host
706 * doesn't touch the memory.
709 for (i = 0; i < MAX_HC_SLOTS; i++) {
712 for (j = 0; j < 31; j++) {
713 temp_ep = &xhci->devs[i]->eps[j];
714 ring = temp_ep->ring;
717 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
718 "ep index %u\n", i, j);
719 while (!list_empty(&ring->td_list)) {
720 cur_td = list_first_entry(&ring->td_list,
723 list_del(&cur_td->td_list);
724 if (!list_empty(&cur_td->cancelled_td_list))
725 list_del(&cur_td->cancelled_td_list);
726 xhci_giveback_urb_in_irq(xhci, cur_td,
727 -ESHUTDOWN, "killed");
729 while (!list_empty(&temp_ep->cancelled_td_list)) {
730 cur_td = list_first_entry(
731 &temp_ep->cancelled_td_list,
734 list_del(&cur_td->cancelled_td_list);
735 xhci_giveback_urb_in_irq(xhci, cur_td,
736 -ESHUTDOWN, "killed");
740 spin_unlock(&xhci->lock);
741 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
742 xhci_dbg(xhci, "Calling usb_hc_died()\n");
743 usb_hc_died(xhci_to_hcd(xhci));
744 xhci_dbg(xhci, "xHCI host controller is dead.\n");
748 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
749 * we need to clear the set deq pending flag in the endpoint ring state, so that
750 * the TD queueing code can ring the doorbell again. We also need to ring the
751 * endpoint doorbell to restart the ring, but only if there aren't more
752 * cancellations pending.
754 static void handle_set_deq_completion(struct xhci_hcd *xhci,
755 struct xhci_event_cmd *event,
758 unsigned int slot_id;
759 unsigned int ep_index;
760 struct xhci_ring *ep_ring;
761 struct xhci_virt_device *dev;
762 struct xhci_ep_ctx *ep_ctx;
763 struct xhci_slot_ctx *slot_ctx;
765 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
766 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
767 dev = xhci->devs[slot_id];
768 ep_ring = dev->eps[ep_index].ring;
769 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
770 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
772 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
773 unsigned int ep_state;
774 unsigned int slot_state;
776 switch (GET_COMP_CODE(event->status)) {
778 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
779 "of stream ID configuration\n");
782 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
783 "to incorrect slot or ep state.\n");
784 ep_state = ep_ctx->ep_info;
785 ep_state &= EP_STATE_MASK;
786 slot_state = slot_ctx->dev_state;
787 slot_state = GET_SLOT_STATE(slot_state);
788 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
789 slot_state, ep_state);
792 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
793 "slot %u was not enabled.\n", slot_id);
796 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
797 "completion code of %u.\n",
798 GET_COMP_CODE(event->status));
801 /* OK what do we do now? The endpoint state is hosed, and we
802 * should never get to this point if the synchronization between
803 * queueing, and endpoint state are correct. This might happen
804 * if the device gets disconnected after we've finished
805 * cancelling URBs, which might not be an error...
808 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
812 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
813 ring_ep_doorbell(xhci, slot_id, ep_index);
816 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
817 struct xhci_event_cmd *event,
821 unsigned int ep_index;
822 struct xhci_ring *ep_ring;
824 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
825 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
826 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
827 /* This command will only fail if the endpoint wasn't halted,
830 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
831 (unsigned int) GET_COMP_CODE(event->status));
833 /* HW with the reset endpoint quirk needs to have a configure endpoint
834 * command complete before the endpoint can be used. Queue that here
835 * because the HW can't handle two commands being queued in a row.
837 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
838 xhci_dbg(xhci, "Queueing configure endpoint command\n");
839 xhci_queue_configure_endpoint(xhci,
840 xhci->devs[slot_id]->in_ctx->dma, slot_id,
842 xhci_ring_cmd_db(xhci);
844 /* Clear our internal halted state and restart the ring */
845 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
846 ring_ep_doorbell(xhci, slot_id, ep_index);
850 /* Check to see if a command in the device's command queue matches this one.
851 * Signal the completion or free the command, and return 1. Return 0 if the
852 * completed command isn't at the head of the command list.
854 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
855 struct xhci_virt_device *virt_dev,
856 struct xhci_event_cmd *event)
858 struct xhci_command *command;
860 if (list_empty(&virt_dev->cmd_list))
863 command = list_entry(virt_dev->cmd_list.next,
864 struct xhci_command, cmd_list);
865 if (xhci->cmd_ring->dequeue != command->command_trb)
869 GET_COMP_CODE(event->status);
870 list_del(&command->cmd_list);
871 if (command->completion)
872 complete(command->completion);
874 xhci_free_command(xhci, command);
878 static void handle_cmd_completion(struct xhci_hcd *xhci,
879 struct xhci_event_cmd *event)
881 int slot_id = TRB_TO_SLOT_ID(event->flags);
883 dma_addr_t cmd_dequeue_dma;
884 struct xhci_input_control_ctx *ctrl_ctx;
885 struct xhci_virt_device *virt_dev;
886 unsigned int ep_index;
887 struct xhci_ring *ep_ring;
888 unsigned int ep_state;
890 cmd_dma = event->cmd_trb;
891 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
892 xhci->cmd_ring->dequeue);
893 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
894 if (cmd_dequeue_dma == 0) {
895 xhci->error_bitmask |= 1 << 4;
898 /* Does the DMA address match our internal dequeue pointer address? */
899 if (cmd_dma != (u64) cmd_dequeue_dma) {
900 xhci->error_bitmask |= 1 << 5;
903 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
904 case TRB_TYPE(TRB_ENABLE_SLOT):
905 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
906 xhci->slot_id = slot_id;
909 complete(&xhci->addr_dev);
911 case TRB_TYPE(TRB_DISABLE_SLOT):
912 if (xhci->devs[slot_id])
913 xhci_free_virt_device(xhci, slot_id);
915 case TRB_TYPE(TRB_CONFIG_EP):
916 virt_dev = xhci->devs[slot_id];
917 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
920 * Configure endpoint commands can come from the USB core
921 * configuration or alt setting changes, or because the HW
922 * needed an extra configure endpoint command after a reset
923 * endpoint command or streams were being configured.
924 * If the command was for a halted endpoint, the xHCI driver
925 * is not waiting on the configure endpoint command.
927 ctrl_ctx = xhci_get_input_control_ctx(xhci,
929 /* Input ctx add_flags are the endpoint index plus one */
930 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
931 /* A usb_set_interface() call directly after clearing a halted
932 * condition may race on this quirky hardware.
933 * Not worth worrying about, since this is prototype hardware.
935 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
936 ep_index != (unsigned int) -1 &&
937 ctrl_ctx->add_flags - SLOT_FLAG ==
938 ctrl_ctx->drop_flags) {
939 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
940 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
941 if (!(ep_state & EP_HALTED))
942 goto bandwidth_change;
943 xhci_dbg(xhci, "Completed config ep cmd - "
944 "last ep index = %d, state = %d\n",
946 /* Clear our internal halted state and restart ring */
947 xhci->devs[slot_id]->eps[ep_index].ep_state &=
949 ring_ep_doorbell(xhci, slot_id, ep_index);
953 xhci_dbg(xhci, "Completed config ep cmd\n");
954 xhci->devs[slot_id]->cmd_status =
955 GET_COMP_CODE(event->status);
956 complete(&xhci->devs[slot_id]->cmd_completion);
958 case TRB_TYPE(TRB_EVAL_CONTEXT):
959 virt_dev = xhci->devs[slot_id];
960 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
962 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
963 complete(&xhci->devs[slot_id]->cmd_completion);
965 case TRB_TYPE(TRB_ADDR_DEV):
966 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
967 complete(&xhci->addr_dev);
969 case TRB_TYPE(TRB_STOP_RING):
970 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
972 case TRB_TYPE(TRB_SET_DEQ):
973 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
975 case TRB_TYPE(TRB_CMD_NOOP):
976 ++xhci->noops_handled;
978 case TRB_TYPE(TRB_RESET_EP):
979 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
981 case TRB_TYPE(TRB_RESET_DEV):
982 xhci_dbg(xhci, "Completed reset device command.\n");
983 slot_id = TRB_TO_SLOT_ID(
984 xhci->cmd_ring->dequeue->generic.field[3]);
985 virt_dev = xhci->devs[slot_id];
987 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
989 xhci_warn(xhci, "Reset device command completion "
990 "for disabled slot %u\n", slot_id);
993 /* Skip over unknown commands on the event ring */
994 xhci->error_bitmask |= 1 << 6;
997 inc_deq(xhci, xhci->cmd_ring, false);
1000 static void handle_port_status(struct xhci_hcd *xhci,
1001 union xhci_trb *event)
1005 /* Port status change events always have a successful completion code */
1006 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1007 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1008 xhci->error_bitmask |= 1 << 8;
1010 /* FIXME: core doesn't care about all port link state changes yet */
1011 port_id = GET_PORT_ID(event->generic.field[0]);
1012 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1014 /* Update event ring dequeue pointer before dropping the lock */
1015 inc_deq(xhci, xhci->event_ring, true);
1016 xhci_set_hc_event_deq(xhci);
1018 spin_unlock(&xhci->lock);
1019 /* Pass this up to the core */
1020 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1021 spin_lock(&xhci->lock);
1025 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1026 * at end_trb, which may be in another segment. If the suspect DMA address is a
1027 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1030 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1031 union xhci_trb *start_trb,
1032 union xhci_trb *end_trb,
1033 dma_addr_t suspect_dma)
1035 dma_addr_t start_dma;
1036 dma_addr_t end_seg_dma;
1037 dma_addr_t end_trb_dma;
1038 struct xhci_segment *cur_seg;
1040 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1041 cur_seg = start_seg;
1046 /* We may get an event for a Link TRB in the middle of a TD */
1047 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1048 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1049 /* If the end TRB isn't in this segment, this is set to 0 */
1050 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1052 if (end_trb_dma > 0) {
1053 /* The end TRB is in this segment, so suspect should be here */
1054 if (start_dma <= end_trb_dma) {
1055 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1058 /* Case for one segment with
1059 * a TD wrapped around to the top
1061 if ((suspect_dma >= start_dma &&
1062 suspect_dma <= end_seg_dma) ||
1063 (suspect_dma >= cur_seg->dma &&
1064 suspect_dma <= end_trb_dma))
1069 /* Might still be somewhere in this segment */
1070 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1073 cur_seg = cur_seg->next;
1074 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1075 } while (cur_seg != start_seg);
1080 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1081 unsigned int slot_id, unsigned int ep_index,
1082 struct xhci_td *td, union xhci_trb *event_trb)
1084 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1085 ep->ep_state |= EP_HALTED;
1086 ep->stopped_td = td;
1087 ep->stopped_trb = event_trb;
1089 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1090 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1092 ep->stopped_td = NULL;
1093 ep->stopped_trb = NULL;
1095 xhci_ring_cmd_db(xhci);
1098 /* Check if an error has halted the endpoint ring. The class driver will
1099 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1100 * However, a babble and other errors also halt the endpoint ring, and the class
1101 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1102 * Ring Dequeue Pointer command manually.
1104 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1105 struct xhci_ep_ctx *ep_ctx,
1106 unsigned int trb_comp_code)
1108 /* TRB completion codes that may require a manual halt cleanup */
1109 if (trb_comp_code == COMP_TX_ERR ||
1110 trb_comp_code == COMP_BABBLE ||
1111 trb_comp_code == COMP_SPLIT_ERR)
1112 /* The 0.96 spec says a babbling control endpoint
1113 * is not halted. The 0.96 spec says it is. Some HW
1114 * claims to be 0.95 compliant, but it halts the control
1115 * endpoint anyway. Check if a babble halted the
1118 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1124 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1126 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1127 /* Vendor defined "informational" completion code,
1128 * treat as not-an-error.
1130 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1132 xhci_dbg(xhci, "Treating code as success.\n");
1139 * If this function returns an error condition, it means it got a Transfer
1140 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1141 * At this point, the host controller is probably hosed and should be reset.
1143 static int handle_tx_event(struct xhci_hcd *xhci,
1144 struct xhci_transfer_event *event)
1146 struct xhci_virt_device *xdev;
1147 struct xhci_virt_ep *ep;
1148 struct xhci_ring *ep_ring;
1149 unsigned int slot_id;
1151 struct xhci_td *td = 0;
1152 dma_addr_t event_dma;
1153 struct xhci_segment *event_seg;
1154 union xhci_trb *event_trb;
1155 struct urb *urb = 0;
1156 int status = -EINPROGRESS;
1157 struct xhci_ep_ctx *ep_ctx;
1160 xhci_dbg(xhci, "In %s\n", __func__);
1161 slot_id = TRB_TO_SLOT_ID(event->flags);
1162 xdev = xhci->devs[slot_id];
1164 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1168 /* Endpoint ID is 1 based, our index is zero based */
1169 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1170 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1171 ep = &xdev->eps[ep_index];
1173 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1174 if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1175 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
1179 event_dma = event->buffer;
1180 /* This TRB should be in the TD at the head of this ring's TD list */
1181 xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
1182 if (list_empty(&ep_ring->td_list)) {
1183 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1184 TRB_TO_SLOT_ID(event->flags), ep_index);
1185 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1186 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1187 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1191 xhci_dbg(xhci, "%s - getting list entry\n", __func__);
1192 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1194 /* Is this a TRB in the currently executing TD? */
1195 xhci_dbg(xhci, "%s - looking for TD\n", __func__);
1196 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1197 td->last_trb, event_dma);
1198 xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
1200 /* HC is busted, give up! */
1201 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1204 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
1205 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1206 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1207 xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
1208 lower_32_bits(event->buffer));
1209 xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
1210 upper_32_bits(event->buffer));
1211 xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
1212 (unsigned int) event->transfer_len);
1213 xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
1214 (unsigned int) event->flags);
1216 /* Look for common error cases */
1217 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1218 switch (trb_comp_code) {
1219 /* Skip codes that require special handling depending on
1226 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1228 case COMP_STOP_INVAL:
1229 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1232 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1233 ep->ep_state |= EP_HALTED;
1237 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1240 case COMP_SPLIT_ERR:
1242 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1246 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1247 status = -EOVERFLOW;
1250 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1254 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1258 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
1262 /* Now update the urb's actual_length and give back to the core */
1263 /* Was this a control transfer? */
1264 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
1265 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1266 switch (trb_comp_code) {
1268 if (event_trb == ep_ring->dequeue) {
1269 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
1270 status = -ESHUTDOWN;
1271 } else if (event_trb != td->last_trb) {
1272 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
1273 status = -ESHUTDOWN;
1275 xhci_dbg(xhci, "Successful control transfer!\n");
1280 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1281 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1282 status = -EREMOTEIO;
1288 if (!xhci_requires_manual_halt_cleanup(xhci,
1289 ep_ctx, trb_comp_code))
1291 xhci_dbg(xhci, "TRB error code %u, "
1292 "halted endpoint index = %u\n",
1293 trb_comp_code, ep_index);
1294 /* else fall through */
1296 /* Did we transfer part of the data (middle) phase? */
1297 if (event_trb != ep_ring->dequeue &&
1298 event_trb != td->last_trb)
1299 td->urb->actual_length =
1300 td->urb->transfer_buffer_length
1301 - TRB_LEN(event->transfer_len);
1303 td->urb->actual_length = 0;
1305 xhci_cleanup_halted_endpoint(xhci,
1306 slot_id, ep_index, td, event_trb);
1310 * Did we transfer any data, despite the errors that might have
1311 * happened? I.e. did we get past the setup stage?
1313 if (event_trb != ep_ring->dequeue) {
1314 /* The event was for the status stage */
1315 if (event_trb == td->last_trb) {
1316 if (td->urb->actual_length != 0) {
1317 /* Don't overwrite a previously set error code */
1318 if ((status == -EINPROGRESS ||
1320 (td->urb->transfer_flags
1321 & URB_SHORT_NOT_OK))
1322 /* Did we already see a short data stage? */
1323 status = -EREMOTEIO;
1325 td->urb->actual_length =
1326 td->urb->transfer_buffer_length;
1329 /* Maybe the event was for the data stage? */
1330 if (trb_comp_code != COMP_STOP_INVAL) {
1331 /* We didn't stop on a link TRB in the middle */
1332 td->urb->actual_length =
1333 td->urb->transfer_buffer_length -
1334 TRB_LEN(event->transfer_len);
1335 xhci_dbg(xhci, "Waiting for status stage event\n");
1342 switch (trb_comp_code) {
1344 /* Double check that the HW transferred everything. */
1345 if (event_trb != td->last_trb) {
1346 xhci_warn(xhci, "WARN Successful completion "
1348 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1349 status = -EREMOTEIO;
1353 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1354 xhci_dbg(xhci, "Successful bulk "
1357 xhci_dbg(xhci, "Successful interrupt "
1363 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1364 status = -EREMOTEIO;
1369 /* Others already handled above */
1372 dev_dbg(&td->urb->dev->dev,
1373 "ep %#x - asked for %d bytes, "
1374 "%d bytes untransferred\n",
1375 td->urb->ep->desc.bEndpointAddress,
1376 td->urb->transfer_buffer_length,
1377 TRB_LEN(event->transfer_len));
1378 /* Fast path - was this the last TRB in the TD for this URB? */
1379 if (event_trb == td->last_trb) {
1380 if (TRB_LEN(event->transfer_len) != 0) {
1381 td->urb->actual_length =
1382 td->urb->transfer_buffer_length -
1383 TRB_LEN(event->transfer_len);
1384 if (td->urb->transfer_buffer_length <
1385 td->urb->actual_length) {
1386 xhci_warn(xhci, "HC gave bad length "
1387 "of %d bytes left\n",
1388 TRB_LEN(event->transfer_len));
1389 td->urb->actual_length = 0;
1390 if (td->urb->transfer_flags &
1392 status = -EREMOTEIO;
1396 /* Don't overwrite a previously set error code */
1397 if (status == -EINPROGRESS) {
1398 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1399 status = -EREMOTEIO;
1404 td->urb->actual_length = td->urb->transfer_buffer_length;
1405 /* Ignore a short packet completion if the
1406 * untransferred length was zero.
1408 if (status == -EREMOTEIO)
1412 /* Slow path - walk the list, starting from the dequeue
1413 * pointer, to get the actual length transferred.
1415 union xhci_trb *cur_trb;
1416 struct xhci_segment *cur_seg;
1418 td->urb->actual_length = 0;
1419 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1420 cur_trb != event_trb;
1421 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1422 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1423 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1424 td->urb->actual_length +=
1425 TRB_LEN(cur_trb->generic.field[2]);
1427 /* If the ring didn't stop on a Link or No-op TRB, add
1428 * in the actual bytes transferred from the Normal TRB
1430 if (trb_comp_code != COMP_STOP_INVAL)
1431 td->urb->actual_length +=
1432 TRB_LEN(cur_trb->generic.field[2]) -
1433 TRB_LEN(event->transfer_len);
1436 if (trb_comp_code == COMP_STOP_INVAL ||
1437 trb_comp_code == COMP_STOP) {
1438 /* The Endpoint Stop Command completion will take care of any
1439 * stopped TDs. A stopped TD may be restarted, so don't update
1440 * the ring dequeue pointer or take this TD off any lists yet.
1442 ep->stopped_td = td;
1443 ep->stopped_trb = event_trb;
1445 if (trb_comp_code == COMP_STALL) {
1446 /* The transfer is completed from the driver's
1447 * perspective, but we need to issue a set dequeue
1448 * command for this stalled endpoint to move the dequeue
1449 * pointer past the TD. We can't do that here because
1450 * the halt condition must be cleared first. Let the
1451 * USB class driver clear the stall later.
1453 ep->stopped_td = td;
1454 ep->stopped_trb = event_trb;
1455 } else if (xhci_requires_manual_halt_cleanup(xhci,
1456 ep_ctx, trb_comp_code)) {
1457 /* Other types of errors halt the endpoint, but the
1458 * class driver doesn't call usb_reset_endpoint() unless
1459 * the error is -EPIPE. Clear the halted status in the
1460 * xHCI hardware manually.
1462 xhci_cleanup_halted_endpoint(xhci,
1463 slot_id, ep_index, td, event_trb);
1465 /* Update ring dequeue pointer */
1466 while (ep_ring->dequeue != td->last_trb)
1467 inc_deq(xhci, ep_ring, false);
1468 inc_deq(xhci, ep_ring, false);
1472 /* Clean up the endpoint's TD list */
1474 /* Do one last check of the actual transfer length.
1475 * If the host controller said we transferred more data than
1476 * the buffer length, urb->actual_length will be a very big
1477 * number (since it's unsigned). Play it safe and say we didn't
1478 * transfer anything.
1480 if (urb->actual_length > urb->transfer_buffer_length) {
1481 xhci_warn(xhci, "URB transfer length is wrong, "
1482 "xHC issue? req. len = %u, "
1484 urb->transfer_buffer_length,
1485 urb->actual_length);
1486 urb->actual_length = 0;
1487 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1488 status = -EREMOTEIO;
1492 list_del(&td->td_list);
1493 /* Was this TD slated to be cancelled but completed anyway? */
1494 if (!list_empty(&td->cancelled_td_list))
1495 list_del(&td->cancelled_td_list);
1497 /* Leave the TD around for the reset endpoint function to use
1498 * (but only if it's not a control endpoint, since we already
1499 * queued the Set TR dequeue pointer command for stalled
1500 * control endpoints).
1502 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1503 (trb_comp_code != COMP_STALL &&
1504 trb_comp_code != COMP_BABBLE)) {
1510 inc_deq(xhci, xhci->event_ring, true);
1511 xhci_set_hc_event_deq(xhci);
1513 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1515 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1516 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1517 urb, urb->actual_length, status);
1518 spin_unlock(&xhci->lock);
1519 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1520 spin_lock(&xhci->lock);
1526 * This function handles all OS-owned events on the event ring. It may drop
1527 * xhci->lock between event processing (e.g. to pass up port status changes).
1529 void xhci_handle_event(struct xhci_hcd *xhci)
1531 union xhci_trb *event;
1532 int update_ptrs = 1;
1535 xhci_dbg(xhci, "In %s\n", __func__);
1536 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1537 xhci->error_bitmask |= 1 << 1;
1541 event = xhci->event_ring->dequeue;
1542 /* Does the HC or OS own the TRB? */
1543 if ((event->event_cmd.flags & TRB_CYCLE) !=
1544 xhci->event_ring->cycle_state) {
1545 xhci->error_bitmask |= 1 << 2;
1548 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1550 /* FIXME: Handle more event types. */
1551 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1552 case TRB_TYPE(TRB_COMPLETION):
1553 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1554 handle_cmd_completion(xhci, &event->event_cmd);
1555 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1557 case TRB_TYPE(TRB_PORT_STATUS):
1558 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1559 handle_port_status(xhci, event);
1560 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1563 case TRB_TYPE(TRB_TRANSFER):
1564 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1565 ret = handle_tx_event(xhci, &event->trans_event);
1566 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1568 xhci->error_bitmask |= 1 << 9;
1573 xhci->error_bitmask |= 1 << 3;
1575 /* Any of the above functions may drop and re-acquire the lock, so check
1576 * to make sure a watchdog timer didn't mark the host as non-responsive.
1578 if (xhci->xhc_state & XHCI_STATE_DYING) {
1579 xhci_dbg(xhci, "xHCI host dying, returning from "
1580 "event handler.\n");
1585 /* Update SW and HC event ring dequeue pointer */
1586 inc_deq(xhci, xhci->event_ring, true);
1587 xhci_set_hc_event_deq(xhci);
1589 /* Are there more items on the event ring? */
1590 xhci_handle_event(xhci);
1593 /**** Endpoint Ring Operations ****/
1596 * Generic function for queueing a TRB on a ring.
1597 * The caller must have checked to make sure there's room on the ring.
1599 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1601 u32 field1, u32 field2, u32 field3, u32 field4)
1603 struct xhci_generic_trb *trb;
1605 trb = &ring->enqueue->generic;
1606 trb->field[0] = field1;
1607 trb->field[1] = field2;
1608 trb->field[2] = field3;
1609 trb->field[3] = field4;
1610 inc_enq(xhci, ring, consumer);
1614 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1615 * FIXME allocate segments if the ring is full.
1617 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1618 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1620 /* Make sure the endpoint has been added to xHC schedule */
1621 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1623 case EP_STATE_DISABLED:
1625 * USB core changed config/interfaces without notifying us,
1626 * or hardware is reporting the wrong state.
1628 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1630 case EP_STATE_ERROR:
1631 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1632 /* FIXME event handling code for error needs to clear it */
1633 /* XXX not sure if this should be -ENOENT or not */
1635 case EP_STATE_HALTED:
1636 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1637 case EP_STATE_STOPPED:
1638 case EP_STATE_RUNNING:
1641 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1643 * FIXME issue Configure Endpoint command to try to get the HC
1644 * back into a known state.
1648 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1649 /* FIXME allocate more room */
1650 xhci_err(xhci, "ERROR no room on ep ring\n");
1656 static int prepare_transfer(struct xhci_hcd *xhci,
1657 struct xhci_virt_device *xdev,
1658 unsigned int ep_index,
1659 unsigned int num_trbs,
1661 struct xhci_td **td,
1665 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1666 ret = prepare_ring(xhci, xdev->eps[ep_index].ring,
1667 ep_ctx->ep_info & EP_STATE_MASK,
1668 num_trbs, mem_flags);
1671 *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1674 INIT_LIST_HEAD(&(*td)->td_list);
1675 INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1677 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1678 if (unlikely(ret)) {
1684 urb->hcpriv = (void *) (*td);
1685 /* Add this TD to the tail of the endpoint ring's TD list */
1686 list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list);
1687 (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg;
1688 (*td)->first_trb = xdev->eps[ep_index].ring->enqueue;
1693 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1695 int num_sgs, num_trbs, running_total, temp, i;
1696 struct scatterlist *sg;
1699 num_sgs = urb->num_sgs;
1700 temp = urb->transfer_buffer_length;
1702 xhci_dbg(xhci, "count sg list trbs: \n");
1704 for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1705 unsigned int previous_total_trbs = num_trbs;
1706 unsigned int len = sg_dma_len(sg);
1708 /* Scatter gather list entries may cross 64KB boundaries */
1709 running_total = TRB_MAX_BUFF_SIZE -
1710 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1711 if (running_total != 0)
1714 /* How many more 64KB chunks to transfer, how many more TRBs? */
1715 while (running_total < sg_dma_len(sg)) {
1717 running_total += TRB_MAX_BUFF_SIZE;
1719 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1720 i, (unsigned long long)sg_dma_address(sg),
1721 len, len, num_trbs - previous_total_trbs);
1723 len = min_t(int, len, temp);
1728 xhci_dbg(xhci, "\n");
1729 if (!in_interrupt())
1730 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1731 urb->ep->desc.bEndpointAddress,
1732 urb->transfer_buffer_length,
1737 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1740 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1741 "TRBs, %d left\n", __func__,
1742 urb->ep->desc.bEndpointAddress, num_trbs);
1743 if (running_total != urb->transfer_buffer_length)
1744 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1745 "queued %#x (%d), asked for %#x (%d)\n",
1747 urb->ep->desc.bEndpointAddress,
1748 running_total, running_total,
1749 urb->transfer_buffer_length,
1750 urb->transfer_buffer_length);
1753 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1754 unsigned int ep_index, int start_cycle,
1755 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1758 * Pass all the TRBs to the hardware at once and make sure this write
1762 start_trb->field[3] |= start_cycle;
1763 ring_ep_doorbell(xhci, slot_id, ep_index);
1767 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1768 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1769 * (comprised of sg list entries) can take several service intervals to
1772 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1773 struct urb *urb, int slot_id, unsigned int ep_index)
1775 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1776 xhci->devs[slot_id]->out_ctx, ep_index);
1780 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1781 ep_interval = urb->interval;
1782 /* Convert to microframes */
1783 if (urb->dev->speed == USB_SPEED_LOW ||
1784 urb->dev->speed == USB_SPEED_FULL)
1786 /* FIXME change this to a warning and a suggestion to use the new API
1787 * to set the polling interval (once the API is added).
1789 if (xhci_interval != ep_interval) {
1790 if (!printk_ratelimit())
1791 dev_dbg(&urb->dev->dev, "Driver uses different interval"
1792 " (%d microframe%s) than xHCI "
1793 "(%d microframe%s)\n",
1795 ep_interval == 1 ? "" : "s",
1797 xhci_interval == 1 ? "" : "s");
1798 urb->interval = xhci_interval;
1799 /* Convert back to frames for LS/FS devices */
1800 if (urb->dev->speed == USB_SPEED_LOW ||
1801 urb->dev->speed == USB_SPEED_FULL)
1804 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1808 * The TD size is the number of bytes remaining in the TD (including this TRB),
1809 * right shifted by 10.
1810 * It must fit in bits 21:17, so it can't be bigger than 31.
1812 static u32 xhci_td_remainder(unsigned int remainder)
1814 u32 max = (1 << (21 - 17 + 1)) - 1;
1816 if ((remainder >> 10) >= max)
1819 return (remainder >> 10) << 17;
1822 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1823 struct urb *urb, int slot_id, unsigned int ep_index)
1825 struct xhci_ring *ep_ring;
1826 unsigned int num_trbs;
1828 struct scatterlist *sg;
1830 int trb_buff_len, this_sg_len, running_total;
1834 struct xhci_generic_trb *start_trb;
1837 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1838 num_trbs = count_sg_trbs_needed(xhci, urb);
1839 num_sgs = urb->num_sgs;
1841 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1842 ep_index, num_trbs, urb, &td, mem_flags);
1843 if (trb_buff_len < 0)
1844 return trb_buff_len;
1846 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1847 * until we've finished creating all the other TRBs. The ring's cycle
1848 * state may change as we enqueue the other TRBs, so save it too.
1850 start_trb = &ep_ring->enqueue->generic;
1851 start_cycle = ep_ring->cycle_state;
1855 * How much data is in the first TRB?
1857 * There are three forces at work for TRB buffer pointers and lengths:
1858 * 1. We don't want to walk off the end of this sg-list entry buffer.
1859 * 2. The transfer length that the driver requested may be smaller than
1860 * the amount of memory allocated for this scatter-gather list.
1861 * 3. TRBs buffers can't cross 64KB boundaries.
1864 addr = (u64) sg_dma_address(sg);
1865 this_sg_len = sg_dma_len(sg);
1866 trb_buff_len = TRB_MAX_BUFF_SIZE -
1867 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1868 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1869 if (trb_buff_len > urb->transfer_buffer_length)
1870 trb_buff_len = urb->transfer_buffer_length;
1871 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1875 /* Queue the first TRB, even if it's zero-length */
1878 u32 length_field = 0;
1881 /* Don't change the cycle bit of the first TRB until later */
1885 field |= ep_ring->cycle_state;
1887 /* Chain all the TRBs together; clear the chain bit in the last
1888 * TRB to indicate it's the last TRB in the chain.
1893 /* FIXME - add check for ZERO_PACKET flag before this */
1894 td->last_trb = ep_ring->enqueue;
1897 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1898 "64KB boundary at %#x, end dma = %#x\n",
1899 (unsigned int) addr, trb_buff_len, trb_buff_len,
1900 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1901 (unsigned int) addr + trb_buff_len);
1902 if (TRB_MAX_BUFF_SIZE -
1903 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1904 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1905 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1906 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1907 (unsigned int) addr + trb_buff_len);
1909 remainder = xhci_td_remainder(urb->transfer_buffer_length -
1911 length_field = TRB_LEN(trb_buff_len) |
1914 queue_trb(xhci, ep_ring, false,
1915 lower_32_bits(addr),
1916 upper_32_bits(addr),
1918 /* We always want to know if the TRB was short,
1919 * or we won't get an event when it completes.
1920 * (Unless we use event data TRBs, which are a
1921 * waste of space and HC resources.)
1923 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1925 running_total += trb_buff_len;
1927 /* Calculate length for next transfer --
1928 * Are we done queueing all the TRBs for this sg entry?
1930 this_sg_len -= trb_buff_len;
1931 if (this_sg_len == 0) {
1936 addr = (u64) sg_dma_address(sg);
1937 this_sg_len = sg_dma_len(sg);
1939 addr += trb_buff_len;
1942 trb_buff_len = TRB_MAX_BUFF_SIZE -
1943 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1944 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1945 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1947 urb->transfer_buffer_length - running_total;
1948 } while (running_total < urb->transfer_buffer_length);
1950 check_trb_math(urb, num_trbs, running_total);
1951 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1955 /* This is very similar to what ehci-q.c qtd_fill() does */
1956 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1957 struct urb *urb, int slot_id, unsigned int ep_index)
1959 struct xhci_ring *ep_ring;
1962 struct xhci_generic_trb *start_trb;
1965 u32 field, length_field;
1967 int running_total, trb_buff_len, ret;
1971 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1973 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1976 /* How much data is (potentially) left before the 64KB boundary? */
1977 running_total = TRB_MAX_BUFF_SIZE -
1978 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1980 /* If there's some data on this 64KB chunk, or we have to send a
1981 * zero-length transfer, we need at least one TRB
1983 if (running_total != 0 || urb->transfer_buffer_length == 0)
1985 /* How many more 64KB chunks to transfer, how many more TRBs? */
1986 while (running_total < urb->transfer_buffer_length) {
1988 running_total += TRB_MAX_BUFF_SIZE;
1990 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1992 if (!in_interrupt())
1993 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1994 urb->ep->desc.bEndpointAddress,
1995 urb->transfer_buffer_length,
1996 urb->transfer_buffer_length,
1997 (unsigned long long)urb->transfer_dma,
2000 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
2001 num_trbs, urb, &td, mem_flags);
2006 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2007 * until we've finished creating all the other TRBs. The ring's cycle
2008 * state may change as we enqueue the other TRBs, so save it too.
2010 start_trb = &ep_ring->enqueue->generic;
2011 start_cycle = ep_ring->cycle_state;
2014 /* How much data is in the first TRB? */
2015 addr = (u64) urb->transfer_dma;
2016 trb_buff_len = TRB_MAX_BUFF_SIZE -
2017 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2018 if (urb->transfer_buffer_length < trb_buff_len)
2019 trb_buff_len = urb->transfer_buffer_length;
2023 /* Queue the first TRB, even if it's zero-length */
2028 /* Don't change the cycle bit of the first TRB until later */
2032 field |= ep_ring->cycle_state;
2034 /* Chain all the TRBs together; clear the chain bit in the last
2035 * TRB to indicate it's the last TRB in the chain.
2040 /* FIXME - add check for ZERO_PACKET flag before this */
2041 td->last_trb = ep_ring->enqueue;
2044 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2046 length_field = TRB_LEN(trb_buff_len) |
2049 queue_trb(xhci, ep_ring, false,
2050 lower_32_bits(addr),
2051 upper_32_bits(addr),
2053 /* We always want to know if the TRB was short,
2054 * or we won't get an event when it completes.
2055 * (Unless we use event data TRBs, which are a
2056 * waste of space and HC resources.)
2058 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2060 running_total += trb_buff_len;
2062 /* Calculate length for next transfer */
2063 addr += trb_buff_len;
2064 trb_buff_len = urb->transfer_buffer_length - running_total;
2065 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2066 trb_buff_len = TRB_MAX_BUFF_SIZE;
2067 } while (running_total < urb->transfer_buffer_length);
2069 check_trb_math(urb, num_trbs, running_total);
2070 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
2074 /* Caller must have locked xhci->lock */
2075 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2076 struct urb *urb, int slot_id, unsigned int ep_index)
2078 struct xhci_ring *ep_ring;
2081 struct usb_ctrlrequest *setup;
2082 struct xhci_generic_trb *start_trb;
2084 u32 field, length_field;
2087 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2090 * Need to copy setup packet into setup TRB, so we can't use the setup
2093 if (!urb->setup_packet)
2096 if (!in_interrupt())
2097 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2099 /* 1 TRB for setup, 1 for status */
2102 * Don't need to check if we need additional event data and normal TRBs,
2103 * since data in control transfers will never get bigger than 16MB
2104 * XXX: can we get a buffer that crosses 64KB boundaries?
2106 if (urb->transfer_buffer_length > 0)
2108 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
2109 urb, &td, mem_flags);
2114 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2115 * until we've finished creating all the other TRBs. The ring's cycle
2116 * state may change as we enqueue the other TRBs, so save it too.
2118 start_trb = &ep_ring->enqueue->generic;
2119 start_cycle = ep_ring->cycle_state;
2121 /* Queue setup TRB - see section 6.4.1.2.1 */
2122 /* FIXME better way to translate setup_packet into two u32 fields? */
2123 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2124 queue_trb(xhci, ep_ring, false,
2125 /* FIXME endianness is probably going to bite my ass here. */
2126 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2127 setup->wIndex | setup->wLength << 16,
2128 TRB_LEN(8) | TRB_INTR_TARGET(0),
2129 /* Immediate data in pointer */
2130 TRB_IDT | TRB_TYPE(TRB_SETUP));
2132 /* If there's data, queue data TRBs */
2134 length_field = TRB_LEN(urb->transfer_buffer_length) |
2135 xhci_td_remainder(urb->transfer_buffer_length) |
2137 if (urb->transfer_buffer_length > 0) {
2138 if (setup->bRequestType & USB_DIR_IN)
2139 field |= TRB_DIR_IN;
2140 queue_trb(xhci, ep_ring, false,
2141 lower_32_bits(urb->transfer_dma),
2142 upper_32_bits(urb->transfer_dma),
2144 /* Event on short tx */
2145 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2148 /* Save the DMA address of the last TRB in the TD */
2149 td->last_trb = ep_ring->enqueue;
2151 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2152 /* If the device sent data, the status stage is an OUT transfer */
2153 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2157 queue_trb(xhci, ep_ring, false,
2161 /* Event on completion */
2162 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2164 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
2168 /**** Command Ring Operations ****/
2170 /* Generic function for queueing a command TRB on the command ring.
2171 * Check to make sure there's room on the command ring for one command TRB.
2172 * Also check that there's room reserved for commands that must not fail.
2173 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2174 * then only check for the number of reserved spots.
2175 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2176 * because the command event handler may want to resubmit a failed command.
2178 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2179 u32 field3, u32 field4, bool command_must_succeed)
2181 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2182 if (!command_must_succeed)
2185 if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
2186 if (!in_interrupt())
2187 xhci_err(xhci, "ERR: No room for command on command ring\n");
2188 if (command_must_succeed)
2189 xhci_err(xhci, "ERR: Reserved TRB counting for "
2190 "unfailable commands failed.\n");
2193 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
2194 field4 | xhci->cmd_ring->cycle_state);
2198 /* Queue a no-op command on the command ring */
2199 static int queue_cmd_noop(struct xhci_hcd *xhci)
2201 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2205 * Place a no-op command on the command ring to test the command and
2208 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2210 if (queue_cmd_noop(xhci) < 0)
2212 xhci->noops_submitted++;
2213 return xhci_ring_cmd_db;
2216 /* Queue a slot enable or disable request on the command ring */
2217 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2219 return queue_command(xhci, 0, 0, 0,
2220 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2223 /* Queue an address device command TRB */
2224 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2227 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2228 upper_32_bits(in_ctx_ptr), 0,
2229 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2233 /* Queue a reset device command TRB */
2234 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
2236 return queue_command(xhci, 0, 0, 0,
2237 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
2241 /* Queue a configure endpoint command TRB */
2242 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2243 u32 slot_id, bool command_must_succeed)
2245 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2246 upper_32_bits(in_ctx_ptr), 0,
2247 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2248 command_must_succeed);
2251 /* Queue an evaluate context command TRB */
2252 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2255 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2256 upper_32_bits(in_ctx_ptr), 0,
2257 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2261 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2262 unsigned int ep_index)
2264 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2265 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2266 u32 type = TRB_TYPE(TRB_STOP_RING);
2268 return queue_command(xhci, 0, 0, 0,
2269 trb_slot_id | trb_ep_index | type, false);
2272 /* Set Transfer Ring Dequeue Pointer command.
2273 * This should not be used for endpoints that have streams enabled.
2275 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2276 unsigned int ep_index, struct xhci_segment *deq_seg,
2277 union xhci_trb *deq_ptr, u32 cycle_state)
2280 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2281 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2282 u32 type = TRB_TYPE(TRB_SET_DEQ);
2284 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2286 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2287 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2291 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2292 upper_32_bits(addr), 0,
2293 trb_slot_id | trb_ep_index | type, false);
2296 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2297 unsigned int ep_index)
2299 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2300 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2301 u32 type = TRB_TYPE(TRB_RESET_EP);
2303 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,