drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 static u32 i915_gem_get_seqno(struct drm_device *dev)
  38 {
  39         drm_i915_private_t *dev_priv = dev->dev_private;
  40         u32 seqno;
  41
  42         seqno = dev_priv->next_seqno;
  43
  44         /* reserve 0 for non-seqno */
  45         if (++dev_priv->next_seqno == 0)
  46                 dev_priv->next_seqno = 1;
  47
  48         return seqno;
  49 }
  50
  51 static void
  52 render_ring_flush(struct intel_ring_buffer *ring,
  53                   u32   invalidate_domains,
  54                   u32   flush_domains)
  55 {
  56         struct drm_device *dev = ring->dev;
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 cmd;
  59
  60 #if WATCH_EXEC
  61         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
  62                   invalidate_domains, flush_domains);
  63 #endif
  64
  65         trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
  66                                      invalidate_domains, flush_domains);
  67
  68         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
  69                 /*
  70                  * read/write caches:
  71                  *
  72                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  73                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  74                  * also flushed at 2d versus 3d pipeline switches.
  75                  *
  76                  * read-only caches:
  77                  *
  78                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  79                  * MI_READ_FLUSH is set, and is always flushed on 965.
  80                  *
  81                  * I915_GEM_DOMAIN_COMMAND may not exist?
  82                  *
  83                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  84                  * invalidated when MI_EXE_FLUSH is set.
  85                  *
  86                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  87                  * invalidated with every MI_FLUSH.
  88                  *
  89                  * TLBs:
  90                  *
  91                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  92                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  93                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  94                  * are flushed at any MI_FLUSH.
  95                  */
  96
  97                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  98                 if ((invalidate_domains|flush_domains) &
  99                     I915_GEM_DOMAIN_RENDER)
 100                         cmd &= ~MI_NO_WRITE_FLUSH;
 101                 if (INTEL_INFO(dev)->gen < 4) {
 102                         /*
 103                          * On the 965, the sampler cache always gets flushed
 104                          * and this bit is reserved.
 105                          */
 106                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                                 cmd |= MI_READ_FLUSH;
 108                 }
 109                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 110                         cmd |= MI_EXE_FLUSH;
 111
 112                 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 113                     (IS_G4X(dev) || IS_GEN5(dev)))
 114                         cmd |= MI_INVALIDATE_ISP;
 115
 116 #if WATCH_EXEC
 117                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 118 #endif
 119                 if (intel_ring_begin(ring, 2) == 0) {
 120                         intel_ring_emit(ring, cmd);
 121                         intel_ring_emit(ring, MI_NOOP);
 122                         intel_ring_advance(ring);
 123                 }
 124         }
 125 }
 126
 127 static void ring_write_tail(struct intel_ring_buffer *ring,
 128                             u32 value)
 129 {
 130         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 131         I915_WRITE_TAIL(ring, value);
 132 }
 133
 134 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 135 {
 136         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 137         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 138                         RING_ACTHD(ring->mmio_base) : ACTHD;
 139
 140         return I915_READ(acthd_reg);
 141 }
 142
 143 static int init_ring_common(struct intel_ring_buffer *ring)
 144 {
 145         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 146         struct drm_i915_gem_object *obj = ring->obj;
 147         u32 head;
 148
 149         /* Stop the ring if it's running. */
 150         I915_WRITE_CTL(ring, 0);
 151         I915_WRITE_HEAD(ring, 0);
 152         ring->write_tail(ring, 0);
 153
 154         /* Initialize the ring. */
 155         I915_WRITE_START(ring, obj->gtt_offset);
 156         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 157
 158         /* G45 ring initialization fails to reset head to zero */
 159         if (head != 0) {
 160                 DRM_DEBUG_KMS("%s head not reset to zero "
 161                               "ctl %08x head %08x tail %08x start %08x\n",
 162                               ring->name,
 163                               I915_READ_CTL(ring),
 164                               I915_READ_HEAD(ring),
 165                               I915_READ_TAIL(ring),
 166                               I915_READ_START(ring));
 167
 168                 I915_WRITE_HEAD(ring, 0);
 169
 170                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 171                         DRM_ERROR("failed to set %s head to zero "
 172                                   "ctl %08x head %08x tail %08x start %08x\n",
 173                                   ring->name,
 174                                   I915_READ_CTL(ring),
 175                                   I915_READ_HEAD(ring),
 176                                   I915_READ_TAIL(ring),
 177                                   I915_READ_START(ring));
 178                 }
 179         }
 180
 181         I915_WRITE_CTL(ring,
 182                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 183                         | RING_REPORT_64K | RING_VALID);
 184
 185         /* If the head is still not zero, the ring is dead */
 186         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 187             I915_READ_START(ring) != obj->gtt_offset ||
 188             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 189                 DRM_ERROR("%s initialization failed "
 190                                 "ctl %08x head %08x tail %08x start %08x\n",
 191                                 ring->name,
 192                                 I915_READ_CTL(ring),
 193                                 I915_READ_HEAD(ring),
 194                                 I915_READ_TAIL(ring),
 195                                 I915_READ_START(ring));
 196                 return -EIO;
 197         }
 198
 199         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 200                 i915_kernel_lost_context(ring->dev);
 201         else {
 202                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 203                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 204                 ring->space = ring->head - (ring->tail + 8);
 205                 if (ring->space < 0)
 206                         ring->space += ring->size;
 207         }
 208
 209         return 0;
 210 }
 211
 212 static int init_render_ring(struct intel_ring_buffer *ring)
 213 {
 214         struct drm_device *dev = ring->dev;
 215         struct drm_i915_private *dev_priv = dev->dev_private;
 216         int ret = init_ring_common(ring);
 217
 218         if (INTEL_INFO(dev)->gen > 3) {
 219                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 220                 if (IS_GEN6(dev))
 221                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 222                 I915_WRITE(MI_MODE, mode);
 223         }
 224
 225         return ret;
 226 }
 227
 228 static void
 229 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
 230 {
 231         struct drm_device *dev = ring->dev;
 232         struct drm_i915_private *dev_priv = dev->dev_private;
 233         int id;
 234
 235         /*
 236          * cs -> 1 = vcs, 0 = bcs
 237          * vcs -> 1 = bcs, 0 = cs,
 238          * bcs -> 1 = cs, 0 = vcs.
 239          */
 240         id = ring - dev_priv->ring;
 241         id += 2 - i;
 242         id %= 3;
 243
 244         intel_ring_emit(ring,
 245                         MI_SEMAPHORE_MBOX |
 246                         MI_SEMAPHORE_REGISTER |
 247                         MI_SEMAPHORE_UPDATE);
 248         intel_ring_emit(ring, seqno);
 249         intel_ring_emit(ring,
 250                         RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
 251 }
 252
 253 static int
 254 gen6_add_request(struct intel_ring_buffer *ring,
 255                  u32 *result)
 256 {
 257         u32 seqno;
 258         int ret;
 259
 260         ret = intel_ring_begin(ring, 10);
 261         if (ret)
 262                 return ret;
 263
 264         seqno = i915_gem_get_seqno(ring->dev);
 265         update_semaphore(ring, 0, seqno);
 266         update_semaphore(ring, 1, seqno);
 267
 268         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 269         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 270         intel_ring_emit(ring, seqno);
 271         intel_ring_emit(ring, MI_USER_INTERRUPT);
 272         intel_ring_advance(ring);
 273
 274         *result = seqno;
 275         return 0;
 276 }
 277
 278 int
 279 intel_ring_sync(struct intel_ring_buffer *ring,
 280                 struct intel_ring_buffer *to,
 281                 u32 seqno)
 282 {
 283         int ret;
 284
 285         ret = intel_ring_begin(ring, 4);
 286         if (ret)
 287                 return ret;
 288
 289         intel_ring_emit(ring,
 290                         MI_SEMAPHORE_MBOX |
 291                         MI_SEMAPHORE_REGISTER |
 292                         intel_ring_sync_index(ring, to) << 17 |
 293                         MI_SEMAPHORE_COMPARE);
 294         intel_ring_emit(ring, seqno);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_emit(ring, MI_NOOP);
 297         intel_ring_advance(ring);
 298
 299         return 0;
 300 }
 301
 302 static int
 303 render_ring_add_request(struct intel_ring_buffer *ring,
 304                         u32 *result)
 305 {
 306         struct drm_device *dev = ring->dev;
 307         u32 seqno = i915_gem_get_seqno(dev);
 308         int ret;
 309
 310         ret = intel_ring_begin(ring, 4);
 311         if (ret)
 312                 return ret;
 313
 314         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 315         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 316         intel_ring_emit(ring, seqno);
 317         intel_ring_emit(ring, MI_USER_INTERRUPT);
 318         intel_ring_advance(ring);
 319
 320         *result = seqno;
 321         return 0;
 322 }
 323
 324 static u32
 325 ring_get_seqno(struct intel_ring_buffer *ring)
 326 {
 327         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 328 }
 329
 330 static void
 331 render_ring_get_irq(struct intel_ring_buffer *ring)
 332 {
 333         struct drm_device *dev = ring->dev;
 334
 335         if (dev->irq_enabled && ++ring->irq_refcount == 1) {
 336                 drm_i915_private_t *dev_priv = dev->dev_private;
 337                 unsigned long irqflags;
 338
 339                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 340
 341                 if (HAS_PCH_SPLIT(dev))
 342                         ironlake_enable_graphics_irq(dev_priv,
 343                                                      GT_USER_INTERRUPT);
 344                 else
 345                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 346
 347                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 348         }
 349 }
 350
 351 static void
 352 render_ring_put_irq(struct intel_ring_buffer *ring)
 353 {
 354         struct drm_device *dev = ring->dev;
 355
 356         BUG_ON(dev->irq_enabled && ring->irq_refcount == 0);
 357         if (dev->irq_enabled && --ring->irq_refcount == 0) {
 358                 drm_i915_private_t *dev_priv = dev->dev_private;
 359                 unsigned long irqflags;
 360
 361                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 362                 if (HAS_PCH_SPLIT(dev))
 363                         ironlake_disable_graphics_irq(dev_priv,
 364                                                       GT_USER_INTERRUPT);
 365                 else
 366                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 367                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 368         }
 369 }
 370
 371 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 372 {
 373         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 374         u32 mmio = IS_GEN6(ring->dev) ?
 375                 RING_HWS_PGA_GEN6(ring->mmio_base) :
 376                 RING_HWS_PGA(ring->mmio_base);
 377         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 378         POSTING_READ(mmio);
 379 }
 380
 381 static void
 382 bsd_ring_flush(struct intel_ring_buffer *ring,
 383                u32     invalidate_domains,
 384                u32     flush_domains)
 385 {
 386         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
 387                 return;
 388
 389         if (intel_ring_begin(ring, 2) == 0) {
 390                 intel_ring_emit(ring, MI_FLUSH);
 391                 intel_ring_emit(ring, MI_NOOP);
 392                 intel_ring_advance(ring);
 393         }
 394 }
 395
 396 static int
 397 ring_add_request(struct intel_ring_buffer *ring,
 398                  u32 *result)
 399 {
 400         u32 seqno;
 401         int ret;
 402
 403         ret = intel_ring_begin(ring, 4);
 404         if (ret)
 405                 return ret;
 406
 407         seqno = i915_gem_get_seqno(ring->dev);
 408
 409         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 410         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 411         intel_ring_emit(ring, seqno);
 412         intel_ring_emit(ring, MI_USER_INTERRUPT);
 413         intel_ring_advance(ring);
 414
 415         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
 416         *result = seqno;
 417         return 0;
 418 }
 419
 420 static void
 421 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
 422 {
 423         struct drm_device *dev = ring->dev;
 424
 425         if (dev->irq_enabled && ++ring->irq_refcount == 1) {
 426                 drm_i915_private_t *dev_priv = dev->dev_private;
 427                 unsigned long irqflags;
 428
 429                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 430                 ironlake_enable_graphics_irq(dev_priv, flag);
 431                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 432         }
 433 }
 434
 435 static void
 436 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
 437 {
 438         struct drm_device *dev = ring->dev;
 439
 440         if (dev->irq_enabled && --ring->irq_refcount == 0) {
 441                 drm_i915_private_t *dev_priv = dev->dev_private;
 442                 unsigned long irqflags;
 443
 444                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 445                 ironlake_disable_graphics_irq(dev_priv, flag);
 446                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 447         }
 448 }
 449
 450
 451 static void
 452 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 453 {
 454     ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
 455 }
 456 static void
 457 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 458 {
 459     ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
 460 }
 461
 462 static int
 463 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 464 {
 465         int ret;
 466
 467         ret = intel_ring_begin(ring, 2);
 468         if (ret)
 469                 return ret;
 470
 471         intel_ring_emit(ring,
 472                         MI_BATCH_BUFFER_START | (2 << 6) |
 473                         MI_BATCH_NON_SECURE_I965);
 474         intel_ring_emit(ring, offset);
 475         intel_ring_advance(ring);
 476
 477         return 0;
 478 }
 479
 480 static int
 481 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 482                                 u32 offset, u32 len)
 483 {
 484         struct drm_device *dev = ring->dev;
 485         drm_i915_private_t *dev_priv = dev->dev_private;
 486         int ret;
 487
 488         trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
 489
 490         if (IS_I830(dev) || IS_845G(dev)) {
 491                 ret = intel_ring_begin(ring, 4);
 492                 if (ret)
 493                         return ret;
 494
 495                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 496                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 497                 intel_ring_emit(ring, offset + len - 8);
 498                 intel_ring_emit(ring, 0);
 499         } else {
 500                 ret = intel_ring_begin(ring, 2);
 501                 if (ret)
 502                         return ret;
 503
 504                 if (INTEL_INFO(dev)->gen >= 4) {
 505                         intel_ring_emit(ring,
 506                                         MI_BATCH_BUFFER_START | (2 << 6) |
 507                                         MI_BATCH_NON_SECURE_I965);
 508                         intel_ring_emit(ring, offset);
 509                 } else {
 510                         intel_ring_emit(ring,
 511                                         MI_BATCH_BUFFER_START | (2 << 6));
 512                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 513                 }
 514         }
 515         intel_ring_advance(ring);
 516
 517         return 0;
 518 }
 519
 520 static void cleanup_status_page(struct intel_ring_buffer *ring)
 521 {
 522         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 523         struct drm_i915_gem_object *obj;
 524
 525         obj = ring->status_page.obj;
 526         if (obj == NULL)
 527                 return;
 528
 529         kunmap(obj->pages[0]);
 530         i915_gem_object_unpin(obj);
 531         drm_gem_object_unreference(&obj->base);
 532         ring->status_page.obj = NULL;
 533
 534         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 535 }
 536
 537 static int init_status_page(struct intel_ring_buffer *ring)
 538 {
 539         struct drm_device *dev = ring->dev;
 540         drm_i915_private_t *dev_priv = dev->dev_private;
 541         struct drm_i915_gem_object *obj;
 542         int ret;
 543
 544         obj = i915_gem_alloc_object(dev, 4096);
 545         if (obj == NULL) {
 546                 DRM_ERROR("Failed to allocate status page\n");
 547                 ret = -ENOMEM;
 548                 goto err;
 549         }
 550         obj->agp_type = AGP_USER_CACHED_MEMORY;
 551
 552         ret = i915_gem_object_pin(obj, 4096, true);
 553         if (ret != 0) {
 554                 goto err_unref;
 555         }
 556
 557         ring->status_page.gfx_addr = obj->gtt_offset;
 558         ring->status_page.page_addr = kmap(obj->pages[0]);
 559         if (ring->status_page.page_addr == NULL) {
 560                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 561                 goto err_unpin;
 562         }
 563         ring->status_page.obj = obj;
 564         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 565
 566         intel_ring_setup_status_page(ring);
 567         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 568                         ring->name, ring->status_page.gfx_addr);
 569
 570         return 0;
 571
 572 err_unpin:
 573         i915_gem_object_unpin(obj);
 574 err_unref:
 575         drm_gem_object_unreference(&obj->base);
 576 err:
 577         return ret;
 578 }
 579
 580 int intel_init_ring_buffer(struct drm_device *dev,
 581                            struct intel_ring_buffer *ring)
 582 {
 583         struct drm_i915_gem_object *obj;
 584         int ret;
 585
 586         ring->dev = dev;
 587         INIT_LIST_HEAD(&ring->active_list);
 588         INIT_LIST_HEAD(&ring->request_list);
 589         INIT_LIST_HEAD(&ring->gpu_write_list);
 590
 591         if (I915_NEED_GFX_HWS(dev)) {
 592                 ret = init_status_page(ring);
 593                 if (ret)
 594                         return ret;
 595         }
 596
 597         obj = i915_gem_alloc_object(dev, ring->size);
 598         if (obj == NULL) {
 599                 DRM_ERROR("Failed to allocate ringbuffer\n");
 600                 ret = -ENOMEM;
 601                 goto err_hws;
 602         }
 603
 604         ring->obj = obj;
 605
 606         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
 607         if (ret)
 608                 goto err_unref;
 609
 610         ring->map.size = ring->size;
 611         ring->map.offset = dev->agp->base + obj->gtt_offset;
 612         ring->map.type = 0;
 613         ring->map.flags = 0;
 614         ring->map.mtrr = 0;
 615
 616         drm_core_ioremap_wc(&ring->map, dev);
 617         if (ring->map.handle == NULL) {
 618                 DRM_ERROR("Failed to map ringbuffer.\n");
 619                 ret = -EINVAL;
 620                 goto err_unpin;
 621         }
 622
 623         ring->virtual_start = ring->map.handle;
 624         ret = ring->init(ring);
 625         if (ret)
 626                 goto err_unmap;
 627
 628         return 0;
 629
 630 err_unmap:
 631         drm_core_ioremapfree(&ring->map, dev);
 632 err_unpin:
 633         i915_gem_object_unpin(obj);
 634 err_unref:
 635         drm_gem_object_unreference(&obj->base);
 636         ring->obj = NULL;
 637 err_hws:
 638         cleanup_status_page(ring);
 639         return ret;
 640 }
 641
 642 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
 643 {
 644         struct drm_i915_private *dev_priv;
 645         int ret;
 646
 647         if (ring->obj == NULL)
 648                 return;
 649
 650         /* Disable the ring buffer. The ring must be idle at this point */
 651         dev_priv = ring->dev->dev_private;
 652         ret = intel_wait_ring_buffer(ring, ring->size - 8);
 653         I915_WRITE_CTL(ring, 0);
 654
 655         drm_core_ioremapfree(&ring->map, ring->dev);
 656
 657         i915_gem_object_unpin(ring->obj);
 658         drm_gem_object_unreference(&ring->obj->base);
 659         ring->obj = NULL;
 660
 661         if (ring->cleanup)
 662                 ring->cleanup(ring);
 663
 664         cleanup_status_page(ring);
 665 }
 666
 667 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
 668 {
 669         unsigned int *virt;
 670         int rem;
 671         rem = ring->size - ring->tail;
 672
 673         if (ring->space < rem) {
 674                 int ret = intel_wait_ring_buffer(ring, rem);
 675                 if (ret)
 676                         return ret;
 677         }
 678
 679         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 680         rem /= 8;
 681         while (rem--) {
 682                 *virt++ = MI_NOOP;
 683                 *virt++ = MI_NOOP;
 684         }
 685
 686         ring->tail = 0;
 687         ring->space = ring->head - 8;
 688
 689         return 0;
 690 }
 691
 692 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
 693 {
 694         struct drm_device *dev = ring->dev;
 695         struct drm_i915_private *dev_priv = dev->dev_private;
 696         unsigned long end;
 697         u32 head;
 698
 699         trace_i915_ring_wait_begin (dev);
 700         end = jiffies + 3 * HZ;
 701         do {
 702                 /* If the reported head position has wrapped or hasn't advanced,
 703                  * fallback to the slow and accurate path.
 704                  */
 705                 head = intel_read_status_page(ring, 4);
 706                 if (head < ring->actual_head)
 707                         head = I915_READ_HEAD(ring);
 708                 ring->actual_head = head;
 709                 ring->head = head & HEAD_ADDR;
 710                 ring->space = ring->head - (ring->tail + 8);
 711                 if (ring->space < 0)
 712                         ring->space += ring->size;
 713                 if (ring->space >= n) {
 714                         trace_i915_ring_wait_end(dev);
 715                         return 0;
 716                 }
 717
 718                 if (dev->primary->master) {
 719                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 720                         if (master_priv->sarea_priv)
 721                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 722                 }
 723
 724                 msleep(1);
 725                 if (atomic_read(&dev_priv->mm.wedged))
 726                         return -EAGAIN;
 727         } while (!time_after(jiffies, end));
 728         trace_i915_ring_wait_end (dev);
 729         return -EBUSY;
 730 }
 731
 732 int intel_ring_begin(struct intel_ring_buffer *ring,
 733                      int num_dwords)
 734 {
 735         int n = 4*num_dwords;
 736         int ret;
 737
 738         if (unlikely(ring->tail + n > ring->size)) {
 739                 ret = intel_wrap_ring_buffer(ring);
 740                 if (unlikely(ret))
 741                         return ret;
 742         }
 743
 744         if (unlikely(ring->space < n)) {
 745                 ret = intel_wait_ring_buffer(ring, n);
 746                 if (unlikely(ret))
 747                         return ret;
 748         }
 749
 750         ring->space -= n;
 751         return 0;
 752 }
 753
 754 void intel_ring_advance(struct intel_ring_buffer *ring)
 755 {
 756         ring->tail &= ring->size - 1;
 757         ring->write_tail(ring, ring->tail);
 758 }
 759
 760 static const struct intel_ring_buffer render_ring = {
 761         .name                   = "render ring",
 762         .id                     = RING_RENDER,
 763         .mmio_base              = RENDER_RING_BASE,
 764         .size                   = 32 * PAGE_SIZE,
 765         .init                   = init_render_ring,
 766         .write_tail             = ring_write_tail,
 767         .flush                  = render_ring_flush,
 768         .add_request            = render_ring_add_request,
 769         .get_seqno              = ring_get_seqno,
 770         .irq_get                = render_ring_get_irq,
 771         .irq_put                = render_ring_put_irq,
 772         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
 773 };
 774
 775 /* ring buffer for bit-stream decoder */
 776
 777 static const struct intel_ring_buffer bsd_ring = {
 778         .name                   = "bsd ring",
 779         .id                     = RING_BSD,
 780         .mmio_base              = BSD_RING_BASE,
 781         .size                   = 32 * PAGE_SIZE,
 782         .init                   = init_ring_common,
 783         .write_tail             = ring_write_tail,
 784         .flush                  = bsd_ring_flush,
 785         .add_request            = ring_add_request,
 786         .get_seqno              = ring_get_seqno,
 787         .irq_get                = bsd_ring_get_irq,
 788         .irq_put                = bsd_ring_put_irq,
 789         .dispatch_execbuffer    = ring_dispatch_execbuffer,
 790 };
 791
 792
 793 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
 794                                      u32 value)
 795 {
 796        drm_i915_private_t *dev_priv = ring->dev->dev_private;
 797
 798        /* Every tail move must follow the sequence below */
 799        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 800                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 801                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
 802        I915_WRITE(GEN6_BSD_RNCID, 0x0);
 803
 804        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
 805                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
 806                        50))
 807                DRM_ERROR("timed out waiting for IDLE Indicator\n");
 808
 809        I915_WRITE_TAIL(ring, value);
 810        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 811                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 812                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
 813 }
 814
 815 static void gen6_ring_flush(struct intel_ring_buffer *ring,
 816                             u32 invalidate_domains,
 817                             u32 flush_domains)
 818 {
 819         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
 820                 return;
 821
 822         if (intel_ring_begin(ring, 4) == 0) {
 823                 intel_ring_emit(ring, MI_FLUSH_DW);
 824                 intel_ring_emit(ring, 0);
 825                 intel_ring_emit(ring, 0);
 826                 intel_ring_emit(ring, 0);
 827                 intel_ring_advance(ring);
 828         }
 829 }
 830
 831 static int
 832 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 833                               u32 offset, u32 len)
 834 {
 835        int ret;
 836
 837        ret = intel_ring_begin(ring, 2);
 838        if (ret)
 839                return ret;
 840
 841        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
 842        /* bit0-7 is the length on GEN6+ */
 843        intel_ring_emit(ring, offset);
 844        intel_ring_advance(ring);
 845
 846        return 0;
 847 }
 848
 849 static void
 850 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
 851 {
 852     ring_get_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
 853 }
 854
 855 static void
 856 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
 857 {
 858     ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
 859 }
 860
 861 /* ring buffer for Video Codec for Gen6+ */
 862 static const struct intel_ring_buffer gen6_bsd_ring = {
 863         .name                   = "gen6 bsd ring",
 864         .id                     = RING_BSD,
 865         .mmio_base              = GEN6_BSD_RING_BASE,
 866         .size                   = 32 * PAGE_SIZE,
 867         .init                   = init_ring_common,
 868         .write_tail             = gen6_bsd_ring_write_tail,
 869         .flush                  = gen6_ring_flush,
 870         .add_request            = gen6_add_request,
 871         .get_seqno              = ring_get_seqno,
 872         .irq_get                = gen6_bsd_ring_get_irq,
 873         .irq_put                = gen6_bsd_ring_put_irq,
 874         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
 875 };
 876
 877 /* Blitter support (SandyBridge+) */
 878
 879 static void
 880 blt_ring_get_irq(struct intel_ring_buffer *ring)
 881 {
 882     ring_get_irq(ring, GT_BLT_USER_INTERRUPT);
 883 }
 884
 885 static void
 886 blt_ring_put_irq(struct intel_ring_buffer *ring)
 887 {
 888     ring_put_irq(ring, GT_BLT_USER_INTERRUPT);
 889 }
 890
 891
 892 /* Workaround for some stepping of SNB,
 893  * each time when BLT engine ring tail moved,
 894  * the first command in the ring to be parsed
 895  * should be MI_BATCH_BUFFER_START
 896  */
 897 #define NEED_BLT_WORKAROUND(dev) \
 898         (IS_GEN6(dev) && (dev->pdev->revision < 8))
 899
 900 static inline struct drm_i915_gem_object *
 901 to_blt_workaround(struct intel_ring_buffer *ring)
 902 {
 903         return ring->private;
 904 }
 905
 906 static int blt_ring_init(struct intel_ring_buffer *ring)
 907 {
 908         if (NEED_BLT_WORKAROUND(ring->dev)) {
 909                 struct drm_i915_gem_object *obj;
 910                 u32 *ptr;
 911                 int ret;
 912
 913                 obj = i915_gem_alloc_object(ring->dev, 4096);
 914                 if (obj == NULL)
 915                         return -ENOMEM;
 916
 917                 ret = i915_gem_object_pin(obj, 4096, true);
 918                 if (ret) {
 919                         drm_gem_object_unreference(&obj->base);
 920                         return ret;
 921                 }
 922
 923                 ptr = kmap(obj->pages[0]);
 924                 *ptr++ = MI_BATCH_BUFFER_END;
 925                 *ptr++ = MI_NOOP;
 926                 kunmap(obj->pages[0]);
 927
 928                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
 929                 if (ret) {
 930                         i915_gem_object_unpin(obj);
 931                         drm_gem_object_unreference(&obj->base);
 932                         return ret;
 933                 }
 934
 935                 ring->private = obj;
 936         }
 937
 938         return init_ring_common(ring);
 939 }
 940
 941 static int blt_ring_begin(struct intel_ring_buffer *ring,
 942                           int num_dwords)
 943 {
 944         if (ring->private) {
 945                 int ret = intel_ring_begin(ring, num_dwords+2);
 946                 if (ret)
 947                         return ret;
 948
 949                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
 950                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
 951
 952                 return 0;
 953         } else
 954                 return intel_ring_begin(ring, 4);
 955 }
 956
 957 static void blt_ring_flush(struct intel_ring_buffer *ring,
 958                            u32 invalidate_domains,
 959                            u32 flush_domains)
 960 {
 961         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
 962                 return;
 963
 964         if (blt_ring_begin(ring, 4) == 0) {
 965                 intel_ring_emit(ring, MI_FLUSH_DW);
 966                 intel_ring_emit(ring, 0);
 967                 intel_ring_emit(ring, 0);
 968                 intel_ring_emit(ring, 0);
 969                 intel_ring_advance(ring);
 970         }
 971 }
 972
 973 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
 974 {
 975         if (!ring->private)
 976                 return;
 977
 978         i915_gem_object_unpin(ring->private);
 979         drm_gem_object_unreference(ring->private);
 980         ring->private = NULL;
 981 }
 982
 983 static const struct intel_ring_buffer gen6_blt_ring = {
 984        .name                    = "blt ring",
 985        .id                      = RING_BLT,
 986        .mmio_base               = BLT_RING_BASE,
 987        .size                    = 32 * PAGE_SIZE,
 988        .init                    = blt_ring_init,
 989        .write_tail              = ring_write_tail,
 990        .flush                   = blt_ring_flush,
 991        .add_request             = gen6_add_request,
 992        .get_seqno               = ring_get_seqno,
 993        .irq_get                 = blt_ring_get_irq,
 994        .irq_put                 = blt_ring_put_irq,
 995        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
 996        .cleanup                 = blt_ring_cleanup,
 997 };
 998
 999 int intel_init_render_ring_buffer(struct drm_device *dev)
1000 {
1001         drm_i915_private_t *dev_priv = dev->dev_private;
1002         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1003
1004         *ring = render_ring;
1005         if (INTEL_INFO(dev)->gen >= 6) {
1006                 ring->add_request = gen6_add_request;
1007         }
1008
1009         if (!I915_NEED_GFX_HWS(dev)) {
1010                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1011                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1012         }
1013
1014         return intel_init_ring_buffer(dev, ring);
1015 }
1016
1017 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1018 {
1019         drm_i915_private_t *dev_priv = dev->dev_private;
1020         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1021
1022         if (IS_GEN6(dev))
1023                 *ring = gen6_bsd_ring;
1024         else
1025                 *ring = bsd_ring;
1026
1027         return intel_init_ring_buffer(dev, ring);
1028 }
1029
1030 int intel_init_blt_ring_buffer(struct drm_device *dev)
1031 {
1032         drm_i915_private_t *dev_priv = dev->dev_private;
1033         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1034
1035         *ring = gen6_blt_ring;
1036
1037         return intel_init_ring_buffer(dev, ring);
1038 }