drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/serial_reg.h>
  18 #include <linux/pci.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24
  25 #include <linux/dmaengine.h>
  26 #include <linux/pch_dma.h>
  27
  28 enum {
  29         PCH_UART_HANDLED_RX_INT_SHIFT,
  30         PCH_UART_HANDLED_TX_INT_SHIFT,
  31         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  33         PCH_UART_HANDLED_MS_INT_SHIFT,
  34 };
  35
  36 enum {
  37         PCH_UART_8LINE,
  38         PCH_UART_2LINE,
  39 };
  40
  41 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  42
  43 /* Set the max number of UART port
  44  * Intel EG20T PCH: 4 port
  45  * OKI SEMICONDUCTOR ML7213 IOH: 3 port
  46 */
  47 #define PCH_UART_NR     4
  48
  49 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  50 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  51 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  52                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  53 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  54                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  55 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  56
  57 #define PCH_UART_RBR            0x00
  58 #define PCH_UART_THR            0x00
  59
  60 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  61                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  62 #define PCH_UART_IER_ERBFI      0x00000001
  63 #define PCH_UART_IER_ETBEI      0x00000002
  64 #define PCH_UART_IER_ELSI       0x00000004
  65 #define PCH_UART_IER_EDSSI      0x00000008
  66
  67 #define PCH_UART_IIR_IP                 0x00000001
  68 #define PCH_UART_IIR_IID                0x00000006
  69 #define PCH_UART_IIR_MSI                0x00000000
  70 #define PCH_UART_IIR_TRI                0x00000002
  71 #define PCH_UART_IIR_RRI                0x00000004
  72 #define PCH_UART_IIR_REI                0x00000006
  73 #define PCH_UART_IIR_TOI                0x00000008
  74 #define PCH_UART_IIR_FIFO256            0x00000020
  75 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  76 #define PCH_UART_IIR_FE                 0x000000C0
  77
  78 #define PCH_UART_FCR_FIFOE              0x00000001
  79 #define PCH_UART_FCR_RFR                0x00000002
  80 #define PCH_UART_FCR_TFR                0x00000004
  81 #define PCH_UART_FCR_DMS                0x00000008
  82 #define PCH_UART_FCR_FIFO256            0x00000020
  83 #define PCH_UART_FCR_RFTL               0x000000C0
  84
  85 #define PCH_UART_FCR_RFTL1              0x00000000
  86 #define PCH_UART_FCR_RFTL64             0x00000040
  87 #define PCH_UART_FCR_RFTL128            0x00000080
  88 #define PCH_UART_FCR_RFTL224            0x000000C0
  89 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  90 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  91 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  92 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  93 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  94 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  95 #define PCH_UART_FCR_RFTL_SHIFT         6
  96
  97 #define PCH_UART_LCR_WLS        0x00000003
  98 #define PCH_UART_LCR_STB        0x00000004
  99 #define PCH_UART_LCR_PEN        0x00000008
 100 #define PCH_UART_LCR_EPS        0x00000010
 101 #define PCH_UART_LCR_SP         0x00000020
 102 #define PCH_UART_LCR_SB         0x00000040
 103 #define PCH_UART_LCR_DLAB       0x00000080
 104 #define PCH_UART_LCR_NP         0x00000000
 105 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 106 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 107 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 108 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 109                                 PCH_UART_LCR_SP)
 110
 111 #define PCH_UART_LCR_5BIT       0x00000000
 112 #define PCH_UART_LCR_6BIT       0x00000001
 113 #define PCH_UART_LCR_7BIT       0x00000002
 114 #define PCH_UART_LCR_8BIT       0x00000003
 115
 116 #define PCH_UART_MCR_DTR        0x00000001
 117 #define PCH_UART_MCR_RTS        0x00000002
 118 #define PCH_UART_MCR_OUT        0x0000000C
 119 #define PCH_UART_MCR_LOOP       0x00000010
 120 #define PCH_UART_MCR_AFE        0x00000020
 121
 122 #define PCH_UART_LSR_DR         0x00000001
 123 #define PCH_UART_LSR_ERR        (1<<7)
 124
 125 #define PCH_UART_MSR_DCTS       0x00000001
 126 #define PCH_UART_MSR_DDSR       0x00000002
 127 #define PCH_UART_MSR_TERI       0x00000004
 128 #define PCH_UART_MSR_DDCD       0x00000008
 129 #define PCH_UART_MSR_CTS        0x00000010
 130 #define PCH_UART_MSR_DSR        0x00000020
 131 #define PCH_UART_MSR_RI         0x00000040
 132 #define PCH_UART_MSR_DCD        0x00000080
 133 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 134                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 135
 136 #define PCH_UART_DLL            0x00
 137 #define PCH_UART_DLM            0x01
 138
 139 #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
 140
 141 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 142 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 143 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 144 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 145 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 146
 147 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 148 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 149 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 150 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 151 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 152 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 153 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 154 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 155 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 156 #define PCH_UART_HAL_STB1               0
 157 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 158
 159 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 160 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 161 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 162                                         PCH_UART_HAL_CLR_RX_FIFO)
 163
 164 #define PCH_UART_HAL_DMA_MODE0          0
 165 #define PCH_UART_HAL_FIFO_DIS           0
 166 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 167 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 168                                         PCH_UART_FCR_FIFO256)
 169 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 170 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 171 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 172 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 173 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 174 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 175 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 176 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 177 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 178 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 179 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 180 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 181 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 182 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 183
 184 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 185 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 186 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 187 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 188 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 189
 190 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 191 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 192 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 193 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 194 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 195
 196 #define PCI_VENDOR_ID_ROHM              0x10DB
 197
 198 struct pch_uart_buffer {
 199         unsigned char *buf;
 200         int size;
 201 };
 202
 203 struct eg20t_port {
 204         struct uart_port port;
 205         int port_type;
 206         void __iomem *membase;
 207         resource_size_t mapbase;
 208         unsigned int iobase;
 209         struct pci_dev *pdev;
 210         int fifo_size;
 211         int base_baud;
 212         int start_tx;
 213         int start_rx;
 214         int tx_empty;
 215         int int_dis_flag;
 216         int trigger;
 217         int trigger_level;
 218         struct pch_uart_buffer rxbuf;
 219         unsigned int dmsr;
 220         unsigned int fcr;
 221         unsigned int use_dma;
 222         unsigned int use_dma_flag;
 223         struct dma_async_tx_descriptor  *desc_tx;
 224         struct dma_async_tx_descriptor  *desc_rx;
 225         struct pch_dma_slave            param_tx;
 226         struct pch_dma_slave            param_rx;
 227         struct dma_chan                 *chan_tx;
 228         struct dma_chan                 *chan_rx;
 229         struct scatterlist              *sg_tx_p;
 230         int                             nent;
 231         struct scatterlist              sg_rx;
 232         int                             tx_dma_use;
 233         void                            *rx_buf_virt;
 234         dma_addr_t                      rx_buf_dma;
 235 };
 236
 237 static unsigned int default_baud = 9600;
 238 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 239 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 240 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 241 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 242
 243 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 244                                  int base_baud)
 245 {
 246         struct eg20t_port *priv = pci_get_drvdata(pdev);
 247
 248         priv->trigger_level = 1;
 249         priv->fcr = 0;
 250 }
 251
 252 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 253 {
 254         unsigned int msr = ioread8(base + UART_MSR);
 255         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 256
 257         return msr;
 258 }
 259
 260 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 261                                           unsigned int flag)
 262 {
 263         u8 ier = ioread8(priv->membase + UART_IER);
 264         ier |= flag & PCH_UART_IER_MASK;
 265         iowrite8(ier, priv->membase + UART_IER);
 266 }
 267
 268 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 269                                            unsigned int flag)
 270 {
 271         u8 ier = ioread8(priv->membase + UART_IER);
 272         ier &= ~(flag & PCH_UART_IER_MASK);
 273         iowrite8(ier, priv->membase + UART_IER);
 274 }
 275
 276 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 277                                  unsigned int parity, unsigned int bits,
 278                                  unsigned int stb)
 279 {
 280         unsigned int dll, dlm, lcr;
 281         int div;
 282
 283         div = DIV_ROUND(priv->base_baud / 16, baud);
 284         if (div < 0 || USHRT_MAX <= div) {
 285                 pr_err("Invalid Baud(div=0x%x)\n", div);
 286                 return -EINVAL;
 287         }
 288
 289         dll = (unsigned int)div & 0x00FFU;
 290         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 291
 292         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 293                 pr_err("Invalid parity(0x%x)\n", parity);
 294                 return -EINVAL;
 295         }
 296
 297         if (bits & ~PCH_UART_LCR_WLS) {
 298                 pr_err("Invalid bits(0x%x)\n", bits);
 299                 return -EINVAL;
 300         }
 301
 302         if (stb & ~PCH_UART_LCR_STB) {
 303                 pr_err("Invalid STB(0x%x)\n", stb);
 304                 return -EINVAL;
 305         }
 306
 307         lcr = parity;
 308         lcr |= bits;
 309         lcr |= stb;
 310
 311         pr_debug("%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 312                  __func__, baud, div, lcr, jiffies);
 313         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 314         iowrite8(dll, priv->membase + PCH_UART_DLL);
 315         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 316         iowrite8(lcr, priv->membase + UART_LCR);
 317
 318         return 0;
 319 }
 320
 321 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 322                                     unsigned int flag)
 323 {
 324         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 325                 pr_err("%s:Invalid flag(0x%x)\n", __func__, flag);
 326                 return -EINVAL;
 327         }
 328
 329         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 330         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 331                  priv->membase + UART_FCR);
 332         iowrite8(priv->fcr, priv->membase + UART_FCR);
 333
 334         return 0;
 335 }
 336
 337 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 338                                  unsigned int dmamode,
 339                                  unsigned int fifo_size, unsigned int trigger)
 340 {
 341         u8 fcr;
 342
 343         if (dmamode & ~PCH_UART_FCR_DMS) {
 344                 pr_err("%s:Invalid DMA Mode(0x%x)\n", __func__, dmamode);
 345                 return -EINVAL;
 346         }
 347
 348         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 349                 pr_err("%s:Invalid FIFO SIZE(0x%x)\n", __func__, fifo_size);
 350                 return -EINVAL;
 351         }
 352
 353         if (trigger & ~PCH_UART_FCR_RFTL) {
 354                 pr_err("%s:Invalid TRIGGER(0x%x)\n", __func__, trigger);
 355                 return -EINVAL;
 356         }
 357
 358         switch (priv->fifo_size) {
 359         case 256:
 360                 priv->trigger_level =
 361                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 362                 break;
 363         case 64:
 364                 priv->trigger_level =
 365                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 366                 break;
 367         case 16:
 368                 priv->trigger_level =
 369                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 370                 break;
 371         default:
 372                 priv->trigger_level =
 373                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 374                 break;
 375         }
 376         fcr =
 377             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 378         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 379         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 380                  priv->membase + UART_FCR);
 381         iowrite8(fcr, priv->membase + UART_FCR);
 382         priv->fcr = fcr;
 383
 384         return 0;
 385 }
 386
 387 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 388 {
 389         priv->dmsr = 0;
 390         return get_msr(priv, priv->membase);
 391 }
 392
 393 static int pch_uart_hal_write(struct eg20t_port *priv,
 394                               const unsigned char *buf, int tx_size)
 395 {
 396         int i;
 397         unsigned int thr;
 398
 399         for (i = 0; i < tx_size;) {
 400                 thr = buf[i++];
 401                 iowrite8(thr, priv->membase + PCH_UART_THR);
 402         }
 403         return i;
 404 }
 405
 406 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 407                              int rx_size)
 408 {
 409         int i;
 410         u8 rbr, lsr;
 411
 412         lsr = ioread8(priv->membase + UART_LSR);
 413         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 414              i < rx_size && lsr & UART_LSR_DR;
 415              lsr = ioread8(priv->membase + UART_LSR)) {
 416                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 417                 buf[i++] = rbr;
 418         }
 419         return i;
 420 }
 421
 422 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 423 {
 424         unsigned int iir;
 425         int ret;
 426
 427         iir = ioread8(priv->membase + UART_IIR);
 428         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 429         return ret;
 430 }
 431
 432 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 433 {
 434         return ioread8(priv->membase + UART_LSR);
 435 }
 436
 437 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 438 {
 439         unsigned int lcr;
 440
 441         lcr = ioread8(priv->membase + UART_LCR);
 442         if (on)
 443                 lcr |= PCH_UART_LCR_SB;
 444         else
 445                 lcr &= ~PCH_UART_LCR_SB;
 446
 447         iowrite8(lcr, priv->membase + UART_LCR);
 448 }
 449
 450 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 451                    int size)
 452 {
 453         struct uart_port *port;
 454         struct tty_struct *tty;
 455
 456         port = &priv->port;
 457         tty = tty_port_tty_get(&port->state->port);
 458         if (!tty) {
 459                 pr_debug("%s:tty is busy now", __func__);
 460                 return -EBUSY;
 461         }
 462
 463         tty_insert_flip_string(tty, buf, size);
 464         tty_flip_buffer_push(tty);
 465         tty_kref_put(tty);
 466
 467         return 0;
 468 }
 469
 470 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 471 {
 472         int ret;
 473         struct uart_port *port = &priv->port;
 474
 475         if (port->x_char) {
 476                 pr_debug("%s:X character send %02x (%lu)\n", __func__,
 477                         port->x_char, jiffies);
 478                 buf[0] = port->x_char;
 479                 port->x_char = 0;
 480                 ret = 1;
 481         } else {
 482                 ret = 0;
 483         }
 484
 485         return ret;
 486 }
 487
 488 static int dma_push_rx(struct eg20t_port *priv, int size)
 489 {
 490         struct tty_struct *tty;
 491         int room;
 492         struct uart_port *port = &priv->port;
 493
 494         port = &priv->port;
 495         tty = tty_port_tty_get(&port->state->port);
 496         if (!tty) {
 497                 pr_debug("%s:tty is busy now", __func__);
 498                 return 0;
 499         }
 500
 501         room = tty_buffer_request_room(tty, size);
 502
 503         if (room < size)
 504                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 505                          size - room);
 506         if (!room)
 507                 return room;
 508
 509         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 510
 511         port->icount.rx += room;
 512         tty_kref_put(tty);
 513
 514         return room;
 515 }
 516
 517 static void pch_free_dma(struct uart_port *port)
 518 {
 519         struct eg20t_port *priv;
 520         priv = container_of(port, struct eg20t_port, port);
 521
 522         if (priv->chan_tx) {
 523                 dma_release_channel(priv->chan_tx);
 524                 priv->chan_tx = NULL;
 525         }
 526         if (priv->chan_rx) {
 527                 dma_release_channel(priv->chan_rx);
 528                 priv->chan_rx = NULL;
 529         }
 530         if (sg_dma_address(&priv->sg_rx))
 531                 dma_free_coherent(port->dev, port->fifosize,
 532                                   sg_virt(&priv->sg_rx),
 533                                   sg_dma_address(&priv->sg_rx));
 534
 535         return;
 536 }
 537
 538 static bool filter(struct dma_chan *chan, void *slave)
 539 {
 540         struct pch_dma_slave *param = slave;
 541
 542         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 543                                                   chan->device->dev)) {
 544                 chan->private = param;
 545                 return true;
 546         } else {
 547                 return false;
 548         }
 549 }
 550
 551 static void pch_request_dma(struct uart_port *port)
 552 {
 553         dma_cap_mask_t mask;
 554         struct dma_chan *chan;
 555         struct pci_dev *dma_dev;
 556         struct pch_dma_slave *param;
 557         struct eg20t_port *priv =
 558                                 container_of(port, struct eg20t_port, port);
 559         dma_cap_zero(mask);
 560         dma_cap_set(DMA_SLAVE, mask);
 561
 562         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 563                                                                 information */
 564         /* Set Tx DMA */
 565         param = &priv->param_tx;
 566         param->dma_dev = &dma_dev->dev;
 567         param->chan_id = priv->port.line;
 568         param->tx_reg = port->mapbase + UART_TX;
 569         chan = dma_request_channel(mask, filter, param);
 570         if (!chan) {
 571                 pr_err("%s:dma_request_channel FAILS(Tx)\n", __func__);
 572                 return;
 573         }
 574         priv->chan_tx = chan;
 575
 576         /* Set Rx DMA */
 577         param = &priv->param_rx;
 578         param->dma_dev = &dma_dev->dev;
 579         param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */
 580         param->rx_reg = port->mapbase + UART_RX;
 581         chan = dma_request_channel(mask, filter, param);
 582         if (!chan) {
 583                 pr_err("%s:dma_request_channel FAILS(Rx)\n", __func__);
 584                 dma_release_channel(priv->chan_tx);
 585                 return;
 586         }
 587
 588         /* Get Consistent memory for DMA */
 589         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 590                                     &priv->rx_buf_dma, GFP_KERNEL);
 591         priv->chan_rx = chan;
 592 }
 593
 594 static void pch_dma_rx_complete(void *arg)
 595 {
 596         struct eg20t_port *priv = arg;
 597         struct uart_port *port = &priv->port;
 598         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 599         int count;
 600
 601         if (!tty) {
 602                 pr_debug("%s:tty is busy now", __func__);
 603                 return;
 604         }
 605
 606         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 607         count = dma_push_rx(priv, priv->trigger_level);
 608         if (count)
 609                 tty_flip_buffer_push(tty);
 610         tty_kref_put(tty);
 611         async_tx_ack(priv->desc_rx);
 612         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
 613 }
 614
 615 static void pch_dma_tx_complete(void *arg)
 616 {
 617         struct eg20t_port *priv = arg;
 618         struct uart_port *port = &priv->port;
 619         struct circ_buf *xmit = &port->state->xmit;
 620         struct scatterlist *sg = priv->sg_tx_p;
 621         int i;
 622
 623         for (i = 0; i < priv->nent; i++, sg++) {
 624                 xmit->tail += sg_dma_len(sg);
 625                 port->icount.tx += sg_dma_len(sg);
 626         }
 627         xmit->tail &= UART_XMIT_SIZE - 1;
 628         async_tx_ack(priv->desc_tx);
 629         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 630         priv->tx_dma_use = 0;
 631         priv->nent = 0;
 632         kfree(priv->sg_tx_p);
 633         if (uart_circ_chars_pending(xmit))
 634                 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 635 }
 636
 637 static int pop_tx(struct eg20t_port *priv, unsigned char *buf, int size)
 638 {
 639         int count = 0;
 640         struct uart_port *port = &priv->port;
 641         struct circ_buf *xmit = &port->state->xmit;
 642
 643         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 644                 goto pop_tx_end;
 645
 646         do {
 647                 int cnt_to_end =
 648                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 649                 int sz = min(size - count, cnt_to_end);
 650                 memcpy(&buf[count], &xmit->buf[xmit->tail], sz);
 651                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 652                 count += sz;
 653         } while (!uart_circ_empty(xmit) && count < size);
 654
 655 pop_tx_end:
 656         pr_debug("%d characters. Remained %d characters. (%lu)\n",
 657                  count, size - count, jiffies);
 658
 659         return count;
 660 }
 661
 662 static int handle_rx_to(struct eg20t_port *priv)
 663 {
 664         struct pch_uart_buffer *buf;
 665         int rx_size;
 666         int ret;
 667         if (!priv->start_rx) {
 668                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 669                 return 0;
 670         }
 671         buf = &priv->rxbuf;
 672         do {
 673                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 674                 ret = push_rx(priv, buf->buf, rx_size);
 675                 if (ret)
 676                         return 0;
 677         } while (rx_size == buf->size);
 678
 679         return PCH_UART_HANDLED_RX_INT;
 680 }
 681
 682 static int handle_rx(struct eg20t_port *priv)
 683 {
 684         return handle_rx_to(priv);
 685 }
 686
 687 static int dma_handle_rx(struct eg20t_port *priv)
 688 {
 689         struct uart_port *port = &priv->port;
 690         struct dma_async_tx_descriptor *desc;
 691         struct scatterlist *sg;
 692
 693         priv = container_of(port, struct eg20t_port, port);
 694         sg = &priv->sg_rx;
 695
 696         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 697
 698         sg_dma_len(sg) = priv->trigger_level;
 699
 700         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 701                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 702                      ~PAGE_MASK);
 703
 704         sg_dma_address(sg) = priv->rx_buf_dma;
 705
 706         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 707                         sg, 1, DMA_FROM_DEVICE,
 708                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 709
 710         if (!desc)
 711                 return 0;
 712
 713         priv->desc_rx = desc;
 714         desc->callback = pch_dma_rx_complete;
 715         desc->callback_param = priv;
 716         desc->tx_submit(desc);
 717         dma_async_issue_pending(priv->chan_rx);
 718
 719         return PCH_UART_HANDLED_RX_INT;
 720 }
 721
 722 static unsigned int handle_tx(struct eg20t_port *priv)
 723 {
 724         struct uart_port *port = &priv->port;
 725         struct circ_buf *xmit = &port->state->xmit;
 726         int ret;
 727         int fifo_size;
 728         int tx_size;
 729         int size;
 730         int tx_empty;
 731
 732         if (!priv->start_tx) {
 733                 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
 734                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 735                 priv->tx_empty = 1;
 736                 return 0;
 737         }
 738
 739         fifo_size = max(priv->fifo_size, 1);
 740         tx_empty = 1;
 741         if (pop_tx_x(priv, xmit->buf)) {
 742                 pch_uart_hal_write(priv, xmit->buf, 1);
 743                 port->icount.tx++;
 744                 tx_empty = 0;
 745                 fifo_size--;
 746         }
 747         size = min(xmit->head - xmit->tail, fifo_size);
 748         if (size < 0)
 749                 size = fifo_size;
 750
 751         tx_size = pop_tx(priv, xmit->buf, size);
 752         if (tx_size > 0) {
 753                 ret = pch_uart_hal_write(priv, xmit->buf, tx_size);
 754                 port->icount.tx += ret;
 755                 tx_empty = 0;
 756         }
 757
 758         priv->tx_empty = tx_empty;
 759
 760         if (tx_empty) {
 761                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 762                 uart_write_wakeup(port);
 763         }
 764
 765         return PCH_UART_HANDLED_TX_INT;
 766 }
 767
 768 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 769 {
 770         struct uart_port *port = &priv->port;
 771         struct circ_buf *xmit = &port->state->xmit;
 772         struct scatterlist *sg;
 773         int nent;
 774         int fifo_size;
 775         int tx_empty;
 776         struct dma_async_tx_descriptor *desc;
 777         int num;
 778         int i;
 779         int bytes;
 780         int size;
 781         int rem;
 782
 783         if (!priv->start_tx) {
 784                 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
 785                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 786                 priv->tx_empty = 1;
 787                 return 0;
 788         }
 789
 790         fifo_size = max(priv->fifo_size, 1);
 791         tx_empty = 1;
 792         if (pop_tx_x(priv, xmit->buf)) {
 793                 pch_uart_hal_write(priv, xmit->buf, 1);
 794                 port->icount.tx++;
 795                 tx_empty = 0;
 796                 fifo_size--;
 797         }
 798
 799         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 800                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 801                              xmit->tail, UART_XMIT_SIZE));
 802         if (!bytes) {
 803                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 804                 uart_write_wakeup(port);
 805                 return 0;
 806         }
 807
 808         if (bytes > fifo_size) {
 809                 num = bytes / fifo_size + 1;
 810                 size = fifo_size;
 811                 rem = bytes % fifo_size;
 812         } else {
 813                 num = 1;
 814                 size = bytes;
 815                 rem = bytes;
 816         }
 817
 818         priv->tx_dma_use = 1;
 819
 820         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 821
 822         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 823         sg = priv->sg_tx_p;
 824
 825         for (i = 0; i < num; i++, sg++) {
 826                 if (i == (num - 1))
 827                         sg_set_page(sg, virt_to_page(xmit->buf),
 828                                     rem, fifo_size * i);
 829                 else
 830                         sg_set_page(sg, virt_to_page(xmit->buf),
 831                                     size, fifo_size * i);
 832         }
 833
 834         sg = priv->sg_tx_p;
 835         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 836         if (!nent) {
 837                 pr_err("%s:dma_map_sg Failed\n", __func__);
 838                 return 0;
 839         }
 840         priv->nent = nent;
 841
 842         for (i = 0; i < nent; i++, sg++) {
 843                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 844                               fifo_size * i;
 845                 sg_dma_address(sg) = (sg_dma_address(sg) &
 846                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 847                 if (i == (nent - 1))
 848                         sg_dma_len(sg) = rem;
 849                 else
 850                         sg_dma_len(sg) = size;
 851         }
 852
 853         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 854                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 855                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 856         if (!desc) {
 857                 pr_err("%s:device_prep_slave_sg Failed\n", __func__);
 858                 return 0;
 859         }
 860         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 861         priv->desc_tx = desc;
 862         desc->callback = pch_dma_tx_complete;
 863         desc->callback_param = priv;
 864
 865         desc->tx_submit(desc);
 866
 867         dma_async_issue_pending(priv->chan_tx);
 868
 869         return PCH_UART_HANDLED_TX_INT;
 870 }
 871
 872 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 873 {
 874         u8 fcr = ioread8(priv->membase + UART_FCR);
 875
 876         /* Reset FIFO */
 877         fcr |= UART_FCR_CLEAR_RCVR;
 878         iowrite8(fcr, priv->membase + UART_FCR);
 879
 880         if (lsr & PCH_UART_LSR_ERR)
 881                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 882
 883         if (lsr & UART_LSR_FE)
 884                 dev_err(&priv->pdev->dev, "Framing Error\n");
 885
 886         if (lsr & UART_LSR_PE)
 887                 dev_err(&priv->pdev->dev, "Parity Error\n");
 888
 889         if (lsr & UART_LSR_OE)
 890                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 891 }
 892
 893 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 894 {
 895         struct eg20t_port *priv = dev_id;
 896         unsigned int handled;
 897         u8 lsr;
 898         int ret = 0;
 899         unsigned int iid;
 900         unsigned long flags;
 901
 902         spin_lock_irqsave(&priv->port.lock, flags);
 903         handled = 0;
 904         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 905                 switch (iid) {
 906                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 907                         lsr = pch_uart_hal_get_line_status(priv);
 908                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 909                                                 UART_LSR_PE | UART_LSR_OE)) {
 910                                 pch_uart_err_ir(priv, lsr);
 911                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 912                         }
 913                         break;
 914                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 915                         if (priv->use_dma) {
 916                                 pch_uart_hal_disable_interrupt(priv,
 917                                                         PCH_UART_HAL_RX_INT);
 918                                 ret = dma_handle_rx(priv);
 919                                 if (!ret)
 920                                         pch_uart_hal_enable_interrupt(priv,
 921                                                         PCH_UART_HAL_RX_INT);
 922                         } else {
 923                                 ret = handle_rx(priv);
 924                         }
 925                         break;
 926                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 927                                                    (FIFO Timeout) */
 928                         ret = handle_rx_to(priv);
 929                         break;
 930                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
 931                                                    Empty */
 932                         if (priv->use_dma)
 933                                 ret = dma_handle_tx(priv);
 934                         else
 935                                 ret = handle_tx(priv);
 936                         break;
 937                 case PCH_UART_IID_MS:   /* Modem Status */
 938                         ret = PCH_UART_HANDLED_MS_INT;
 939                         break;
 940                 default:        /* Never junp to this label */
 941                         pr_err("%s:iid=%d (%lu)\n", __func__, iid, jiffies);
 942                         ret = -1;
 943                         break;
 944                 }
 945                 handled |= (unsigned int)ret;
 946         }
 947         if (handled == 0 && iid <= 1) {
 948                 if (priv->int_dis_flag)
 949                         priv->int_dis_flag = 0;
 950         }
 951
 952         spin_unlock_irqrestore(&priv->port.lock, flags);
 953         return IRQ_RETVAL(handled);
 954 }
 955
 956 /* This function tests whether the transmitter fifo and shifter for the port
 957                                                 described by 'port' is empty. */
 958 static unsigned int pch_uart_tx_empty(struct uart_port *port)
 959 {
 960         struct eg20t_port *priv;
 961         int ret;
 962         priv = container_of(port, struct eg20t_port, port);
 963         if (priv->tx_empty)
 964                 ret = TIOCSER_TEMT;
 965         else
 966                 ret = 0;
 967
 968         return ret;
 969 }
 970
 971 /* Returns the current state of modem control inputs. */
 972 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
 973 {
 974         struct eg20t_port *priv;
 975         u8 modem;
 976         unsigned int ret = 0;
 977
 978         priv = container_of(port, struct eg20t_port, port);
 979         modem = pch_uart_hal_get_modem(priv);
 980
 981         if (modem & UART_MSR_DCD)
 982                 ret |= TIOCM_CAR;
 983
 984         if (modem & UART_MSR_RI)
 985                 ret |= TIOCM_RNG;
 986
 987         if (modem & UART_MSR_DSR)
 988                 ret |= TIOCM_DSR;
 989
 990         if (modem & UART_MSR_CTS)
 991                 ret |= TIOCM_CTS;
 992
 993         return ret;
 994 }
 995
 996 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 997 {
 998         u32 mcr = 0;
 999         unsigned int dat;
1000         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1001
1002         if (mctrl & TIOCM_DTR)
1003                 mcr |= UART_MCR_DTR;
1004         if (mctrl & TIOCM_RTS)
1005                 mcr |= UART_MCR_RTS;
1006         if (mctrl & TIOCM_LOOP)
1007                 mcr |= UART_MCR_LOOP;
1008
1009         if (mctrl) {
1010                 dat = pch_uart_get_mctrl(port);
1011                 dat |= mcr;
1012                 iowrite8(dat, priv->membase + UART_MCR);
1013         }
1014 }
1015
1016 static void pch_uart_stop_tx(struct uart_port *port)
1017 {
1018         struct eg20t_port *priv;
1019         priv = container_of(port, struct eg20t_port, port);
1020         priv->start_tx = 0;
1021         priv->tx_dma_use = 0;
1022 }
1023
1024 static void pch_uart_start_tx(struct uart_port *port)
1025 {
1026         struct eg20t_port *priv;
1027
1028         priv = container_of(port, struct eg20t_port, port);
1029
1030         if (priv->use_dma)
1031                 if (priv->tx_dma_use)
1032                         return;
1033
1034         priv->start_tx = 1;
1035         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1036 }
1037
1038 static void pch_uart_stop_rx(struct uart_port *port)
1039 {
1040         struct eg20t_port *priv;
1041         priv = container_of(port, struct eg20t_port, port);
1042         priv->start_rx = 0;
1043         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1044         priv->int_dis_flag = 1;
1045 }
1046
1047 /* Enable the modem status interrupts. */
1048 static void pch_uart_enable_ms(struct uart_port *port)
1049 {
1050         struct eg20t_port *priv;
1051         priv = container_of(port, struct eg20t_port, port);
1052         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1053 }
1054
1055 /* Control the transmission of a break signal. */
1056 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1057 {
1058         struct eg20t_port *priv;
1059         unsigned long flags;
1060
1061         priv = container_of(port, struct eg20t_port, port);
1062         spin_lock_irqsave(&port->lock, flags);
1063         pch_uart_hal_set_break(priv, ctl);
1064         spin_unlock_irqrestore(&port->lock, flags);
1065 }
1066
1067 /* Grab any interrupt resources and initialise any low level driver state. */
1068 static int pch_uart_startup(struct uart_port *port)
1069 {
1070         struct eg20t_port *priv;
1071         int ret;
1072         int fifo_size;
1073         int trigger_level;
1074
1075         priv = container_of(port, struct eg20t_port, port);
1076         priv->tx_empty = 1;
1077         port->uartclk = priv->base_baud;
1078         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1079         ret = pch_uart_hal_set_line(priv, default_baud,
1080                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1081                               PCH_UART_HAL_STB1);
1082         if (ret)
1083                 return ret;
1084
1085         switch (priv->fifo_size) {
1086         case 256:
1087                 fifo_size = PCH_UART_HAL_FIFO256;
1088                 break;
1089         case 64:
1090                 fifo_size = PCH_UART_HAL_FIFO64;
1091                 break;
1092         case 16:
1093                 fifo_size = PCH_UART_HAL_FIFO16;
1094         case 1:
1095         default:
1096                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1097                 break;
1098         }
1099
1100         switch (priv->trigger) {
1101         case PCH_UART_HAL_TRIGGER1:
1102                 trigger_level = 1;
1103                 break;
1104         case PCH_UART_HAL_TRIGGER_L:
1105                 trigger_level = priv->fifo_size / 4;
1106                 break;
1107         case PCH_UART_HAL_TRIGGER_M:
1108                 trigger_level = priv->fifo_size / 2;
1109                 break;
1110         case PCH_UART_HAL_TRIGGER_H:
1111         default:
1112                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1113                 break;
1114         }
1115
1116         priv->trigger_level = trigger_level;
1117         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1118                                     fifo_size, priv->trigger);
1119         if (ret < 0)
1120                 return ret;
1121
1122         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1123                         KBUILD_MODNAME, priv);
1124         if (ret < 0)
1125                 return ret;
1126
1127         if (priv->use_dma)
1128                 pch_request_dma(port);
1129
1130         priv->start_rx = 1;
1131         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1132         uart_update_timeout(port, CS8, default_baud);
1133
1134         return 0;
1135 }
1136
1137 static void pch_uart_shutdown(struct uart_port *port)
1138 {
1139         struct eg20t_port *priv;
1140         int ret;
1141
1142         priv = container_of(port, struct eg20t_port, port);
1143         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1144         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1145         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1146                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1147         if (ret)
1148                 pr_err("pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1149
1150         if (priv->use_dma_flag)
1151                 pch_free_dma(port);
1152
1153         free_irq(priv->port.irq, priv);
1154 }
1155
1156 /* Change the port parameters, including word length, parity, stop
1157  *bits.  Update read_status_mask and ignore_status_mask to indicate
1158  *the types of events we are interested in receiving.  */
1159 static void pch_uart_set_termios(struct uart_port *port,
1160                                  struct ktermios *termios, struct ktermios *old)
1161 {
1162         int baud;
1163         int rtn;
1164         unsigned int parity, bits, stb;
1165         struct eg20t_port *priv;
1166         unsigned long flags;
1167
1168         priv = container_of(port, struct eg20t_port, port);
1169         switch (termios->c_cflag & CSIZE) {
1170         case CS5:
1171                 bits = PCH_UART_HAL_5BIT;
1172                 break;
1173         case CS6:
1174                 bits = PCH_UART_HAL_6BIT;
1175                 break;
1176         case CS7:
1177                 bits = PCH_UART_HAL_7BIT;
1178                 break;
1179         default:                /* CS8 */
1180                 bits = PCH_UART_HAL_8BIT;
1181                 break;
1182         }
1183         if (termios->c_cflag & CSTOPB)
1184                 stb = PCH_UART_HAL_STB2;
1185         else
1186                 stb = PCH_UART_HAL_STB1;
1187
1188         if (termios->c_cflag & PARENB) {
1189                 if (!(termios->c_cflag & PARODD))
1190                         parity = PCH_UART_HAL_PARITY_ODD;
1191                 else
1192                         parity = PCH_UART_HAL_PARITY_EVEN;
1193
1194         } else {
1195                 parity = PCH_UART_HAL_PARITY_NONE;
1196         }
1197         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1198
1199         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1200
1201         spin_lock_irqsave(&port->lock, flags);
1202
1203         uart_update_timeout(port, termios->c_cflag, baud);
1204         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1205         if (rtn)
1206                 goto out;
1207
1208         /* Don't rewrite B0 */
1209         if (tty_termios_baud_rate(termios))
1210                 tty_termios_encode_baud_rate(termios, baud, baud);
1211
1212 out:
1213         spin_unlock_irqrestore(&port->lock, flags);
1214 }
1215
1216 static const char *pch_uart_type(struct uart_port *port)
1217 {
1218         return KBUILD_MODNAME;
1219 }
1220
1221 static void pch_uart_release_port(struct uart_port *port)
1222 {
1223         struct eg20t_port *priv;
1224
1225         priv = container_of(port, struct eg20t_port, port);
1226         pci_iounmap(priv->pdev, priv->membase);
1227         pci_release_regions(priv->pdev);
1228 }
1229
1230 static int pch_uart_request_port(struct uart_port *port)
1231 {
1232         struct eg20t_port *priv;
1233         int ret;
1234         void __iomem *membase;
1235
1236         priv = container_of(port, struct eg20t_port, port);
1237         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1238         if (ret < 0)
1239                 return -EBUSY;
1240
1241         membase = pci_iomap(priv->pdev, 1, 0);
1242         if (!membase) {
1243                 pci_release_regions(priv->pdev);
1244                 return -EBUSY;
1245         }
1246         priv->membase = port->membase = membase;
1247
1248         return 0;
1249 }
1250
1251 static void pch_uart_config_port(struct uart_port *port, int type)
1252 {
1253         struct eg20t_port *priv;
1254
1255         priv = container_of(port, struct eg20t_port, port);
1256         if (type & UART_CONFIG_TYPE) {
1257                 port->type = priv->port_type;
1258                 pch_uart_request_port(port);
1259         }
1260 }
1261
1262 static int pch_uart_verify_port(struct uart_port *port,
1263                                 struct serial_struct *serinfo)
1264 {
1265         struct eg20t_port *priv;
1266
1267         priv = container_of(port, struct eg20t_port, port);
1268         if (serinfo->flags & UPF_LOW_LATENCY) {
1269                 pr_info("PCH UART : Use PIO Mode (without DMA)\n");
1270                 priv->use_dma = 0;
1271                 serinfo->flags &= ~UPF_LOW_LATENCY;
1272         } else {
1273 #ifndef CONFIG_PCH_DMA
1274                 pr_err("%s : PCH DMA is not Loaded.\n", __func__);
1275                 return -EOPNOTSUPP;
1276 #endif
1277                 priv->use_dma = 1;
1278                 priv->use_dma_flag = 1;
1279                 pr_info("PCH UART : Use DMA Mode\n");
1280         }
1281
1282         return 0;
1283 }
1284
1285 static struct uart_ops pch_uart_ops = {
1286         .tx_empty = pch_uart_tx_empty,
1287         .set_mctrl = pch_uart_set_mctrl,
1288         .get_mctrl = pch_uart_get_mctrl,
1289         .stop_tx = pch_uart_stop_tx,
1290         .start_tx = pch_uart_start_tx,
1291         .stop_rx = pch_uart_stop_rx,
1292         .enable_ms = pch_uart_enable_ms,
1293         .break_ctl = pch_uart_break_ctl,
1294         .startup = pch_uart_startup,
1295         .shutdown = pch_uart_shutdown,
1296         .set_termios = pch_uart_set_termios,
1297 /*      .pm             = pch_uart_pm,          Not supported yet */
1298 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1299         .type = pch_uart_type,
1300         .release_port = pch_uart_release_port,
1301         .request_port = pch_uart_request_port,
1302         .config_port = pch_uart_config_port,
1303         .verify_port = pch_uart_verify_port
1304 };
1305
1306 static struct uart_driver pch_uart_driver = {
1307         .owner = THIS_MODULE,
1308         .driver_name = KBUILD_MODNAME,
1309         .dev_name = PCH_UART_DRIVER_DEVICE,
1310         .major = 0,
1311         .minor = 0,
1312         .nr = PCH_UART_NR,
1313 };
1314
1315 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1316                                              const struct pci_device_id *id)
1317 {
1318         struct eg20t_port *priv;
1319         int ret;
1320         unsigned int iobase;
1321         unsigned int mapbase;
1322         unsigned char *rxbuf;
1323         int fifosize, base_baud;
1324         static int num;
1325         int port_type = id->driver_data;
1326
1327         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1328         if (priv == NULL)
1329                 goto init_port_alloc_err;
1330
1331         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1332         if (!rxbuf)
1333                 goto init_port_free_txbuf;
1334
1335         switch (port_type) {
1336         case PORT_UNKNOWN:
1337                 fifosize = 256; /* EG20T/ML7213: UART0 */
1338                 base_baud = 1843200; /* 1.8432MHz */
1339                 break;
1340         case PORT_8250:
1341                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1342                 base_baud = 1843200; /* 1.8432MHz */
1343                 break;
1344         default:
1345                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1346                 goto init_port_hal_free;
1347         }
1348
1349         iobase = pci_resource_start(pdev, 0);
1350         mapbase = pci_resource_start(pdev, 1);
1351         priv->mapbase = mapbase;
1352         priv->iobase = iobase;
1353         priv->pdev = pdev;
1354         priv->tx_empty = 1;
1355         priv->rxbuf.buf = rxbuf;
1356         priv->rxbuf.size = PAGE_SIZE;
1357
1358         priv->fifo_size = fifosize;
1359         priv->base_baud = base_baud;
1360         priv->port_type = PORT_MAX_8250 + port_type + 1;
1361         priv->port.dev = &pdev->dev;
1362         priv->port.iobase = iobase;
1363         priv->port.membase = NULL;
1364         priv->port.mapbase = mapbase;
1365         priv->port.irq = pdev->irq;
1366         priv->port.iotype = UPIO_PORT;
1367         priv->port.ops = &pch_uart_ops;
1368         priv->port.flags = UPF_BOOT_AUTOCONF;
1369         priv->port.fifosize = fifosize;
1370         priv->port.line = num++;
1371         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1372
1373         spin_lock_init(&priv->port.lock);
1374
1375         pci_set_drvdata(pdev, priv);
1376         pch_uart_hal_request(pdev, fifosize, base_baud);
1377
1378         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1379         if (ret < 0)
1380                 goto init_port_hal_free;
1381
1382         return priv;
1383
1384 init_port_hal_free:
1385         free_page((unsigned long)rxbuf);
1386 init_port_free_txbuf:
1387         kfree(priv);
1388 init_port_alloc_err:
1389
1390         return NULL;
1391 }
1392
1393 static void pch_uart_exit_port(struct eg20t_port *priv)
1394 {
1395         uart_remove_one_port(&pch_uart_driver, &priv->port);
1396         pci_set_drvdata(priv->pdev, NULL);
1397         free_page((unsigned long)priv->rxbuf.buf);
1398 }
1399
1400 static void pch_uart_pci_remove(struct pci_dev *pdev)
1401 {
1402         struct eg20t_port *priv;
1403
1404         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1405         pch_uart_exit_port(priv);
1406         pci_disable_device(pdev);
1407         kfree(priv);
1408         return;
1409 }
1410 #ifdef CONFIG_PM
1411 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1412 {
1413         struct eg20t_port *priv = pci_get_drvdata(pdev);
1414
1415         uart_suspend_port(&pch_uart_driver, &priv->port);
1416
1417         pci_save_state(pdev);
1418         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1419         return 0;
1420 }
1421
1422 static int pch_uart_pci_resume(struct pci_dev *pdev)
1423 {
1424         struct eg20t_port *priv = pci_get_drvdata(pdev);
1425         int ret;
1426
1427         pci_set_power_state(pdev, PCI_D0);
1428         pci_restore_state(pdev);
1429
1430         ret = pci_enable_device(pdev);
1431         if (ret) {
1432                 dev_err(&pdev->dev,
1433                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1434                 return ret;
1435         }
1436
1437         uart_resume_port(&pch_uart_driver, &priv->port);
1438
1439         return 0;
1440 }
1441 #else
1442 #define pch_uart_pci_suspend NULL
1443 #define pch_uart_pci_resume NULL
1444 #endif
1445
1446 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1447         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1448          .driver_data = PCH_UART_8LINE},
1449         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1450          .driver_data = PCH_UART_2LINE},
1451         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1452          .driver_data = PCH_UART_2LINE},
1453         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1454          .driver_data = PCH_UART_2LINE},
1455         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1456          .driver_data = PCH_UART_8LINE},
1457         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1458          .driver_data = PCH_UART_2LINE},
1459         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1460          .driver_data = PCH_UART_2LINE},
1461         {0,},
1462 };
1463
1464 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1465                                         const struct pci_device_id *id)
1466 {
1467         int ret;
1468         struct eg20t_port *priv;
1469
1470         ret = pci_enable_device(pdev);
1471         if (ret < 0)
1472                 goto probe_error;
1473
1474         priv = pch_uart_init_port(pdev, id);
1475         if (!priv) {
1476                 ret = -EBUSY;
1477                 goto probe_disable_device;
1478         }
1479         pci_set_drvdata(pdev, priv);
1480
1481         return ret;
1482
1483 probe_disable_device:
1484         pci_disable_device(pdev);
1485 probe_error:
1486         return ret;
1487 }
1488
1489 static struct pci_driver pch_uart_pci_driver = {
1490         .name = "pch_uart",
1491         .id_table = pch_uart_pci_id,
1492         .probe = pch_uart_pci_probe,
1493         .remove = __devexit_p(pch_uart_pci_remove),
1494         .suspend = pch_uart_pci_suspend,
1495         .resume = pch_uart_pci_resume,
1496 };
1497
1498 static int __init pch_uart_module_init(void)
1499 {
1500         int ret;
1501
1502         /* register as UART driver */
1503         ret = uart_register_driver(&pch_uart_driver);
1504         if (ret < 0)
1505                 return ret;
1506
1507         /* register as PCI driver */
1508         ret = pci_register_driver(&pch_uart_pci_driver);
1509         if (ret < 0)
1510                 uart_unregister_driver(&pch_uart_driver);
1511
1512         return ret;
1513 }
1514 module_init(pch_uart_module_init);
1515
1516 static void __exit pch_uart_module_exit(void)
1517 {
1518         pci_unregister_driver(&pch_uart_pci_driver);
1519         uart_unregister_driver(&pch_uart_driver);
1520 }
1521 module_exit(pch_uart_module_exit);
1522
1523 MODULE_LICENSE("GPL v2");
1524 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1525 module_param(default_baud, uint, S_IRUGO);