drivers/gpu/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 /* Firmware Names */
  42 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  43 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  44 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  45 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  46 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  47 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  48 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  49
  50 MODULE_FIRMWARE(FIRMWARE_R100);
  51 MODULE_FIRMWARE(FIRMWARE_R200);
  52 MODULE_FIRMWARE(FIRMWARE_R300);
  53 MODULE_FIRMWARE(FIRMWARE_R420);
  54 MODULE_FIRMWARE(FIRMWARE_RS690);
  55 MODULE_FIRMWARE(FIRMWARE_RS600);
  56 MODULE_FIRMWARE(FIRMWARE_R520);
  57
  58 static int radeon_do_cleanup_cp(struct drm_device * dev);
  59 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  60
  61 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  62 {
  63         u32 val;
  64
  65         if (dev_priv->flags & RADEON_IS_AGP) {
  66                 val = DRM_READ32(dev_priv->ring_rptr, off);
  67         } else {
  68                 val = *(((volatile u32 *)
  69                          dev_priv->ring_rptr->handle) +
  70                         (off / sizeof(u32)));
  71                 val = le32_to_cpu(val);
  72         }
  73         return val;
  74 }
  75
  76 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  77 {
  78         if (dev_priv->writeback_works)
  79                 return radeon_read_ring_rptr(dev_priv, 0);
  80         else {
  81                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  82                         return RADEON_READ(R600_CP_RB_RPTR);
  83                 else
  84                         return RADEON_READ(RADEON_CP_RB_RPTR);
  85         }
  86 }
  87
  88 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  89 {
  90         if (dev_priv->flags & RADEON_IS_AGP)
  91                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  92         else
  93                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  94                   (off / sizeof(u32))) = cpu_to_le32(val);
  95 }
  96
  97 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  98 {
  99         radeon_write_ring_rptr(dev_priv, 0, val);
 100 }
 101
 102 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
 103 {
 104         if (dev_priv->writeback_works) {
 105                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 106                         return radeon_read_ring_rptr(dev_priv,
 107                                                      R600_SCRATCHOFF(index));
 108                 else
 109                         return radeon_read_ring_rptr(dev_priv,
 110                                                      RADEON_SCRATCHOFF(index));
 111         } else {
 112                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 113                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
 114                 else
 115                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 116         }
 117 }
 118
 119 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 120 {
 121         u32 ret;
 122
 123         if (addr < 0x10000)
 124                 ret = DRM_READ32(dev_priv->mmio, addr);
 125         else {
 126                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 127                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 128         }
 129
 130         return ret;
 131 }
 132
 133 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 134 {
 135         u32 ret;
 136         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 137         ret = RADEON_READ(R520_MC_IND_DATA);
 138         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 139         return ret;
 140 }
 141
 142 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 143 {
 144         u32 ret;
 145         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 146         ret = RADEON_READ(RS480_NB_MC_DATA);
 147         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 148         return ret;
 149 }
 150
 151 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 152 {
 153         u32 ret;
 154         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 155         ret = RADEON_READ(RS690_MC_DATA);
 156         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 157         return ret;
 158 }
 159
 160 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 161 {
 162         u32 ret;
 163         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 164                                       RS600_MC_IND_CITF_ARB0));
 165         ret = RADEON_READ(RS600_MC_DATA);
 166         return ret;
 167 }
 168
 169 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 170 {
 171         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 172             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 173                 return RS690_READ_MCIND(dev_priv, addr);
 174         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 175                 return RS600_READ_MCIND(dev_priv, addr);
 176         else
 177                 return RS480_READ_MCIND(dev_priv, addr);
 178 }
 179
 180 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 181 {
 182
 183         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 184                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 185         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 186                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 187         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 188                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 189         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 190                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 191                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 192         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 193                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 194         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 195                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 196         else
 197                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 198 }
 199
 200 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 201 {
 202         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 203                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 204         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 205                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 206         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 207                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 208         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 209                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 210                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 211         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 212                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 213         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 214                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 215         else
 216                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 217 }
 218
 219 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 220 {
 221         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 222         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 223                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 224                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 225         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 226                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 227                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 228         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 229                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 230         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 231                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 232                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 233         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 234                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 235         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 236                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 237         else
 238                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 239 }
 240
 241 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 242 {
 243         u32 agp_base_hi = upper_32_bits(agp_base);
 244         u32 agp_base_lo = agp_base & 0xffffffff;
 245         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 246
 247         /* R6xx/R7xx must be aligned to a 4MB boundry */
 248         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 249                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 250         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 251                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 252         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 253                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 254                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 255         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 256                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 257                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 258                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 259         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 260                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 261                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 262         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 263                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 264                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 265         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 266                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 267                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 268                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 269         } else {
 270                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 271                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 272                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 273         }
 274 }
 275
 276 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 277 {
 278         u32 tmp;
 279         /* Turn on bus mastering */
 280         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 281             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 282                 /* rs600/rs690/rs740 */
 283                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 284                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 285         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 286                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 287                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 288                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 289                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 290                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 291                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 292         } /* PCIE cards appears to not need this */
 293 }
 294
 295 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 296 {
 297         drm_radeon_private_t *dev_priv = dev->dev_private;
 298
 299         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 300         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 301 }
 302
 303 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 304 {
 305         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 306         return RADEON_READ(RADEON_PCIE_DATA);
 307 }
 308
 309 #if RADEON_FIFO_DEBUG
 310 static void radeon_status(drm_radeon_private_t * dev_priv)
 311 {
 312         printk("%s:\n", __func__);
 313         printk("RBBM_STATUS = 0x%08x\n",
 314                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 315         printk("CP_RB_RTPR = 0x%08x\n",
 316                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 317         printk("CP_RB_WTPR = 0x%08x\n",
 318                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 319         printk("AIC_CNTL = 0x%08x\n",
 320                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 321         printk("AIC_STAT = 0x%08x\n",
 322                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 323         printk("AIC_PT_BASE = 0x%08x\n",
 324                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 325         printk("TLB_ADDR = 0x%08x\n",
 326                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 327         printk("TLB_DATA = 0x%08x\n",
 328                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 329 }
 330 #endif
 331
 332 /* ================================================================
 333  * Engine, FIFO control
 334  */
 335
 336 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 337 {
 338         u32 tmp;
 339         int i;
 340
 341         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 342
 343         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 344                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 345                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 346                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 347
 348                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 349                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 350                               & RADEON_RB3D_DC_BUSY)) {
 351                                 return 0;
 352                         }
 353                         DRM_UDELAY(1);
 354                 }
 355         } else {
 356                 /* don't flush or purge cache here or lockup */
 357                 return 0;
 358         }
 359
 360 #if RADEON_FIFO_DEBUG
 361         DRM_ERROR("failed!\n");
 362         radeon_status(dev_priv);
 363 #endif
 364         return -EBUSY;
 365 }
 366
 367 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 368 {
 369         int i;
 370
 371         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 372
 373         for (i = 0; i < dev_priv->usec_timeout; i++) {
 374                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 375                              & RADEON_RBBM_FIFOCNT_MASK);
 376                 if (slots >= entries)
 377                         return 0;
 378                 DRM_UDELAY(1);
 379         }
 380         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 381                  RADEON_READ(RADEON_RBBM_STATUS),
 382                  RADEON_READ(R300_VAP_CNTL_STATUS));
 383
 384 #if RADEON_FIFO_DEBUG
 385         DRM_ERROR("failed!\n");
 386         radeon_status(dev_priv);
 387 #endif
 388         return -EBUSY;
 389 }
 390
 391 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 392 {
 393         int i, ret;
 394
 395         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 396
 397         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 398         if (ret)
 399                 return ret;
 400
 401         for (i = 0; i < dev_priv->usec_timeout; i++) {
 402                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 403                       & RADEON_RBBM_ACTIVE)) {
 404                         radeon_do_pixcache_flush(dev_priv);
 405                         return 0;
 406                 }
 407                 DRM_UDELAY(1);
 408         }
 409         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 410                  RADEON_READ(RADEON_RBBM_STATUS),
 411                  RADEON_READ(R300_VAP_CNTL_STATUS));
 412
 413 #if RADEON_FIFO_DEBUG
 414         DRM_ERROR("failed!\n");
 415         radeon_status(dev_priv);
 416 #endif
 417         return -EBUSY;
 418 }
 419
 420 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 421 {
 422         uint32_t gb_tile_config, gb_pipe_sel = 0;
 423
 424         /* RS4xx/RS6xx/R4xx/R5xx */
 425         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 426                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 427                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 428         } else {
 429                 /* R3xx */
 430                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 431                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 432                         dev_priv->num_gb_pipes = 2;
 433                 } else {
 434                         /* R3Vxx */
 435                         dev_priv->num_gb_pipes = 1;
 436                 }
 437         }
 438         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 439
 440         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 441
 442         switch (dev_priv->num_gb_pipes) {
 443         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 444         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 445         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 446         default:
 447         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 448         }
 449
 450         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 451                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 452                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 453         }
 454         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 455         radeon_do_wait_for_idle(dev_priv);
 456         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 457         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 458                                                R300_DC_AUTOFLUSH_ENABLE |
 459                                                R300_DC_DC_DISABLE_IGNORE_PE));
 460
 461
 462 }
 463
 464 /* ================================================================
 465  * CP control, initialization
 466  */
 467
 468 /* Load the microcode for the CP */
 469 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
 470 {
 471         struct platform_device *pdev;
 472         const char *fw_name = NULL;
 473         int err;
 474
 475         DRM_DEBUG("\n");
 476
 477         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 478         err = IS_ERR(pdev);
 479         if (err) {
 480                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 481                 return -EINVAL;
 482         }
 483
 484         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 485             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 486             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 487             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 488             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 489                 DRM_INFO("Loading R100 Microcode\n");
 490                 fw_name = FIRMWARE_R100;
 491         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 492                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 493                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 494                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 495                 DRM_INFO("Loading R200 Microcode\n");
 496                 fw_name = FIRMWARE_R200;
 497         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 498                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 499                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 500                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 501                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 502                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 503                 DRM_INFO("Loading R300 Microcode\n");
 504                 fw_name = FIRMWARE_R300;
 505         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 506                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 507                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 508                 DRM_INFO("Loading R400 Microcode\n");
 509                 fw_name = FIRMWARE_R420;
 510         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 511                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 512                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 513                 fw_name = FIRMWARE_RS690;
 514         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 515                 DRM_INFO("Loading RS600 Microcode\n");
 516                 fw_name = FIRMWARE_RS600;
 517         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 518                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 519                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 520                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 521                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 522                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 523                 DRM_INFO("Loading R500 Microcode\n");
 524                 fw_name = FIRMWARE_R520;
 525         }
 526
 527         err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
 528         platform_device_unregister(pdev);
 529         if (err) {
 530                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 531                        fw_name);
 532         } else if (dev_priv->me_fw->size % 8) {
 533                 printk(KERN_ERR
 534                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 535                        dev_priv->me_fw->size, fw_name);
 536                 err = -EINVAL;
 537                 release_firmware(dev_priv->me_fw);
 538                 dev_priv->me_fw = NULL;
 539         }
 540         return err;
 541 }
 542
 543 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
 544 {
 545         const __be32 *fw_data;
 546         int i, size;
 547
 548         radeon_do_wait_for_idle(dev_priv);
 549
 550         if (dev_priv->me_fw) {
 551                 size = dev_priv->me_fw->size / 4;
 552                 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
 553                 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 554                 for (i = 0; i < size; i += 2) {
 555                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 556                                      be32_to_cpup(&fw_data[i]));
 557                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 558                                      be32_to_cpup(&fw_data[i + 1]));
 559                 }
 560         }
 561 }
 562
 563 /* Flush any pending commands to the CP.  This should only be used just
 564  * prior to a wait for idle, as it informs the engine that the command
 565  * stream is ending.
 566  */
 567 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 568 {
 569         DRM_DEBUG("\n");
 570 #if 0
 571         u32 tmp;
 572
 573         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 574         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 575 #endif
 576 }
 577
 578 /* Wait for the CP to go idle.
 579  */
 580 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 581 {
 582         RING_LOCALS;
 583         DRM_DEBUG("\n");
 584
 585         BEGIN_RING(6);
 586
 587         RADEON_PURGE_CACHE();
 588         RADEON_PURGE_ZCACHE();
 589         RADEON_WAIT_UNTIL_IDLE();
 590
 591         ADVANCE_RING();
 592         COMMIT_RING();
 593
 594         return radeon_do_wait_for_idle(dev_priv);
 595 }
 596
 597 /* Start the Command Processor.
 598  */
 599 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 600 {
 601         RING_LOCALS;
 602         DRM_DEBUG("\n");
 603
 604         radeon_do_wait_for_idle(dev_priv);
 605
 606         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 607
 608         dev_priv->cp_running = 1;
 609
 610         BEGIN_RING(8);
 611         /* isync can only be written through cp on r5xx write it here */
 612         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 613         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 614                  RADEON_ISYNC_ANY3D_IDLE2D |
 615                  RADEON_ISYNC_WAIT_IDLEGUI |
 616                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 617         RADEON_PURGE_CACHE();
 618         RADEON_PURGE_ZCACHE();
 619         RADEON_WAIT_UNTIL_IDLE();
 620         ADVANCE_RING();
 621         COMMIT_RING();
 622
 623         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 624 }
 625
 626 /* Reset the Command Processor.  This will not flush any pending
 627  * commands, so you must wait for the CP command stream to complete
 628  * before calling this routine.
 629  */
 630 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 631 {
 632         u32 cur_read_ptr;
 633         DRM_DEBUG("\n");
 634
 635         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 636         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 637         SET_RING_HEAD(dev_priv, cur_read_ptr);
 638         dev_priv->ring.tail = cur_read_ptr;
 639 }
 640
 641 /* Stop the Command Processor.  This will not flush any pending
 642  * commands, so you must flush the command stream and wait for the CP
 643  * to go idle before calling this routine.
 644  */
 645 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 646 {
 647         DRM_DEBUG("\n");
 648
 649         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 650
 651         dev_priv->cp_running = 0;
 652 }
 653
 654 /* Reset the engine.  This will stop the CP if it is running.
 655  */
 656 static int radeon_do_engine_reset(struct drm_device * dev)
 657 {
 658         drm_radeon_private_t *dev_priv = dev->dev_private;
 659         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 660         DRM_DEBUG("\n");
 661
 662         radeon_do_pixcache_flush(dev_priv);
 663
 664         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 665                 /* may need something similar for newer chips */
 666                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 667                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 668
 669                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 670                                                     RADEON_FORCEON_MCLKA |
 671                                                     RADEON_FORCEON_MCLKB |
 672                                                     RADEON_FORCEON_YCLKA |
 673                                                     RADEON_FORCEON_YCLKB |
 674                                                     RADEON_FORCEON_MC |
 675                                                     RADEON_FORCEON_AIC));
 676         }
 677
 678         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 679
 680         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 681                                               RADEON_SOFT_RESET_CP |
 682                                               RADEON_SOFT_RESET_HI |
 683                                               RADEON_SOFT_RESET_SE |
 684                                               RADEON_SOFT_RESET_RE |
 685                                               RADEON_SOFT_RESET_PP |
 686                                               RADEON_SOFT_RESET_E2 |
 687                                               RADEON_SOFT_RESET_RB));
 688         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 689         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 690                                               ~(RADEON_SOFT_RESET_CP |
 691                                                 RADEON_SOFT_RESET_HI |
 692                                                 RADEON_SOFT_RESET_SE |
 693                                                 RADEON_SOFT_RESET_RE |
 694                                                 RADEON_SOFT_RESET_PP |
 695                                                 RADEON_SOFT_RESET_E2 |
 696                                                 RADEON_SOFT_RESET_RB)));
 697         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 698
 699         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 700                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 701                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 702                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 703         }
 704
 705         /* setup the raster pipes */
 706         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 707             radeon_init_pipes(dev_priv);
 708
 709         /* Reset the CP ring */
 710         radeon_do_cp_reset(dev_priv);
 711
 712         /* The CP is no longer running after an engine reset */
 713         dev_priv->cp_running = 0;
 714
 715         /* Reset any pending vertex, indirect buffers */
 716         radeon_freelist_reset(dev);
 717
 718         return 0;
 719 }
 720
 721 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 722                                        drm_radeon_private_t *dev_priv,
 723                                        struct drm_file *file_priv)
 724 {
 725         struct drm_radeon_master_private *master_priv;
 726         u32 ring_start, cur_read_ptr;
 727
 728         /* Initialize the memory controller. With new memory map, the fb location
 729          * is not changed, it should have been properly initialized already. Part
 730          * of the problem is that the code below is bogus, assuming the GART is
 731          * always appended to the fb which is not necessarily the case
 732          */
 733         if (!dev_priv->new_memmap)
 734                 radeon_write_fb_location(dev_priv,
 735                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 736                              | (dev_priv->fb_location >> 16));
 737
 738 #if __OS_HAS_AGP
 739         if (dev_priv->flags & RADEON_IS_AGP) {
 740                 radeon_write_agp_base(dev_priv, dev->agp->base);
 741
 742                 radeon_write_agp_location(dev_priv,
 743                              (((dev_priv->gart_vm_start - 1 +
 744                                 dev_priv->gart_size) & 0xffff0000) |
 745                               (dev_priv->gart_vm_start >> 16)));
 746
 747                 ring_start = (dev_priv->cp_ring->offset
 748                               - dev->agp->base
 749                               + dev_priv->gart_vm_start);
 750         } else
 751 #endif
 752                 ring_start = (dev_priv->cp_ring->offset
 753                               - (unsigned long)dev->sg->virtual
 754                               + dev_priv->gart_vm_start);
 755
 756         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 757
 758         /* Set the write pointer delay */
 759         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 760
 761         /* Initialize the ring buffer's read and write pointers */
 762         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 763         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 764         SET_RING_HEAD(dev_priv, cur_read_ptr);
 765         dev_priv->ring.tail = cur_read_ptr;
 766
 767 #if __OS_HAS_AGP
 768         if (dev_priv->flags & RADEON_IS_AGP) {
 769                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 770                              dev_priv->ring_rptr->offset
 771                              - dev->agp->base + dev_priv->gart_vm_start);
 772         } else
 773 #endif
 774         {
 775                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 776                              dev_priv->ring_rptr->offset
 777                              - ((unsigned long) dev->sg->virtual)
 778                              + dev_priv->gart_vm_start);
 779         }
 780
 781         /* Set ring buffer size */
 782 #ifdef __BIG_ENDIAN
 783         RADEON_WRITE(RADEON_CP_RB_CNTL,
 784                      RADEON_BUF_SWAP_32BIT |
 785                      (dev_priv->ring.fetch_size_l2ow << 18) |
 786                      (dev_priv->ring.rptr_update_l2qw << 8) |
 787                      dev_priv->ring.size_l2qw);
 788 #else
 789         RADEON_WRITE(RADEON_CP_RB_CNTL,
 790                      (dev_priv->ring.fetch_size_l2ow << 18) |
 791                      (dev_priv->ring.rptr_update_l2qw << 8) |
 792                      dev_priv->ring.size_l2qw);
 793 #endif
 794
 795
 796         /* Initialize the scratch register pointer.  This will cause
 797          * the scratch register values to be written out to memory
 798          * whenever they are updated.
 799          *
 800          * We simply put this behind the ring read pointer, this works
 801          * with PCI GART as well as (whatever kind of) AGP GART
 802          */
 803         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 804                      + RADEON_SCRATCH_REG_OFFSET);
 805
 806         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 807
 808         radeon_enable_bm(dev_priv);
 809
 810         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 811         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 812
 813         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 814         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 815
 816         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 817         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 818
 819         /* reset sarea copies of these */
 820         master_priv = file_priv->master->driver_priv;
 821         if (master_priv->sarea_priv) {
 822                 master_priv->sarea_priv->last_frame = 0;
 823                 master_priv->sarea_priv->last_dispatch = 0;
 824                 master_priv->sarea_priv->last_clear = 0;
 825         }
 826
 827         radeon_do_wait_for_idle(dev_priv);
 828
 829         /* Sync everything up */
 830         RADEON_WRITE(RADEON_ISYNC_CNTL,
 831                      (RADEON_ISYNC_ANY2D_IDLE3D |
 832                       RADEON_ISYNC_ANY3D_IDLE2D |
 833                       RADEON_ISYNC_WAIT_IDLEGUI |
 834                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 835
 836 }
 837
 838 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 839 {
 840         u32 tmp;
 841
 842         /* Start with assuming that writeback doesn't work */
 843         dev_priv->writeback_works = 0;
 844
 845         /* Writeback doesn't seem to work everywhere, test it here and possibly
 846          * enable it if it appears to work
 847          */
 848         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 849
 850         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 851
 852         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 853                 u32 val;
 854
 855                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 856                 if (val == 0xdeadbeef)
 857                         break;
 858                 DRM_UDELAY(1);
 859         }
 860
 861         if (tmp < dev_priv->usec_timeout) {
 862                 dev_priv->writeback_works = 1;
 863                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 864         } else {
 865                 dev_priv->writeback_works = 0;
 866                 DRM_INFO("writeback test failed\n");
 867         }
 868         if (radeon_no_wb == 1) {
 869                 dev_priv->writeback_works = 0;
 870                 DRM_INFO("writeback forced off\n");
 871         }
 872
 873         if (!dev_priv->writeback_works) {
 874                 /* Disable writeback to avoid unnecessary bus master transfer */
 875                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 876                              RADEON_RB_NO_UPDATE);
 877                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 878         }
 879 }
 880
 881 /* Enable or disable IGP GART on the chip */
 882 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 883 {
 884         u32 temp;
 885
 886         if (on) {
 887                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 888                           dev_priv->gart_vm_start,
 889                           (long)dev_priv->gart_info.bus_addr,
 890                           dev_priv->gart_size);
 891
 892                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 893                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 894                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 895                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 896                                                              RS690_BLOCK_GFX_D3_EN));
 897                 else
 898                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 899
 900                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 901                                                                RS480_VA_SIZE_32MB));
 902
 903                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 904                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 905                                                         RS480_TLB_ENABLE |
 906                                                         RS480_GTW_LAC_EN |
 907                                                         RS480_1LEVEL_GART));
 908
 909                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 910                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 911                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 912
 913                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 914                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 915                                                       RS480_REQ_TYPE_SNOOP_DIS));
 916
 917                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 918
 919                 dev_priv->gart_size = 32*1024*1024;
 920                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 921                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 922
 923                 radeon_write_agp_location(dev_priv, temp);
 924
 925                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 926                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 927                                                                RS480_VA_SIZE_32MB));
 928
 929                 do {
 930                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 931                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 932                                 break;
 933                         DRM_UDELAY(1);
 934                 } while (1);
 935
 936                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 937                                 RS480_GART_CACHE_INVALIDATE);
 938
 939                 do {
 940                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 941                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 942                                 break;
 943                         DRM_UDELAY(1);
 944                 } while (1);
 945
 946                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 947         } else {
 948                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 949         }
 950 }
 951
 952 /* Enable or disable IGP GART on the chip */
 953 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 954 {
 955         u32 temp;
 956         int i;
 957
 958         if (on) {
 959                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 960                          dev_priv->gart_vm_start,
 961                          (long)dev_priv->gart_info.bus_addr,
 962                          dev_priv->gart_size);
 963
 964                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 965                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 966
 967                 for (i = 0; i < 19; i++)
 968                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 969                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 970                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 971                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 972                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 973                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 974                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 975
 976                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 977                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 978
 979                 /* disable all other contexts */
 980                 for (i = 1; i < 8; i++)
 981                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
 982
 983                 /* setup the page table aperture */
 984                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 985                                 dev_priv->gart_info.bus_addr);
 986                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
 987                                 dev_priv->gart_vm_start);
 988                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
 989                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 990                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 991
 992                 /* setup the system aperture */
 993                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
 994                                 dev_priv->gart_vm_start);
 995                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
 996                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 997
 998                 /* enable page tables */
 999                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1000                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1001
1002                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1003                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1004
1005                 /* invalidate the cache */
1006                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1007
1008                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1009                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1010                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1011
1012                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1013                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1014                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1015
1016                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1017                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1018                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1019
1020         } else {
1021                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1022                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1023                 temp &= ~RS600_ENABLE_PAGE_TABLES;
1024                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1025         }
1026 }
1027
1028 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1029 {
1030         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1031         if (on) {
1032
1033                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1034                           dev_priv->gart_vm_start,
1035                           (long)dev_priv->gart_info.bus_addr,
1036                           dev_priv->gart_size);
1037                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1038                                   dev_priv->gart_vm_start);
1039                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1040                                   dev_priv->gart_info.bus_addr);
1041                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1042                                   dev_priv->gart_vm_start);
1043                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1044                                   dev_priv->gart_vm_start +
1045                                   dev_priv->gart_size - 1);
1046
1047                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1048
1049                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1050                                   RADEON_PCIE_TX_GART_EN);
1051         } else {
1052                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1053                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1054         }
1055 }
1056
1057 /* Enable or disable PCI GART on the chip */
1058 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1059 {
1060         u32 tmp;
1061
1062         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1063             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1064             (dev_priv->flags & RADEON_IS_IGPGART)) {
1065                 radeon_set_igpgart(dev_priv, on);
1066                 return;
1067         }
1068
1069         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1070                 rs600_set_igpgart(dev_priv, on);
1071                 return;
1072         }
1073
1074         if (dev_priv->flags & RADEON_IS_PCIE) {
1075                 radeon_set_pciegart(dev_priv, on);
1076                 return;
1077         }
1078
1079         tmp = RADEON_READ(RADEON_AIC_CNTL);
1080
1081         if (on) {
1082                 RADEON_WRITE(RADEON_AIC_CNTL,
1083                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1084
1085                 /* set PCI GART page-table base address
1086                  */
1087                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1088
1089                 /* set address range for PCI address translate
1090                  */
1091                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1092                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1093                              + dev_priv->gart_size - 1);
1094
1095                 /* Turn off AGP aperture -- is this required for PCI GART?
1096                  */
1097                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1098                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1099         } else {
1100                 RADEON_WRITE(RADEON_AIC_CNTL,
1101                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1102         }
1103 }
1104
1105 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1106 {
1107         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1108         struct radeon_virt_surface *vp;
1109         int i;
1110
1111         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1112                 if (!dev_priv->virt_surfaces[i].file_priv ||
1113                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1114                         break;
1115         }
1116         if (i >= 2 * RADEON_MAX_SURFACES)
1117                 return -ENOMEM;
1118         vp = &dev_priv->virt_surfaces[i];
1119
1120         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1121                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1122                 if (sp->refcount)
1123                         continue;
1124
1125                 vp->surface_index = i;
1126                 vp->lower = gart_info->bus_addr;
1127                 vp->upper = vp->lower + gart_info->table_size;
1128                 vp->flags = 0;
1129                 vp->file_priv = PCIGART_FILE_PRIV;
1130
1131                 sp->refcount = 1;
1132                 sp->lower = vp->lower;
1133                 sp->upper = vp->upper;
1134                 sp->flags = 0;
1135
1136                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1137                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1138                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1139                 return 0;
1140         }
1141
1142         return -ENOMEM;
1143 }
1144
1145 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1146                              struct drm_file *file_priv)
1147 {
1148         drm_radeon_private_t *dev_priv = dev->dev_private;
1149         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1150
1151         DRM_DEBUG("\n");
1152
1153         /* if we require new memory map but we don't have it fail */
1154         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1155                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1156                 radeon_do_cleanup_cp(dev);
1157                 return -EINVAL;
1158         }
1159
1160         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1161                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1162                 dev_priv->flags &= ~RADEON_IS_AGP;
1163         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1164                    && !init->is_pci) {
1165                 DRM_DEBUG("Restoring AGP flag\n");
1166                 dev_priv->flags |= RADEON_IS_AGP;
1167         }
1168
1169         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1170                 DRM_ERROR("PCI GART memory not allocated!\n");
1171                 radeon_do_cleanup_cp(dev);
1172                 return -EINVAL;
1173         }
1174
1175         dev_priv->usec_timeout = init->usec_timeout;
1176         if (dev_priv->usec_timeout < 1 ||
1177             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1178                 DRM_DEBUG("TIMEOUT problem!\n");
1179                 radeon_do_cleanup_cp(dev);
1180                 return -EINVAL;
1181         }
1182
1183         /* Enable vblank on CRTC1 for older X servers
1184          */
1185         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1186
1187         switch(init->func) {
1188         case RADEON_INIT_R200_CP:
1189                 dev_priv->microcode_version = UCODE_R200;
1190                 break;
1191         case RADEON_INIT_R300_CP:
1192                 dev_priv->microcode_version = UCODE_R300;
1193                 break;
1194         default:
1195                 dev_priv->microcode_version = UCODE_R100;
1196         }
1197
1198         dev_priv->do_boxes = 0;
1199         dev_priv->cp_mode = init->cp_mode;
1200
1201         /* We don't support anything other than bus-mastering ring mode,
1202          * but the ring can be in either AGP or PCI space for the ring
1203          * read pointer.
1204          */
1205         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1206             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1207                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1208                 radeon_do_cleanup_cp(dev);
1209                 return -EINVAL;
1210         }
1211
1212         switch (init->fb_bpp) {
1213         case 16:
1214                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1215                 break;
1216         case 32:
1217         default:
1218                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1219                 break;
1220         }
1221         dev_priv->front_offset = init->front_offset;
1222         dev_priv->front_pitch = init->front_pitch;
1223         dev_priv->back_offset = init->back_offset;
1224         dev_priv->back_pitch = init->back_pitch;
1225
1226         switch (init->depth_bpp) {
1227         case 16:
1228                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1229                 break;
1230         case 32:
1231         default:
1232                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1233                 break;
1234         }
1235         dev_priv->depth_offset = init->depth_offset;
1236         dev_priv->depth_pitch = init->depth_pitch;
1237
1238         /* Hardware state for depth clears.  Remove this if/when we no
1239          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1240          * all values to prevent unwanted 3D state from slipping through
1241          * and screwing with the clear operation.
1242          */
1243         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1244                                            (dev_priv->color_fmt << 10) |
1245                                            (dev_priv->microcode_version ==
1246                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1247
1248         dev_priv->depth_clear.rb3d_zstencilcntl =
1249             (dev_priv->depth_fmt |
1250              RADEON_Z_TEST_ALWAYS |
1251              RADEON_STENCIL_TEST_ALWAYS |
1252              RADEON_STENCIL_S_FAIL_REPLACE |
1253              RADEON_STENCIL_ZPASS_REPLACE |
1254              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1255
1256         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1257                                          RADEON_BFACE_SOLID |
1258                                          RADEON_FFACE_SOLID |
1259                                          RADEON_FLAT_SHADE_VTX_LAST |
1260                                          RADEON_DIFFUSE_SHADE_FLAT |
1261                                          RADEON_ALPHA_SHADE_FLAT |
1262                                          RADEON_SPECULAR_SHADE_FLAT |
1263                                          RADEON_FOG_SHADE_FLAT |
1264                                          RADEON_VTX_PIX_CENTER_OGL |
1265                                          RADEON_ROUND_MODE_TRUNC |
1266                                          RADEON_ROUND_PREC_8TH_PIX);
1267
1268
1269         dev_priv->ring_offset = init->ring_offset;
1270         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1271         dev_priv->buffers_offset = init->buffers_offset;
1272         dev_priv->gart_textures_offset = init->gart_textures_offset;
1273
1274         master_priv->sarea = drm_getsarea(dev);
1275         if (!master_priv->sarea) {
1276                 DRM_ERROR("could not find sarea!\n");
1277                 radeon_do_cleanup_cp(dev);
1278                 return -EINVAL;
1279         }
1280
1281         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1282         if (!dev_priv->cp_ring) {
1283                 DRM_ERROR("could not find cp ring region!\n");
1284                 radeon_do_cleanup_cp(dev);
1285                 return -EINVAL;
1286         }
1287         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1288         if (!dev_priv->ring_rptr) {
1289                 DRM_ERROR("could not find ring read pointer!\n");
1290                 radeon_do_cleanup_cp(dev);
1291                 return -EINVAL;
1292         }
1293         dev->agp_buffer_token = init->buffers_offset;
1294         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1295         if (!dev->agp_buffer_map) {
1296                 DRM_ERROR("could not find dma buffer region!\n");
1297                 radeon_do_cleanup_cp(dev);
1298                 return -EINVAL;
1299         }
1300
1301         if (init->gart_textures_offset) {
1302                 dev_priv->gart_textures =
1303                     drm_core_findmap(dev, init->gart_textures_offset);
1304                 if (!dev_priv->gart_textures) {
1305                         DRM_ERROR("could not find GART texture region!\n");
1306                         radeon_do_cleanup_cp(dev);
1307                         return -EINVAL;
1308                 }
1309         }
1310
1311 #if __OS_HAS_AGP
1312         if (dev_priv->flags & RADEON_IS_AGP) {
1313                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1314                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1315                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1316                 if (!dev_priv->cp_ring->handle ||
1317                     !dev_priv->ring_rptr->handle ||
1318                     !dev->agp_buffer_map->handle) {
1319                         DRM_ERROR("could not find ioremap agp regions!\n");
1320                         radeon_do_cleanup_cp(dev);
1321                         return -EINVAL;
1322                 }
1323         } else
1324 #endif
1325         {
1326                 dev_priv->cp_ring->handle =
1327                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1328                 dev_priv->ring_rptr->handle =
1329                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1330                 dev->agp_buffer_map->handle =
1331                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1332
1333                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1334                           dev_priv->cp_ring->handle);
1335                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1336                           dev_priv->ring_rptr->handle);
1337                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1338                           dev->agp_buffer_map->handle);
1339         }
1340
1341         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1342         dev_priv->fb_size =
1343                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1344                 - dev_priv->fb_location;
1345
1346         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1347                                         ((dev_priv->front_offset
1348                                           + dev_priv->fb_location) >> 10));
1349
1350         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1351                                        ((dev_priv->back_offset
1352                                          + dev_priv->fb_location) >> 10));
1353
1354         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1355                                         ((dev_priv->depth_offset
1356                                           + dev_priv->fb_location) >> 10));
1357
1358         dev_priv->gart_size = init->gart_size;
1359
1360         /* New let's set the memory map ... */
1361         if (dev_priv->new_memmap) {
1362                 u32 base = 0;
1363
1364                 DRM_INFO("Setting GART location based on new memory map\n");
1365
1366                 /* If using AGP, try to locate the AGP aperture at the same
1367                  * location in the card and on the bus, though we have to
1368                  * align it down.
1369                  */
1370 #if __OS_HAS_AGP
1371                 if (dev_priv->flags & RADEON_IS_AGP) {
1372                         base = dev->agp->base;
1373                         /* Check if valid */
1374                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1375                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1376                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1377                                          dev->agp->base);
1378                                 base = 0;
1379                         }
1380                 }
1381 #endif
1382                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1383                 if (base == 0) {
1384                         base = dev_priv->fb_location + dev_priv->fb_size;
1385                         if (base < dev_priv->fb_location ||
1386                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1387                                 base = dev_priv->fb_location
1388                                         - dev_priv->gart_size;
1389                 }
1390                 dev_priv->gart_vm_start = base & 0xffc00000u;
1391                 if (dev_priv->gart_vm_start != base)
1392                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1393                                  base, dev_priv->gart_vm_start);
1394         } else {
1395                 DRM_INFO("Setting GART location based on old memory map\n");
1396                 dev_priv->gart_vm_start = dev_priv->fb_location +
1397                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1398         }
1399
1400 #if __OS_HAS_AGP
1401         if (dev_priv->flags & RADEON_IS_AGP)
1402                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1403                                                  - dev->agp->base
1404                                                  + dev_priv->gart_vm_start);
1405         else
1406 #endif
1407                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1408                                         - (unsigned long)dev->sg->virtual
1409                                         + dev_priv->gart_vm_start);
1410
1411         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1412         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1413         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1414                   dev_priv->gart_buffers_offset);
1415
1416         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1417         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1418                               + init->ring_size / sizeof(u32));
1419         dev_priv->ring.size = init->ring_size;
1420         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1421
1422         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1423         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1424
1425         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1426         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1427         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1428
1429         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1430
1431 #if __OS_HAS_AGP
1432         if (dev_priv->flags & RADEON_IS_AGP) {
1433                 /* Turn off PCI GART */
1434                 radeon_set_pcigart(dev_priv, 0);
1435         } else
1436 #endif
1437         {
1438                 u32 sctrl;
1439                 int ret;
1440
1441                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1442                 /* if we have an offset set from userspace */
1443                 if (dev_priv->pcigart_offset_set) {
1444                         dev_priv->gart_info.bus_addr =
1445                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1446                         dev_priv->gart_info.mapping.offset =
1447                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1448                         dev_priv->gart_info.mapping.size =
1449                             dev_priv->gart_info.table_size;
1450
1451                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1452                         dev_priv->gart_info.addr =
1453                             dev_priv->gart_info.mapping.handle;
1454
1455                         if (dev_priv->flags & RADEON_IS_PCIE)
1456                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1457                         else
1458                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1459                         dev_priv->gart_info.gart_table_location =
1460                             DRM_ATI_GART_FB;
1461
1462                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1463                                   dev_priv->gart_info.addr,
1464                                   dev_priv->pcigart_offset);
1465                 } else {
1466                         if (dev_priv->flags & RADEON_IS_IGPGART)
1467                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1468                         else
1469                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1470                         dev_priv->gart_info.gart_table_location =
1471                             DRM_ATI_GART_MAIN;
1472                         dev_priv->gart_info.addr = NULL;
1473                         dev_priv->gart_info.bus_addr = 0;
1474                         if (dev_priv->flags & RADEON_IS_PCIE) {
1475                                 DRM_ERROR
1476                                     ("Cannot use PCI Express without GART in FB memory\n");
1477                                 radeon_do_cleanup_cp(dev);
1478                                 return -EINVAL;
1479                         }
1480                 }
1481
1482                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1483                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1484                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1485                         ret = r600_page_table_init(dev);
1486                 else
1487                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1488                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1489
1490                 if (!ret) {
1491                         DRM_ERROR("failed to init PCI GART!\n");
1492                         radeon_do_cleanup_cp(dev);
1493                         return -ENOMEM;
1494                 }
1495
1496                 ret = radeon_setup_pcigart_surface(dev_priv);
1497                 if (ret) {
1498                         DRM_ERROR("failed to setup GART surface!\n");
1499                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1500                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1501                         else
1502                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1503                         radeon_do_cleanup_cp(dev);
1504                         return ret;
1505                 }
1506
1507                 /* Turn on PCI GART */
1508                 radeon_set_pcigart(dev_priv, 1);
1509         }
1510
1511         if (!dev_priv->me_fw) {
1512                 int err = radeon_cp_init_microcode(dev_priv);
1513                 if (err) {
1514                         DRM_ERROR("Failed to load firmware!\n");
1515                         radeon_do_cleanup_cp(dev);
1516                         return err;
1517                 }
1518         }
1519         radeon_cp_load_microcode(dev_priv);
1520         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1521
1522         dev_priv->last_buf = 0;
1523
1524         radeon_do_engine_reset(dev);
1525         radeon_test_writeback(dev_priv);
1526
1527         return 0;
1528 }
1529
1530 static int radeon_do_cleanup_cp(struct drm_device * dev)
1531 {
1532         drm_radeon_private_t *dev_priv = dev->dev_private;
1533         DRM_DEBUG("\n");
1534
1535         /* Make sure interrupts are disabled here because the uninstall ioctl
1536          * may not have been called from userspace and after dev_private
1537          * is freed, it's too late.
1538          */
1539         if (dev->irq_enabled)
1540                 drm_irq_uninstall(dev);
1541
1542 #if __OS_HAS_AGP
1543         if (dev_priv->flags & RADEON_IS_AGP) {
1544                 if (dev_priv->cp_ring != NULL) {
1545                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1546                         dev_priv->cp_ring = NULL;
1547                 }
1548                 if (dev_priv->ring_rptr != NULL) {
1549                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1550                         dev_priv->ring_rptr = NULL;
1551                 }
1552                 if (dev->agp_buffer_map != NULL) {
1553                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1554                         dev->agp_buffer_map = NULL;
1555                 }
1556         } else
1557 #endif
1558         {
1559
1560                 if (dev_priv->gart_info.bus_addr) {
1561                         /* Turn off PCI GART */
1562                         radeon_set_pcigart(dev_priv, 0);
1563                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1564                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1565                         else {
1566                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1567                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1568                         }
1569                 }
1570
1571                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1572                 {
1573                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1574                         dev_priv->gart_info.addr = NULL;
1575                 }
1576         }
1577         /* only clear to the start of flags */
1578         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1579
1580         return 0;
1581 }
1582
1583 /* This code will reinit the Radeon CP hardware after a resume from disc.
1584  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1585  * here we make sure that all Radeon hardware initialisation is re-done without
1586  * affecting running applications.
1587  *
1588  * Charl P. Botha <http://cpbotha.net>
1589  */
1590 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1591 {
1592         drm_radeon_private_t *dev_priv = dev->dev_private;
1593
1594         if (!dev_priv) {
1595                 DRM_ERROR("Called with no initialization\n");
1596                 return -EINVAL;
1597         }
1598
1599         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1600
1601 #if __OS_HAS_AGP
1602         if (dev_priv->flags & RADEON_IS_AGP) {
1603                 /* Turn off PCI GART */
1604                 radeon_set_pcigart(dev_priv, 0);
1605         } else
1606 #endif
1607         {
1608                 /* Turn on PCI GART */
1609                 radeon_set_pcigart(dev_priv, 1);
1610         }
1611
1612         radeon_cp_load_microcode(dev_priv);
1613         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1614
1615         radeon_do_engine_reset(dev);
1616         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1617
1618         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1619
1620         return 0;
1621 }
1622
1623 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1624 {
1625         drm_radeon_private_t *dev_priv = dev->dev_private;
1626         drm_radeon_init_t *init = data;
1627
1628         LOCK_TEST_WITH_RETURN(dev, file_priv);
1629
1630         if (init->func == RADEON_INIT_R300_CP)
1631                 r300_init_reg_flags(dev);
1632
1633         switch (init->func) {
1634         case RADEON_INIT_CP:
1635         case RADEON_INIT_R200_CP:
1636         case RADEON_INIT_R300_CP:
1637                 return radeon_do_init_cp(dev, init, file_priv);
1638         case RADEON_INIT_R600_CP:
1639                 return r600_do_init_cp(dev, init, file_priv);
1640         case RADEON_CLEANUP_CP:
1641                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1642                         return r600_do_cleanup_cp(dev);
1643                 else
1644                         return radeon_do_cleanup_cp(dev);
1645         }
1646
1647         return -EINVAL;
1648 }
1649
1650 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1651 {
1652         drm_radeon_private_t *dev_priv = dev->dev_private;
1653         DRM_DEBUG("\n");
1654
1655         LOCK_TEST_WITH_RETURN(dev, file_priv);
1656
1657         if (dev_priv->cp_running) {
1658                 DRM_DEBUG("while CP running\n");
1659                 return 0;
1660         }
1661         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1662                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1663                           dev_priv->cp_mode);
1664                 return 0;
1665         }
1666
1667         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1668                 r600_do_cp_start(dev_priv);
1669         else
1670                 radeon_do_cp_start(dev_priv);
1671
1672         return 0;
1673 }
1674
1675 /* Stop the CP.  The engine must have been idled before calling this
1676  * routine.
1677  */
1678 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1679 {
1680         drm_radeon_private_t *dev_priv = dev->dev_private;
1681         drm_radeon_cp_stop_t *stop = data;
1682         int ret;
1683         DRM_DEBUG("\n");
1684
1685         LOCK_TEST_WITH_RETURN(dev, file_priv);
1686
1687         if (!dev_priv->cp_running)
1688                 return 0;
1689
1690         /* Flush any pending CP commands.  This ensures any outstanding
1691          * commands are exectuted by the engine before we turn it off.
1692          */
1693         if (stop->flush) {
1694                 radeon_do_cp_flush(dev_priv);
1695         }
1696
1697         /* If we fail to make the engine go idle, we return an error
1698          * code so that the DRM ioctl wrapper can try again.
1699          */
1700         if (stop->idle) {
1701                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1702                         ret = r600_do_cp_idle(dev_priv);
1703                 else
1704                         ret = radeon_do_cp_idle(dev_priv);
1705                 if (ret)
1706                         return ret;
1707         }
1708
1709         /* Finally, we can turn off the CP.  If the engine isn't idle,
1710          * we will get some dropped triangles as they won't be fully
1711          * rendered before the CP is shut down.
1712          */
1713         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1714                 r600_do_cp_stop(dev_priv);
1715         else
1716                 radeon_do_cp_stop(dev_priv);
1717
1718         /* Reset the engine */
1719         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1720                 r600_do_engine_reset(dev);
1721         else
1722                 radeon_do_engine_reset(dev);
1723
1724         return 0;
1725 }
1726
1727 void radeon_do_release(struct drm_device * dev)
1728 {
1729         drm_radeon_private_t *dev_priv = dev->dev_private;
1730         int i, ret;
1731
1732         if (dev_priv) {
1733                 if (dev_priv->cp_running) {
1734                         /* Stop the cp */
1735                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1736                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1737                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1738 #ifdef __linux__
1739                                         schedule();
1740 #else
1741                                         tsleep(&ret, PZERO, "rdnrel", 1);
1742 #endif
1743                                 }
1744                         } else {
1745                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1746                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1747 #ifdef __linux__
1748                                         schedule();
1749 #else
1750                                         tsleep(&ret, PZERO, "rdnrel", 1);
1751 #endif
1752                                 }
1753                         }
1754                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1755                                 r600_do_cp_stop(dev_priv);
1756                                 r600_do_engine_reset(dev);
1757                         } else {
1758                                 radeon_do_cp_stop(dev_priv);
1759                                 radeon_do_engine_reset(dev);
1760                         }
1761                 }
1762
1763                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1764                         /* Disable *all* interrupts */
1765                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1766                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1767
1768                         if (dev_priv->mmio) {   /* remove all surfaces */
1769                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1770                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1771                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1772                                                      16 * i, 0);
1773                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1774                                                      16 * i, 0);
1775                                 }
1776                         }
1777                 }
1778
1779                 /* Free memory heap structures */
1780                 radeon_mem_takedown(&(dev_priv->gart_heap));
1781                 radeon_mem_takedown(&(dev_priv->fb_heap));
1782
1783                 /* deallocate kernel resources */
1784                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1785                         r600_do_cleanup_cp(dev);
1786                 else
1787                         radeon_do_cleanup_cp(dev);
1788                 if (dev_priv->me_fw) {
1789                         release_firmware(dev_priv->me_fw);
1790                         dev_priv->me_fw = NULL;
1791                 }
1792                 if (dev_priv->pfp_fw) {
1793                         release_firmware(dev_priv->pfp_fw);
1794                         dev_priv->pfp_fw = NULL;
1795                 }
1796         }
1797 }
1798
1799 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1800  */
1801 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1802 {
1803         drm_radeon_private_t *dev_priv = dev->dev_private;
1804         DRM_DEBUG("\n");
1805
1806         LOCK_TEST_WITH_RETURN(dev, file_priv);
1807
1808         if (!dev_priv) {
1809                 DRM_DEBUG("called before init done\n");
1810                 return -EINVAL;
1811         }
1812
1813         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1814                 r600_do_cp_reset(dev_priv);
1815         else
1816                 radeon_do_cp_reset(dev_priv);
1817
1818         /* The CP is no longer running after an engine reset */
1819         dev_priv->cp_running = 0;
1820
1821         return 0;
1822 }
1823
1824 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1825 {
1826         drm_radeon_private_t *dev_priv = dev->dev_private;
1827         DRM_DEBUG("\n");
1828
1829         LOCK_TEST_WITH_RETURN(dev, file_priv);
1830
1831         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1832                 return r600_do_cp_idle(dev_priv);
1833         else
1834                 return radeon_do_cp_idle(dev_priv);
1835 }
1836
1837 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1838  */
1839 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1840 {
1841         drm_radeon_private_t *dev_priv = dev->dev_private;
1842         DRM_DEBUG("\n");
1843
1844         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1845                 return r600_do_resume_cp(dev, file_priv);
1846         else
1847                 return radeon_do_resume_cp(dev, file_priv);
1848 }
1849
1850 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1851 {
1852         drm_radeon_private_t *dev_priv = dev->dev_private;
1853         DRM_DEBUG("\n");
1854
1855         LOCK_TEST_WITH_RETURN(dev, file_priv);
1856
1857         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1858                 return r600_do_engine_reset(dev);
1859         else
1860                 return radeon_do_engine_reset(dev);
1861 }
1862
1863 /* ================================================================
1864  * Fullscreen mode
1865  */
1866
1867 /* KW: Deprecated to say the least:
1868  */
1869 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1870 {
1871         return 0;
1872 }
1873
1874 /* ================================================================
1875  * Freelist management
1876  */
1877
1878 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1879  *   bufs until freelist code is used.  Note this hides a problem with
1880  *   the scratch register * (used to keep track of last buffer
1881  *   completed) being written to before * the last buffer has actually
1882  *   completed rendering.
1883  *
1884  * KW:  It's also a good way to find free buffers quickly.
1885  *
1886  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1887  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1888  * we essentially have to do this, else old clients will break.
1889  *
1890  * However, it does leave open a potential deadlock where all the
1891  * buffers are held by other clients, which can't release them because
1892  * they can't get the lock.
1893  */
1894
1895 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1896 {
1897         struct drm_device_dma *dma = dev->dma;
1898         drm_radeon_private_t *dev_priv = dev->dev_private;
1899         drm_radeon_buf_priv_t *buf_priv;
1900         struct drm_buf *buf;
1901         int i, t;
1902         int start;
1903
1904         if (++dev_priv->last_buf >= dma->buf_count)
1905                 dev_priv->last_buf = 0;
1906
1907         start = dev_priv->last_buf;
1908
1909         for (t = 0; t < dev_priv->usec_timeout; t++) {
1910                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1911                 DRM_DEBUG("done_age = %d\n", done_age);
1912                 for (i = start; i < dma->buf_count; i++) {
1913                         buf = dma->buflist[i];
1914                         buf_priv = buf->dev_private;
1915                         if (buf->file_priv == NULL || (buf->pending &&
1916                                                        buf_priv->age <=
1917                                                        done_age)) {
1918                                 dev_priv->stats.requested_bufs++;
1919                                 buf->pending = 0;
1920                                 return buf;
1921                         }
1922                         start = 0;
1923                 }
1924
1925                 if (t) {
1926                         DRM_UDELAY(1);
1927                         dev_priv->stats.freelist_loops++;
1928                 }
1929         }
1930
1931         DRM_DEBUG("returning NULL!\n");
1932         return NULL;
1933 }
1934
1935 #if 0
1936 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1937 {
1938         struct drm_device_dma *dma = dev->dma;
1939         drm_radeon_private_t *dev_priv = dev->dev_private;
1940         drm_radeon_buf_priv_t *buf_priv;
1941         struct drm_buf *buf;
1942         int i, t;
1943         int start;
1944         u32 done_age;
1945
1946         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1947         if (++dev_priv->last_buf >= dma->buf_count)
1948                 dev_priv->last_buf = 0;
1949
1950         start = dev_priv->last_buf;
1951         dev_priv->stats.freelist_loops++;
1952
1953         for (t = 0; t < 2; t++) {
1954                 for (i = start; i < dma->buf_count; i++) {
1955                         buf = dma->buflist[i];
1956                         buf_priv = buf->dev_private;
1957                         if (buf->file_priv == 0 || (buf->pending &&
1958                                                     buf_priv->age <=
1959                                                     done_age)) {
1960                                 dev_priv->stats.requested_bufs++;
1961                                 buf->pending = 0;
1962                                 return buf;
1963                         }
1964                 }
1965                 start = 0;
1966         }
1967
1968         return NULL;
1969 }
1970 #endif
1971
1972 void radeon_freelist_reset(struct drm_device * dev)
1973 {
1974         struct drm_device_dma *dma = dev->dma;
1975         drm_radeon_private_t *dev_priv = dev->dev_private;
1976         int i;
1977
1978         dev_priv->last_buf = 0;
1979         for (i = 0; i < dma->buf_count; i++) {
1980                 struct drm_buf *buf = dma->buflist[i];
1981                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1982                 buf_priv->age = 0;
1983         }
1984 }
1985
1986 /* ================================================================
1987  * CP command submission
1988  */
1989
1990 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1991 {
1992         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1993         int i;
1994         u32 last_head = GET_RING_HEAD(dev_priv);
1995
1996         for (i = 0; i < dev_priv->usec_timeout; i++) {
1997                 u32 head = GET_RING_HEAD(dev_priv);
1998
1999                 ring->space = (head - ring->tail) * sizeof(u32);
2000                 if (ring->space <= 0)
2001                         ring->space += ring->size;
2002                 if (ring->space > n)
2003                         return 0;
2004
2005                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2006
2007                 if (head != last_head)
2008                         i = 0;
2009                 last_head = head;
2010
2011                 DRM_UDELAY(1);
2012         }
2013
2014         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2015 #if RADEON_FIFO_DEBUG
2016         radeon_status(dev_priv);
2017         DRM_ERROR("failed!\n");
2018 #endif
2019         return -EBUSY;
2020 }
2021
2022 static int radeon_cp_get_buffers(struct drm_device *dev,
2023                                  struct drm_file *file_priv,
2024                                  struct drm_dma * d)
2025 {
2026         int i;
2027         struct drm_buf *buf;
2028
2029         for (i = d->granted_count; i < d->request_count; i++) {
2030                 buf = radeon_freelist_get(dev);
2031                 if (!buf)
2032                         return -EBUSY;  /* NOTE: broken client */
2033
2034                 buf->file_priv = file_priv;
2035
2036                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2037                                      sizeof(buf->idx)))
2038                         return -EFAULT;
2039                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2040                                      sizeof(buf->total)))
2041                         return -EFAULT;
2042
2043                 d->granted_count++;
2044         }
2045         return 0;
2046 }
2047
2048 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2049 {
2050         struct drm_device_dma *dma = dev->dma;
2051         int ret = 0;
2052         struct drm_dma *d = data;
2053
2054         LOCK_TEST_WITH_RETURN(dev, file_priv);
2055
2056         /* Please don't send us buffers.
2057          */
2058         if (d->send_count != 0) {
2059                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2060                           DRM_CURRENTPID, d->send_count);
2061                 return -EINVAL;
2062         }
2063
2064         /* We'll send you buffers.
2065          */
2066         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2067                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2068                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2069                 return -EINVAL;
2070         }
2071
2072         d->granted_count = 0;
2073
2074         if (d->request_count) {
2075                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2076         }
2077
2078         return ret;
2079 }
2080
2081 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2082 {
2083         drm_radeon_private_t *dev_priv;
2084         int ret = 0;
2085
2086         dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2087         if (dev_priv == NULL)
2088                 return -ENOMEM;
2089
2090         dev->dev_private = (void *)dev_priv;
2091         dev_priv->flags = flags;
2092
2093         switch (flags & RADEON_FAMILY_MASK) {
2094         case CHIP_R100:
2095         case CHIP_RV200:
2096         case CHIP_R200:
2097         case CHIP_R300:
2098         case CHIP_R350:
2099         case CHIP_R420:
2100         case CHIP_R423:
2101         case CHIP_RV410:
2102         case CHIP_RV515:
2103         case CHIP_R520:
2104         case CHIP_RV570:
2105         case CHIP_R580:
2106                 dev_priv->flags |= RADEON_HAS_HIERZ;
2107                 break;
2108         default:
2109                 /* all other chips have no hierarchical z buffer */
2110                 break;
2111         }
2112
2113         if (drm_device_is_agp(dev))
2114                 dev_priv->flags |= RADEON_IS_AGP;
2115         else if (drm_device_is_pcie(dev))
2116                 dev_priv->flags |= RADEON_IS_PCIE;
2117         else
2118                 dev_priv->flags |= RADEON_IS_PCI;
2119
2120         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2121                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2122                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2123         if (ret != 0)
2124                 return ret;
2125
2126         ret = drm_vblank_init(dev, 2);
2127         if (ret) {
2128                 radeon_driver_unload(dev);
2129                 return ret;
2130         }
2131
2132         DRM_DEBUG("%s card detected\n",
2133                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2134         return ret;
2135 }
2136
2137 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2138 {
2139         struct drm_radeon_master_private *master_priv;
2140         unsigned long sareapage;
2141         int ret;
2142
2143         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2144         if (!master_priv)
2145                 return -ENOMEM;
2146
2147         /* prebuild the SAREA */
2148         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2149         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2150                          &master_priv->sarea);
2151         if (ret) {
2152                 DRM_ERROR("SAREA setup failed\n");
2153                 return ret;
2154         }
2155         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2156         master_priv->sarea_priv->pfCurrentPage = 0;
2157
2158         master->driver_priv = master_priv;
2159         return 0;
2160 }
2161
2162 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2163 {
2164         struct drm_radeon_master_private *master_priv = master->driver_priv;
2165
2166         if (!master_priv)
2167                 return;
2168
2169         if (master_priv->sarea_priv &&
2170             master_priv->sarea_priv->pfCurrentPage != 0)
2171                 radeon_cp_dispatch_flip(dev, master);
2172
2173         master_priv->sarea_priv = NULL;
2174         if (master_priv->sarea)
2175                 drm_rmmap_locked(dev, master_priv->sarea);
2176
2177         kfree(master_priv);
2178
2179         master->driver_priv = NULL;
2180 }
2181
2182 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2183  * have to find them.
2184  */
2185 int radeon_driver_firstopen(struct drm_device *dev)
2186 {
2187         int ret;
2188         drm_local_map_t *map;
2189         drm_radeon_private_t *dev_priv = dev->dev_private;
2190
2191         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2192
2193         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2194         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2195                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2196                          _DRM_WRITE_COMBINING, &map);
2197         if (ret != 0)
2198                 return ret;
2199
2200         return 0;
2201 }
2202
2203 int radeon_driver_unload(struct drm_device *dev)
2204 {
2205         drm_radeon_private_t *dev_priv = dev->dev_private;
2206
2207         DRM_DEBUG("\n");
2208
2209         drm_rmmap(dev, dev_priv->mmio);
2210
2211         kfree(dev_priv);
2212
2213         dev->dev_private = NULL;
2214         return 0;
2215 }
2216
2217 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2218 {
2219         int i;
2220         u32 *ring;
2221         int tail_aligned;
2222
2223         /* check if the ring is padded out to 16-dword alignment */
2224
2225         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2226         if (tail_aligned) {
2227                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2228
2229                 ring = dev_priv->ring.start;
2230                 /* pad with some CP_PACKET2 */
2231                 for (i = 0; i < num_p2; i++)
2232                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2233
2234                 dev_priv->ring.tail += i;
2235
2236                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2237         }
2238
2239         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2240
2241         DRM_MEMORYBARRIER();
2242         GET_RING_HEAD( dev_priv );
2243
2244         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2245                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2246                 /* read from PCI bus to ensure correct posting */
2247                 RADEON_READ(R600_CP_RB_RPTR);
2248         } else {
2249                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2250                 /* read from PCI bus to ensure correct posting */
2251                 RADEON_READ(RADEON_CP_RB_RPTR);
2252         }
2253 }