drivers/dma/ioat/dma_v2.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine (versions >= 2), which
  25  * does asynchronous data movement and checksumming operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/dmaengine.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/i7300_idle.h>
  37 #include "dma.h"
  38 #include "dma_v2.h"
  39 #include "registers.h"
  40 #include "hw.h"
  41
  42 static int ioat_ring_alloc_order = 8;
  43 module_param(ioat_ring_alloc_order, int, 0644);
  44 MODULE_PARM_DESC(ioat_ring_alloc_order,
  45                  "ioat2+: allocate 2^n descriptors per channel (default: n=8)");
  46
  47 static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
  48 {
  49         void * __iomem reg_base = ioat->base.reg_base;
  50
  51         ioat->pending = 0;
  52         ioat->dmacount += ioat2_ring_pending(ioat);
  53         ioat->issued = ioat->head;
  54         /* make descriptor updates globally visible before notifying channel */
  55         wmb();
  56         writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
  57         dev_dbg(to_dev(&ioat->base),
  58                 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
  59                 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
  60 }
  61
  62 static void ioat2_issue_pending(struct dma_chan *chan)
  63 {
  64         struct ioat2_dma_chan *ioat = to_ioat2_chan(chan);
  65
  66         spin_lock_bh(&ioat->ring_lock);
  67         if (ioat->pending == 1)
  68                 __ioat2_issue_pending(ioat);
  69         spin_unlock_bh(&ioat->ring_lock);
  70 }
  71
  72 /**
  73  * ioat2_update_pending - log pending descriptors
  74  * @ioat: ioat2+ channel
  75  *
  76  * set pending to '1' unless pending is already set to '2', pending == 2
  77  * indicates that submission is temporarily blocked due to an in-flight
  78  * reset.  If we are already above the ioat_pending_level threshold then
  79  * just issue pending.
  80  *
  81  * called with ring_lock held
  82  */
  83 static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
  84 {
  85         if (unlikely(ioat->pending == 2))
  86                 return;
  87         else if (ioat2_ring_pending(ioat) > ioat_pending_level)
  88                 __ioat2_issue_pending(ioat);
  89         else
  90                 ioat->pending = 1;
  91 }
  92
  93 static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
  94 {
  95         void __iomem *reg_base = ioat->base.reg_base;
  96         struct ioat_ring_ent *desc;
  97         struct ioat_dma_descriptor *hw;
  98         int idx;
  99
 100         if (ioat2_ring_space(ioat) < 1) {
 101                 dev_err(to_dev(&ioat->base),
 102                         "Unable to start null desc - ring full\n");
 103                 return;
 104         }
 105
 106         dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
 107                 __func__, ioat->head, ioat->tail, ioat->issued);
 108         idx = ioat2_desc_alloc(ioat, 1);
 109         desc = ioat2_get_ring_ent(ioat, idx);
 110
 111         hw = desc->hw;
 112         hw->ctl = 0;
 113         hw->ctl_f.null = 1;
 114         hw->ctl_f.int_en = 1;
 115         hw->ctl_f.compl_write = 1;
 116         /* set size to non-zero value (channel returns error when size is 0) */
 117         hw->size = NULL_DESC_BUFFER_SIZE;
 118         hw->src_addr = 0;
 119         hw->dst_addr = 0;
 120         async_tx_ack(&desc->txd);
 121         writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
 122                reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
 123         writel(((u64) desc->txd.phys) >> 32,
 124                reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
 125         dump_desc_dbg(ioat, desc);
 126         __ioat2_issue_pending(ioat);
 127 }
 128
 129 static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
 130 {
 131         spin_lock_bh(&ioat->ring_lock);
 132         __ioat2_start_null_desc(ioat);
 133         spin_unlock_bh(&ioat->ring_lock);
 134 }
 135
 136 static void ioat2_cleanup(struct ioat2_dma_chan *ioat);
 137
 138 /**
 139  * ioat2_reset_part2 - reinit the channel after a reset
 140  */
 141 static void ioat2_reset_part2(struct work_struct *work)
 142 {
 143         struct ioat_chan_common *chan;
 144         struct ioat2_dma_chan *ioat;
 145
 146         chan = container_of(work, struct ioat_chan_common, work.work);
 147         ioat = container_of(chan, struct ioat2_dma_chan, base);
 148
 149         /* ensure that ->tail points to the stalled descriptor
 150          * (ioat->pending is set to 2 at this point so no new
 151          * descriptors will be issued while we perform this cleanup)
 152          */
 153         ioat2_cleanup(ioat);
 154
 155         spin_lock_bh(&chan->cleanup_lock);
 156         spin_lock_bh(&ioat->ring_lock);
 157
 158         /* set the tail to be re-issued */
 159         ioat->issued = ioat->tail;
 160         ioat->dmacount = 0;
 161
 162         dev_dbg(to_dev(&ioat->base),
 163                 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
 164                 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
 165
 166         if (ioat2_ring_pending(ioat)) {
 167                 struct ioat_ring_ent *desc;
 168
 169                 desc = ioat2_get_ring_ent(ioat, ioat->tail);
 170                 writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
 171                        chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
 172                 writel(((u64) desc->txd.phys) >> 32,
 173                        chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
 174                 __ioat2_issue_pending(ioat);
 175         } else
 176                 __ioat2_start_null_desc(ioat);
 177
 178         spin_unlock_bh(&ioat->ring_lock);
 179         spin_unlock_bh(&chan->cleanup_lock);
 180
 181         dev_info(to_dev(chan),
 182                  "chan%d reset - %d descs waiting, %d total desc\n",
 183                  chan_num(chan), ioat->dmacount, 1 << ioat->alloc_order);
 184 }
 185
 186 /**
 187  * ioat2_reset_channel - restart a channel
 188  * @ioat: IOAT DMA channel handle
 189  */
 190 static void ioat2_reset_channel(struct ioat2_dma_chan *ioat)
 191 {
 192         u32 chansts, chanerr;
 193         struct ioat_chan_common *chan = &ioat->base;
 194         u16 active;
 195
 196         spin_lock_bh(&ioat->ring_lock);
 197         active = ioat2_ring_active(ioat);
 198         spin_unlock_bh(&ioat->ring_lock);
 199         if (!active)
 200                 return;
 201
 202         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 203         chansts = (chan->completion_virt->low
 204                                         & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
 205         if (chanerr) {
 206                 dev_err(to_dev(chan),
 207                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 208                         chan_num(chan), chansts, chanerr);
 209                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 210         }
 211
 212         spin_lock_bh(&ioat->ring_lock);
 213         ioat->pending = 2;
 214         writeb(IOAT_CHANCMD_RESET,
 215                chan->reg_base
 216                + IOAT_CHANCMD_OFFSET(chan->device->version));
 217         spin_unlock_bh(&ioat->ring_lock);
 218         schedule_delayed_work(&chan->work, RESET_DELAY);
 219 }
 220
 221 /**
 222  * ioat2_chan_watchdog - watch for stuck channels
 223  */
 224 static void ioat2_chan_watchdog(struct work_struct *work)
 225 {
 226         struct ioatdma_device *device =
 227                 container_of(work, struct ioatdma_device, work.work);
 228         struct ioat2_dma_chan *ioat;
 229         struct ioat_chan_common *chan;
 230         u16 active;
 231         int i;
 232
 233         dev_dbg(&device->pdev->dev, "%s\n", __func__);
 234
 235         for (i = 0; i < device->common.chancnt; i++) {
 236                 chan = ioat_chan_by_index(device, i);
 237                 ioat = container_of(chan, struct ioat2_dma_chan, base);
 238
 239                 /*
 240                  * for version 2.0 if there are descriptors yet to be processed
 241                  * and the last completed hasn't changed since the last watchdog
 242                  *      if they haven't hit the pending level
 243                  *          issue the pending to push them through
 244                  *      else
 245                  *          try resetting the channel
 246                  */
 247                 spin_lock_bh(&ioat->ring_lock);
 248                 active = ioat2_ring_active(ioat);
 249                 spin_unlock_bh(&ioat->ring_lock);
 250
 251                 if (active &&
 252                     chan->last_completion &&
 253                     chan->last_completion == chan->watchdog_completion) {
 254
 255                         if (ioat->pending == 1)
 256                                 ioat2_issue_pending(&chan->common);
 257                         else {
 258                                 ioat2_reset_channel(ioat);
 259                                 chan->watchdog_completion = 0;
 260                         }
 261                 } else {
 262                         chan->last_compl_desc_addr_hw = 0;
 263                         chan->watchdog_completion = chan->last_completion;
 264                 }
 265                 chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie;
 266         }
 267         schedule_delayed_work(&device->work, WATCHDOG_DELAY);
 268 }
 269
 270 /**
 271  * ioat2_cleanup - clean finished descriptors (advance tail pointer)
 272  * @chan: ioat channel to be cleaned up
 273  */
 274 static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
 275 {
 276         struct ioat_chan_common *chan = &ioat->base;
 277         unsigned long phys_complete;
 278         struct ioat_ring_ent *desc;
 279         bool seen_current = false;
 280         u16 active;
 281         int i;
 282         struct dma_async_tx_descriptor *tx;
 283
 284         prefetch(chan->completion_virt);
 285
 286         spin_lock_bh(&chan->cleanup_lock);
 287         phys_complete = ioat_get_current_completion(chan);
 288         if (phys_complete == chan->last_completion) {
 289                 spin_unlock_bh(&chan->cleanup_lock);
 290                 /*
 291                  * perhaps we're stuck so hard that the watchdog can't go off?
 292                  * try to catch it after WATCHDOG_DELAY seconds
 293                  */
 294                 if (chan->device->version < IOAT_VER_3_0) {
 295                         unsigned long tmo;
 296
 297                         tmo = chan->last_completion_time + HZ*WATCHDOG_DELAY;
 298                         if (time_after(jiffies, tmo)) {
 299                                 ioat2_chan_watchdog(&(chan->device->work.work));
 300                                 chan->last_completion_time = jiffies;
 301                         }
 302                 }
 303                 return;
 304         }
 305         chan->last_completion_time = jiffies;
 306
 307         spin_lock_bh(&ioat->ring_lock);
 308
 309         dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
 310                 __func__, ioat->head, ioat->tail, ioat->issued);
 311
 312         active = ioat2_ring_active(ioat);
 313         for (i = 0; i < active && !seen_current; i++) {
 314                 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
 315                 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
 316                 tx = &desc->txd;
 317                 dump_desc_dbg(ioat, desc);
 318                 if (tx->cookie) {
 319                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 320                         chan->completed_cookie = tx->cookie;
 321                         tx->cookie = 0;
 322                         if (tx->callback) {
 323                                 tx->callback(tx->callback_param);
 324                                 tx->callback = NULL;
 325                         }
 326                 }
 327
 328                 if (tx->phys == phys_complete)
 329                         seen_current = true;
 330         }
 331         ioat->tail += i;
 332         BUG_ON(!seen_current); /* no active descs have written a completion? */
 333         spin_unlock_bh(&ioat->ring_lock);
 334
 335         chan->last_completion = phys_complete;
 336
 337         spin_unlock_bh(&chan->cleanup_lock);
 338 }
 339
 340 static void ioat2_cleanup_tasklet(unsigned long data)
 341 {
 342         struct ioat2_dma_chan *ioat = (void *) data;
 343
 344         ioat2_cleanup(ioat);
 345         writew(IOAT_CHANCTRL_INT_DISABLE,
 346                ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
 347 }
 348
 349 /**
 350  * ioat2_enumerate_channels - find and initialize the device's channels
 351  * @device: the device to be enumerated
 352  */
 353 static int ioat2_enumerate_channels(struct ioatdma_device *device)
 354 {
 355         struct ioat2_dma_chan *ioat;
 356         struct device *dev = &device->pdev->dev;
 357         struct dma_device *dma = &device->common;
 358         u8 xfercap_log;
 359         int i;
 360
 361         INIT_LIST_HEAD(&dma->channels);
 362         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 363         xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 364         if (xfercap_log == 0)
 365                 return 0;
 366         dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
 367
 368         /* FIXME which i/oat version is i7300? */
 369 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
 370         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 371                 dma->chancnt--;
 372 #endif
 373         for (i = 0; i < dma->chancnt; i++) {
 374                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 375                 if (!ioat)
 376                         break;
 377
 378                 ioat_init_channel(device, &ioat->base, i,
 379                                   ioat2_reset_part2,
 380                                   ioat2_cleanup_tasklet,
 381                                   (unsigned long) ioat);
 382                 ioat->xfercap_log = xfercap_log;
 383                 spin_lock_init(&ioat->ring_lock);
 384         }
 385         dma->chancnt = i;
 386         return i;
 387 }
 388
 389 static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
 390 {
 391         struct dma_chan *c = tx->chan;
 392         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 393         dma_cookie_t cookie = c->cookie;
 394
 395         cookie++;
 396         if (cookie < 0)
 397                 cookie = 1;
 398         tx->cookie = cookie;
 399         c->cookie = cookie;
 400         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 401
 402         ioat2_update_pending(ioat);
 403         spin_unlock_bh(&ioat->ring_lock);
 404
 405         return cookie;
 406 }
 407
 408 static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan)
 409 {
 410         struct ioat_dma_descriptor *hw;
 411         struct ioat_ring_ent *desc;
 412         struct ioatdma_device *dma;
 413         dma_addr_t phys;
 414
 415         dma = to_ioatdma_device(chan->device);
 416         hw = pci_pool_alloc(dma->dma_pool, GFP_KERNEL, &phys);
 417         if (!hw)
 418                 return NULL;
 419         memset(hw, 0, sizeof(*hw));
 420
 421         desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 422         if (!desc) {
 423                 pci_pool_free(dma->dma_pool, hw, phys);
 424                 return NULL;
 425         }
 426
 427         dma_async_tx_descriptor_init(&desc->txd, chan);
 428         desc->txd.tx_submit = ioat2_tx_submit_unlock;
 429         desc->hw = hw;
 430         desc->txd.phys = phys;
 431         return desc;
 432 }
 433
 434 static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
 435 {
 436         struct ioatdma_device *dma;
 437
 438         dma = to_ioatdma_device(chan->device);
 439         pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
 440         kfree(desc);
 441 }
 442
 443 /* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
 444  * @chan: channel to be initialized
 445  */
 446 static int ioat2_alloc_chan_resources(struct dma_chan *c)
 447 {
 448         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 449         struct ioat_chan_common *chan = &ioat->base;
 450         struct ioat_ring_ent **ring;
 451         u16 chanctrl;
 452         u32 chanerr;
 453         int descs;
 454         int i;
 455
 456         /* have we already been set up? */
 457         if (ioat->ring)
 458                 return 1 << ioat->alloc_order;
 459
 460         /* Setup register to interrupt and write completion status on error */
 461         chanctrl = IOAT_CHANCTRL_ERR_INT_EN | IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
 462                    IOAT_CHANCTRL_ERR_COMPLETION_EN;
 463         writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 464
 465         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 466         if (chanerr) {
 467                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
 468                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 469         }
 470
 471         /* allocate a completion writeback area */
 472         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 473         chan->completion_virt = pci_pool_alloc(chan->device->completion_pool,
 474                                                GFP_KERNEL,
 475                                                &chan->completion_addr);
 476         if (!chan->completion_virt)
 477                 return -ENOMEM;
 478
 479         memset(chan->completion_virt, 0,
 480                sizeof(*chan->completion_virt));
 481         writel(((u64) chan->completion_addr) & 0x00000000FFFFFFFF,
 482                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 483         writel(((u64) chan->completion_addr) >> 32,
 484                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 485
 486         ioat->alloc_order = ioat_get_alloc_order();
 487         descs = 1 << ioat->alloc_order;
 488
 489         /* allocate the array to hold the software ring */
 490         ring = kcalloc(descs, sizeof(*ring), GFP_KERNEL);
 491         if (!ring)
 492                 return -ENOMEM;
 493         for (i = 0; i < descs; i++) {
 494                 ring[i] = ioat2_alloc_ring_ent(c);
 495                 if (!ring[i]) {
 496                         while (i--)
 497                                 ioat2_free_ring_ent(ring[i], c);
 498                         kfree(ring);
 499                         return -ENOMEM;
 500                 }
 501                 set_desc_id(ring[i], i);
 502         }
 503
 504         /* link descs */
 505         for (i = 0; i < descs-1; i++) {
 506                 struct ioat_ring_ent *next = ring[i+1];
 507                 struct ioat_dma_descriptor *hw = ring[i]->hw;
 508
 509                 hw->next = next->txd.phys;
 510         }
 511         ring[i]->hw->next = ring[0]->txd.phys;
 512
 513         spin_lock_bh(&ioat->ring_lock);
 514         ioat->ring = ring;
 515         ioat->head = 0;
 516         ioat->issued = 0;
 517         ioat->tail = 0;
 518         ioat->pending = 0;
 519         spin_unlock_bh(&ioat->ring_lock);
 520
 521         tasklet_enable(&chan->cleanup_task);
 522         ioat2_start_null_desc(ioat);
 523
 524         return descs;
 525 }
 526
 527 /**
 528  * ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops
 529  * @idx: gets starting descriptor index on successful allocation
 530  * @ioat: ioat2,3 channel (ring) to operate on
 531  * @num_descs: allocation length
 532  */
 533 static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs)
 534 {
 535         struct ioat_chan_common *chan = &ioat->base;
 536
 537         spin_lock_bh(&ioat->ring_lock);
 538         if (unlikely(ioat2_ring_space(ioat) < num_descs)) {
 539                 if (printk_ratelimit())
 540                         dev_dbg(to_dev(chan),
 541                                 "%s: ring full! num_descs: %d (%x:%x:%x)\n",
 542                                 __func__, num_descs, ioat->head, ioat->tail,
 543                                 ioat->issued);
 544                 spin_unlock_bh(&ioat->ring_lock);
 545
 546                 /* do direct reclaim in the allocation failure case */
 547                 ioat2_cleanup(ioat);
 548
 549                 return -ENOMEM;
 550         }
 551
 552         dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
 553                 __func__, num_descs, ioat->head, ioat->tail, ioat->issued);
 554
 555         *idx = ioat2_desc_alloc(ioat, num_descs);
 556         return 0;  /* with ioat->ring_lock held */
 557 }
 558
 559 static struct dma_async_tx_descriptor *
 560 ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
 561                            dma_addr_t dma_src, size_t len, unsigned long flags)
 562 {
 563         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 564         struct ioat_dma_descriptor *hw;
 565         struct ioat_ring_ent *desc;
 566         dma_addr_t dst = dma_dest;
 567         dma_addr_t src = dma_src;
 568         size_t total_len = len;
 569         int num_descs;
 570         u16 idx;
 571         int i;
 572
 573         num_descs = ioat2_xferlen_to_descs(ioat, len);
 574         if (likely(num_descs) &&
 575             ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
 576                 /* pass */;
 577         else
 578                 return NULL;
 579         for (i = 0; i < num_descs; i++) {
 580                 size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
 581
 582                 desc = ioat2_get_ring_ent(ioat, idx + i);
 583                 hw = desc->hw;
 584
 585                 hw->size = copy;
 586                 hw->ctl = 0;
 587                 hw->src_addr = src;
 588                 hw->dst_addr = dst;
 589
 590                 len -= copy;
 591                 dst += copy;
 592                 src += copy;
 593                 dump_desc_dbg(ioat, desc);
 594         }
 595
 596         desc->txd.flags = flags;
 597         desc->len = total_len;
 598         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 599         hw->ctl_f.compl_write = 1;
 600         dump_desc_dbg(ioat, desc);
 601         /* we leave the channel locked to ensure in order submission */
 602
 603         return &desc->txd;
 604 }
 605
 606 /**
 607  * ioat2_free_chan_resources - release all the descriptors
 608  * @chan: the channel to be cleaned
 609  */
 610 static void ioat2_free_chan_resources(struct dma_chan *c)
 611 {
 612         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 613         struct ioat_chan_common *chan = &ioat->base;
 614         struct ioatdma_device *ioatdma_device = chan->device;
 615         struct ioat_ring_ent *desc;
 616         const u16 total_descs = 1 << ioat->alloc_order;
 617         int descs;
 618         int i;
 619
 620         /* Before freeing channel resources first check
 621          * if they have been previously allocated for this channel.
 622          */
 623         if (!ioat->ring)
 624                 return;
 625
 626         tasklet_disable(&chan->cleanup_task);
 627         ioat2_cleanup(ioat);
 628
 629         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 630          * before removing DMA descriptor resources.
 631          */
 632         writeb(IOAT_CHANCMD_RESET,
 633                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 634         mdelay(100);
 635
 636         spin_lock_bh(&ioat->ring_lock);
 637         descs = ioat2_ring_space(ioat);
 638         dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
 639         for (i = 0; i < descs; i++) {
 640                 desc = ioat2_get_ring_ent(ioat, ioat->head + i);
 641                 ioat2_free_ring_ent(desc, c);
 642         }
 643
 644         if (descs < total_descs)
 645                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 646                         total_descs - descs);
 647
 648         for (i = 0; i < total_descs - descs; i++) {
 649                 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
 650                 dump_desc_dbg(ioat, desc);
 651                 ioat2_free_ring_ent(desc, c);
 652         }
 653
 654         kfree(ioat->ring);
 655         ioat->ring = NULL;
 656         ioat->alloc_order = 0;
 657         pci_pool_free(ioatdma_device->completion_pool,
 658                       chan->completion_virt,
 659                       chan->completion_addr);
 660         spin_unlock_bh(&ioat->ring_lock);
 661
 662         chan->last_completion = 0;
 663         chan->completion_addr = 0;
 664         ioat->pending = 0;
 665         ioat->dmacount = 0;
 666         chan->watchdog_completion = 0;
 667         chan->last_compl_desc_addr_hw = 0;
 668         chan->watchdog_tcp_cookie = 0;
 669         chan->watchdog_last_tcp_cookie = 0;
 670 }
 671
 672 static enum dma_status
 673 ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie,
 674                      dma_cookie_t *done, dma_cookie_t *used)
 675 {
 676         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 677
 678         if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
 679                 return DMA_SUCCESS;
 680
 681         ioat2_cleanup(ioat);
 682
 683         return ioat_is_complete(c, cookie, done, used);
 684 }
 685
 686 int ioat2_dma_probe(struct ioatdma_device *device, int dca)
 687 {
 688         struct pci_dev *pdev = device->pdev;
 689         struct dma_device *dma;
 690         struct dma_chan *c;
 691         struct ioat_chan_common *chan;
 692         int err;
 693
 694         device->enumerate_channels = ioat2_enumerate_channels;
 695         dma = &device->common;
 696         dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
 697         dma->device_issue_pending = ioat2_issue_pending;
 698         dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
 699         dma->device_free_chan_resources = ioat2_free_chan_resources;
 700         dma->device_is_tx_complete = ioat2_is_complete;
 701
 702         err = ioat_probe(device);
 703         if (err)
 704                 return err;
 705         ioat_set_tcp_copy_break(2048);
 706
 707         list_for_each_entry(c, &dma->channels, device_node) {
 708                 chan = to_chan_common(c);
 709                 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
 710                        chan->reg_base + IOAT_DCACTRL_OFFSET);
 711         }
 712
 713         err = ioat_register(device);
 714         if (err)
 715                 return err;
 716         if (dca)
 717                 device->dca = ioat2_dca_init(pdev, device->reg_base);
 718
 719         INIT_DELAYED_WORK(&device->work, ioat2_chan_watchdog);
 720         schedule_delayed_work(&device->work, WATCHDOG_DELAY);
 721
 722         return err;
 723 }
 724
 725 int ioat3_dma_probe(struct ioatdma_device *device, int dca)
 726 {
 727         struct pci_dev *pdev = device->pdev;
 728         struct dma_device *dma;
 729         struct dma_chan *c;
 730         struct ioat_chan_common *chan;
 731         int err;
 732         u16 dev_id;
 733
 734         device->enumerate_channels = ioat2_enumerate_channels;
 735         dma = &device->common;
 736         dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
 737         dma->device_issue_pending = ioat2_issue_pending;
 738         dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
 739         dma->device_free_chan_resources = ioat2_free_chan_resources;
 740         dma->device_is_tx_complete = ioat2_is_complete;
 741
 742         /* -= IOAT ver.3 workarounds =- */
 743         /* Write CHANERRMSK_INT with 3E07h to mask out the errors
 744          * that can cause stability issues for IOAT ver.3
 745          */
 746         pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
 747
 748         /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
 749          * (workaround for spurious config parity error after restart)
 750          */
 751         pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
 752         if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
 753                 pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
 754
 755         err = ioat_probe(device);
 756         if (err)
 757                 return err;
 758         ioat_set_tcp_copy_break(262144);
 759
 760         list_for_each_entry(c, &dma->channels, device_node) {
 761                 chan = to_chan_common(c);
 762                 writel(IOAT_DMA_DCA_ANY_CPU,
 763                        chan->reg_base + IOAT_DCACTRL_OFFSET);
 764         }
 765
 766         err = ioat_register(device);
 767         if (err)
 768                 return err;
 769         if (dca)
 770                 device->dca = ioat3_dca_init(pdev, device->reg_base);
 771
 772         return err;
 773 }