drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/serial_reg.h>
  18 #include <linux/pci.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/dmi.h>
  25
  26 #include <linux/dmaengine.h>
  27 #include <linux/pch_dma.h>
  28
  29 enum {
  30         PCH_UART_HANDLED_RX_INT_SHIFT,
  31         PCH_UART_HANDLED_TX_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  33         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  34         PCH_UART_HANDLED_MS_INT_SHIFT,
  35 };
  36
  37 enum {
  38         PCH_UART_8LINE,
  39         PCH_UART_2LINE,
  40 };
  41
  42 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  43
  44 /* Set the max number of UART port
  45  * Intel EG20T PCH: 4 port
  46  * OKI SEMICONDUCTOR ML7213 IOH: 3 port
  47 */
  48 #define PCH_UART_NR     4
  49
  50 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  51 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  52 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  53                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  54 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  55                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  56 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  57
  58 #define PCH_UART_RBR            0x00
  59 #define PCH_UART_THR            0x00
  60
  61 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  62                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  63 #define PCH_UART_IER_ERBFI      0x00000001
  64 #define PCH_UART_IER_ETBEI      0x00000002
  65 #define PCH_UART_IER_ELSI       0x00000004
  66 #define PCH_UART_IER_EDSSI      0x00000008
  67
  68 #define PCH_UART_IIR_IP                 0x00000001
  69 #define PCH_UART_IIR_IID                0x00000006
  70 #define PCH_UART_IIR_MSI                0x00000000
  71 #define PCH_UART_IIR_TRI                0x00000002
  72 #define PCH_UART_IIR_RRI                0x00000004
  73 #define PCH_UART_IIR_REI                0x00000006
  74 #define PCH_UART_IIR_TOI                0x00000008
  75 #define PCH_UART_IIR_FIFO256            0x00000020
  76 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  77 #define PCH_UART_IIR_FE                 0x000000C0
  78
  79 #define PCH_UART_FCR_FIFOE              0x00000001
  80 #define PCH_UART_FCR_RFR                0x00000002
  81 #define PCH_UART_FCR_TFR                0x00000004
  82 #define PCH_UART_FCR_DMS                0x00000008
  83 #define PCH_UART_FCR_FIFO256            0x00000020
  84 #define PCH_UART_FCR_RFTL               0x000000C0
  85
  86 #define PCH_UART_FCR_RFTL1              0x00000000
  87 #define PCH_UART_FCR_RFTL64             0x00000040
  88 #define PCH_UART_FCR_RFTL128            0x00000080
  89 #define PCH_UART_FCR_RFTL224            0x000000C0
  90 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  91 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  92 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  93 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  94 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  95 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  96 #define PCH_UART_FCR_RFTL_SHIFT         6
  97
  98 #define PCH_UART_LCR_WLS        0x00000003
  99 #define PCH_UART_LCR_STB        0x00000004
 100 #define PCH_UART_LCR_PEN        0x00000008
 101 #define PCH_UART_LCR_EPS        0x00000010
 102 #define PCH_UART_LCR_SP         0x00000020
 103 #define PCH_UART_LCR_SB         0x00000040
 104 #define PCH_UART_LCR_DLAB       0x00000080
 105 #define PCH_UART_LCR_NP         0x00000000
 106 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 107 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 108 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 109 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 110                                 PCH_UART_LCR_SP)
 111
 112 #define PCH_UART_LCR_5BIT       0x00000000
 113 #define PCH_UART_LCR_6BIT       0x00000001
 114 #define PCH_UART_LCR_7BIT       0x00000002
 115 #define PCH_UART_LCR_8BIT       0x00000003
 116
 117 #define PCH_UART_MCR_DTR        0x00000001
 118 #define PCH_UART_MCR_RTS        0x00000002
 119 #define PCH_UART_MCR_OUT        0x0000000C
 120 #define PCH_UART_MCR_LOOP       0x00000010
 121 #define PCH_UART_MCR_AFE        0x00000020
 122
 123 #define PCH_UART_LSR_DR         0x00000001
 124 #define PCH_UART_LSR_ERR        (1<<7)
 125
 126 #define PCH_UART_MSR_DCTS       0x00000001
 127 #define PCH_UART_MSR_DDSR       0x00000002
 128 #define PCH_UART_MSR_TERI       0x00000004
 129 #define PCH_UART_MSR_DDCD       0x00000008
 130 #define PCH_UART_MSR_CTS        0x00000010
 131 #define PCH_UART_MSR_DSR        0x00000020
 132 #define PCH_UART_MSR_RI         0x00000040
 133 #define PCH_UART_MSR_DCD        0x00000080
 134 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 135                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 136
 137 #define PCH_UART_DLL            0x00
 138 #define PCH_UART_DLM            0x01
 139
 140 #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
 141
 142 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 143 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 144 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 145 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 146 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 147
 148 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 149 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 150 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 151 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 152 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 153 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 154 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 155 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 156 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 157 #define PCH_UART_HAL_STB1               0
 158 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 159
 160 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 161 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 162 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 163                                         PCH_UART_HAL_CLR_RX_FIFO)
 164
 165 #define PCH_UART_HAL_DMA_MODE0          0
 166 #define PCH_UART_HAL_FIFO_DIS           0
 167 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 168 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 169                                         PCH_UART_FCR_FIFO256)
 170 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 171 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 172 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 173 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 174 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 175 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 176 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 177 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 178 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 179 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 180 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 181 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 182 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 183 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 184
 185 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 186 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 187 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 188 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 189 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 190
 191 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 192 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 193 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 194 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 195 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 196
 197 #define PCI_VENDOR_ID_ROHM              0x10DB
 198
 199 struct pch_uart_buffer {
 200         unsigned char *buf;
 201         int size;
 202 };
 203
 204 struct eg20t_port {
 205         struct uart_port port;
 206         int port_type;
 207         void __iomem *membase;
 208         resource_size_t mapbase;
 209         unsigned int iobase;
 210         struct pci_dev *pdev;
 211         int fifo_size;
 212         int base_baud;
 213         int start_tx;
 214         int start_rx;
 215         int tx_empty;
 216         int int_dis_flag;
 217         int trigger;
 218         int trigger_level;
 219         struct pch_uart_buffer rxbuf;
 220         unsigned int dmsr;
 221         unsigned int fcr;
 222         unsigned int mcr;
 223         unsigned int use_dma;
 224         unsigned int use_dma_flag;
 225         struct dma_async_tx_descriptor  *desc_tx;
 226         struct dma_async_tx_descriptor  *desc_rx;
 227         struct pch_dma_slave            param_tx;
 228         struct pch_dma_slave            param_rx;
 229         struct dma_chan                 *chan_tx;
 230         struct dma_chan                 *chan_rx;
 231         struct scatterlist              *sg_tx_p;
 232         int                             nent;
 233         struct scatterlist              sg_rx;
 234         int                             tx_dma_use;
 235         void                            *rx_buf_virt;
 236         dma_addr_t                      rx_buf_dma;
 237 };
 238
 239 /**
 240  * struct pch_uart_driver_data - private data structure for UART-DMA
 241  * @port_type:                  The number of DMA channel
 242  * @line_no:                    UART port line number (0, 1, 2...)
 243  */
 244 struct pch_uart_driver_data {
 245         int port_type;
 246         int line_no;
 247 };
 248
 249 enum pch_uart_num_t {
 250         pch_et20t_uart0 = 0,
 251         pch_et20t_uart1,
 252         pch_et20t_uart2,
 253         pch_et20t_uart3,
 254         pch_ml7213_uart0,
 255         pch_ml7213_uart1,
 256         pch_ml7213_uart2,
 257 };
 258
 259 static struct pch_uart_driver_data drv_dat[] = {
 260         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 261         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 262         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 263         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 264         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 265         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 266         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 267 };
 268
 269 static unsigned int default_baud = 9600;
 270 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 271 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 272 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 273 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 274
 275 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 276                                  int base_baud)
 277 {
 278         struct eg20t_port *priv = pci_get_drvdata(pdev);
 279
 280         priv->trigger_level = 1;
 281         priv->fcr = 0;
 282 }
 283
 284 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 285 {
 286         unsigned int msr = ioread8(base + UART_MSR);
 287         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 288
 289         return msr;
 290 }
 291
 292 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 293                                           unsigned int flag)
 294 {
 295         u8 ier = ioread8(priv->membase + UART_IER);
 296         ier |= flag & PCH_UART_IER_MASK;
 297         iowrite8(ier, priv->membase + UART_IER);
 298 }
 299
 300 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 301                                            unsigned int flag)
 302 {
 303         u8 ier = ioread8(priv->membase + UART_IER);
 304         ier &= ~(flag & PCH_UART_IER_MASK);
 305         iowrite8(ier, priv->membase + UART_IER);
 306 }
 307
 308 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 309                                  unsigned int parity, unsigned int bits,
 310                                  unsigned int stb)
 311 {
 312         unsigned int dll, dlm, lcr;
 313         int div;
 314
 315         div = DIV_ROUND(priv->base_baud / 16, baud);
 316         if (div < 0 || USHRT_MAX <= div) {
 317                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 318                 return -EINVAL;
 319         }
 320
 321         dll = (unsigned int)div & 0x00FFU;
 322         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 323
 324         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 325                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 326                 return -EINVAL;
 327         }
 328
 329         if (bits & ~PCH_UART_LCR_WLS) {
 330                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 331                 return -EINVAL;
 332         }
 333
 334         if (stb & ~PCH_UART_LCR_STB) {
 335                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 336                 return -EINVAL;
 337         }
 338
 339         lcr = parity;
 340         lcr |= bits;
 341         lcr |= stb;
 342
 343         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 344                  __func__, baud, div, lcr, jiffies);
 345         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 346         iowrite8(dll, priv->membase + PCH_UART_DLL);
 347         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 348         iowrite8(lcr, priv->membase + UART_LCR);
 349
 350         return 0;
 351 }
 352
 353 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 354                                     unsigned int flag)
 355 {
 356         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 357                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 358                         __func__, flag);
 359                 return -EINVAL;
 360         }
 361
 362         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 363         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 364                  priv->membase + UART_FCR);
 365         iowrite8(priv->fcr, priv->membase + UART_FCR);
 366
 367         return 0;
 368 }
 369
 370 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 371                                  unsigned int dmamode,
 372                                  unsigned int fifo_size, unsigned int trigger)
 373 {
 374         u8 fcr;
 375
 376         if (dmamode & ~PCH_UART_FCR_DMS) {
 377                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 378                         __func__, dmamode);
 379                 return -EINVAL;
 380         }
 381
 382         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 383                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 384                         __func__, fifo_size);
 385                 return -EINVAL;
 386         }
 387
 388         if (trigger & ~PCH_UART_FCR_RFTL) {
 389                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 390                         __func__, trigger);
 391                 return -EINVAL;
 392         }
 393
 394         switch (priv->fifo_size) {
 395         case 256:
 396                 priv->trigger_level =
 397                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 398                 break;
 399         case 64:
 400                 priv->trigger_level =
 401                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 402                 break;
 403         case 16:
 404                 priv->trigger_level =
 405                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 406                 break;
 407         default:
 408                 priv->trigger_level =
 409                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 410                 break;
 411         }
 412         fcr =
 413             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 414         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 415         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 416                  priv->membase + UART_FCR);
 417         iowrite8(fcr, priv->membase + UART_FCR);
 418         priv->fcr = fcr;
 419
 420         return 0;
 421 }
 422
 423 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 424 {
 425         priv->dmsr = 0;
 426         return get_msr(priv, priv->membase);
 427 }
 428
 429 static void pch_uart_hal_write(struct eg20t_port *priv,
 430                               const unsigned char *buf, int tx_size)
 431 {
 432         int i;
 433         unsigned int thr;
 434
 435         for (i = 0; i < tx_size;) {
 436                 thr = buf[i++];
 437                 iowrite8(thr, priv->membase + PCH_UART_THR);
 438         }
 439 }
 440
 441 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 442                              int rx_size)
 443 {
 444         int i;
 445         u8 rbr, lsr;
 446
 447         lsr = ioread8(priv->membase + UART_LSR);
 448         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 449              i < rx_size && lsr & UART_LSR_DR;
 450              lsr = ioread8(priv->membase + UART_LSR)) {
 451                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 452                 buf[i++] = rbr;
 453         }
 454         return i;
 455 }
 456
 457 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 458 {
 459         unsigned int iir;
 460         int ret;
 461
 462         iir = ioread8(priv->membase + UART_IIR);
 463         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 464         return ret;
 465 }
 466
 467 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 468 {
 469         return ioread8(priv->membase + UART_LSR);
 470 }
 471
 472 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 473 {
 474         unsigned int lcr;
 475
 476         lcr = ioread8(priv->membase + UART_LCR);
 477         if (on)
 478                 lcr |= PCH_UART_LCR_SB;
 479         else
 480                 lcr &= ~PCH_UART_LCR_SB;
 481
 482         iowrite8(lcr, priv->membase + UART_LCR);
 483 }
 484
 485 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 486                    int size)
 487 {
 488         struct uart_port *port;
 489         struct tty_struct *tty;
 490
 491         port = &priv->port;
 492         tty = tty_port_tty_get(&port->state->port);
 493         if (!tty) {
 494                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 495                 return -EBUSY;
 496         }
 497
 498         tty_insert_flip_string(tty, buf, size);
 499         tty_flip_buffer_push(tty);
 500         tty_kref_put(tty);
 501
 502         return 0;
 503 }
 504
 505 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 506 {
 507         int ret;
 508         struct uart_port *port = &priv->port;
 509
 510         if (port->x_char) {
 511                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 512                         __func__, port->x_char, jiffies);
 513                 buf[0] = port->x_char;
 514                 port->x_char = 0;
 515                 ret = 1;
 516         } else {
 517                 ret = 0;
 518         }
 519
 520         return ret;
 521 }
 522
 523 static int dma_push_rx(struct eg20t_port *priv, int size)
 524 {
 525         struct tty_struct *tty;
 526         int room;
 527         struct uart_port *port = &priv->port;
 528
 529         port = &priv->port;
 530         tty = tty_port_tty_get(&port->state->port);
 531         if (!tty) {
 532                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 533                 return 0;
 534         }
 535
 536         room = tty_buffer_request_room(tty, size);
 537
 538         if (room < size)
 539                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 540                          size - room);
 541         if (!room)
 542                 return room;
 543
 544         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 545
 546         port->icount.rx += room;
 547         tty_kref_put(tty);
 548
 549         return room;
 550 }
 551
 552 static void pch_free_dma(struct uart_port *port)
 553 {
 554         struct eg20t_port *priv;
 555         priv = container_of(port, struct eg20t_port, port);
 556
 557         if (priv->chan_tx) {
 558                 dma_release_channel(priv->chan_tx);
 559                 priv->chan_tx = NULL;
 560         }
 561         if (priv->chan_rx) {
 562                 dma_release_channel(priv->chan_rx);
 563                 priv->chan_rx = NULL;
 564         }
 565         if (sg_dma_address(&priv->sg_rx))
 566                 dma_free_coherent(port->dev, port->fifosize,
 567                                   sg_virt(&priv->sg_rx),
 568                                   sg_dma_address(&priv->sg_rx));
 569
 570         return;
 571 }
 572
 573 static bool filter(struct dma_chan *chan, void *slave)
 574 {
 575         struct pch_dma_slave *param = slave;
 576
 577         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 578                                                   chan->device->dev)) {
 579                 chan->private = param;
 580                 return true;
 581         } else {
 582                 return false;
 583         }
 584 }
 585
 586 static void pch_request_dma(struct uart_port *port)
 587 {
 588         dma_cap_mask_t mask;
 589         struct dma_chan *chan;
 590         struct pci_dev *dma_dev;
 591         struct pch_dma_slave *param;
 592         struct eg20t_port *priv =
 593                                 container_of(port, struct eg20t_port, port);
 594         dma_cap_zero(mask);
 595         dma_cap_set(DMA_SLAVE, mask);
 596
 597         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 598                                                                 information */
 599         /* Set Tx DMA */
 600         param = &priv->param_tx;
 601         param->dma_dev = &dma_dev->dev;
 602         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 603
 604         param->tx_reg = port->mapbase + UART_TX;
 605         chan = dma_request_channel(mask, filter, param);
 606         if (!chan) {
 607                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 608                         __func__);
 609                 return;
 610         }
 611         priv->chan_tx = chan;
 612
 613         /* Set Rx DMA */
 614         param = &priv->param_rx;
 615         param->dma_dev = &dma_dev->dev;
 616         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 617
 618         param->rx_reg = port->mapbase + UART_RX;
 619         chan = dma_request_channel(mask, filter, param);
 620         if (!chan) {
 621                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 622                         __func__);
 623                 dma_release_channel(priv->chan_tx);
 624                 return;
 625         }
 626
 627         /* Get Consistent memory for DMA */
 628         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 629                                     &priv->rx_buf_dma, GFP_KERNEL);
 630         priv->chan_rx = chan;
 631 }
 632
 633 static void pch_dma_rx_complete(void *arg)
 634 {
 635         struct eg20t_port *priv = arg;
 636         struct uart_port *port = &priv->port;
 637         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 638         int count;
 639
 640         if (!tty) {
 641                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 642                 return;
 643         }
 644
 645         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 646         count = dma_push_rx(priv, priv->trigger_level);
 647         if (count)
 648                 tty_flip_buffer_push(tty);
 649         tty_kref_put(tty);
 650         async_tx_ack(priv->desc_rx);
 651         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
 652 }
 653
 654 static void pch_dma_tx_complete(void *arg)
 655 {
 656         struct eg20t_port *priv = arg;
 657         struct uart_port *port = &priv->port;
 658         struct circ_buf *xmit = &port->state->xmit;
 659         struct scatterlist *sg = priv->sg_tx_p;
 660         int i;
 661
 662         for (i = 0; i < priv->nent; i++, sg++) {
 663                 xmit->tail += sg_dma_len(sg);
 664                 port->icount.tx += sg_dma_len(sg);
 665         }
 666         xmit->tail &= UART_XMIT_SIZE - 1;
 667         async_tx_ack(priv->desc_tx);
 668         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 669         priv->tx_dma_use = 0;
 670         priv->nent = 0;
 671         kfree(priv->sg_tx_p);
 672         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 673 }
 674
 675 static int pop_tx(struct eg20t_port *priv, int size)
 676 {
 677         int count = 0;
 678         struct uart_port *port = &priv->port;
 679         struct circ_buf *xmit = &port->state->xmit;
 680
 681         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 682                 goto pop_tx_end;
 683
 684         do {
 685                 int cnt_to_end =
 686                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 687                 int sz = min(size - count, cnt_to_end);
 688                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 689                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 690                 count += sz;
 691         } while (!uart_circ_empty(xmit) && count < size);
 692
 693 pop_tx_end:
 694         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 695                  count, size - count, jiffies);
 696
 697         return count;
 698 }
 699
 700 static int handle_rx_to(struct eg20t_port *priv)
 701 {
 702         struct pch_uart_buffer *buf;
 703         int rx_size;
 704         int ret;
 705         if (!priv->start_rx) {
 706                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 707                 return 0;
 708         }
 709         buf = &priv->rxbuf;
 710         do {
 711                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 712                 ret = push_rx(priv, buf->buf, rx_size);
 713                 if (ret)
 714                         return 0;
 715         } while (rx_size == buf->size);
 716
 717         return PCH_UART_HANDLED_RX_INT;
 718 }
 719
 720 static int handle_rx(struct eg20t_port *priv)
 721 {
 722         return handle_rx_to(priv);
 723 }
 724
 725 static int dma_handle_rx(struct eg20t_port *priv)
 726 {
 727         struct uart_port *port = &priv->port;
 728         struct dma_async_tx_descriptor *desc;
 729         struct scatterlist *sg;
 730
 731         priv = container_of(port, struct eg20t_port, port);
 732         sg = &priv->sg_rx;
 733
 734         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 735
 736         sg_dma_len(sg) = priv->trigger_level;
 737
 738         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 739                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 740                      ~PAGE_MASK);
 741
 742         sg_dma_address(sg) = priv->rx_buf_dma;
 743
 744         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 745                         sg, 1, DMA_FROM_DEVICE,
 746                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 747
 748         if (!desc)
 749                 return 0;
 750
 751         priv->desc_rx = desc;
 752         desc->callback = pch_dma_rx_complete;
 753         desc->callback_param = priv;
 754         desc->tx_submit(desc);
 755         dma_async_issue_pending(priv->chan_rx);
 756
 757         return PCH_UART_HANDLED_RX_INT;
 758 }
 759
 760 static unsigned int handle_tx(struct eg20t_port *priv)
 761 {
 762         struct uart_port *port = &priv->port;
 763         struct circ_buf *xmit = &port->state->xmit;
 764         int fifo_size;
 765         int tx_size;
 766         int size;
 767         int tx_empty;
 768
 769         if (!priv->start_tx) {
 770                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 771                         __func__, jiffies);
 772                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 773                 priv->tx_empty = 1;
 774                 return 0;
 775         }
 776
 777         fifo_size = max(priv->fifo_size, 1);
 778         tx_empty = 1;
 779         if (pop_tx_x(priv, xmit->buf)) {
 780                 pch_uart_hal_write(priv, xmit->buf, 1);
 781                 port->icount.tx++;
 782                 tx_empty = 0;
 783                 fifo_size--;
 784         }
 785         size = min(xmit->head - xmit->tail, fifo_size);
 786         if (size < 0)
 787                 size = fifo_size;
 788
 789         tx_size = pop_tx(priv, size);
 790         if (tx_size > 0) {
 791                 port->icount.tx += tx_size;
 792                 tx_empty = 0;
 793         }
 794
 795         priv->tx_empty = tx_empty;
 796
 797         if (tx_empty) {
 798                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 799                 uart_write_wakeup(port);
 800         }
 801
 802         return PCH_UART_HANDLED_TX_INT;
 803 }
 804
 805 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 806 {
 807         struct uart_port *port = &priv->port;
 808         struct circ_buf *xmit = &port->state->xmit;
 809         struct scatterlist *sg;
 810         int nent;
 811         int fifo_size;
 812         int tx_empty;
 813         struct dma_async_tx_descriptor *desc;
 814         int num;
 815         int i;
 816         int bytes;
 817         int size;
 818         int rem;
 819
 820         if (!priv->start_tx) {
 821                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 822                         __func__, jiffies);
 823                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 824                 priv->tx_empty = 1;
 825                 return 0;
 826         }
 827
 828         if (priv->tx_dma_use) {
 829                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 830                         __func__, jiffies);
 831                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 832                 priv->tx_empty = 1;
 833                 return 0;
 834         }
 835
 836         fifo_size = max(priv->fifo_size, 1);
 837         tx_empty = 1;
 838         if (pop_tx_x(priv, xmit->buf)) {
 839                 pch_uart_hal_write(priv, xmit->buf, 1);
 840                 port->icount.tx++;
 841                 tx_empty = 0;
 842                 fifo_size--;
 843         }
 844
 845         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 846                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 847                              xmit->tail, UART_XMIT_SIZE));
 848         if (!bytes) {
 849                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 850                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 851                 uart_write_wakeup(port);
 852                 return 0;
 853         }
 854
 855         if (bytes > fifo_size) {
 856                 num = bytes / fifo_size + 1;
 857                 size = fifo_size;
 858                 rem = bytes % fifo_size;
 859         } else {
 860                 num = 1;
 861                 size = bytes;
 862                 rem = bytes;
 863         }
 864
 865         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 866                 __func__, num, size, rem);
 867
 868         priv->tx_dma_use = 1;
 869
 870         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 871
 872         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 873         sg = priv->sg_tx_p;
 874
 875         for (i = 0; i < num; i++, sg++) {
 876                 if (i == (num - 1))
 877                         sg_set_page(sg, virt_to_page(xmit->buf),
 878                                     rem, fifo_size * i);
 879                 else
 880                         sg_set_page(sg, virt_to_page(xmit->buf),
 881                                     size, fifo_size * i);
 882         }
 883
 884         sg = priv->sg_tx_p;
 885         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 886         if (!nent) {
 887                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 888                 return 0;
 889         }
 890         priv->nent = nent;
 891
 892         for (i = 0; i < nent; i++, sg++) {
 893                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 894                               fifo_size * i;
 895                 sg_dma_address(sg) = (sg_dma_address(sg) &
 896                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 897                 if (i == (nent - 1))
 898                         sg_dma_len(sg) = rem;
 899                 else
 900                         sg_dma_len(sg) = size;
 901         }
 902
 903         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 904                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 905                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 906         if (!desc) {
 907                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
 908                         __func__);
 909                 return 0;
 910         }
 911         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 912         priv->desc_tx = desc;
 913         desc->callback = pch_dma_tx_complete;
 914         desc->callback_param = priv;
 915
 916         desc->tx_submit(desc);
 917
 918         dma_async_issue_pending(priv->chan_tx);
 919
 920         return PCH_UART_HANDLED_TX_INT;
 921 }
 922
 923 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 924 {
 925         u8 fcr = ioread8(priv->membase + UART_FCR);
 926
 927         /* Reset FIFO */
 928         fcr |= UART_FCR_CLEAR_RCVR;
 929         iowrite8(fcr, priv->membase + UART_FCR);
 930
 931         if (lsr & PCH_UART_LSR_ERR)
 932                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 933
 934         if (lsr & UART_LSR_FE)
 935                 dev_err(&priv->pdev->dev, "Framing Error\n");
 936
 937         if (lsr & UART_LSR_PE)
 938                 dev_err(&priv->pdev->dev, "Parity Error\n");
 939
 940         if (lsr & UART_LSR_OE)
 941                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 942 }
 943
 944 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 945 {
 946         struct eg20t_port *priv = dev_id;
 947         unsigned int handled;
 948         u8 lsr;
 949         int ret = 0;
 950         unsigned int iid;
 951         unsigned long flags;
 952
 953         spin_lock_irqsave(&priv->port.lock, flags);
 954         handled = 0;
 955         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 956                 switch (iid) {
 957                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 958                         lsr = pch_uart_hal_get_line_status(priv);
 959                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 960                                                 UART_LSR_PE | UART_LSR_OE)) {
 961                                 pch_uart_err_ir(priv, lsr);
 962                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 963                         }
 964                         break;
 965                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 966                         if (priv->use_dma) {
 967                                 pch_uart_hal_disable_interrupt(priv,
 968                                                         PCH_UART_HAL_RX_INT);
 969                                 ret = dma_handle_rx(priv);
 970                                 if (!ret)
 971                                         pch_uart_hal_enable_interrupt(priv,
 972                                                         PCH_UART_HAL_RX_INT);
 973                         } else {
 974                                 ret = handle_rx(priv);
 975                         }
 976                         break;
 977                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 978                                                    (FIFO Timeout) */
 979                         ret = handle_rx_to(priv);
 980                         break;
 981                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
 982                                                    Empty */
 983                         if (priv->use_dma)
 984                                 ret = dma_handle_tx(priv);
 985                         else
 986                                 ret = handle_tx(priv);
 987                         break;
 988                 case PCH_UART_IID_MS:   /* Modem Status */
 989                         ret = PCH_UART_HANDLED_MS_INT;
 990                         break;
 991                 default:        /* Never junp to this label */
 992                         dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
 993                                 iid, jiffies);
 994                         ret = -1;
 995                         break;
 996                 }
 997                 handled |= (unsigned int)ret;
 998         }
 999         if (handled == 0 && iid <= 1) {
1000                 if (priv->int_dis_flag)
1001                         priv->int_dis_flag = 0;
1002         }
1003
1004         spin_unlock_irqrestore(&priv->port.lock, flags);
1005         return IRQ_RETVAL(handled);
1006 }
1007
1008 /* This function tests whether the transmitter fifo and shifter for the port
1009                                                 described by 'port' is empty. */
1010 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1011 {
1012         struct eg20t_port *priv;
1013         int ret;
1014         priv = container_of(port, struct eg20t_port, port);
1015         if (priv->tx_empty)
1016                 ret = TIOCSER_TEMT;
1017         else
1018                 ret = 0;
1019
1020         return ret;
1021 }
1022
1023 /* Returns the current state of modem control inputs. */
1024 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1025 {
1026         struct eg20t_port *priv;
1027         u8 modem;
1028         unsigned int ret = 0;
1029
1030         priv = container_of(port, struct eg20t_port, port);
1031         modem = pch_uart_hal_get_modem(priv);
1032
1033         if (modem & UART_MSR_DCD)
1034                 ret |= TIOCM_CAR;
1035
1036         if (modem & UART_MSR_RI)
1037                 ret |= TIOCM_RNG;
1038
1039         if (modem & UART_MSR_DSR)
1040                 ret |= TIOCM_DSR;
1041
1042         if (modem & UART_MSR_CTS)
1043                 ret |= TIOCM_CTS;
1044
1045         return ret;
1046 }
1047
1048 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1049 {
1050         u32 mcr = 0;
1051         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1052
1053         if (mctrl & TIOCM_DTR)
1054                 mcr |= UART_MCR_DTR;
1055         if (mctrl & TIOCM_RTS)
1056                 mcr |= UART_MCR_RTS;
1057         if (mctrl & TIOCM_LOOP)
1058                 mcr |= UART_MCR_LOOP;
1059
1060         if (priv->mcr & UART_MCR_AFE)
1061                 mcr |= UART_MCR_AFE;
1062
1063         if (mctrl)
1064                 iowrite8(mcr, priv->membase + UART_MCR);
1065 }
1066
1067 static void pch_uart_stop_tx(struct uart_port *port)
1068 {
1069         struct eg20t_port *priv;
1070         priv = container_of(port, struct eg20t_port, port);
1071         priv->start_tx = 0;
1072         priv->tx_dma_use = 0;
1073 }
1074
1075 static void pch_uart_start_tx(struct uart_port *port)
1076 {
1077         struct eg20t_port *priv;
1078
1079         priv = container_of(port, struct eg20t_port, port);
1080
1081         if (priv->use_dma) {
1082                 if (priv->tx_dma_use) {
1083                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1084                                 __func__);
1085                         return;
1086                 }
1087         }
1088
1089         priv->start_tx = 1;
1090         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1091 }
1092
1093 static void pch_uart_stop_rx(struct uart_port *port)
1094 {
1095         struct eg20t_port *priv;
1096         priv = container_of(port, struct eg20t_port, port);
1097         priv->start_rx = 0;
1098         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1099         priv->int_dis_flag = 1;
1100 }
1101
1102 /* Enable the modem status interrupts. */
1103 static void pch_uart_enable_ms(struct uart_port *port)
1104 {
1105         struct eg20t_port *priv;
1106         priv = container_of(port, struct eg20t_port, port);
1107         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1108 }
1109
1110 /* Control the transmission of a break signal. */
1111 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1112 {
1113         struct eg20t_port *priv;
1114         unsigned long flags;
1115
1116         priv = container_of(port, struct eg20t_port, port);
1117         spin_lock_irqsave(&port->lock, flags);
1118         pch_uart_hal_set_break(priv, ctl);
1119         spin_unlock_irqrestore(&port->lock, flags);
1120 }
1121
1122 /* Grab any interrupt resources and initialise any low level driver state. */
1123 static int pch_uart_startup(struct uart_port *port)
1124 {
1125         struct eg20t_port *priv;
1126         int ret;
1127         int fifo_size;
1128         int trigger_level;
1129
1130         priv = container_of(port, struct eg20t_port, port);
1131         priv->tx_empty = 1;
1132
1133         if (port->uartclk)
1134                 priv->base_baud = port->uartclk;
1135         else
1136                 port->uartclk = priv->base_baud;
1137
1138         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1139         ret = pch_uart_hal_set_line(priv, default_baud,
1140                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1141                               PCH_UART_HAL_STB1);
1142         if (ret)
1143                 return ret;
1144
1145         switch (priv->fifo_size) {
1146         case 256:
1147                 fifo_size = PCH_UART_HAL_FIFO256;
1148                 break;
1149         case 64:
1150                 fifo_size = PCH_UART_HAL_FIFO64;
1151                 break;
1152         case 16:
1153                 fifo_size = PCH_UART_HAL_FIFO16;
1154         case 1:
1155         default:
1156                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1157                 break;
1158         }
1159
1160         switch (priv->trigger) {
1161         case PCH_UART_HAL_TRIGGER1:
1162                 trigger_level = 1;
1163                 break;
1164         case PCH_UART_HAL_TRIGGER_L:
1165                 trigger_level = priv->fifo_size / 4;
1166                 break;
1167         case PCH_UART_HAL_TRIGGER_M:
1168                 trigger_level = priv->fifo_size / 2;
1169                 break;
1170         case PCH_UART_HAL_TRIGGER_H:
1171         default:
1172                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1173                 break;
1174         }
1175
1176         priv->trigger_level = trigger_level;
1177         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1178                                     fifo_size, priv->trigger);
1179         if (ret < 0)
1180                 return ret;
1181
1182         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1183                         KBUILD_MODNAME, priv);
1184         if (ret < 0)
1185                 return ret;
1186
1187         if (priv->use_dma)
1188                 pch_request_dma(port);
1189
1190         priv->start_rx = 1;
1191         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1192         uart_update_timeout(port, CS8, default_baud);
1193
1194         return 0;
1195 }
1196
1197 static void pch_uart_shutdown(struct uart_port *port)
1198 {
1199         struct eg20t_port *priv;
1200         int ret;
1201
1202         priv = container_of(port, struct eg20t_port, port);
1203         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1204         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1205         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1206                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1207         if (ret)
1208                 dev_err(priv->port.dev,
1209                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1210
1211         if (priv->use_dma_flag)
1212                 pch_free_dma(port);
1213
1214         free_irq(priv->port.irq, priv);
1215 }
1216
1217 /* Change the port parameters, including word length, parity, stop
1218  *bits.  Update read_status_mask and ignore_status_mask to indicate
1219  *the types of events we are interested in receiving.  */
1220 static void pch_uart_set_termios(struct uart_port *port,
1221                                  struct ktermios *termios, struct ktermios *old)
1222 {
1223         int baud;
1224         int rtn;
1225         unsigned int parity, bits, stb;
1226         struct eg20t_port *priv;
1227         unsigned long flags;
1228
1229         priv = container_of(port, struct eg20t_port, port);
1230         switch (termios->c_cflag & CSIZE) {
1231         case CS5:
1232                 bits = PCH_UART_HAL_5BIT;
1233                 break;
1234         case CS6:
1235                 bits = PCH_UART_HAL_6BIT;
1236                 break;
1237         case CS7:
1238                 bits = PCH_UART_HAL_7BIT;
1239                 break;
1240         default:                /* CS8 */
1241                 bits = PCH_UART_HAL_8BIT;
1242                 break;
1243         }
1244         if (termios->c_cflag & CSTOPB)
1245                 stb = PCH_UART_HAL_STB2;
1246         else
1247                 stb = PCH_UART_HAL_STB1;
1248
1249         if (termios->c_cflag & PARENB) {
1250                 if (!(termios->c_cflag & PARODD))
1251                         parity = PCH_UART_HAL_PARITY_ODD;
1252                 else
1253                         parity = PCH_UART_HAL_PARITY_EVEN;
1254
1255         } else {
1256                 parity = PCH_UART_HAL_PARITY_NONE;
1257         }
1258
1259         /* Only UART0 has auto hardware flow function */
1260         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1261                 priv->mcr |= UART_MCR_AFE;
1262         else
1263                 priv->mcr &= ~UART_MCR_AFE;
1264
1265         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1266
1267         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1268
1269         spin_lock_irqsave(&port->lock, flags);
1270
1271         uart_update_timeout(port, termios->c_cflag, baud);
1272         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1273         if (rtn)
1274                 goto out;
1275
1276         /* Don't rewrite B0 */
1277         if (tty_termios_baud_rate(termios))
1278                 tty_termios_encode_baud_rate(termios, baud, baud);
1279
1280 out:
1281         spin_unlock_irqrestore(&port->lock, flags);
1282 }
1283
1284 static const char *pch_uart_type(struct uart_port *port)
1285 {
1286         return KBUILD_MODNAME;
1287 }
1288
1289 static void pch_uart_release_port(struct uart_port *port)
1290 {
1291         struct eg20t_port *priv;
1292
1293         priv = container_of(port, struct eg20t_port, port);
1294         pci_iounmap(priv->pdev, priv->membase);
1295         pci_release_regions(priv->pdev);
1296 }
1297
1298 static int pch_uart_request_port(struct uart_port *port)
1299 {
1300         struct eg20t_port *priv;
1301         int ret;
1302         void __iomem *membase;
1303
1304         priv = container_of(port, struct eg20t_port, port);
1305         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1306         if (ret < 0)
1307                 return -EBUSY;
1308
1309         membase = pci_iomap(priv->pdev, 1, 0);
1310         if (!membase) {
1311                 pci_release_regions(priv->pdev);
1312                 return -EBUSY;
1313         }
1314         priv->membase = port->membase = membase;
1315
1316         return 0;
1317 }
1318
1319 static void pch_uart_config_port(struct uart_port *port, int type)
1320 {
1321         struct eg20t_port *priv;
1322
1323         priv = container_of(port, struct eg20t_port, port);
1324         if (type & UART_CONFIG_TYPE) {
1325                 port->type = priv->port_type;
1326                 pch_uart_request_port(port);
1327         }
1328 }
1329
1330 static int pch_uart_verify_port(struct uart_port *port,
1331                                 struct serial_struct *serinfo)
1332 {
1333         struct eg20t_port *priv;
1334
1335         priv = container_of(port, struct eg20t_port, port);
1336         if (serinfo->flags & UPF_LOW_LATENCY) {
1337                 dev_info(priv->port.dev,
1338                         "PCH UART : Use PIO Mode (without DMA)\n");
1339                 priv->use_dma = 0;
1340                 serinfo->flags &= ~UPF_LOW_LATENCY;
1341         } else {
1342 #ifndef CONFIG_PCH_DMA
1343                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1344                         __func__);
1345                 return -EOPNOTSUPP;
1346 #endif
1347                 priv->use_dma = 1;
1348                 priv->use_dma_flag = 1;
1349                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1350         }
1351
1352         return 0;
1353 }
1354
1355 static struct uart_ops pch_uart_ops = {
1356         .tx_empty = pch_uart_tx_empty,
1357         .set_mctrl = pch_uart_set_mctrl,
1358         .get_mctrl = pch_uart_get_mctrl,
1359         .stop_tx = pch_uart_stop_tx,
1360         .start_tx = pch_uart_start_tx,
1361         .stop_rx = pch_uart_stop_rx,
1362         .enable_ms = pch_uart_enable_ms,
1363         .break_ctl = pch_uart_break_ctl,
1364         .startup = pch_uart_startup,
1365         .shutdown = pch_uart_shutdown,
1366         .set_termios = pch_uart_set_termios,
1367 /*      .pm             = pch_uart_pm,          Not supported yet */
1368 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1369         .type = pch_uart_type,
1370         .release_port = pch_uart_release_port,
1371         .request_port = pch_uart_request_port,
1372         .config_port = pch_uart_config_port,
1373         .verify_port = pch_uart_verify_port
1374 };
1375
1376 static struct uart_driver pch_uart_driver = {
1377         .owner = THIS_MODULE,
1378         .driver_name = KBUILD_MODNAME,
1379         .dev_name = PCH_UART_DRIVER_DEVICE,
1380         .major = 0,
1381         .minor = 0,
1382         .nr = PCH_UART_NR,
1383 };
1384
1385 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1386                                              const struct pci_device_id *id)
1387 {
1388         struct eg20t_port *priv;
1389         int ret;
1390         unsigned int iobase;
1391         unsigned int mapbase;
1392         unsigned char *rxbuf;
1393         int fifosize, base_baud;
1394         int port_type;
1395         struct pch_uart_driver_data *board;
1396
1397         board = &drv_dat[id->driver_data];
1398         port_type = board->port_type;
1399
1400         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1401         if (priv == NULL)
1402                 goto init_port_alloc_err;
1403
1404         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1405         if (!rxbuf)
1406                 goto init_port_free_txbuf;
1407
1408         base_baud = 1843200; /* 1.8432MHz */
1409
1410         /* quirk for CM-iTC board */
1411         if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
1412                 base_baud = 192000000; /* 192.0MHz */
1413
1414         switch (port_type) {
1415         case PORT_UNKNOWN:
1416                 fifosize = 256; /* EG20T/ML7213: UART0 */
1417                 break;
1418         case PORT_8250:
1419                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1420                 break;
1421         default:
1422                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1423                 goto init_port_hal_free;
1424         }
1425
1426         iobase = pci_resource_start(pdev, 0);
1427         mapbase = pci_resource_start(pdev, 1);
1428         priv->mapbase = mapbase;
1429         priv->iobase = iobase;
1430         priv->pdev = pdev;
1431         priv->tx_empty = 1;
1432         priv->rxbuf.buf = rxbuf;
1433         priv->rxbuf.size = PAGE_SIZE;
1434
1435         priv->fifo_size = fifosize;
1436         priv->base_baud = base_baud;
1437         priv->port_type = PORT_MAX_8250 + port_type + 1;
1438         priv->port.dev = &pdev->dev;
1439         priv->port.iobase = iobase;
1440         priv->port.membase = NULL;
1441         priv->port.mapbase = mapbase;
1442         priv->port.irq = pdev->irq;
1443         priv->port.iotype = UPIO_PORT;
1444         priv->port.ops = &pch_uart_ops;
1445         priv->port.flags = UPF_BOOT_AUTOCONF;
1446         priv->port.fifosize = fifosize;
1447         priv->port.line = board->line_no;
1448         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1449
1450         spin_lock_init(&priv->port.lock);
1451
1452         pci_set_drvdata(pdev, priv);
1453         pch_uart_hal_request(pdev, fifosize, base_baud);
1454
1455         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1456         if (ret < 0)
1457                 goto init_port_hal_free;
1458
1459         return priv;
1460
1461 init_port_hal_free:
1462         free_page((unsigned long)rxbuf);
1463 init_port_free_txbuf:
1464         kfree(priv);
1465 init_port_alloc_err:
1466
1467         return NULL;
1468 }
1469
1470 static void pch_uart_exit_port(struct eg20t_port *priv)
1471 {
1472         uart_remove_one_port(&pch_uart_driver, &priv->port);
1473         pci_set_drvdata(priv->pdev, NULL);
1474         free_page((unsigned long)priv->rxbuf.buf);
1475 }
1476
1477 static void pch_uart_pci_remove(struct pci_dev *pdev)
1478 {
1479         struct eg20t_port *priv;
1480
1481         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1482         pch_uart_exit_port(priv);
1483         pci_disable_device(pdev);
1484         kfree(priv);
1485         return;
1486 }
1487 #ifdef CONFIG_PM
1488 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1489 {
1490         struct eg20t_port *priv = pci_get_drvdata(pdev);
1491
1492         uart_suspend_port(&pch_uart_driver, &priv->port);
1493
1494         pci_save_state(pdev);
1495         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1496         return 0;
1497 }
1498
1499 static int pch_uart_pci_resume(struct pci_dev *pdev)
1500 {
1501         struct eg20t_port *priv = pci_get_drvdata(pdev);
1502         int ret;
1503
1504         pci_set_power_state(pdev, PCI_D0);
1505         pci_restore_state(pdev);
1506
1507         ret = pci_enable_device(pdev);
1508         if (ret) {
1509                 dev_err(&pdev->dev,
1510                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1511                 return ret;
1512         }
1513
1514         uart_resume_port(&pch_uart_driver, &priv->port);
1515
1516         return 0;
1517 }
1518 #else
1519 #define pch_uart_pci_suspend NULL
1520 #define pch_uart_pci_resume NULL
1521 #endif
1522
1523 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1524         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1525          .driver_data = pch_et20t_uart0},
1526         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1527          .driver_data = pch_et20t_uart1},
1528         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1529          .driver_data = pch_et20t_uart2},
1530         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1531          .driver_data = pch_et20t_uart3},
1532         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1533          .driver_data = pch_ml7213_uart0},
1534         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1535          .driver_data = pch_ml7213_uart1},
1536         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1537          .driver_data = pch_ml7213_uart2},
1538         {0,},
1539 };
1540
1541 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1542                                         const struct pci_device_id *id)
1543 {
1544         int ret;
1545         struct eg20t_port *priv;
1546
1547         ret = pci_enable_device(pdev);
1548         if (ret < 0)
1549                 goto probe_error;
1550
1551         priv = pch_uart_init_port(pdev, id);
1552         if (!priv) {
1553                 ret = -EBUSY;
1554                 goto probe_disable_device;
1555         }
1556         pci_set_drvdata(pdev, priv);
1557
1558         return ret;
1559
1560 probe_disable_device:
1561         pci_disable_device(pdev);
1562 probe_error:
1563         return ret;
1564 }
1565
1566 static struct pci_driver pch_uart_pci_driver = {
1567         .name = "pch_uart",
1568         .id_table = pch_uart_pci_id,
1569         .probe = pch_uart_pci_probe,
1570         .remove = __devexit_p(pch_uart_pci_remove),
1571         .suspend = pch_uart_pci_suspend,
1572         .resume = pch_uart_pci_resume,
1573 };
1574
1575 static int __init pch_uart_module_init(void)
1576 {
1577         int ret;
1578
1579         /* register as UART driver */
1580         ret = uart_register_driver(&pch_uart_driver);
1581         if (ret < 0)
1582                 return ret;
1583
1584         /* register as PCI driver */
1585         ret = pci_register_driver(&pch_uart_pci_driver);
1586         if (ret < 0)
1587                 uart_unregister_driver(&pch_uart_driver);
1588
1589         return ret;
1590 }
1591 module_init(pch_uart_module_init);
1592
1593 static void __exit pch_uart_module_exit(void)
1594 {
1595         pci_unregister_driver(&pch_uart_pci_driver);
1596         uart_unregister_driver(&pch_uart_driver);
1597 }
1598 module_exit(pch_uart_module_exit);
1599
1600 MODULE_LICENSE("GPL v2");
1601 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1602 module_param(default_baud, uint, S_IRUGO);