drivers/usb/gadget/pch_udc.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  */
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/errno.h>
  14 #include <linux/list.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/usb/ch9.h>
  17 #include <linux/usb/gadget.h>
  18
  19 /* Address offset of Registers */
  20 #define UDC_EP_REG_SHIFT        0x20    /* Offset to next EP */
  21
  22 #define UDC_EPCTL_ADDR          0x00    /* Endpoint control */
  23 #define UDC_EPSTS_ADDR          0x04    /* Endpoint status */
  24 #define UDC_BUFIN_FRAMENUM_ADDR 0x08    /* buffer size in / frame number out */
  25 #define UDC_BUFOUT_MAXPKT_ADDR  0x0C    /* buffer size out / maxpkt in */
  26 #define UDC_SUBPTR_ADDR         0x10    /* setup buffer pointer */
  27 #define UDC_DESPTR_ADDR         0x14    /* Data descriptor pointer */
  28 #define UDC_CONFIRM_ADDR        0x18    /* Write/Read confirmation */
  29
  30 #define UDC_DEVCFG_ADDR         0x400   /* Device configuration */
  31 #define UDC_DEVCTL_ADDR         0x404   /* Device control */
  32 #define UDC_DEVSTS_ADDR         0x408   /* Device status */
  33 #define UDC_DEVIRQSTS_ADDR      0x40C   /* Device irq status */
  34 #define UDC_DEVIRQMSK_ADDR      0x410   /* Device irq mask */
  35 #define UDC_EPIRQSTS_ADDR       0x414   /* Endpoint irq status */
  36 #define UDC_EPIRQMSK_ADDR       0x418   /* Endpoint irq mask */
  37 #define UDC_DEVLPM_ADDR         0x41C   /* LPM control / status */
  38 #define UDC_CSR_BUSY_ADDR       0x4f0   /* UDC_CSR_BUSY Status register */
  39 #define UDC_SRST_ADDR           0x4fc   /* SOFT RESET register */
  40 #define UDC_CSR_ADDR            0x500   /* USB_DEVICE endpoint register */
  41
  42 /* Endpoint control register */
  43 /* Bit position */
  44 #define UDC_EPCTL_MRXFLUSH              (1 << 12)
  45 #define UDC_EPCTL_RRDY                  (1 << 9)
  46 #define UDC_EPCTL_CNAK                  (1 << 8)
  47 #define UDC_EPCTL_SNAK                  (1 << 7)
  48 #define UDC_EPCTL_NAK                   (1 << 6)
  49 #define UDC_EPCTL_P                     (1 << 3)
  50 #define UDC_EPCTL_F                     (1 << 1)
  51 #define UDC_EPCTL_S                     (1 << 0)
  52 #define UDC_EPCTL_ET_SHIFT              4
  53 /* Mask patern */
  54 #define UDC_EPCTL_ET_MASK               0x00000030
  55 /* Value for ET field */
  56 #define UDC_EPCTL_ET_CONTROL            0
  57 #define UDC_EPCTL_ET_ISO                1
  58 #define UDC_EPCTL_ET_BULK               2
  59 #define UDC_EPCTL_ET_INTERRUPT          3
  60
  61 /* Endpoint status register */
  62 /* Bit position */
  63 #define UDC_EPSTS_XFERDONE              (1 << 27)
  64 #define UDC_EPSTS_RSS                   (1 << 26)
  65 #define UDC_EPSTS_RCS                   (1 << 25)
  66 #define UDC_EPSTS_TXEMPTY               (1 << 24)
  67 #define UDC_EPSTS_TDC                   (1 << 10)
  68 #define UDC_EPSTS_HE                    (1 << 9)
  69 #define UDC_EPSTS_MRXFIFO_EMP           (1 << 8)
  70 #define UDC_EPSTS_BNA                   (1 << 7)
  71 #define UDC_EPSTS_IN                    (1 << 6)
  72 #define UDC_EPSTS_OUT_SHIFT             4
  73 /* Mask patern */
  74 #define UDC_EPSTS_OUT_MASK              0x00000030
  75 #define UDC_EPSTS_ALL_CLR_MASK          0x1F0006F0
  76 /* Value for OUT field */
  77 #define UDC_EPSTS_OUT_SETUP             2
  78 #define UDC_EPSTS_OUT_DATA              1
  79
  80 /* Device configuration register */
  81 /* Bit position */
  82 #define UDC_DEVCFG_CSR_PRG              (1 << 17)
  83 #define UDC_DEVCFG_SP                   (1 << 3)
  84 /* SPD Valee */
  85 #define UDC_DEVCFG_SPD_HS               0x0
  86 #define UDC_DEVCFG_SPD_FS               0x1
  87 #define UDC_DEVCFG_SPD_LS               0x2
  88
  89 /* Device control register */
  90 /* Bit position */
  91 #define UDC_DEVCTL_THLEN_SHIFT          24
  92 #define UDC_DEVCTL_BRLEN_SHIFT          16
  93 #define UDC_DEVCTL_CSR_DONE             (1 << 13)
  94 #define UDC_DEVCTL_SD                   (1 << 10)
  95 #define UDC_DEVCTL_MODE                 (1 << 9)
  96 #define UDC_DEVCTL_BREN                 (1 << 8)
  97 #define UDC_DEVCTL_THE                  (1 << 7)
  98 #define UDC_DEVCTL_DU                   (1 << 4)
  99 #define UDC_DEVCTL_TDE                  (1 << 3)
 100 #define UDC_DEVCTL_RDE                  (1 << 2)
 101 #define UDC_DEVCTL_RES                  (1 << 0)
 102
 103 /* Device status register */
 104 /* Bit position */
 105 #define UDC_DEVSTS_TS_SHIFT             18
 106 #define UDC_DEVSTS_ENUM_SPEED_SHIFT     13
 107 #define UDC_DEVSTS_ALT_SHIFT            8
 108 #define UDC_DEVSTS_INTF_SHIFT           4
 109 #define UDC_DEVSTS_CFG_SHIFT            0
 110 /* Mask patern */
 111 #define UDC_DEVSTS_TS_MASK              0xfffc0000
 112 #define UDC_DEVSTS_ENUM_SPEED_MASK      0x00006000
 113 #define UDC_DEVSTS_ALT_MASK             0x00000f00
 114 #define UDC_DEVSTS_INTF_MASK            0x000000f0
 115 #define UDC_DEVSTS_CFG_MASK             0x0000000f
 116 /* value for maximum speed for SPEED field */
 117 #define UDC_DEVSTS_ENUM_SPEED_FULL      1
 118 #define UDC_DEVSTS_ENUM_SPEED_HIGH      0
 119 #define UDC_DEVSTS_ENUM_SPEED_LOW       2
 120 #define UDC_DEVSTS_ENUM_SPEED_FULLX     3
 121
 122 /* Device irq register */
 123 /* Bit position */
 124 #define UDC_DEVINT_RWKP                 (1 << 7)
 125 #define UDC_DEVINT_ENUM                 (1 << 6)
 126 #define UDC_DEVINT_SOF                  (1 << 5)
 127 #define UDC_DEVINT_US                   (1 << 4)
 128 #define UDC_DEVINT_UR                   (1 << 3)
 129 #define UDC_DEVINT_ES                   (1 << 2)
 130 #define UDC_DEVINT_SI                   (1 << 1)
 131 #define UDC_DEVINT_SC                   (1 << 0)
 132 /* Mask patern */
 133 #define UDC_DEVINT_MSK                  0x7f
 134
 135 /* Endpoint irq register */
 136 /* Bit position */
 137 #define UDC_EPINT_IN_SHIFT              0
 138 #define UDC_EPINT_OUT_SHIFT             16
 139 #define UDC_EPINT_IN_EP0                (1 << 0)
 140 #define UDC_EPINT_OUT_EP0               (1 << 16)
 141 /* Mask patern */
 142 #define UDC_EPINT_MSK_DISABLE_ALL       0xffffffff
 143
 144 /* UDC_CSR_BUSY Status register */
 145 /* Bit position */
 146 #define UDC_CSR_BUSY                    (1 << 0)
 147
 148 /* SOFT RESET register */
 149 /* Bit position */
 150 #define UDC_PSRST                       (1 << 1)
 151 #define UDC_SRST                        (1 << 0)
 152
 153 /* USB_DEVICE endpoint register */
 154 /* Bit position */
 155 #define UDC_CSR_NE_NUM_SHIFT            0
 156 #define UDC_CSR_NE_DIR_SHIFT            4
 157 #define UDC_CSR_NE_TYPE_SHIFT           5
 158 #define UDC_CSR_NE_CFG_SHIFT            7
 159 #define UDC_CSR_NE_INTF_SHIFT           11
 160 #define UDC_CSR_NE_ALT_SHIFT            15
 161 #define UDC_CSR_NE_MAX_PKT_SHIFT        19
 162 /* Mask patern */
 163 #define UDC_CSR_NE_NUM_MASK             0x0000000f
 164 #define UDC_CSR_NE_DIR_MASK             0x00000010
 165 #define UDC_CSR_NE_TYPE_MASK            0x00000060
 166 #define UDC_CSR_NE_CFG_MASK             0x00000780
 167 #define UDC_CSR_NE_INTF_MASK            0x00007800
 168 #define UDC_CSR_NE_ALT_MASK             0x00078000
 169 #define UDC_CSR_NE_MAX_PKT_MASK         0x3ff80000
 170
 171 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
 172 #define PCH_UDC_EPINT(in, num)\
 173                 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
 174
 175 /* Index of endpoint */
 176 #define UDC_EP0IN_IDX           0
 177 #define UDC_EP0OUT_IDX          1
 178 #define UDC_EPIN_IDX(ep)        (ep * 2)
 179 #define UDC_EPOUT_IDX(ep)       (ep * 2 + 1)
 180 #define PCH_UDC_EP0             0
 181 #define PCH_UDC_EP1             1
 182 #define PCH_UDC_EP2             2
 183 #define PCH_UDC_EP3             3
 184
 185 /* Number of endpoint */
 186 #define PCH_UDC_EP_NUM          32      /* Total number of EPs (16 IN,16 OUT) */
 187 #define PCH_UDC_USED_EP_NUM     4       /* EP number of EP's really used */
 188 /* Length Value */
 189 #define PCH_UDC_BRLEN           0x0F    /* Burst length */
 190 #define PCH_UDC_THLEN           0x1F    /* Threshold length */
 191 /* Value of EP Buffer Size */
 192 #define UDC_EP0IN_BUFF_SIZE     16
 193 #define UDC_EPIN_BUFF_SIZE      256
 194 #define UDC_EP0OUT_BUFF_SIZE    16
 195 #define UDC_EPOUT_BUFF_SIZE     256
 196 /* Value of EP maximum packet size */
 197 #define UDC_EP0IN_MAX_PKT_SIZE  64
 198 #define UDC_EP0OUT_MAX_PKT_SIZE 64
 199 #define UDC_BULK_MAX_PKT_SIZE   512
 200
 201 /* DMA */
 202 #define DMA_DIR_RX              1       /* DMA for data receive */
 203 #define DMA_DIR_TX              2       /* DMA for data transmit */
 204 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
 205 #define UDC_DMA_MAXPACKET       65536   /* maximum packet size for DMA */
 206
 207 /**
 208  * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
 209  *                                for data
 210  * @status:             Status quadlet
 211  * @reserved:           Reserved
 212  * @dataptr:            Buffer descriptor
 213  * @next:               Next descriptor
 214  */
 215 struct pch_udc_data_dma_desc {
 216         u32 status;
 217         u32 reserved;
 218         u32 dataptr;
 219         u32 next;
 220 };
 221
 222 /**
 223  * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
 224  *                               for control data
 225  * @status:     Status
 226  * @reserved:   Reserved
 227  * @data12:     First setup word
 228  * @data34:     Second setup word
 229  */
 230 struct pch_udc_stp_dma_desc {
 231         u32 status;
 232         u32 reserved;
 233         struct usb_ctrlrequest request;
 234 } __attribute((packed));
 235
 236 /* DMA status definitions */
 237 /* Buffer status */
 238 #define PCH_UDC_BUFF_STS        0xC0000000
 239 #define PCH_UDC_BS_HST_RDY      0x00000000
 240 #define PCH_UDC_BS_DMA_BSY      0x40000000
 241 #define PCH_UDC_BS_DMA_DONE     0x80000000
 242 #define PCH_UDC_BS_HST_BSY      0xC0000000
 243 /*  Rx/Tx Status */
 244 #define PCH_UDC_RXTX_STS        0x30000000
 245 #define PCH_UDC_RTS_SUCC        0x00000000
 246 #define PCH_UDC_RTS_DESERR      0x10000000
 247 #define PCH_UDC_RTS_BUFERR      0x30000000
 248 /* Last Descriptor Indication */
 249 #define PCH_UDC_DMA_LAST        0x08000000
 250 /* Number of Rx/Tx Bytes Mask */
 251 #define PCH_UDC_RXTX_BYTES      0x0000ffff
 252
 253 /**
 254  * struct pch_udc_cfg_data - Structure to hold current configuration
 255  *                           and interface information
 256  * @cur_cfg:    current configuration in use
 257  * @cur_intf:   current interface in use
 258  * @cur_alt:    current alt interface in use
 259  */
 260 struct pch_udc_cfg_data {
 261         u16 cur_cfg;
 262         u16 cur_intf;
 263         u16 cur_alt;
 264 };
 265
 266 /**
 267  * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
 268  * @ep:                 embedded ep request
 269  * @td_stp_phys:        for setup request
 270  * @td_data_phys:       for data request
 271  * @td_stp:             for setup request
 272  * @td_data:            for data request
 273  * @dev:                reference to device struct
 274  * @offset_addr:        offset address of ep register
 275  * @desc:               for this ep
 276  * @queue:              queue for requests
 277  * @num:                endpoint number
 278  * @in:                 endpoint is IN
 279  * @halted:             endpoint halted?
 280  * @epsts:              Endpoint status
 281  */
 282 struct pch_udc_ep {
 283         struct usb_ep                   ep;
 284         dma_addr_t                      td_stp_phys;
 285         dma_addr_t                      td_data_phys;
 286         struct pch_udc_stp_dma_desc     *td_stp;
 287         struct pch_udc_data_dma_desc    *td_data;
 288         struct pch_udc_dev              *dev;
 289         unsigned long                   offset_addr;
 290         const struct usb_endpoint_descriptor    *desc;
 291         struct list_head                queue;
 292         unsigned                        num:5,
 293                                         in:1,
 294                                         halted:1;
 295         unsigned long                   epsts;
 296 };
 297
 298 /**
 299  * struct pch_udc_dev - Structure holding complete information
 300  *                      of the PCH USB device
 301  * @gadget:             gadget driver data
 302  * @driver:             reference to gadget driver bound
 303  * @pdev:               reference to the PCI device
 304  * @ep:                 array of endpoints
 305  * @lock:               protects all state
 306  * @active:             enabled the PCI device
 307  * @stall:              stall requested
 308  * @prot_stall:         protcol stall requested
 309  * @irq_registered:     irq registered with system
 310  * @mem_region:         device memory mapped
 311  * @registered:         driver regsitered with system
 312  * @suspended:          driver in suspended state
 313  * @connected:          gadget driver associated
 314  * @vbus_session:       required vbus_session state
 315  * @set_cfg_not_acked:  pending acknowledgement 4 setup
 316  * @waiting_zlp_ack:    pending acknowledgement 4 ZLP
 317  * @data_requests:      DMA pool for data requests
 318  * @stp_requests:       DMA pool for setup requests
 319  * @dma_addr:           DMA pool for received
 320  * @ep0out_buf:         Buffer for DMA
 321  * @setup_data:         Received setup data
 322  * @phys_addr:          of device memory
 323  * @base_addr:          for mapped device memory
 324  * @irq:                IRQ line for the device
 325  * @cfg_data:           current cfg, intf, and alt in use
 326  */
 327 struct pch_udc_dev {
 328         struct usb_gadget               gadget;
 329         struct usb_gadget_driver        *driver;
 330         struct pci_dev                  *pdev;
 331         struct pch_udc_ep               ep[PCH_UDC_EP_NUM];
 332         spinlock_t                      lock; /* protects all state */
 333         unsigned        active:1,
 334                         stall:1,
 335                         prot_stall:1,
 336                         irq_registered:1,
 337                         mem_region:1,
 338                         registered:1,
 339                         suspended:1,
 340                         connected:1,
 341                         vbus_session:1,
 342                         set_cfg_not_acked:1,
 343                         waiting_zlp_ack:1;
 344         struct pci_pool         *data_requests;
 345         struct pci_pool         *stp_requests;
 346         dma_addr_t                      dma_addr;
 347         void                            *ep0out_buf;
 348         struct usb_ctrlrequest          setup_data;
 349         unsigned long                   phys_addr;
 350         void __iomem                    *base_addr;
 351         unsigned                        irq;
 352         struct pch_udc_cfg_data cfg_data;
 353 };
 354
 355 #define PCH_UDC_PCI_BAR                 1
 356 #define PCI_DEVICE_ID_INTEL_EG20T_UDC   0x8808
 357 #define PCI_VENDOR_ID_ROHM              0x10DB
 358 #define PCI_DEVICE_ID_ML7213_IOH_UDC    0x801D
 359 #define PCI_DEVICE_ID_ML7831_IOH_UDC    0x8808
 360
 361 static const char       ep0_string[] = "ep0in";
 362 static DEFINE_SPINLOCK(udc_stall_spinlock);     /* stall spin lock */
 363 struct pch_udc_dev *pch_udc;            /* pointer to device object */
 364 static int speed_fs;
 365 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
 366 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
 367
 368 /**
 369  * struct pch_udc_request - Structure holding a PCH USB device request packet
 370  * @req:                embedded ep request
 371  * @td_data_phys:       phys. address
 372  * @td_data:            first dma desc. of chain
 373  * @td_data_last:       last dma desc. of chain
 374  * @queue:              associated queue
 375  * @dma_going:          DMA in progress for request
 376  * @dma_mapped:         DMA memory mapped for request
 377  * @dma_done:           DMA completed for request
 378  * @chain_len:          chain length
 379  * @buf:                Buffer memory for align adjustment
 380  * @dma:                DMA memory for align adjustment
 381  */
 382 struct pch_udc_request {
 383         struct usb_request              req;
 384         dma_addr_t                      td_data_phys;
 385         struct pch_udc_data_dma_desc    *td_data;
 386         struct pch_udc_data_dma_desc    *td_data_last;
 387         struct list_head                queue;
 388         unsigned                        dma_going:1,
 389                                         dma_mapped:1,
 390                                         dma_done:1;
 391         unsigned                        chain_len;
 392         void                            *buf;
 393         dma_addr_t                      dma;
 394 };
 395
 396 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
 397 {
 398         return ioread32(dev->base_addr + reg);
 399 }
 400
 401 static inline void pch_udc_writel(struct pch_udc_dev *dev,
 402                                     unsigned long val, unsigned long reg)
 403 {
 404         iowrite32(val, dev->base_addr + reg);
 405 }
 406
 407 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
 408                                      unsigned long reg,
 409                                      unsigned long bitmask)
 410 {
 411         pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
 412 }
 413
 414 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
 415                                      unsigned long reg,
 416                                      unsigned long bitmask)
 417 {
 418         pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
 419 }
 420
 421 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
 422 {
 423         return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
 424 }
 425
 426 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
 427                                     unsigned long val, unsigned long reg)
 428 {
 429         iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
 430 }
 431
 432 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
 433                                      unsigned long reg,
 434                                      unsigned long bitmask)
 435 {
 436         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
 437 }
 438
 439 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
 440                                      unsigned long reg,
 441                                      unsigned long bitmask)
 442 {
 443         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
 444 }
 445
 446 /**
 447  * pch_udc_csr_busy() - Wait till idle.
 448  * @dev:        Reference to pch_udc_dev structure
 449  */
 450 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
 451 {
 452         unsigned int count = 200;
 453
 454         /* Wait till idle */
 455         while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
 456                 && --count)
 457                 cpu_relax();
 458         if (!count)
 459                 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
 460 }
 461
 462 /**
 463  * pch_udc_write_csr() - Write the command and status registers.
 464  * @dev:        Reference to pch_udc_dev structure
 465  * @val:        value to be written to CSR register
 466  * @addr:       address of CSR register
 467  */
 468 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
 469                                unsigned int ep)
 470 {
 471         unsigned long reg = PCH_UDC_CSR(ep);
 472
 473         pch_udc_csr_busy(dev);          /* Wait till idle */
 474         pch_udc_writel(dev, val, reg);
 475         pch_udc_csr_busy(dev);          /* Wait till idle */
 476 }
 477
 478 /**
 479  * pch_udc_read_csr() - Read the command and status registers.
 480  * @dev:        Reference to pch_udc_dev structure
 481  * @addr:       address of CSR register
 482  *
 483  * Return codes:        content of CSR register
 484  */
 485 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
 486 {
 487         unsigned long reg = PCH_UDC_CSR(ep);
 488
 489         pch_udc_csr_busy(dev);          /* Wait till idle */
 490         pch_udc_readl(dev, reg);        /* Dummy read */
 491         pch_udc_csr_busy(dev);          /* Wait till idle */
 492         return pch_udc_readl(dev, reg);
 493 }
 494
 495 /**
 496  * pch_udc_rmt_wakeup() - Initiate for remote wakeup
 497  * @dev:        Reference to pch_udc_dev structure
 498  */
 499 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
 500 {
 501         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 502         mdelay(1);
 503         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 504 }
 505
 506 /**
 507  * pch_udc_get_frame() - Get the current frame from device status register
 508  * @dev:        Reference to pch_udc_dev structure
 509  * Retern       current frame
 510  */
 511 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
 512 {
 513         u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 514         return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
 515 }
 516
 517 /**
 518  * pch_udc_clear_selfpowered() - Clear the self power control
 519  * @dev:        Reference to pch_udc_regs structure
 520  */
 521 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
 522 {
 523         pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 524 }
 525
 526 /**
 527  * pch_udc_set_selfpowered() - Set the self power control
 528  * @dev:        Reference to pch_udc_regs structure
 529  */
 530 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
 531 {
 532         pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 533 }
 534
 535 /**
 536  * pch_udc_set_disconnect() - Set the disconnect status.
 537  * @dev:        Reference to pch_udc_regs structure
 538  */
 539 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
 540 {
 541         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 542 }
 543
 544 /**
 545  * pch_udc_clear_disconnect() - Clear the disconnect status.
 546  * @dev:        Reference to pch_udc_regs structure
 547  */
 548 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
 549 {
 550         /* Clear the disconnect */
 551         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 552         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 553         mdelay(1);
 554         /* Resume USB signalling */
 555         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 556 }
 557
 558 /**
 559  * pch_udc_reconnect() - This API initializes usb device controller,
 560  *                                              and clear the disconnect status.
 561  * @dev:                Reference to pch_udc_regs structure
 562  */
 563 static void pch_udc_init(struct pch_udc_dev *dev);
 564 static void pch_udc_reconnect(struct pch_udc_dev *dev)
 565 {
 566         pch_udc_init(dev);
 567
 568         /* enable device interrupts */
 569         /* pch_udc_enable_interrupts() */
 570         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
 571                         UDC_DEVINT_UR | UDC_DEVINT_US |
 572                         UDC_DEVINT_ENUM |
 573                         UDC_DEVINT_SI | UDC_DEVINT_SC);
 574
 575         /* Clear the disconnect */
 576         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 577         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 578         mdelay(1);
 579         /* Resume USB signalling */
 580         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 581 }
 582
 583 /**
 584  * pch_udc_vbus_session() - set or clearr the disconnect status.
 585  * @dev:        Reference to pch_udc_regs structure
 586  * @is_active:  Parameter specifying the action
 587  *                0:   indicating VBUS power is ending
 588  *                !0:  indicating VBUS power is starting
 589  */
 590 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
 591                                           int is_active)
 592 {
 593         if (is_active) {
 594                 pch_udc_reconnect(dev);
 595                 dev->vbus_session = 1;
 596         } else {
 597                 if (dev->driver && dev->driver->disconnect) {
 598                         spin_unlock(&dev->lock);
 599                         dev->driver->disconnect(&dev->gadget);
 600                         spin_lock(&dev->lock);
 601                 }
 602                 pch_udc_set_disconnect(dev);
 603                 dev->vbus_session = 0;
 604         }
 605 }
 606
 607 /**
 608  * pch_udc_ep_set_stall() - Set the stall of endpoint
 609  * @ep:         Reference to structure of type pch_udc_ep_regs
 610  */
 611 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
 612 {
 613         if (ep->in) {
 614                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 615                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 616         } else {
 617                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 618         }
 619 }
 620
 621 /**
 622  * pch_udc_ep_clear_stall() - Clear the stall of endpoint
 623  * @ep:         Reference to structure of type pch_udc_ep_regs
 624  */
 625 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
 626 {
 627         /* Clear the stall */
 628         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 629         /* Clear NAK by writing CNAK */
 630         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 631 }
 632
 633 /**
 634  * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
 635  * @ep:         Reference to structure of type pch_udc_ep_regs
 636  * @type:       Type of endpoint
 637  */
 638 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
 639                                         u8 type)
 640 {
 641         pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
 642                                 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
 643 }
 644
 645 /**
 646  * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
 647  * @ep:         Reference to structure of type pch_udc_ep_regs
 648  * @buf_size:   The buffer word size
 649  */
 650 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
 651                                                  u32 buf_size, u32 ep_in)
 652 {
 653         u32 data;
 654         if (ep_in) {
 655                 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
 656                 data = (data & 0xffff0000) | (buf_size & 0xffff);
 657                 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
 658         } else {
 659                 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 660                 data = (buf_size << 16) | (data & 0xffff);
 661                 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 662         }
 663 }
 664
 665 /**
 666  * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
 667  * @ep:         Reference to structure of type pch_udc_ep_regs
 668  * @pkt_size:   The packet byte size
 669  */
 670 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
 671 {
 672         u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 673         data = (data & 0xffff0000) | (pkt_size & 0xffff);
 674         pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 675 }
 676
 677 /**
 678  * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
 679  * @ep:         Reference to structure of type pch_udc_ep_regs
 680  * @addr:       Address of the register
 681  */
 682 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
 683 {
 684         pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
 685 }
 686
 687 /**
 688  * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
 689  * @ep:         Reference to structure of type pch_udc_ep_regs
 690  * @addr:       Address of the register
 691  */
 692 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
 693 {
 694         pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
 695 }
 696
 697 /**
 698  * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
 699  * @ep:         Reference to structure of type pch_udc_ep_regs
 700  */
 701 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
 702 {
 703         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
 704 }
 705
 706 /**
 707  * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
 708  * @ep:         Reference to structure of type pch_udc_ep_regs
 709  */
 710 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
 711 {
 712         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 713 }
 714
 715 /**
 716  * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
 717  * @ep:         Reference to structure of type pch_udc_ep_regs
 718  */
 719 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
 720 {
 721         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 722 }
 723
 724 /**
 725  * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
 726  *                      register depending on the direction specified
 727  * @dev:        Reference to structure of type pch_udc_regs
 728  * @dir:        whether Tx or Rx
 729  *                DMA_DIR_RX: Receive
 730  *                DMA_DIR_TX: Transmit
 731  */
 732 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
 733 {
 734         if (dir == DMA_DIR_RX)
 735                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 736         else if (dir == DMA_DIR_TX)
 737                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 738 }
 739
 740 /**
 741  * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
 742  *                               register depending on the direction specified
 743  * @dev:        Reference to structure of type pch_udc_regs
 744  * @dir:        Whether Tx or Rx
 745  *                DMA_DIR_RX: Receive
 746  *                DMA_DIR_TX: Transmit
 747  */
 748 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
 749 {
 750         if (dir == DMA_DIR_RX)
 751                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 752         else if (dir == DMA_DIR_TX)
 753                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 754 }
 755
 756 /**
 757  * pch_udc_set_csr_done() - Set the device control register
 758  *                              CSR done field (bit 13)
 759  * @dev:        reference to structure of type pch_udc_regs
 760  */
 761 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
 762 {
 763         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
 764 }
 765
 766 /**
 767  * pch_udc_disable_interrupts() - Disables the specified interrupts
 768  * @dev:        Reference to structure of type pch_udc_regs
 769  * @mask:       Mask to disable interrupts
 770  */
 771 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
 772                                             u32 mask)
 773 {
 774         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
 775 }
 776
 777 /**
 778  * pch_udc_enable_interrupts() - Enable the specified interrupts
 779  * @dev:        Reference to structure of type pch_udc_regs
 780  * @mask:       Mask to enable interrupts
 781  */
 782 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
 783                                            u32 mask)
 784 {
 785         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
 786 }
 787
 788 /**
 789  * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
 790  * @dev:        Reference to structure of type pch_udc_regs
 791  * @mask:       Mask to disable interrupts
 792  */
 793 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
 794                                                 u32 mask)
 795 {
 796         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
 797 }
 798
 799 /**
 800  * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
 801  * @dev:        Reference to structure of type pch_udc_regs
 802  * @mask:       Mask to enable interrupts
 803  */
 804 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
 805                                               u32 mask)
 806 {
 807         pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
 808 }
 809
 810 /**
 811  * pch_udc_read_device_interrupts() - Read the device interrupts
 812  * @dev:        Reference to structure of type pch_udc_regs
 813  * Retern       The device interrupts
 814  */
 815 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
 816 {
 817         return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
 818 }
 819
 820 /**
 821  * pch_udc_write_device_interrupts() - Write device interrupts
 822  * @dev:        Reference to structure of type pch_udc_regs
 823  * @val:        The value to be written to interrupt register
 824  */
 825 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
 826                                                      u32 val)
 827 {
 828         pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
 829 }
 830
 831 /**
 832  * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
 833  * @dev:        Reference to structure of type pch_udc_regs
 834  * Retern       The endpoint interrupt
 835  */
 836 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
 837 {
 838         return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
 839 }
 840
 841 /**
 842  * pch_udc_write_ep_interrupts() - Clear endpoint interupts
 843  * @dev:        Reference to structure of type pch_udc_regs
 844  * @val:        The value to be written to interrupt register
 845  */
 846 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
 847                                              u32 val)
 848 {
 849         pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
 850 }
 851
 852 /**
 853  * pch_udc_read_device_status() - Read the device status
 854  * @dev:        Reference to structure of type pch_udc_regs
 855  * Retern       The device status
 856  */
 857 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
 858 {
 859         return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 860 }
 861
 862 /**
 863  * pch_udc_read_ep_control() - Read the endpoint control
 864  * @ep:         Reference to structure of type pch_udc_ep_regs
 865  * Retern       The endpoint control register value
 866  */
 867 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
 868 {
 869         return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
 870 }
 871
 872 /**
 873  * pch_udc_clear_ep_control() - Clear the endpoint control register
 874  * @ep:         Reference to structure of type pch_udc_ep_regs
 875  * Retern       The endpoint control register value
 876  */
 877 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
 878 {
 879         return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
 880 }
 881
 882 /**
 883  * pch_udc_read_ep_status() - Read the endpoint status
 884  * @ep:         Reference to structure of type pch_udc_ep_regs
 885  * Retern       The endpoint status
 886  */
 887 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
 888 {
 889         return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
 890 }
 891
 892 /**
 893  * pch_udc_clear_ep_status() - Clear the endpoint status
 894  * @ep:         Reference to structure of type pch_udc_ep_regs
 895  * @stat:       Endpoint status
 896  */
 897 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
 898                                          u32 stat)
 899 {
 900         return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
 901 }
 902
 903 /**
 904  * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
 905  *                              of the endpoint control register
 906  * @ep:         Reference to structure of type pch_udc_ep_regs
 907  */
 908 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
 909 {
 910         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
 911 }
 912
 913 /**
 914  * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
 915  *                              of the endpoint control register
 916  * @ep:         reference to structure of type pch_udc_ep_regs
 917  */
 918 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
 919 {
 920         unsigned int loopcnt = 0;
 921         struct pch_udc_dev *dev = ep->dev;
 922
 923         if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
 924                 return;
 925         if (!ep->in) {
 926                 loopcnt = 10000;
 927                 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
 928                         --loopcnt)
 929                         udelay(5);
 930                 if (!loopcnt)
 931                         dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
 932                                 __func__);
 933         }
 934         loopcnt = 10000;
 935         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
 936                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 937                 udelay(5);
 938         }
 939         if (!loopcnt)
 940                 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
 941                         __func__, ep->num, (ep->in ? "in" : "out"));
 942 }
 943
 944 /**
 945  * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
 946  * @ep: reference to structure of type pch_udc_ep_regs
 947  * @dir:        direction of endpoint
 948  *                0:  endpoint is OUT
 949  *                !0: endpoint is IN
 950  */
 951 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
 952 {
 953         if (dir) {      /* IN ep */
 954                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 955                 return;
 956         }
 957 }
 958
 959 /**
 960  * pch_udc_ep_enable() - This api enables endpoint
 961  * @regs:       Reference to structure pch_udc_ep_regs
 962  * @desc:       endpoint descriptor
 963  */
 964 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
 965                                struct pch_udc_cfg_data *cfg,
 966                                const struct usb_endpoint_descriptor *desc)
 967 {
 968         u32 val = 0;
 969         u32 buff_size = 0;
 970
 971         pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
 972         if (ep->in)
 973                 buff_size = UDC_EPIN_BUFF_SIZE;
 974         else
 975                 buff_size = UDC_EPOUT_BUFF_SIZE;
 976         pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
 977         pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
 978         pch_udc_ep_set_nak(ep);
 979         pch_udc_ep_fifo_flush(ep, ep->in);
 980         /* Configure the endpoint */
 981         val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
 982               ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
 983                 UDC_CSR_NE_TYPE_SHIFT) |
 984               (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
 985               (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
 986               (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
 987               usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
 988
 989         if (ep->in)
 990                 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
 991         else
 992                 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
 993 }
 994
 995 /**
 996  * pch_udc_ep_disable() - This api disables endpoint
 997  * @regs:       Reference to structure pch_udc_ep_regs
 998  */
 999 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1000 {
1001         if (ep->in) {
1002                 /* flush the fifo */
1003                 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1004                 /* set NAK */
1005                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1006                 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1007         } else {
1008                 /* set NAK */
1009                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1010         }
1011         /* reset desc pointer */
1012         pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1013 }
1014
1015 /**
1016  * pch_udc_wait_ep_stall() - Wait EP stall.
1017  * @dev:        Reference to pch_udc_dev structure
1018  */
1019 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1020 {
1021         unsigned int count = 10000;
1022
1023         /* Wait till idle */
1024         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1025                 udelay(5);
1026         if (!count)
1027                 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1028 }
1029
1030 /**
1031  * pch_udc_init() - This API initializes usb device controller
1032  * @dev:        Rreference to pch_udc_regs structure
1033  */
1034 static void pch_udc_init(struct pch_udc_dev *dev)
1035 {
1036         if (NULL == dev) {
1037                 pr_err("%s: Invalid address\n", __func__);
1038                 return;
1039         }
1040         /* Soft Reset and Reset PHY */
1041         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1042         pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1043         mdelay(1);
1044         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1045         pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1046         mdelay(1);
1047         /* mask and clear all device interrupts */
1048         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1049         pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1050
1051         /* mask and clear all ep interrupts */
1052         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1053         pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1054
1055         /* enable dynamic CSR programmingi, self powered and device speed */
1056         if (speed_fs)
1057                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1058                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1059         else /* defaul high speed */
1060                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1061                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1062         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1063                         (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1064                         (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1065                         UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1066                         UDC_DEVCTL_THE);
1067 }
1068
1069 /**
1070  * pch_udc_exit() - This API exit usb device controller
1071  * @dev:        Reference to pch_udc_regs structure
1072  */
1073 static void pch_udc_exit(struct pch_udc_dev *dev)
1074 {
1075         /* mask all device interrupts */
1076         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1077         /* mask all ep interrupts */
1078         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1079         /* put device in disconnected state */
1080         pch_udc_set_disconnect(dev);
1081 }
1082
1083 /**
1084  * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1085  * @gadget:     Reference to the gadget driver
1086  *
1087  * Return codes:
1088  *      0:              Success
1089  *      -EINVAL:        If the gadget passed is NULL
1090  */
1091 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1092 {
1093         struct pch_udc_dev      *dev;
1094
1095         if (!gadget)
1096                 return -EINVAL;
1097         dev = container_of(gadget, struct pch_udc_dev, gadget);
1098         return pch_udc_get_frame(dev);
1099 }
1100
1101 /**
1102  * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1103  * @gadget:     Reference to the gadget driver
1104  *
1105  * Return codes:
1106  *      0:              Success
1107  *      -EINVAL:        If the gadget passed is NULL
1108  */
1109 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1110 {
1111         struct pch_udc_dev      *dev;
1112         unsigned long           flags;
1113
1114         if (!gadget)
1115                 return -EINVAL;
1116         dev = container_of(gadget, struct pch_udc_dev, gadget);
1117         spin_lock_irqsave(&dev->lock, flags);
1118         pch_udc_rmt_wakeup(dev);
1119         spin_unlock_irqrestore(&dev->lock, flags);
1120         return 0;
1121 }
1122
1123 /**
1124  * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1125  *                              is self powered or not
1126  * @gadget:     Reference to the gadget driver
1127  * @value:      Specifies self powered or not
1128  *
1129  * Return codes:
1130  *      0:              Success
1131  *      -EINVAL:        If the gadget passed is NULL
1132  */
1133 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1134 {
1135         struct pch_udc_dev      *dev;
1136
1137         if (!gadget)
1138                 return -EINVAL;
1139         dev = container_of(gadget, struct pch_udc_dev, gadget);
1140         if (value)
1141                 pch_udc_set_selfpowered(dev);
1142         else
1143                 pch_udc_clear_selfpowered(dev);
1144         return 0;
1145 }
1146
1147 /**
1148  * pch_udc_pcd_pullup() - This API is invoked to make the device
1149  *                              visible/invisible to the host
1150  * @gadget:     Reference to the gadget driver
1151  * @is_on:      Specifies whether the pull up is made active or inactive
1152  *
1153  * Return codes:
1154  *      0:              Success
1155  *      -EINVAL:        If the gadget passed is NULL
1156  */
1157 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1158 {
1159         struct pch_udc_dev      *dev;
1160
1161         if (!gadget)
1162                 return -EINVAL;
1163         dev = container_of(gadget, struct pch_udc_dev, gadget);
1164         if (is_on) {
1165                 pch_udc_reconnect(dev);
1166         } else {
1167                 if (dev->driver && dev->driver->disconnect) {
1168                         spin_unlock(&dev->lock);
1169                         dev->driver->disconnect(&dev->gadget);
1170                         spin_lock(&dev->lock);
1171                 }
1172                 pch_udc_set_disconnect(dev);
1173         }
1174
1175         return 0;
1176 }
1177
1178 /**
1179  * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1180  *                              transceiver (or GPIO) that
1181  *                              detects a VBUS power session starting/ending
1182  * @gadget:     Reference to the gadget driver
1183  * @is_active:  specifies whether the session is starting or ending
1184  *
1185  * Return codes:
1186  *      0:              Success
1187  *      -EINVAL:        If the gadget passed is NULL
1188  */
1189 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1190 {
1191         struct pch_udc_dev      *dev;
1192
1193         if (!gadget)
1194                 return -EINVAL;
1195         dev = container_of(gadget, struct pch_udc_dev, gadget);
1196         pch_udc_vbus_session(dev, is_active);
1197         return 0;
1198 }
1199
1200 /**
1201  * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1202  *                              SET_CONFIGURATION calls to
1203  *                              specify how much power the device can consume
1204  * @gadget:     Reference to the gadget driver
1205  * @mA:         specifies the current limit in 2mA unit
1206  *
1207  * Return codes:
1208  *      -EINVAL:        If the gadget passed is NULL
1209  *      -EOPNOTSUPP:
1210  */
1211 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1212 {
1213         return -EOPNOTSUPP;
1214 }
1215
1216 static int pch_udc_start(struct usb_gadget_driver *driver,
1217         int (*bind)(struct usb_gadget *));
1218 static int pch_udc_stop(struct usb_gadget_driver *driver);
1219 static const struct usb_gadget_ops pch_udc_ops = {
1220         .get_frame = pch_udc_pcd_get_frame,
1221         .wakeup = pch_udc_pcd_wakeup,
1222         .set_selfpowered = pch_udc_pcd_selfpowered,
1223         .pullup = pch_udc_pcd_pullup,
1224         .vbus_session = pch_udc_pcd_vbus_session,
1225         .vbus_draw = pch_udc_pcd_vbus_draw,
1226         .start  = pch_udc_start,
1227         .stop   = pch_udc_stop,
1228 };
1229
1230 /**
1231  * complete_req() - This API is invoked from the driver when processing
1232  *                      of a request is complete
1233  * @ep:         Reference to the endpoint structure
1234  * @req:        Reference to the request structure
1235  * @status:     Indicates the success/failure of completion
1236  */
1237 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1238                                                                  int status)
1239 {
1240         struct pch_udc_dev      *dev;
1241         unsigned halted = ep->halted;
1242
1243         list_del_init(&req->queue);
1244
1245         /* set new status if pending */
1246         if (req->req.status == -EINPROGRESS)
1247                 req->req.status = status;
1248         else
1249                 status = req->req.status;
1250
1251         dev = ep->dev;
1252         if (req->dma_mapped) {
1253                 if (req->dma == DMA_ADDR_INVALID) {
1254                         if (ep->in)
1255                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1256                                                  req->req.length,
1257                                                  DMA_TO_DEVICE);
1258                         else
1259                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1260                                                  req->req.length,
1261                                                  DMA_FROM_DEVICE);
1262                         req->req.dma = DMA_ADDR_INVALID;
1263                 } else {
1264                         if (ep->in)
1265                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1266                                                  req->req.length,
1267                                                  DMA_TO_DEVICE);
1268                         else {
1269                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1270                                                  req->req.length,
1271                                                  DMA_FROM_DEVICE);
1272                                 memcpy(req->req.buf, req->buf, req->req.length);
1273                         }
1274                         kfree(req->buf);
1275                         req->dma = DMA_ADDR_INVALID;
1276                 }
1277                 req->dma_mapped = 0;
1278         }
1279         ep->halted = 1;
1280         spin_unlock(&dev->lock);
1281         if (!ep->in)
1282                 pch_udc_ep_clear_rrdy(ep);
1283         req->req.complete(&ep->ep, &req->req);
1284         spin_lock(&dev->lock);
1285         ep->halted = halted;
1286 }
1287
1288 /**
1289  * empty_req_queue() - This API empties the request queue of an endpoint
1290  * @ep:         Reference to the endpoint structure
1291  */
1292 static void empty_req_queue(struct pch_udc_ep *ep)
1293 {
1294         struct pch_udc_request  *req;
1295
1296         ep->halted = 1;
1297         while (!list_empty(&ep->queue)) {
1298                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1299                 complete_req(ep, req, -ESHUTDOWN);      /* Remove from list */
1300         }
1301 }
1302
1303 /**
1304  * pch_udc_free_dma_chain() - This function frees the DMA chain created
1305  *                              for the request
1306  * @dev         Reference to the driver structure
1307  * @req         Reference to the request to be freed
1308  *
1309  * Return codes:
1310  *      0: Success
1311  */
1312 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1313                                    struct pch_udc_request *req)
1314 {
1315         struct pch_udc_data_dma_desc *td = req->td_data;
1316         unsigned i = req->chain_len;
1317
1318         dma_addr_t addr2;
1319         dma_addr_t addr = (dma_addr_t)td->next;
1320         td->next = 0x00;
1321         for (; i > 1; --i) {
1322                 /* do not free first desc., will be done by free for request */
1323                 td = phys_to_virt(addr);
1324                 addr2 = (dma_addr_t)td->next;
1325                 pci_pool_free(dev->data_requests, td, addr);
1326                 td->next = 0x00;
1327                 addr = addr2;
1328         }
1329         req->chain_len = 1;
1330 }
1331
1332 /**
1333  * pch_udc_create_dma_chain() - This function creates or reinitializes
1334  *                              a DMA chain
1335  * @ep:         Reference to the endpoint structure
1336  * @req:        Reference to the request
1337  * @buf_len:    The buffer length
1338  * @gfp_flags:  Flags to be used while mapping the data buffer
1339  *
1340  * Return codes:
1341  *      0:              success,
1342  *      -ENOMEM:        pci_pool_alloc invocation fails
1343  */
1344 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1345                                     struct pch_udc_request *req,
1346                                     unsigned long buf_len,
1347                                     gfp_t gfp_flags)
1348 {
1349         struct pch_udc_data_dma_desc *td = req->td_data, *last;
1350         unsigned long bytes = req->req.length, i = 0;
1351         dma_addr_t dma_addr;
1352         unsigned len = 1;
1353
1354         if (req->chain_len > 1)
1355                 pch_udc_free_dma_chain(ep->dev, req);
1356
1357         if (req->dma == DMA_ADDR_INVALID)
1358                 td->dataptr = req->req.dma;
1359         else
1360                 td->dataptr = req->dma;
1361
1362         td->status = PCH_UDC_BS_HST_BSY;
1363         for (; ; bytes -= buf_len, ++len) {
1364                 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1365                 if (bytes <= buf_len)
1366                         break;
1367                 last = td;
1368                 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1369                                     &dma_addr);
1370                 if (!td)
1371                         goto nomem;
1372                 i += buf_len;
1373                 td->dataptr = req->td_data->dataptr + i;
1374                 last->next = dma_addr;
1375         }
1376
1377         req->td_data_last = td;
1378         td->status |= PCH_UDC_DMA_LAST;
1379         td->next = req->td_data_phys;
1380         req->chain_len = len;
1381         return 0;
1382
1383 nomem:
1384         if (len > 1) {
1385                 req->chain_len = len;
1386                 pch_udc_free_dma_chain(ep->dev, req);
1387         }
1388         req->chain_len = 1;
1389         return -ENOMEM;
1390 }
1391
1392 /**
1393  * prepare_dma() - This function creates and initializes the DMA chain
1394  *                      for the request
1395  * @ep:         Reference to the endpoint structure
1396  * @req:        Reference to the request
1397  * @gfp:        Flag to be used while mapping the data buffer
1398  *
1399  * Return codes:
1400  *      0:              Success
1401  *      Other 0:        linux error number on failure
1402  */
1403 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1404                           gfp_t gfp)
1405 {
1406         int     retval;
1407
1408         /* Allocate and create a DMA chain */
1409         retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1410         if (retval) {
1411                 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1412                 return retval;
1413         }
1414         if (ep->in)
1415                 req->td_data->status = (req->td_data->status &
1416                                 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1417         return 0;
1418 }
1419
1420 /**
1421  * process_zlp() - This function process zero length packets
1422  *                      from the gadget driver
1423  * @ep:         Reference to the endpoint structure
1424  * @req:        Reference to the request
1425  */
1426 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1427 {
1428         struct pch_udc_dev      *dev = ep->dev;
1429
1430         /* IN zlp's are handled by hardware */
1431         complete_req(ep, req, 0);
1432
1433         /* if set_config or set_intf is waiting for ack by zlp
1434          * then set CSR_DONE
1435          */
1436         if (dev->set_cfg_not_acked) {
1437                 pch_udc_set_csr_done(dev);
1438                 dev->set_cfg_not_acked = 0;
1439         }
1440         /* setup command is ACK'ed now by zlp */
1441         if (!dev->stall && dev->waiting_zlp_ack) {
1442                 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1443                 dev->waiting_zlp_ack = 0;
1444         }
1445 }
1446
1447 /**
1448  * pch_udc_start_rxrequest() - This function starts the receive requirement.
1449  * @ep:         Reference to the endpoint structure
1450  * @req:        Reference to the request structure
1451  */
1452 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1453                                          struct pch_udc_request *req)
1454 {
1455         struct pch_udc_data_dma_desc *td_data;
1456
1457         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1458         td_data = req->td_data;
1459         /* Set the status bits for all descriptors */
1460         while (1) {
1461                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1462                                     PCH_UDC_BS_HST_RDY;
1463                 if ((td_data->status & PCH_UDC_DMA_LAST) ==  PCH_UDC_DMA_LAST)
1464                         break;
1465                 td_data = phys_to_virt(td_data->next);
1466         }
1467         /* Write the descriptor pointer */
1468         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1469         req->dma_going = 1;
1470         pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1471         pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1472         pch_udc_ep_clear_nak(ep);
1473         pch_udc_ep_set_rrdy(ep);
1474 }
1475
1476 /**
1477  * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1478  *                              from gadget driver
1479  * @usbep:      Reference to the USB endpoint structure
1480  * @desc:       Reference to the USB endpoint descriptor structure
1481  *
1482  * Return codes:
1483  *      0:              Success
1484  *      -EINVAL:
1485  *      -ESHUTDOWN:
1486  */
1487 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1488                                     const struct usb_endpoint_descriptor *desc)
1489 {
1490         struct pch_udc_ep       *ep;
1491         struct pch_udc_dev      *dev;
1492         unsigned long           iflags;
1493
1494         if (!usbep || (usbep->name == ep0_string) || !desc ||
1495             (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1496                 return -EINVAL;
1497
1498         ep = container_of(usbep, struct pch_udc_ep, ep);
1499         dev = ep->dev;
1500         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1501                 return -ESHUTDOWN;
1502         spin_lock_irqsave(&dev->lock, iflags);
1503         ep->desc = desc;
1504         ep->halted = 0;
1505         pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1506         ep->ep.maxpacket = usb_endpoint_maxp(desc);
1507         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1508         spin_unlock_irqrestore(&dev->lock, iflags);
1509         return 0;
1510 }
1511
1512 /**
1513  * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1514  *                              from gadget driver
1515  * @usbep       Reference to the USB endpoint structure
1516  *
1517  * Return codes:
1518  *      0:              Success
1519  *      -EINVAL:
1520  */
1521 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1522 {
1523         struct pch_udc_ep       *ep;
1524         struct pch_udc_dev      *dev;
1525         unsigned long   iflags;
1526
1527         if (!usbep)
1528                 return -EINVAL;
1529
1530         ep = container_of(usbep, struct pch_udc_ep, ep);
1531         dev = ep->dev;
1532         if ((usbep->name == ep0_string) || !ep->desc)
1533                 return -EINVAL;
1534
1535         spin_lock_irqsave(&ep->dev->lock, iflags);
1536         empty_req_queue(ep);
1537         ep->halted = 1;
1538         pch_udc_ep_disable(ep);
1539         pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1540         ep->desc = NULL;
1541         INIT_LIST_HEAD(&ep->queue);
1542         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1543         return 0;
1544 }
1545
1546 /**
1547  * pch_udc_alloc_request() - This function allocates request structure.
1548  *                              It is called by gadget driver
1549  * @usbep:      Reference to the USB endpoint structure
1550  * @gfp:        Flag to be used while allocating memory
1551  *
1552  * Return codes:
1553  *      NULL:                   Failure
1554  *      Allocated address:      Success
1555  */
1556 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1557                                                   gfp_t gfp)
1558 {
1559         struct pch_udc_request          *req;
1560         struct pch_udc_ep               *ep;
1561         struct pch_udc_data_dma_desc    *dma_desc;
1562         struct pch_udc_dev              *dev;
1563
1564         if (!usbep)
1565                 return NULL;
1566         ep = container_of(usbep, struct pch_udc_ep, ep);
1567         dev = ep->dev;
1568         req = kzalloc(sizeof *req, gfp);
1569         if (!req)
1570                 return NULL;
1571         req->req.dma = DMA_ADDR_INVALID;
1572         req->dma = DMA_ADDR_INVALID;
1573         INIT_LIST_HEAD(&req->queue);
1574         if (!ep->dev->dma_addr)
1575                 return &req->req;
1576         /* ep0 in requests are allocated from data pool here */
1577         dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1578                                   &req->td_data_phys);
1579         if (NULL == dma_desc) {
1580                 kfree(req);
1581                 return NULL;
1582         }
1583         /* prevent from using desc. - set HOST BUSY */
1584         dma_desc->status |= PCH_UDC_BS_HST_BSY;
1585         dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1586         req->td_data = dma_desc;
1587         req->td_data_last = dma_desc;
1588         req->chain_len = 1;
1589         return &req->req;
1590 }
1591
1592 /**
1593  * pch_udc_free_request() - This function frees request structure.
1594  *                              It is called by gadget driver
1595  * @usbep:      Reference to the USB endpoint structure
1596  * @usbreq:     Reference to the USB request
1597  */
1598 static void pch_udc_free_request(struct usb_ep *usbep,
1599                                   struct usb_request *usbreq)
1600 {
1601         struct pch_udc_ep       *ep;
1602         struct pch_udc_request  *req;
1603         struct pch_udc_dev      *dev;
1604
1605         if (!usbep || !usbreq)
1606                 return;
1607         ep = container_of(usbep, struct pch_udc_ep, ep);
1608         req = container_of(usbreq, struct pch_udc_request, req);
1609         dev = ep->dev;
1610         if (!list_empty(&req->queue))
1611                 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1612                         __func__, usbep->name, req);
1613         if (req->td_data != NULL) {
1614                 if (req->chain_len > 1)
1615                         pch_udc_free_dma_chain(ep->dev, req);
1616                 pci_pool_free(ep->dev->data_requests, req->td_data,
1617                               req->td_data_phys);
1618         }
1619         kfree(req);
1620 }
1621
1622 /**
1623  * pch_udc_pcd_queue() - This function queues a request packet. It is called
1624  *                      by gadget driver
1625  * @usbep:      Reference to the USB endpoint structure
1626  * @usbreq:     Reference to the USB request
1627  * @gfp:        Flag to be used while mapping the data buffer
1628  *
1629  * Return codes:
1630  *      0:                      Success
1631  *      linux error number:     Failure
1632  */
1633 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1634                                                                  gfp_t gfp)
1635 {
1636         int retval = 0;
1637         struct pch_udc_ep       *ep;
1638         struct pch_udc_dev      *dev;
1639         struct pch_udc_request  *req;
1640         unsigned long   iflags;
1641
1642         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1643                 return -EINVAL;
1644         ep = container_of(usbep, struct pch_udc_ep, ep);
1645         dev = ep->dev;
1646         if (!ep->desc && ep->num)
1647                 return -EINVAL;
1648         req = container_of(usbreq, struct pch_udc_request, req);
1649         if (!list_empty(&req->queue))
1650                 return -EINVAL;
1651         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1652                 return -ESHUTDOWN;
1653         spin_lock_irqsave(&dev->lock, iflags);
1654         /* map the buffer for dma */
1655         if (usbreq->length &&
1656             ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1657                 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1658                         if (ep->in)
1659                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1660                                                              usbreq->buf,
1661                                                              usbreq->length,
1662                                                              DMA_TO_DEVICE);
1663                         else
1664                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1665                                                              usbreq->buf,
1666                                                              usbreq->length,
1667                                                              DMA_FROM_DEVICE);
1668                 } else {
1669                         req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1670                         if (!req->buf) {
1671                                 retval = -ENOMEM;
1672                                 goto probe_end;
1673                         }
1674                         if (ep->in) {
1675                                 memcpy(req->buf, usbreq->buf, usbreq->length);
1676                                 req->dma = dma_map_single(&dev->pdev->dev,
1677                                                           req->buf,
1678                                                           usbreq->length,
1679                                                           DMA_TO_DEVICE);
1680                         } else
1681                                 req->dma = dma_map_single(&dev->pdev->dev,
1682                                                           req->buf,
1683                                                           usbreq->length,
1684                                                           DMA_FROM_DEVICE);
1685                 }
1686                 req->dma_mapped = 1;
1687         }
1688         if (usbreq->length > 0) {
1689                 retval = prepare_dma(ep, req, GFP_ATOMIC);
1690                 if (retval)
1691                         goto probe_end;
1692         }
1693         usbreq->actual = 0;
1694         usbreq->status = -EINPROGRESS;
1695         req->dma_done = 0;
1696         if (list_empty(&ep->queue) && !ep->halted) {
1697                 /* no pending transfer, so start this req */
1698                 if (!usbreq->length) {
1699                         process_zlp(ep, req);
1700                         retval = 0;
1701                         goto probe_end;
1702                 }
1703                 if (!ep->in) {
1704                         pch_udc_start_rxrequest(ep, req);
1705                 } else {
1706                         /*
1707                         * For IN trfr the descriptors will be programmed and
1708                         * P bit will be set when
1709                         * we get an IN token
1710                         */
1711                         pch_udc_wait_ep_stall(ep);
1712                         pch_udc_ep_clear_nak(ep);
1713                         pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1714                 }
1715         }
1716         /* Now add this request to the ep's pending requests */
1717         if (req != NULL)
1718                 list_add_tail(&req->queue, &ep->queue);
1719
1720 probe_end:
1721         spin_unlock_irqrestore(&dev->lock, iflags);
1722         return retval;
1723 }
1724
1725 /**
1726  * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1727  *                              It is called by gadget driver
1728  * @usbep:      Reference to the USB endpoint structure
1729  * @usbreq:     Reference to the USB request
1730  *
1731  * Return codes:
1732  *      0:                      Success
1733  *      linux error number:     Failure
1734  */
1735 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1736                                 struct usb_request *usbreq)
1737 {
1738         struct pch_udc_ep       *ep;
1739         struct pch_udc_request  *req;
1740         struct pch_udc_dev      *dev;
1741         unsigned long           flags;
1742         int ret = -EINVAL;
1743
1744         ep = container_of(usbep, struct pch_udc_ep, ep);
1745         dev = ep->dev;
1746         if (!usbep || !usbreq || (!ep->desc && ep->num))
1747                 return ret;
1748         req = container_of(usbreq, struct pch_udc_request, req);
1749         spin_lock_irqsave(&ep->dev->lock, flags);
1750         /* make sure it's still queued on this endpoint */
1751         list_for_each_entry(req, &ep->queue, queue) {
1752                 if (&req->req == usbreq) {
1753                         pch_udc_ep_set_nak(ep);
1754                         if (!list_empty(&req->queue))
1755                                 complete_req(ep, req, -ECONNRESET);
1756                         ret = 0;
1757                         break;
1758                 }
1759         }
1760         spin_unlock_irqrestore(&ep->dev->lock, flags);
1761         return ret;
1762 }
1763
1764 /**
1765  * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1766  *                          feature
1767  * @usbep:      Reference to the USB endpoint structure
1768  * @halt:       Specifies whether to set or clear the feature
1769  *
1770  * Return codes:
1771  *      0:                      Success
1772  *      linux error number:     Failure
1773  */
1774 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1775 {
1776         struct pch_udc_ep       *ep;
1777         struct pch_udc_dev      *dev;
1778         unsigned long iflags;
1779         int ret;
1780
1781         if (!usbep)
1782                 return -EINVAL;
1783         ep = container_of(usbep, struct pch_udc_ep, ep);
1784         dev = ep->dev;
1785         if (!ep->desc && !ep->num)
1786                 return -EINVAL;
1787         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1788                 return -ESHUTDOWN;
1789         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1790         if (list_empty(&ep->queue)) {
1791                 if (halt) {
1792                         if (ep->num == PCH_UDC_EP0)
1793                                 ep->dev->stall = 1;
1794                         pch_udc_ep_set_stall(ep);
1795                         pch_udc_enable_ep_interrupts(ep->dev,
1796                                                      PCH_UDC_EPINT(ep->in,
1797                                                                    ep->num));
1798                 } else {
1799                         pch_udc_ep_clear_stall(ep);
1800                 }
1801                 ret = 0;
1802         } else {
1803                 ret = -EAGAIN;
1804         }
1805         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1806         return ret;
1807 }
1808
1809 /**
1810  * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1811  *                              halt feature
1812  * @usbep:      Reference to the USB endpoint structure
1813  * @halt:       Specifies whether to set or clear the feature
1814  *
1815  * Return codes:
1816  *      0:                      Success
1817  *      linux error number:     Failure
1818  */
1819 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1820 {
1821         struct pch_udc_ep       *ep;
1822         struct pch_udc_dev      *dev;
1823         unsigned long iflags;
1824         int ret;
1825
1826         if (!usbep)
1827                 return -EINVAL;
1828         ep = container_of(usbep, struct pch_udc_ep, ep);
1829         dev = ep->dev;
1830         if (!ep->desc && !ep->num)
1831                 return -EINVAL;
1832         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1833                 return -ESHUTDOWN;
1834         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1835         if (!list_empty(&ep->queue)) {
1836                 ret = -EAGAIN;
1837         } else {
1838                 if (ep->num == PCH_UDC_EP0)
1839                         ep->dev->stall = 1;
1840                 pch_udc_ep_set_stall(ep);
1841                 pch_udc_enable_ep_interrupts(ep->dev,
1842                                              PCH_UDC_EPINT(ep->in, ep->num));
1843                 ep->dev->prot_stall = 1;
1844                 ret = 0;
1845         }
1846         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1847         return ret;
1848 }
1849
1850 /**
1851  * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1852  * @usbep:      Reference to the USB endpoint structure
1853  */
1854 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1855 {
1856         struct pch_udc_ep  *ep;
1857
1858         if (!usbep)
1859                 return;
1860
1861         ep = container_of(usbep, struct pch_udc_ep, ep);
1862         if (ep->desc || !ep->num)
1863                 pch_udc_ep_fifo_flush(ep, ep->in);
1864 }
1865
1866 static const struct usb_ep_ops pch_udc_ep_ops = {
1867         .enable         = pch_udc_pcd_ep_enable,
1868         .disable        = pch_udc_pcd_ep_disable,
1869         .alloc_request  = pch_udc_alloc_request,
1870         .free_request   = pch_udc_free_request,
1871         .queue          = pch_udc_pcd_queue,
1872         .dequeue        = pch_udc_pcd_dequeue,
1873         .set_halt       = pch_udc_pcd_set_halt,
1874         .set_wedge      = pch_udc_pcd_set_wedge,
1875         .fifo_status    = NULL,
1876         .fifo_flush     = pch_udc_pcd_fifo_flush,
1877 };
1878
1879 /**
1880  * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1881  * @td_stp:     Reference to the SETP buffer structure
1882  */
1883 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1884 {
1885         static u32      pky_marker;
1886
1887         if (!td_stp)
1888                 return;
1889         td_stp->reserved = ++pky_marker;
1890         memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1891         td_stp->status = PCH_UDC_BS_HST_RDY;
1892 }
1893
1894 /**
1895  * pch_udc_start_next_txrequest() - This function starts
1896  *                                      the next transmission requirement
1897  * @ep: Reference to the endpoint structure
1898  */
1899 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1900 {
1901         struct pch_udc_request *req;
1902         struct pch_udc_data_dma_desc *td_data;
1903
1904         if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1905                 return;
1906
1907         if (list_empty(&ep->queue))
1908                 return;
1909
1910         /* next request */
1911         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1912         if (req->dma_going)
1913                 return;
1914         if (!req->td_data)
1915                 return;
1916         pch_udc_wait_ep_stall(ep);
1917         req->dma_going = 1;
1918         pch_udc_ep_set_ddptr(ep, 0);
1919         td_data = req->td_data;
1920         while (1) {
1921                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1922                                    PCH_UDC_BS_HST_RDY;
1923                 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1924                         break;
1925                 td_data = phys_to_virt(td_data->next);
1926         }
1927         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1928         pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1929         pch_udc_ep_set_pd(ep);
1930         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1931         pch_udc_ep_clear_nak(ep);
1932 }
1933
1934 /**
1935  * pch_udc_complete_transfer() - This function completes a transfer
1936  * @ep:         Reference to the endpoint structure
1937  */
1938 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1939 {
1940         struct pch_udc_request *req;
1941         struct pch_udc_dev *dev = ep->dev;
1942
1943         if (list_empty(&ep->queue))
1944                 return;
1945         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1946         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1947             PCH_UDC_BS_DMA_DONE)
1948                 return;
1949         if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1950              PCH_UDC_RTS_SUCC) {
1951                 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1952                         "epstatus=0x%08x\n",
1953                        (req->td_data_last->status & PCH_UDC_RXTX_STS),
1954                        (int)(ep->epsts));
1955                 return;
1956         }
1957
1958         req->req.actual = req->req.length;
1959         req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1960         req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1961         complete_req(ep, req, 0);
1962         req->dma_going = 0;
1963         if (!list_empty(&ep->queue)) {
1964                 pch_udc_wait_ep_stall(ep);
1965                 pch_udc_ep_clear_nak(ep);
1966                 pch_udc_enable_ep_interrupts(ep->dev,
1967                                              PCH_UDC_EPINT(ep->in, ep->num));
1968         } else {
1969                 pch_udc_disable_ep_interrupts(ep->dev,
1970                                               PCH_UDC_EPINT(ep->in, ep->num));
1971         }
1972 }
1973
1974 /**
1975  * pch_udc_complete_receiver() - This function completes a receiver
1976  * @ep:         Reference to the endpoint structure
1977  */
1978 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1979 {
1980         struct pch_udc_request *req;
1981         struct pch_udc_dev *dev = ep->dev;
1982         unsigned int count;
1983         struct pch_udc_data_dma_desc *td;
1984         dma_addr_t addr;
1985
1986         if (list_empty(&ep->queue))
1987                 return;
1988         /* next request */
1989         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1990         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1991         pch_udc_ep_set_ddptr(ep, 0);
1992         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
1993             PCH_UDC_BS_DMA_DONE)
1994                 td = req->td_data_last;
1995         else
1996                 td = req->td_data;
1997
1998         while (1) {
1999                 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
2000                         dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2001                                 "epstatus=0x%08x\n",
2002                                 (req->td_data->status & PCH_UDC_RXTX_STS),
2003                                 (int)(ep->epsts));
2004                         return;
2005                 }
2006                 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2007                         if (td->status | PCH_UDC_DMA_LAST) {
2008                                 count = td->status & PCH_UDC_RXTX_BYTES;
2009                                 break;
2010                         }
2011                 if (td == req->td_data_last) {
2012                         dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2013                         return;
2014                 }
2015                 addr = (dma_addr_t)td->next;
2016                 td = phys_to_virt(addr);
2017         }
2018         /* on 64k packets the RXBYTES field is zero */
2019         if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2020                 count = UDC_DMA_MAXPACKET;
2021         req->td_data->status |= PCH_UDC_DMA_LAST;
2022         td->status |= PCH_UDC_BS_HST_BSY;
2023
2024         req->dma_going = 0;
2025         req->req.actual = count;
2026         complete_req(ep, req, 0);
2027         /* If there is a new/failed requests try that now */
2028         if (!list_empty(&ep->queue)) {
2029                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2030                 pch_udc_start_rxrequest(ep, req);
2031         }
2032 }
2033
2034 /**
2035  * pch_udc_svc_data_in() - This function process endpoint interrupts
2036  *                              for IN endpoints
2037  * @dev:        Reference to the device structure
2038  * @ep_num:     Endpoint that generated the interrupt
2039  */
2040 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2041 {
2042         u32     epsts;
2043         struct pch_udc_ep       *ep;
2044
2045         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2046         epsts = ep->epsts;
2047         ep->epsts = 0;
2048
2049         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA  | UDC_EPSTS_HE |
2050                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2051                        UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2052                 return;
2053         if ((epsts & UDC_EPSTS_BNA))
2054                 return;
2055         if (epsts & UDC_EPSTS_HE)
2056                 return;
2057         if (epsts & UDC_EPSTS_RSS) {
2058                 pch_udc_ep_set_stall(ep);
2059                 pch_udc_enable_ep_interrupts(ep->dev,
2060                                              PCH_UDC_EPINT(ep->in, ep->num));
2061         }
2062         if (epsts & UDC_EPSTS_RCS) {
2063                 if (!dev->prot_stall) {
2064                         pch_udc_ep_clear_stall(ep);
2065                 } else {
2066                         pch_udc_ep_set_stall(ep);
2067                         pch_udc_enable_ep_interrupts(ep->dev,
2068                                                 PCH_UDC_EPINT(ep->in, ep->num));
2069                 }
2070         }
2071         if (epsts & UDC_EPSTS_TDC)
2072                 pch_udc_complete_transfer(ep);
2073         /* On IN interrupt, provide data if we have any */
2074         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2075             !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2076                 pch_udc_start_next_txrequest(ep);
2077 }
2078
2079 /**
2080  * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2081  * @dev:        Reference to the device structure
2082  * @ep_num:     Endpoint that generated the interrupt
2083  */
2084 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2085 {
2086         u32                     epsts;
2087         struct pch_udc_ep               *ep;
2088         struct pch_udc_request          *req = NULL;
2089
2090         ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2091         epsts = ep->epsts;
2092         ep->epsts = 0;
2093
2094         if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2095                 /* next request */
2096                 req = list_entry(ep->queue.next, struct pch_udc_request,
2097                                  queue);
2098                 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2099                      PCH_UDC_BS_DMA_DONE) {
2100                         if (!req->dma_going)
2101                                 pch_udc_start_rxrequest(ep, req);
2102                         return;
2103                 }
2104         }
2105         if (epsts & UDC_EPSTS_HE)
2106                 return;
2107         if (epsts & UDC_EPSTS_RSS) {
2108                 pch_udc_ep_set_stall(ep);
2109                 pch_udc_enable_ep_interrupts(ep->dev,
2110                                              PCH_UDC_EPINT(ep->in, ep->num));
2111         }
2112         if (epsts & UDC_EPSTS_RCS) {
2113                 if (!dev->prot_stall) {
2114                         pch_udc_ep_clear_stall(ep);
2115                 } else {
2116                         pch_udc_ep_set_stall(ep);
2117                         pch_udc_enable_ep_interrupts(ep->dev,
2118                                                 PCH_UDC_EPINT(ep->in, ep->num));
2119                 }
2120         }
2121         if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2122             UDC_EPSTS_OUT_DATA) {
2123                 if (ep->dev->prot_stall == 1) {
2124                         pch_udc_ep_set_stall(ep);
2125                         pch_udc_enable_ep_interrupts(ep->dev,
2126                                                 PCH_UDC_EPINT(ep->in, ep->num));
2127                 } else {
2128                         pch_udc_complete_receiver(ep);
2129                 }
2130         }
2131         if (list_empty(&ep->queue))
2132                 pch_udc_set_dma(dev, DMA_DIR_RX);
2133 }
2134
2135 /**
2136  * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2137  * @dev:        Reference to the device structure
2138  */
2139 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2140 {
2141         u32     epsts;
2142         struct pch_udc_ep       *ep;
2143         struct pch_udc_ep       *ep_out;
2144
2145         ep = &dev->ep[UDC_EP0IN_IDX];
2146         ep_out = &dev->ep[UDC_EP0OUT_IDX];
2147         epsts = ep->epsts;
2148         ep->epsts = 0;
2149
2150         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2151                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2152                        UDC_EPSTS_XFERDONE)))
2153                 return;
2154         if ((epsts & UDC_EPSTS_BNA))
2155                 return;
2156         if (epsts & UDC_EPSTS_HE)
2157                 return;
2158         if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2159                 pch_udc_complete_transfer(ep);
2160                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2161                 ep_out->td_data->status = (ep_out->td_data->status &
2162                                         ~PCH_UDC_BUFF_STS) |
2163                                         PCH_UDC_BS_HST_RDY;
2164                 pch_udc_ep_clear_nak(ep_out);
2165                 pch_udc_set_dma(dev, DMA_DIR_RX);
2166                 pch_udc_ep_set_rrdy(ep_out);
2167         }
2168         /* On IN interrupt, provide data if we have any */
2169         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2170              !(epsts & UDC_EPSTS_TXEMPTY))
2171                 pch_udc_start_next_txrequest(ep);
2172 }
2173
2174 /**
2175  * pch_udc_svc_control_out() - Routine that handle Control
2176  *                                      OUT endpoint interrupts
2177  * @dev:        Reference to the device structure
2178  */
2179 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2180 {
2181         u32     stat;
2182         int setup_supported;
2183         struct pch_udc_ep       *ep;
2184
2185         ep = &dev->ep[UDC_EP0OUT_IDX];
2186         stat = ep->epsts;
2187         ep->epsts = 0;
2188
2189         /* If setup data */
2190         if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2191             UDC_EPSTS_OUT_SETUP) {
2192                 dev->stall = 0;
2193                 dev->ep[UDC_EP0IN_IDX].halted = 0;
2194                 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2195                 dev->setup_data = ep->td_stp->request;
2196                 pch_udc_init_setup_buff(ep->td_stp);
2197                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2198                 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2199                                       dev->ep[UDC_EP0IN_IDX].in);
2200                 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2201                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2202                 else /* OUT */
2203                         dev->gadget.ep0 = &ep->ep;
2204                 spin_unlock(&dev->lock);
2205                 /* If Mass storage Reset */
2206                 if ((dev->setup_data.bRequestType == 0x21) &&
2207                     (dev->setup_data.bRequest == 0xFF))
2208                         dev->prot_stall = 0;
2209                 /* call gadget with setup data received */
2210                 setup_supported = dev->driver->setup(&dev->gadget,
2211                                                      &dev->setup_data);
2212                 spin_lock(&dev->lock);
2213
2214                 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2215                         ep->td_data->status = (ep->td_data->status &
2216                                                 ~PCH_UDC_BUFF_STS) |
2217                                                 PCH_UDC_BS_HST_RDY;
2218                         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2219                 }
2220                 /* ep0 in returns data on IN phase */
2221                 if (setup_supported >= 0 && setup_supported <
2222                                             UDC_EP0IN_MAX_PKT_SIZE) {
2223                         pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2224                         /* Gadget would have queued a request when
2225                          * we called the setup */
2226                         if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2227                                 pch_udc_set_dma(dev, DMA_DIR_RX);
2228                                 pch_udc_ep_clear_nak(ep);
2229                         }
2230                 } else if (setup_supported < 0) {
2231                         /* if unsupported request, then stall */
2232                         pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2233                         pch_udc_enable_ep_interrupts(ep->dev,
2234                                                 PCH_UDC_EPINT(ep->in, ep->num));
2235                         dev->stall = 0;
2236                         pch_udc_set_dma(dev, DMA_DIR_RX);
2237                 } else {
2238                         dev->waiting_zlp_ack = 1;
2239                 }
2240         } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2241                      UDC_EPSTS_OUT_DATA) && !dev->stall) {
2242                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2243                 pch_udc_ep_set_ddptr(ep, 0);
2244                 if (!list_empty(&ep->queue)) {
2245                         ep->epsts = stat;
2246                         pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2247                 }
2248                 pch_udc_set_dma(dev, DMA_DIR_RX);
2249         }
2250         pch_udc_ep_set_rrdy(ep);
2251 }
2252
2253
2254 /**
2255  * pch_udc_postsvc_epinters() - This function enables end point interrupts
2256  *                              and clears NAK status
2257  * @dev:        Reference to the device structure
2258  * @ep_num:     End point number
2259  */
2260 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2261 {
2262         struct pch_udc_ep       *ep;
2263         struct pch_udc_request *req;
2264
2265         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2266         if (!list_empty(&ep->queue)) {
2267                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2268                 pch_udc_enable_ep_interrupts(ep->dev,
2269                                              PCH_UDC_EPINT(ep->in, ep->num));
2270                 pch_udc_ep_clear_nak(ep);
2271         }
2272 }
2273
2274 /**
2275  * pch_udc_read_all_epstatus() - This function read all endpoint status
2276  * @dev:        Reference to the device structure
2277  * @ep_intr:    Status of endpoint interrupt
2278  */
2279 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2280 {
2281         int i;
2282         struct pch_udc_ep       *ep;
2283
2284         for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2285                 /* IN */
2286                 if (ep_intr & (0x1 << i)) {
2287                         ep = &dev->ep[UDC_EPIN_IDX(i)];
2288                         ep->epsts = pch_udc_read_ep_status(ep);
2289                         pch_udc_clear_ep_status(ep, ep->epsts);
2290                 }
2291                 /* OUT */
2292                 if (ep_intr & (0x10000 << i)) {
2293                         ep = &dev->ep[UDC_EPOUT_IDX(i)];
2294                         ep->epsts = pch_udc_read_ep_status(ep);
2295                         pch_udc_clear_ep_status(ep, ep->epsts);
2296                 }
2297         }
2298 }
2299
2300 /**
2301  * pch_udc_activate_control_ep() - This function enables the control endpoints
2302  *                                      for traffic after a reset
2303  * @dev:        Reference to the device structure
2304  */
2305 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2306 {
2307         struct pch_udc_ep       *ep;
2308         u32 val;
2309
2310         /* Setup the IN endpoint */
2311         ep = &dev->ep[UDC_EP0IN_IDX];
2312         pch_udc_clear_ep_control(ep);
2313         pch_udc_ep_fifo_flush(ep, ep->in);
2314         pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2315         pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2316         /* Initialize the IN EP Descriptor */
2317         ep->td_data      = NULL;
2318         ep->td_stp       = NULL;
2319         ep->td_data_phys = 0;
2320         ep->td_stp_phys  = 0;
2321
2322         /* Setup the OUT endpoint */
2323         ep = &dev->ep[UDC_EP0OUT_IDX];
2324         pch_udc_clear_ep_control(ep);
2325         pch_udc_ep_fifo_flush(ep, ep->in);
2326         pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2327         pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2328         val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2329         pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2330
2331         /* Initialize the SETUP buffer */
2332         pch_udc_init_setup_buff(ep->td_stp);
2333         /* Write the pointer address of dma descriptor */
2334         pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2335         /* Write the pointer address of Setup descriptor */
2336         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2337
2338         /* Initialize the dma descriptor */
2339         ep->td_data->status  = PCH_UDC_DMA_LAST;
2340         ep->td_data->dataptr = dev->dma_addr;
2341         ep->td_data->next    = ep->td_data_phys;
2342
2343         pch_udc_ep_clear_nak(ep);
2344 }
2345
2346
2347 /**
2348  * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2349  * @dev:        Reference to driver structure
2350  */
2351 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2352 {
2353         struct pch_udc_ep       *ep;
2354         int i;
2355
2356         pch_udc_clear_dma(dev, DMA_DIR_TX);
2357         pch_udc_clear_dma(dev, DMA_DIR_RX);
2358         /* Mask all endpoint interrupts */
2359         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2360         /* clear all endpoint interrupts */
2361         pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2362
2363         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2364                 ep = &dev->ep[i];
2365                 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2366                 pch_udc_clear_ep_control(ep);
2367                 pch_udc_ep_set_ddptr(ep, 0);
2368                 pch_udc_write_csr(ep->dev, 0x00, i);
2369         }
2370         dev->stall = 0;
2371         dev->prot_stall = 0;
2372         dev->waiting_zlp_ack = 0;
2373         dev->set_cfg_not_acked = 0;
2374
2375         /* disable ep to empty req queue. Skip the control EP's */
2376         for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2377                 ep = &dev->ep[i];
2378                 pch_udc_ep_set_nak(ep);
2379                 pch_udc_ep_fifo_flush(ep, ep->in);
2380                 /* Complete request queue */
2381                 empty_req_queue(ep);
2382         }
2383         if (dev->driver && dev->driver->disconnect) {
2384                 spin_unlock(&dev->lock);
2385                 dev->driver->disconnect(&dev->gadget);
2386                 spin_lock(&dev->lock);
2387         }
2388 }
2389
2390 /**
2391  * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2392  *                              done interrupt
2393  * @dev:        Reference to driver structure
2394  */
2395 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2396 {
2397         u32 dev_stat, dev_speed;
2398         u32 speed = USB_SPEED_FULL;
2399
2400         dev_stat = pch_udc_read_device_status(dev);
2401         dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2402                                                  UDC_DEVSTS_ENUM_SPEED_SHIFT;
2403         switch (dev_speed) {
2404         case UDC_DEVSTS_ENUM_SPEED_HIGH:
2405                 speed = USB_SPEED_HIGH;
2406                 break;
2407         case  UDC_DEVSTS_ENUM_SPEED_FULL:
2408                 speed = USB_SPEED_FULL;
2409                 break;
2410         case  UDC_DEVSTS_ENUM_SPEED_LOW:
2411                 speed = USB_SPEED_LOW;
2412                 break;
2413         default:
2414                 BUG();
2415         }
2416         dev->gadget.speed = speed;
2417         pch_udc_activate_control_ep(dev);
2418         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2419         pch_udc_set_dma(dev, DMA_DIR_TX);
2420         pch_udc_set_dma(dev, DMA_DIR_RX);
2421         pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2422 }
2423
2424 /**
2425  * pch_udc_svc_intf_interrupt() - This function handles a set interface
2426  *                                interrupt
2427  * @dev:        Reference to driver structure
2428  */
2429 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2430 {
2431         u32 reg, dev_stat = 0;
2432         int i, ret;
2433
2434         dev_stat = pch_udc_read_device_status(dev);
2435         dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2436                                                          UDC_DEVSTS_INTF_SHIFT;
2437         dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2438                                                          UDC_DEVSTS_ALT_SHIFT;
2439         dev->set_cfg_not_acked = 1;
2440         /* Construct the usb request for gadget driver and inform it */
2441         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2442         dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2443         dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2444         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2445         dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2446         /* programm the Endpoint Cfg registers */
2447         /* Only one end point cfg register */
2448         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2449         reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2450               (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2451         reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2452               (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2453         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2454         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2455                 /* clear stall bits */
2456                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2457                 dev->ep[i].halted = 0;
2458         }
2459         dev->stall = 0;
2460         spin_unlock(&dev->lock);
2461         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2462         spin_lock(&dev->lock);
2463 }
2464
2465 /**
2466  * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2467  *                              interrupt
2468  * @dev:        Reference to driver structure
2469  */
2470 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2471 {
2472         int i, ret;
2473         u32 reg, dev_stat = 0;
2474
2475         dev_stat = pch_udc_read_device_status(dev);
2476         dev->set_cfg_not_acked = 1;
2477         dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2478                                 UDC_DEVSTS_CFG_SHIFT;
2479         /* make usb request for gadget driver */
2480         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2481         dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2482         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2483         /* program the NE registers */
2484         /* Only one end point cfg register */
2485         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2486         reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2487               (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2488         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2489         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2490                 /* clear stall bits */
2491                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2492                 dev->ep[i].halted = 0;
2493         }
2494         dev->stall = 0;
2495
2496         /* call gadget zero with setup data received */
2497         spin_unlock(&dev->lock);
2498         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2499         spin_lock(&dev->lock);
2500 }
2501
2502 /**
2503  * pch_udc_dev_isr() - This function services device interrupts
2504  *                      by invoking appropriate routines.
2505  * @dev:        Reference to the device structure
2506  * @dev_intr:   The Device interrupt status.
2507  */
2508 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2509 {
2510         /* USB Reset Interrupt */
2511         if (dev_intr & UDC_DEVINT_UR)
2512                 pch_udc_svc_ur_interrupt(dev);
2513         /* Enumeration Done Interrupt */
2514         if (dev_intr & UDC_DEVINT_ENUM)
2515                 pch_udc_svc_enum_interrupt(dev);
2516         /* Set Interface Interrupt */
2517         if (dev_intr & UDC_DEVINT_SI)
2518                 pch_udc_svc_intf_interrupt(dev);
2519         /* Set Config Interrupt */
2520         if (dev_intr & UDC_DEVINT_SC)
2521                 pch_udc_svc_cfg_interrupt(dev);
2522         /* USB Suspend interrupt */
2523         if (dev_intr & UDC_DEVINT_US) {
2524                 if (dev->driver
2525                         && dev->driver->suspend) {
2526                         spin_unlock(&dev->lock);
2527                         dev->driver->suspend(&dev->gadget);
2528                         spin_lock(&dev->lock);
2529                 }
2530
2531                 if (dev->vbus_session == 0) {
2532                         if (dev->driver && dev->driver->disconnect) {
2533                                 spin_unlock(&dev->lock);
2534                                 dev->driver->disconnect(&dev->gadget);
2535                                 spin_lock(&dev->lock);
2536                         }
2537                         pch_udc_reconnect(dev);
2538                 }
2539                 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2540         }
2541         /* Clear the SOF interrupt, if enabled */
2542         if (dev_intr & UDC_DEVINT_SOF)
2543                 dev_dbg(&dev->pdev->dev, "SOF\n");
2544         /* ES interrupt, IDLE > 3ms on the USB */
2545         if (dev_intr & UDC_DEVINT_ES)
2546                 dev_dbg(&dev->pdev->dev, "ES\n");
2547         /* RWKP interrupt */
2548         if (dev_intr & UDC_DEVINT_RWKP)
2549                 dev_dbg(&dev->pdev->dev, "RWKP\n");
2550 }
2551
2552 /**
2553  * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2554  * @irq:        Interrupt request number
2555  * @dev:        Reference to the device structure
2556  */
2557 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2558 {
2559         struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2560         u32 dev_intr, ep_intr;
2561         int i;
2562
2563         dev_intr = pch_udc_read_device_interrupts(dev);
2564         ep_intr = pch_udc_read_ep_interrupts(dev);
2565
2566         /* For a hot plug, this find that the controller is hung up. */
2567         if (dev_intr == ep_intr)
2568                 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2569                         dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2570                         /* The controller is reset */
2571                         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2572                         return IRQ_HANDLED;
2573                 }
2574         if (dev_intr)
2575                 /* Clear device interrupts */
2576                 pch_udc_write_device_interrupts(dev, dev_intr);
2577         if (ep_intr)
2578                 /* Clear ep interrupts */
2579                 pch_udc_write_ep_interrupts(dev, ep_intr);
2580         if (!dev_intr && !ep_intr)
2581                 return IRQ_NONE;
2582         spin_lock(&dev->lock);
2583         if (dev_intr)
2584                 pch_udc_dev_isr(dev, dev_intr);
2585         if (ep_intr) {
2586                 pch_udc_read_all_epstatus(dev, ep_intr);
2587                 /* Process Control In interrupts, if present */
2588                 if (ep_intr & UDC_EPINT_IN_EP0) {
2589                         pch_udc_svc_control_in(dev);
2590                         pch_udc_postsvc_epinters(dev, 0);
2591                 }
2592                 /* Process Control Out interrupts, if present */
2593                 if (ep_intr & UDC_EPINT_OUT_EP0)
2594                         pch_udc_svc_control_out(dev);
2595                 /* Process data in end point interrupts */
2596                 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2597                         if (ep_intr & (1 <<  i)) {
2598                                 pch_udc_svc_data_in(dev, i);
2599                                 pch_udc_postsvc_epinters(dev, i);
2600                         }
2601                 }
2602                 /* Process data out end point interrupts */
2603                 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2604                                                  PCH_UDC_USED_EP_NUM); i++)
2605                         if (ep_intr & (1 <<  i))
2606                                 pch_udc_svc_data_out(dev, i -
2607                                                          UDC_EPINT_OUT_SHIFT);
2608         }
2609         spin_unlock(&dev->lock);
2610         return IRQ_HANDLED;
2611 }
2612
2613 /**
2614  * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2615  * @dev:        Reference to the device structure
2616  */
2617 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2618 {
2619         /* enable ep0 interrupts */
2620         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2621                                                 UDC_EPINT_OUT_EP0);
2622         /* enable device interrupts */
2623         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2624                                        UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2625                                        UDC_DEVINT_SI | UDC_DEVINT_SC);
2626 }
2627
2628 /**
2629  * gadget_release() - Free the gadget driver private data
2630  * @pdev        reference to struct pci_dev
2631  */
2632 static void gadget_release(struct device *pdev)
2633 {
2634         struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2635
2636         kfree(dev);
2637 }
2638
2639 /**
2640  * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2641  * @dev:        Reference to the driver structure
2642  */
2643 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2644 {
2645         const char *const ep_string[] = {
2646                 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2647                 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2648                 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2649                 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2650                 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2651                 "ep15in", "ep15out",
2652         };
2653         int i;
2654
2655         dev->gadget.speed = USB_SPEED_UNKNOWN;
2656         INIT_LIST_HEAD(&dev->gadget.ep_list);
2657
2658         /* Initialize the endpoints structures */
2659         memset(dev->ep, 0, sizeof dev->ep);
2660         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2661                 struct pch_udc_ep *ep = &dev->ep[i];
2662                 ep->dev = dev;
2663                 ep->halted = 1;
2664                 ep->num = i / 2;
2665                 ep->in = ~i & 1;
2666                 ep->ep.name = ep_string[i];
2667                 ep->ep.ops = &pch_udc_ep_ops;
2668                 if (ep->in)
2669                         ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2670                 else
2671                         ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2672                                           UDC_EP_REG_SHIFT;
2673                 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2674                 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2675                 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2676                 INIT_LIST_HEAD(&ep->queue);
2677         }
2678         dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2679         dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2680
2681         /* remove ep0 in and out from the list.  They have own pointer */
2682         list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2683         list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2684
2685         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2686         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2687 }
2688
2689 /**
2690  * pch_udc_pcd_init() - This API initializes the driver structure
2691  * @dev:        Reference to the driver structure
2692  *
2693  * Return codes:
2694  *      0: Success
2695  */
2696 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2697 {
2698         pch_udc_init(dev);
2699         pch_udc_pcd_reinit(dev);
2700         return 0;
2701 }
2702
2703 /**
2704  * init_dma_pools() - create dma pools during initialization
2705  * @pdev:       reference to struct pci_dev
2706  */
2707 static int init_dma_pools(struct pch_udc_dev *dev)
2708 {
2709         struct pch_udc_stp_dma_desc     *td_stp;
2710         struct pch_udc_data_dma_desc    *td_data;
2711
2712         /* DMA setup */
2713         dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2714                 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2715         if (!dev->data_requests) {
2716                 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2717                         __func__);
2718                 return -ENOMEM;
2719         }
2720
2721         /* dma desc for setup data */
2722         dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2723                 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2724         if (!dev->stp_requests) {
2725                 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2726                         __func__);
2727                 return -ENOMEM;
2728         }
2729         /* setup */
2730         td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2731                                 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2732         if (!td_stp) {
2733                 dev_err(&dev->pdev->dev,
2734                         "%s: can't allocate setup dma descriptor\n", __func__);
2735                 return -ENOMEM;
2736         }
2737         dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2738
2739         /* data: 0 packets !? */
2740         td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2741                                 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2742         if (!td_data) {
2743                 dev_err(&dev->pdev->dev,
2744                         "%s: can't allocate data dma descriptor\n", __func__);
2745                 return -ENOMEM;
2746         }
2747         dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2748         dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2749         dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2750         dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2751         dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2752
2753         dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2754         if (!dev->ep0out_buf)
2755                 return -ENOMEM;
2756         dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2757                                        UDC_EP0OUT_BUFF_SIZE * 4,
2758                                        DMA_FROM_DEVICE);
2759         return 0;
2760 }
2761
2762 static int pch_udc_start(struct usb_gadget_driver *driver,
2763         int (*bind)(struct usb_gadget *))
2764 {
2765         struct pch_udc_dev      *dev = pch_udc;
2766         int                     retval;
2767
2768         if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
2769             !driver->setup || !driver->unbind || !driver->disconnect) {
2770                 dev_err(&dev->pdev->dev,
2771                         "%s: invalid driver parameter\n", __func__);
2772                 return -EINVAL;
2773         }
2774
2775         if (!dev)
2776                 return -ENODEV;
2777
2778         if (dev->driver) {
2779                 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2780                 return -EBUSY;
2781         }
2782         driver->driver.bus = NULL;
2783         dev->driver = driver;
2784         dev->gadget.dev.driver = &driver->driver;
2785
2786         /* Invoke the bind routine of the gadget driver */
2787         retval = bind(&dev->gadget);
2788
2789         if (retval) {
2790                 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2791                        __func__, driver->driver.name, retval);
2792                 dev->driver = NULL;
2793                 dev->gadget.dev.driver = NULL;
2794                 return retval;
2795         }
2796         /* get ready for ep0 traffic */
2797         pch_udc_setup_ep0(dev);
2798
2799         /* clear SD */
2800         pch_udc_clear_disconnect(dev);
2801
2802         dev->connected = 1;
2803         return 0;
2804 }
2805
2806 static int pch_udc_stop(struct usb_gadget_driver *driver)
2807 {
2808         struct pch_udc_dev      *dev = pch_udc;
2809
2810         if (!dev)
2811                 return -ENODEV;
2812
2813         if (!driver || (driver != dev->driver)) {
2814                 dev_err(&dev->pdev->dev,
2815                         "%s: invalid driver parameter\n", __func__);
2816                 return -EINVAL;
2817         }
2818
2819         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2820
2821         /* Assures that there are no pending requests with this driver */
2822         driver->disconnect(&dev->gadget);
2823         driver->unbind(&dev->gadget);
2824         dev->gadget.dev.driver = NULL;
2825         dev->driver = NULL;
2826         dev->connected = 0;
2827
2828         /* set SD */
2829         pch_udc_set_disconnect(dev);
2830         return 0;
2831 }
2832
2833 static void pch_udc_shutdown(struct pci_dev *pdev)
2834 {
2835         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2836
2837         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2838         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2839
2840         /* disable the pullup so the host will think we're gone */
2841         pch_udc_set_disconnect(dev);
2842 }
2843
2844 static void pch_udc_remove(struct pci_dev *pdev)
2845 {
2846         struct pch_udc_dev      *dev = pci_get_drvdata(pdev);
2847
2848         usb_del_gadget_udc(&dev->gadget);
2849
2850         /* gadget driver must not be registered */
2851         if (dev->driver)
2852                 dev_err(&pdev->dev,
2853                         "%s: gadget driver still bound!!!\n", __func__);
2854         /* dma pool cleanup */
2855         if (dev->data_requests)
2856                 pci_pool_destroy(dev->data_requests);
2857
2858         if (dev->stp_requests) {
2859                 /* cleanup DMA desc's for ep0in */
2860                 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2861                         pci_pool_free(dev->stp_requests,
2862                                 dev->ep[UDC_EP0OUT_IDX].td_stp,
2863                                 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2864                 }
2865                 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2866                         pci_pool_free(dev->stp_requests,
2867                                 dev->ep[UDC_EP0OUT_IDX].td_data,
2868                                 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2869                 }
2870                 pci_pool_destroy(dev->stp_requests);
2871         }
2872
2873         if (dev->dma_addr)
2874                 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
2875                                  UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
2876         kfree(dev->ep0out_buf);
2877
2878         pch_udc_exit(dev);
2879
2880         if (dev->irq_registered)
2881                 free_irq(pdev->irq, dev);
2882         if (dev->base_addr)
2883                 iounmap(dev->base_addr);
2884         if (dev->mem_region)
2885                 release_mem_region(dev->phys_addr,
2886                                    pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2887         if (dev->active)
2888                 pci_disable_device(pdev);
2889         if (dev->registered)
2890                 device_unregister(&dev->gadget.dev);
2891         kfree(dev);
2892         pci_set_drvdata(pdev, NULL);
2893 }
2894
2895 #ifdef CONFIG_PM
2896 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2897 {
2898         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2899
2900         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2901         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2902
2903         pci_disable_device(pdev);
2904         pci_enable_wake(pdev, PCI_D3hot, 0);
2905
2906         if (pci_save_state(pdev)) {
2907                 dev_err(&pdev->dev,
2908                         "%s: could not save PCI config state\n", __func__);
2909                 return -ENOMEM;
2910         }
2911         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2912         return 0;
2913 }
2914
2915 static int pch_udc_resume(struct pci_dev *pdev)
2916 {
2917         int ret;
2918
2919         pci_set_power_state(pdev, PCI_D0);
2920         pci_restore_state(pdev);
2921         ret = pci_enable_device(pdev);
2922         if (ret) {
2923                 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2924                 return ret;
2925         }
2926         pci_enable_wake(pdev, PCI_D3hot, 0);
2927         return 0;
2928 }
2929 #else
2930 #define pch_udc_suspend NULL
2931 #define pch_udc_resume  NULL
2932 #endif /* CONFIG_PM */
2933
2934 static int pch_udc_probe(struct pci_dev *pdev,
2935                           const struct pci_device_id *id)
2936 {
2937         unsigned long           resource;
2938         unsigned long           len;
2939         int                     retval;
2940         struct pch_udc_dev      *dev;
2941
2942         /* one udc only */
2943         if (pch_udc) {
2944                 pr_err("%s: already probed\n", __func__);
2945                 return -EBUSY;
2946         }
2947         /* init */
2948         dev = kzalloc(sizeof *dev, GFP_KERNEL);
2949         if (!dev) {
2950                 pr_err("%s: no memory for device structure\n", __func__);
2951                 return -ENOMEM;
2952         }
2953         /* pci setup */
2954         if (pci_enable_device(pdev) < 0) {
2955                 kfree(dev);
2956                 pr_err("%s: pci_enable_device failed\n", __func__);
2957                 return -ENODEV;
2958         }
2959         dev->active = 1;
2960         pci_set_drvdata(pdev, dev);
2961
2962         /* PCI resource allocation */
2963         resource = pci_resource_start(pdev, 1);
2964         len = pci_resource_len(pdev, 1);
2965
2966         if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2967                 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2968                 retval = -EBUSY;
2969                 goto finished;
2970         }
2971         dev->phys_addr = resource;
2972         dev->mem_region = 1;
2973
2974         dev->base_addr = ioremap_nocache(resource, len);
2975         if (!dev->base_addr) {
2976                 pr_err("%s: device memory cannot be mapped\n", __func__);
2977                 retval = -ENOMEM;
2978                 goto finished;
2979         }
2980         if (!pdev->irq) {
2981                 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2982                 retval = -ENODEV;
2983                 goto finished;
2984         }
2985         pch_udc = dev;
2986         /* initialize the hardware */
2987         if (pch_udc_pcd_init(dev)) {
2988                 retval = -ENODEV;
2989                 goto finished;
2990         }
2991         if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2992                         dev)) {
2993                 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2994                         pdev->irq);
2995                 retval = -ENODEV;
2996                 goto finished;
2997         }
2998         dev->irq = pdev->irq;
2999         dev->irq_registered = 1;
3000
3001         pci_set_master(pdev);
3002         pci_try_set_mwi(pdev);
3003
3004         /* device struct setup */
3005         spin_lock_init(&dev->lock);
3006         dev->pdev = pdev;
3007         dev->gadget.ops = &pch_udc_ops;
3008
3009         retval = init_dma_pools(dev);
3010         if (retval)
3011                 goto finished;
3012
3013         dev_set_name(&dev->gadget.dev, "gadget");
3014         dev->gadget.dev.parent = &pdev->dev;
3015         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3016         dev->gadget.dev.release = gadget_release;
3017         dev->gadget.name = KBUILD_MODNAME;
3018         dev->gadget.is_dualspeed = 1;
3019
3020         retval = device_register(&dev->gadget.dev);
3021         if (retval)
3022                 goto finished;
3023         dev->registered = 1;
3024
3025         /* Put the device in disconnected state till a driver is bound */
3026         pch_udc_set_disconnect(dev);
3027         retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3028         if (retval)
3029                 goto finished;
3030         return 0;
3031
3032 finished:
3033         pch_udc_remove(pdev);
3034         return retval;
3035 }
3036
3037 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
3038         {
3039                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3040                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3041                 .class_mask = 0xffffffff,
3042         },
3043         {
3044                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3045                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3046                 .class_mask = 0xffffffff,
3047         },
3048         {
3049                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3050                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3051                 .class_mask = 0xffffffff,
3052         },
3053         { 0 },
3054 };
3055
3056 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3057
3058
3059 static struct pci_driver pch_udc_driver = {
3060         .name = KBUILD_MODNAME,
3061         .id_table =     pch_udc_pcidev_id,
3062         .probe =        pch_udc_probe,
3063         .remove =       pch_udc_remove,
3064         .suspend =      pch_udc_suspend,
3065         .resume =       pch_udc_resume,
3066         .shutdown =     pch_udc_shutdown,
3067 };
3068
3069 static int __init pch_udc_pci_init(void)
3070 {
3071         return pci_register_driver(&pch_udc_driver);
3072 }
3073 module_init(pch_udc_pci_init);
3074
3075 static void __exit pch_udc_pci_exit(void)
3076 {
3077         pci_unregister_driver(&pch_udc_driver);
3078 }
3079 module_exit(pch_udc_pci_exit);
3080
3081 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3082 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3083 MODULE_LICENSE("GPL");