drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 159         switch (max_lane_count) {
 160         case 1: case 2: case 4:
 161                 break;
 162         default:
 163                 max_lane_count = 4;
 164         }
 165         return max_lane_count;
 166 }
 167
 168 static int
 169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 170 {
 171         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 172
 173         switch (max_link_bw) {
 174         case DP_LINK_BW_1_62:
 175         case DP_LINK_BW_2_7:
 176                 break;
 177         default:
 178                 max_link_bw = DP_LINK_BW_1_62;
 179                 break;
 180         }
 181         return max_link_bw;
 182 }
 183
 184 static int
 185 intel_dp_link_clock(uint8_t link_bw)
 186 {
 187         if (link_bw == DP_LINK_BW_2_7)
 188                 return 270000;
 189         else
 190                 return 162000;
 191 }
 192
 193 /*
 194  * The units on the numbers in the next two are... bizarre.  Examples will
 195  * make it clearer; this one parallels an example in the eDP spec.
 196  *
 197  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 198  *
 199  *     270000 * 1 * 8 / 10 == 216000
 200  *
 201  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 202  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 203  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 204  * 119000.  At 18bpp that's 2142000 kilobits per second.
 205  *
 206  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 207  * get the result in decakilobits instead of kilobits.
 208  */
 209
 210 static int
 211 intel_dp_link_required(int pixel_clock, int bpp)
 212 {
 213         return (pixel_clock * bpp + 9) / 10;
 214 }
 215
 216 static int
 217 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 218 {
 219         return (max_link_clock * max_lanes * 8) / 10;
 220 }
 221
 222 static bool
 223 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 224                           struct drm_display_mode *mode,
 225                           struct drm_display_mode *adjusted_mode)
 226 {
 227         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 228         int max_lanes = intel_dp_max_lane_count(intel_dp);
 229         int max_rate, mode_rate;
 230
 231         mode_rate = intel_dp_link_required(mode->clock, 24);
 232         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 233
 234         if (mode_rate > max_rate) {
 235                 mode_rate = intel_dp_link_required(mode->clock, 18);
 236                 if (mode_rate > max_rate)
 237                         return false;
 238
 239                 if (adjusted_mode)
 240                         adjusted_mode->private_flags
 241                                 |= INTEL_MODE_DP_FORCE_6BPC;
 242
 243                 return true;
 244         }
 245
 246         return true;
 247 }
 248
 249 static int
 250 intel_dp_mode_valid(struct drm_connector *connector,
 251                     struct drm_display_mode *mode)
 252 {
 253         struct intel_dp *intel_dp = intel_attached_dp(connector);
 254
 255         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 256                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 257                         return MODE_PANEL;
 258
 259                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 260                         return MODE_PANEL;
 261         }
 262
 263         if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
 264                 return MODE_CLOCK_HIGH;
 265
 266         if (mode->clock < 10000)
 267                 return MODE_CLOCK_LOW;
 268
 269         return MODE_OK;
 270 }
 271
 272 static uint32_t
 273 pack_aux(uint8_t *src, int src_bytes)
 274 {
 275         int     i;
 276         uint32_t v = 0;
 277
 278         if (src_bytes > 4)
 279                 src_bytes = 4;
 280         for (i = 0; i < src_bytes; i++)
 281                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 282         return v;
 283 }
 284
 285 static void
 286 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 287 {
 288         int i;
 289         if (dst_bytes > 4)
 290                 dst_bytes = 4;
 291         for (i = 0; i < dst_bytes; i++)
 292                 dst[i] = src >> ((3-i) * 8);
 293 }
 294
 295 /* hrawclock is 1/4 the FSB frequency */
 296 static int
 297 intel_hrawclk(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         uint32_t clkcfg;
 301
 302         clkcfg = I915_READ(CLKCFG);
 303         switch (clkcfg & CLKCFG_FSB_MASK) {
 304         case CLKCFG_FSB_400:
 305                 return 100;
 306         case CLKCFG_FSB_533:
 307                 return 133;
 308         case CLKCFG_FSB_667:
 309                 return 166;
 310         case CLKCFG_FSB_800:
 311                 return 200;
 312         case CLKCFG_FSB_1067:
 313                 return 266;
 314         case CLKCFG_FSB_1333:
 315                 return 333;
 316         /* these two are just a guess; one of them might be right */
 317         case CLKCFG_FSB_1600:
 318         case CLKCFG_FSB_1600_ALT:
 319                 return 400;
 320         default:
 321                 return 133;
 322         }
 323 }
 324
 325 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 326 {
 327         struct drm_device *dev = intel_dp->base.base.dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329
 330         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 331 }
 332
 333 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 334 {
 335         struct drm_device *dev = intel_dp->base.base.dev;
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337
 338         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 339 }
 340
 341 static void
 342 intel_dp_check_edp(struct intel_dp *intel_dp)
 343 {
 344         struct drm_device *dev = intel_dp->base.base.dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346
 347         if (!is_edp(intel_dp))
 348                 return;
 349         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 350                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 351                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 352                               I915_READ(PCH_PP_STATUS),
 353                               I915_READ(PCH_PP_CONTROL));
 354         }
 355 }
 356
 357 static int
 358 intel_dp_aux_ch(struct intel_dp *intel_dp,
 359                 uint8_t *send, int send_bytes,
 360                 uint8_t *recv, int recv_size)
 361 {
 362         uint32_t output_reg = intel_dp->output_reg;
 363         struct drm_device *dev = intel_dp->base.base.dev;
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         uint32_t ch_ctl = output_reg + 0x10;
 366         uint32_t ch_data = ch_ctl + 4;
 367         int i;
 368         int recv_bytes;
 369         uint32_t status;
 370         uint32_t aux_clock_divider;
 371         int try, precharge;
 372
 373         intel_dp_check_edp(intel_dp);
 374         /* The clock divider is based off the hrawclk,
 375          * and would like to run at 2MHz. So, take the
 376          * hrawclk value and divide by 2 and use that
 377          *
 378          * Note that PCH attached eDP panels should use a 125MHz input
 379          * clock divider.
 380          */
 381         if (is_cpu_edp(intel_dp)) {
 382                 if (IS_GEN6(dev) || IS_GEN7(dev))
 383                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 384                 else
 385                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 386         } else if (HAS_PCH_SPLIT(dev))
 387                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 388         else
 389                 aux_clock_divider = intel_hrawclk(dev) / 2;
 390
 391         if (IS_GEN6(dev))
 392                 precharge = 3;
 393         else
 394                 precharge = 5;
 395
 396         /* Try to wait for any previous AUX channel activity */
 397         for (try = 0; try < 3; try++) {
 398                 status = I915_READ(ch_ctl);
 399                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 400                         break;
 401                 msleep(1);
 402         }
 403
 404         if (try == 3) {
 405                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 406                      I915_READ(ch_ctl));
 407                 return -EBUSY;
 408         }
 409
 410         /* Must try at least 3 times according to DP spec */
 411         for (try = 0; try < 5; try++) {
 412                 /* Load the send data into the aux channel data registers */
 413                 for (i = 0; i < send_bytes; i += 4)
 414                         I915_WRITE(ch_data + i,
 415                                    pack_aux(send + i, send_bytes - i));
 416
 417                 /* Send the command and wait for it to complete */
 418                 I915_WRITE(ch_ctl,
 419                            DP_AUX_CH_CTL_SEND_BUSY |
 420                            DP_AUX_CH_CTL_TIME_OUT_400us |
 421                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 422                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 423                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 424                            DP_AUX_CH_CTL_DONE |
 425                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 426                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 427                 for (;;) {
 428                         status = I915_READ(ch_ctl);
 429                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 430                                 break;
 431                         udelay(100);
 432                 }
 433
 434                 /* Clear done status and any errors */
 435                 I915_WRITE(ch_ctl,
 436                            status |
 437                            DP_AUX_CH_CTL_DONE |
 438                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 439                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 440                 if (status & DP_AUX_CH_CTL_DONE)
 441                         break;
 442         }
 443
 444         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 445                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 446                 return -EBUSY;
 447         }
 448
 449         /* Check for timeout or receive error.
 450          * Timeouts occur when the sink is not connected
 451          */
 452         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 453                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 454                 return -EIO;
 455         }
 456
 457         /* Timeouts occur when the device isn't connected, so they're
 458          * "normal" -- don't fill the kernel log with these */
 459         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 460                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 461                 return -ETIMEDOUT;
 462         }
 463
 464         /* Unload any bytes sent back from the other side */
 465         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 466                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 467         if (recv_bytes > recv_size)
 468                 recv_bytes = recv_size;
 469
 470         for (i = 0; i < recv_bytes; i += 4)
 471                 unpack_aux(I915_READ(ch_data + i),
 472                            recv + i, recv_bytes - i);
 473
 474         return recv_bytes;
 475 }
 476
 477 /* Write data to the aux channel in native mode */
 478 static int
 479 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 480                           uint16_t address, uint8_t *send, int send_bytes)
 481 {
 482         int ret;
 483         uint8_t msg[20];
 484         int msg_bytes;
 485         uint8_t ack;
 486
 487         intel_dp_check_edp(intel_dp);
 488         if (send_bytes > 16)
 489                 return -1;
 490         msg[0] = AUX_NATIVE_WRITE << 4;
 491         msg[1] = address >> 8;
 492         msg[2] = address & 0xff;
 493         msg[3] = send_bytes - 1;
 494         memcpy(&msg[4], send, send_bytes);
 495         msg_bytes = send_bytes + 4;
 496         for (;;) {
 497                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 498                 if (ret < 0)
 499                         return ret;
 500                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 501                         break;
 502                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 503                         udelay(100);
 504                 else
 505                         return -EIO;
 506         }
 507         return send_bytes;
 508 }
 509
 510 /* Write a single byte to the aux channel in native mode */
 511 static int
 512 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 513                             uint16_t address, uint8_t byte)
 514 {
 515         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 516 }
 517
 518 /* read bytes from a native aux channel */
 519 static int
 520 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 521                          uint16_t address, uint8_t *recv, int recv_bytes)
 522 {
 523         uint8_t msg[4];
 524         int msg_bytes;
 525         uint8_t reply[20];
 526         int reply_bytes;
 527         uint8_t ack;
 528         int ret;
 529
 530         intel_dp_check_edp(intel_dp);
 531         msg[0] = AUX_NATIVE_READ << 4;
 532         msg[1] = address >> 8;
 533         msg[2] = address & 0xff;
 534         msg[3] = recv_bytes - 1;
 535
 536         msg_bytes = 4;
 537         reply_bytes = recv_bytes + 1;
 538
 539         for (;;) {
 540                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 541                                       reply, reply_bytes);
 542                 if (ret == 0)
 543                         return -EPROTO;
 544                 if (ret < 0)
 545                         return ret;
 546                 ack = reply[0];
 547                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 548                         memcpy(recv, reply + 1, ret - 1);
 549                         return ret - 1;
 550                 }
 551                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 552                         udelay(100);
 553                 else
 554                         return -EIO;
 555         }
 556 }
 557
 558 static int
 559 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 560                     uint8_t write_byte, uint8_t *read_byte)
 561 {
 562         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 563         struct intel_dp *intel_dp = container_of(adapter,
 564                                                 struct intel_dp,
 565                                                 adapter);
 566         uint16_t address = algo_data->address;
 567         uint8_t msg[5];
 568         uint8_t reply[2];
 569         unsigned retry;
 570         int msg_bytes;
 571         int reply_bytes;
 572         int ret;
 573
 574         intel_dp_check_edp(intel_dp);
 575         /* Set up the command byte */
 576         if (mode & MODE_I2C_READ)
 577                 msg[0] = AUX_I2C_READ << 4;
 578         else
 579                 msg[0] = AUX_I2C_WRITE << 4;
 580
 581         if (!(mode & MODE_I2C_STOP))
 582                 msg[0] |= AUX_I2C_MOT << 4;
 583
 584         msg[1] = address >> 8;
 585         msg[2] = address;
 586
 587         switch (mode) {
 588         case MODE_I2C_WRITE:
 589                 msg[3] = 0;
 590                 msg[4] = write_byte;
 591                 msg_bytes = 5;
 592                 reply_bytes = 1;
 593                 break;
 594         case MODE_I2C_READ:
 595                 msg[3] = 0;
 596                 msg_bytes = 4;
 597                 reply_bytes = 2;
 598                 break;
 599         default:
 600                 msg_bytes = 3;
 601                 reply_bytes = 1;
 602                 break;
 603         }
 604
 605         for (retry = 0; retry < 5; retry++) {
 606                 ret = intel_dp_aux_ch(intel_dp,
 607                                       msg, msg_bytes,
 608                                       reply, reply_bytes);
 609                 if (ret < 0) {
 610                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 611                         return ret;
 612                 }
 613
 614                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 615                 case AUX_NATIVE_REPLY_ACK:
 616                         /* I2C-over-AUX Reply field is only valid
 617                          * when paired with AUX ACK.
 618                          */
 619                         break;
 620                 case AUX_NATIVE_REPLY_NACK:
 621                         DRM_DEBUG_KMS("aux_ch native nack\n");
 622                         return -EREMOTEIO;
 623                 case AUX_NATIVE_REPLY_DEFER:
 624                         udelay(100);
 625                         continue;
 626                 default:
 627                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 628                                   reply[0]);
 629                         return -EREMOTEIO;
 630                 }
 631
 632                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 633                 case AUX_I2C_REPLY_ACK:
 634                         if (mode == MODE_I2C_READ) {
 635                                 *read_byte = reply[1];
 636                         }
 637                         return reply_bytes - 1;
 638                 case AUX_I2C_REPLY_NACK:
 639                         DRM_DEBUG_KMS("aux_i2c nack\n");
 640                         return -EREMOTEIO;
 641                 case AUX_I2C_REPLY_DEFER:
 642                         DRM_DEBUG_KMS("aux_i2c defer\n");
 643                         udelay(100);
 644                         break;
 645                 default:
 646                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 647                         return -EREMOTEIO;
 648                 }
 649         }
 650
 651         DRM_ERROR("too many retries, giving up\n");
 652         return -EREMOTEIO;
 653 }
 654
 655 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 656 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 657
 658 static int
 659 intel_dp_i2c_init(struct intel_dp *intel_dp,
 660                   struct intel_connector *intel_connector, const char *name)
 661 {
 662         int     ret;
 663
 664         DRM_DEBUG_KMS("i2c_init %s\n", name);
 665         intel_dp->algo.running = false;
 666         intel_dp->algo.address = 0;
 667         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 668
 669         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 670         intel_dp->adapter.owner = THIS_MODULE;
 671         intel_dp->adapter.class = I2C_CLASS_DDC;
 672         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 673         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 674         intel_dp->adapter.algo_data = &intel_dp->algo;
 675         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 676
 677         ironlake_edp_panel_vdd_on(intel_dp);
 678         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 679         ironlake_edp_panel_vdd_off(intel_dp, false);
 680         return ret;
 681 }
 682
 683 static bool
 684 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 685                     struct drm_display_mode *adjusted_mode)
 686 {
 687         struct drm_device *dev = encoder->dev;
 688         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 689         int lane_count, clock;
 690         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 691         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 692         int bpp;
 693         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 694
 695         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 696                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 697                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 698                                         mode, adjusted_mode);
 699                 /*
 700                  * the mode->clock is used to calculate the Data&Link M/N
 701                  * of the pipe. For the eDP the fixed clock should be used.
 702                  */
 703                 mode->clock = intel_dp->panel_fixed_mode->clock;
 704         }
 705
 706         if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
 707                 return false;
 708
 709         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 710
 711         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 712                 for (clock = 0; clock <= max_clock; clock++) {
 713                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 714
 715                         if (intel_dp_link_required(mode->clock, bpp)
 716                                         <= link_avail) {
 717                                 intel_dp->link_bw = bws[clock];
 718                                 intel_dp->lane_count = lane_count;
 719                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 720                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 721                                                 "count %d clock %d\n",
 722                                        intel_dp->link_bw, intel_dp->lane_count,
 723                                        adjusted_mode->clock);
 724                                 return true;
 725                         }
 726                 }
 727         }
 728
 729         return false;
 730 }
 731
 732 struct intel_dp_m_n {
 733         uint32_t        tu;
 734         uint32_t        gmch_m;
 735         uint32_t        gmch_n;
 736         uint32_t        link_m;
 737         uint32_t        link_n;
 738 };
 739
 740 static void
 741 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 742 {
 743         while (*num > 0xffffff || *den > 0xffffff) {
 744                 *num >>= 1;
 745                 *den >>= 1;
 746         }
 747 }
 748
 749 static void
 750 intel_dp_compute_m_n(int bpp,
 751                      int nlanes,
 752                      int pixel_clock,
 753                      int link_clock,
 754                      struct intel_dp_m_n *m_n)
 755 {
 756         m_n->tu = 64;
 757         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 758         m_n->gmch_n = link_clock * nlanes;
 759         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 760         m_n->link_m = pixel_clock;
 761         m_n->link_n = link_clock;
 762         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 763 }
 764
 765 void
 766 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 767                  struct drm_display_mode *adjusted_mode)
 768 {
 769         struct drm_device *dev = crtc->dev;
 770         struct drm_mode_config *mode_config = &dev->mode_config;
 771         struct drm_encoder *encoder;
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 774         int lane_count = 4;
 775         struct intel_dp_m_n m_n;
 776         int pipe = intel_crtc->pipe;
 777
 778         /*
 779          * Find the lane count in the intel_encoder private
 780          */
 781         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 782                 struct intel_dp *intel_dp;
 783
 784                 if (encoder->crtc != crtc)
 785                         continue;
 786
 787                 intel_dp = enc_to_intel_dp(encoder);
 788                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 789                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 790                 {
 791                         lane_count = intel_dp->lane_count;
 792                         break;
 793                 }
 794         }
 795
 796         /*
 797          * Compute the GMCH and Link ratios. The '3' here is
 798          * the number of bytes_per_pixel post-LUT, which we always
 799          * set up for 8-bits of R/G/B, or 3 bytes total.
 800          */
 801         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 802                              mode->clock, adjusted_mode->clock, &m_n);
 803
 804         if (HAS_PCH_SPLIT(dev)) {
 805                 I915_WRITE(TRANSDATA_M1(pipe),
 806                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 807                            m_n.gmch_m);
 808                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 809                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 810                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 811         } else {
 812                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 813                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 814                            m_n.gmch_m);
 815                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 816                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 817                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 818         }
 819 }
 820
 821 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 822 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 823
 824 static void
 825 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 826                   struct drm_display_mode *adjusted_mode)
 827 {
 828         struct drm_device *dev = encoder->dev;
 829         struct drm_i915_private *dev_priv = dev->dev_private;
 830         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 831         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 833
 834         /* Turn on the eDP PLL if needed */
 835         if (is_edp(intel_dp)) {
 836                 if (!is_pch_edp(intel_dp))
 837                         ironlake_edp_pll_on(encoder);
 838                 else
 839                         ironlake_edp_pll_off(encoder);
 840         }
 841
 842         /*
 843          * There are four kinds of DP registers:
 844          *
 845          *      IBX PCH
 846          *      SNB CPU
 847          *      IVB CPU
 848          *      CPT PCH
 849          *
 850          * IBX PCH and CPU are the same for almost everything,
 851          * except that the CPU DP PLL is configured in this
 852          * register
 853          *
 854          * CPT PCH is quite different, having many bits moved
 855          * to the TRANS_DP_CTL register instead. That
 856          * configuration happens (oddly) in ironlake_pch_enable
 857          */
 858
 859         /* Preserve the BIOS-computed detected bit. This is
 860          * supposed to be read-only.
 861          */
 862         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 863         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 864
 865         /* Handle DP bits in common between all three register formats */
 866
 867         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 868
 869         switch (intel_dp->lane_count) {
 870         case 1:
 871                 intel_dp->DP |= DP_PORT_WIDTH_1;
 872                 break;
 873         case 2:
 874                 intel_dp->DP |= DP_PORT_WIDTH_2;
 875                 break;
 876         case 4:
 877                 intel_dp->DP |= DP_PORT_WIDTH_4;
 878                 break;
 879         }
 880         if (intel_dp->has_audio) {
 881                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 882                                  pipe_name(intel_crtc->pipe));
 883                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 884                 intel_write_eld(encoder, adjusted_mode);
 885         }
 886         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 887         intel_dp->link_configuration[0] = intel_dp->link_bw;
 888         intel_dp->link_configuration[1] = intel_dp->lane_count;
 889         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 890         /*
 891          * Check for DPCD version > 1.1 and enhanced framing support
 892          */
 893         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 894             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 895                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 896         }
 897
 898         /* Split out the IBX/CPU vs CPT settings */
 899
 900         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 901                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 902                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 903                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 904                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 905                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 906
 907                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 908                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 909
 910                 intel_dp->DP |= intel_crtc->pipe << 29;
 911
 912                 /* don't miss out required setting for eDP */
 913                 intel_dp->DP |= DP_PLL_ENABLE;
 914                 if (adjusted_mode->clock < 200000)
 915                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 916                 else
 917                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 918         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 919                 intel_dp->DP |= intel_dp->color_range;
 920
 921                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 922                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 923                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 924                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 925                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 926
 927                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 928                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 929
 930                 if (intel_crtc->pipe == 1)
 931                         intel_dp->DP |= DP_PIPEB_SELECT;
 932
 933                 if (is_cpu_edp(intel_dp)) {
 934                         /* don't miss out required setting for eDP */
 935                         intel_dp->DP |= DP_PLL_ENABLE;
 936                         if (adjusted_mode->clock < 200000)
 937                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 938                         else
 939                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 940                 }
 941         } else {
 942                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 943         }
 944 }
 945
 946 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 947 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 948
 949 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 950 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 951
 952 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 953 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 954
 955 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 956                                        u32 mask,
 957                                        u32 value)
 958 {
 959         struct drm_device *dev = intel_dp->base.base.dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961
 962         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 963                       mask, value,
 964                       I915_READ(PCH_PP_STATUS),
 965                       I915_READ(PCH_PP_CONTROL));
 966
 967         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 968                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 969                           I915_READ(PCH_PP_STATUS),
 970                           I915_READ(PCH_PP_CONTROL));
 971         }
 972 }
 973
 974 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 975 {
 976         DRM_DEBUG_KMS("Wait for panel power on\n");
 977         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 978 }
 979
 980 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 981 {
 982         DRM_DEBUG_KMS("Wait for panel power off time\n");
 983         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 984 }
 985
 986 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 987 {
 988         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 989         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 990 }
 991
 992
 993 /* Read the current pp_control value, unlocking the register if it
 994  * is locked
 995  */
 996
 997 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 998 {
 999         u32     control = I915_READ(PCH_PP_CONTROL);
1000
1001         control &= ~PANEL_UNLOCK_MASK;
1002         control |= PANEL_UNLOCK_REGS;
1003         return control;
1004 }
1005
1006 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1007 {
1008         struct drm_device *dev = intel_dp->base.base.dev;
1009         struct drm_i915_private *dev_priv = dev->dev_private;
1010         u32 pp;
1011
1012         if (!is_edp(intel_dp))
1013                 return;
1014         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1015
1016         WARN(intel_dp->want_panel_vdd,
1017              "eDP VDD already requested on\n");
1018
1019         intel_dp->want_panel_vdd = true;
1020
1021         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1022                 DRM_DEBUG_KMS("eDP VDD already on\n");
1023                 return;
1024         }
1025
1026         if (!ironlake_edp_have_panel_power(intel_dp))
1027                 ironlake_wait_panel_power_cycle(intel_dp);
1028
1029         pp = ironlake_get_pp_control(dev_priv);
1030         pp |= EDP_FORCE_VDD;
1031         I915_WRITE(PCH_PP_CONTROL, pp);
1032         POSTING_READ(PCH_PP_CONTROL);
1033         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1034                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1035
1036         /*
1037          * If the panel wasn't on, delay before accessing aux channel
1038          */
1039         if (!ironlake_edp_have_panel_power(intel_dp)) {
1040                 DRM_DEBUG_KMS("eDP was not running\n");
1041                 msleep(intel_dp->panel_power_up_delay);
1042         }
1043 }
1044
1045 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1046 {
1047         struct drm_device *dev = intel_dp->base.base.dev;
1048         struct drm_i915_private *dev_priv = dev->dev_private;
1049         u32 pp;
1050
1051         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1052                 pp = ironlake_get_pp_control(dev_priv);
1053                 pp &= ~EDP_FORCE_VDD;
1054                 I915_WRITE(PCH_PP_CONTROL, pp);
1055                 POSTING_READ(PCH_PP_CONTROL);
1056
1057                 /* Make sure sequencer is idle before allowing subsequent activity */
1058                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1059                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1060
1061                 msleep(intel_dp->panel_power_down_delay);
1062         }
1063 }
1064
1065 static void ironlake_panel_vdd_work(struct work_struct *__work)
1066 {
1067         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1068                                                  struct intel_dp, panel_vdd_work);
1069         struct drm_device *dev = intel_dp->base.base.dev;
1070
1071         mutex_lock(&dev->mode_config.mutex);
1072         ironlake_panel_vdd_off_sync(intel_dp);
1073         mutex_unlock(&dev->mode_config.mutex);
1074 }
1075
1076 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1077 {
1078         if (!is_edp(intel_dp))
1079                 return;
1080
1081         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1082         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1083
1084         intel_dp->want_panel_vdd = false;
1085
1086         if (sync) {
1087                 ironlake_panel_vdd_off_sync(intel_dp);
1088         } else {
1089                 /*
1090                  * Queue the timer to fire a long
1091                  * time from now (relative to the power down delay)
1092                  * to keep the panel power up across a sequence of operations
1093                  */
1094                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1095                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1096         }
1097 }
1098
1099 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1100 {
1101         struct drm_device *dev = intel_dp->base.base.dev;
1102         struct drm_i915_private *dev_priv = dev->dev_private;
1103         u32 pp;
1104
1105         if (!is_edp(intel_dp))
1106                 return;
1107
1108         DRM_DEBUG_KMS("Turn eDP power on\n");
1109
1110         if (ironlake_edp_have_panel_power(intel_dp)) {
1111                 DRM_DEBUG_KMS("eDP power already on\n");
1112                 return;
1113         }
1114
1115         ironlake_wait_panel_power_cycle(intel_dp);
1116
1117         pp = ironlake_get_pp_control(dev_priv);
1118         if (IS_GEN5(dev)) {
1119                 /* ILK workaround: disable reset around power sequence */
1120                 pp &= ~PANEL_POWER_RESET;
1121                 I915_WRITE(PCH_PP_CONTROL, pp);
1122                 POSTING_READ(PCH_PP_CONTROL);
1123         }
1124
1125         pp |= POWER_TARGET_ON;
1126         if (!IS_GEN5(dev))
1127                 pp |= PANEL_POWER_RESET;
1128
1129         I915_WRITE(PCH_PP_CONTROL, pp);
1130         POSTING_READ(PCH_PP_CONTROL);
1131
1132         ironlake_wait_panel_on(intel_dp);
1133
1134         if (IS_GEN5(dev)) {
1135                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1136                 I915_WRITE(PCH_PP_CONTROL, pp);
1137                 POSTING_READ(PCH_PP_CONTROL);
1138         }
1139 }
1140
1141 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1142 {
1143         struct drm_device *dev = intel_dp->base.base.dev;
1144         struct drm_i915_private *dev_priv = dev->dev_private;
1145         u32 pp;
1146
1147         if (!is_edp(intel_dp))
1148                 return;
1149
1150         DRM_DEBUG_KMS("Turn eDP power off\n");
1151
1152         WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1153
1154         pp = ironlake_get_pp_control(dev_priv);
1155         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1156         I915_WRITE(PCH_PP_CONTROL, pp);
1157         POSTING_READ(PCH_PP_CONTROL);
1158
1159         ironlake_wait_panel_off(intel_dp);
1160 }
1161
1162 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1163 {
1164         struct drm_device *dev = intel_dp->base.base.dev;
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         u32 pp;
1167
1168         if (!is_edp(intel_dp))
1169                 return;
1170
1171         DRM_DEBUG_KMS("\n");
1172         /*
1173          * If we enable the backlight right away following a panel power
1174          * on, we may see slight flicker as the panel syncs with the eDP
1175          * link.  So delay a bit to make sure the image is solid before
1176          * allowing it to appear.
1177          */
1178         msleep(intel_dp->backlight_on_delay);
1179         pp = ironlake_get_pp_control(dev_priv);
1180         pp |= EDP_BLC_ENABLE;
1181         I915_WRITE(PCH_PP_CONTROL, pp);
1182         POSTING_READ(PCH_PP_CONTROL);
1183 }
1184
1185 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1186 {
1187         struct drm_device *dev = intel_dp->base.base.dev;
1188         struct drm_i915_private *dev_priv = dev->dev_private;
1189         u32 pp;
1190
1191         if (!is_edp(intel_dp))
1192                 return;
1193
1194         DRM_DEBUG_KMS("\n");
1195         pp = ironlake_get_pp_control(dev_priv);
1196         pp &= ~EDP_BLC_ENABLE;
1197         I915_WRITE(PCH_PP_CONTROL, pp);
1198         POSTING_READ(PCH_PP_CONTROL);
1199         msleep(intel_dp->backlight_off_delay);
1200 }
1201
1202 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1203 {
1204         struct drm_device *dev = encoder->dev;
1205         struct drm_i915_private *dev_priv = dev->dev_private;
1206         u32 dpa_ctl;
1207
1208         DRM_DEBUG_KMS("\n");
1209         dpa_ctl = I915_READ(DP_A);
1210         dpa_ctl |= DP_PLL_ENABLE;
1211         I915_WRITE(DP_A, dpa_ctl);
1212         POSTING_READ(DP_A);
1213         udelay(200);
1214 }
1215
1216 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1217 {
1218         struct drm_device *dev = encoder->dev;
1219         struct drm_i915_private *dev_priv = dev->dev_private;
1220         u32 dpa_ctl;
1221
1222         dpa_ctl = I915_READ(DP_A);
1223         dpa_ctl &= ~DP_PLL_ENABLE;
1224         I915_WRITE(DP_A, dpa_ctl);
1225         POSTING_READ(DP_A);
1226         udelay(200);
1227 }
1228
1229 /* If the sink supports it, try to set the power state appropriately */
1230 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1231 {
1232         int ret, i;
1233
1234         /* Should have a valid DPCD by this point */
1235         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1236                 return;
1237
1238         if (mode != DRM_MODE_DPMS_ON) {
1239                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1240                                                   DP_SET_POWER_D3);
1241                 if (ret != 1)
1242                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1243         } else {
1244                 /*
1245                  * When turning on, we need to retry for 1ms to give the sink
1246                  * time to wake up.
1247                  */
1248                 for (i = 0; i < 3; i++) {
1249                         ret = intel_dp_aux_native_write_1(intel_dp,
1250                                                           DP_SET_POWER,
1251                                                           DP_SET_POWER_D0);
1252                         if (ret == 1)
1253                                 break;
1254                         msleep(1);
1255                 }
1256         }
1257 }
1258
1259 static void intel_dp_prepare(struct drm_encoder *encoder)
1260 {
1261         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1262
1263         ironlake_edp_backlight_off(intel_dp);
1264         ironlake_edp_panel_off(intel_dp);
1265
1266         /* Wake up the sink first */
1267         ironlake_edp_panel_vdd_on(intel_dp);
1268         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1269         intel_dp_link_down(intel_dp);
1270         ironlake_edp_panel_vdd_off(intel_dp, false);
1271
1272         /* Make sure the panel is off before trying to
1273          * change the mode
1274          */
1275 }
1276
1277 static void intel_dp_commit(struct drm_encoder *encoder)
1278 {
1279         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1280         struct drm_device *dev = encoder->dev;
1281         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1282
1283         ironlake_edp_panel_vdd_on(intel_dp);
1284         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1285         intel_dp_start_link_train(intel_dp);
1286         ironlake_edp_panel_on(intel_dp);
1287         ironlake_edp_panel_vdd_off(intel_dp, true);
1288         intel_dp_complete_link_train(intel_dp);
1289         ironlake_edp_backlight_on(intel_dp);
1290
1291         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1292
1293         if (HAS_PCH_CPT(dev))
1294                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1295 }
1296
1297 static void
1298 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1299 {
1300         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1301         struct drm_device *dev = encoder->dev;
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1304
1305         if (mode != DRM_MODE_DPMS_ON) {
1306                 ironlake_edp_backlight_off(intel_dp);
1307                 ironlake_edp_panel_off(intel_dp);
1308
1309                 ironlake_edp_panel_vdd_on(intel_dp);
1310                 intel_dp_sink_dpms(intel_dp, mode);
1311                 intel_dp_link_down(intel_dp);
1312                 ironlake_edp_panel_vdd_off(intel_dp, false);
1313
1314                 if (is_cpu_edp(intel_dp))
1315                         ironlake_edp_pll_off(encoder);
1316         } else {
1317                 if (is_cpu_edp(intel_dp))
1318                         ironlake_edp_pll_on(encoder);
1319
1320                 ironlake_edp_panel_vdd_on(intel_dp);
1321                 intel_dp_sink_dpms(intel_dp, mode);
1322                 if (!(dp_reg & DP_PORT_EN)) {
1323                         intel_dp_start_link_train(intel_dp);
1324                         ironlake_edp_panel_on(intel_dp);
1325                         ironlake_edp_panel_vdd_off(intel_dp, true);
1326                         intel_dp_complete_link_train(intel_dp);
1327                 } else
1328                         ironlake_edp_panel_vdd_off(intel_dp, false);
1329                 ironlake_edp_backlight_on(intel_dp);
1330         }
1331         intel_dp->dpms_mode = mode;
1332 }
1333
1334 /*
1335  * Native read with retry for link status and receiver capability reads for
1336  * cases where the sink may still be asleep.
1337  */
1338 static bool
1339 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1340                                uint8_t *recv, int recv_bytes)
1341 {
1342         int ret, i;
1343
1344         /*
1345          * Sinks are *supposed* to come up within 1ms from an off state,
1346          * but we're also supposed to retry 3 times per the spec.
1347          */
1348         for (i = 0; i < 3; i++) {
1349                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1350                                                recv_bytes);
1351                 if (ret == recv_bytes)
1352                         return true;
1353                 msleep(1);
1354         }
1355
1356         return false;
1357 }
1358
1359 /*
1360  * Fetch AUX CH registers 0x202 - 0x207 which contain
1361  * link status information
1362  */
1363 static bool
1364 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1365 {
1366         return intel_dp_aux_native_read_retry(intel_dp,
1367                                               DP_LANE0_1_STATUS,
1368                                               link_status,
1369                                               DP_LINK_STATUS_SIZE);
1370 }
1371
1372 static uint8_t
1373 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1374                      int r)
1375 {
1376         return link_status[r - DP_LANE0_1_STATUS];
1377 }
1378
1379 static uint8_t
1380 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1381                                  int lane)
1382 {
1383         int         s = ((lane & 1) ?
1384                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1385                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1386         uint8_t l = adjust_request[lane>>1];
1387
1388         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1389 }
1390
1391 static uint8_t
1392 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1393                                       int lane)
1394 {
1395         int         s = ((lane & 1) ?
1396                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1397                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1398         uint8_t l = adjust_request[lane>>1];
1399
1400         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1401 }
1402
1403
1404 #if 0
1405 static char     *voltage_names[] = {
1406         "0.4V", "0.6V", "0.8V", "1.2V"
1407 };
1408 static char     *pre_emph_names[] = {
1409         "0dB", "3.5dB", "6dB", "9.5dB"
1410 };
1411 static char     *link_train_names[] = {
1412         "pattern 1", "pattern 2", "idle", "off"
1413 };
1414 #endif
1415
1416 /*
1417  * These are source-specific values; current Intel hardware supports
1418  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1419  */
1420
1421 static uint8_t
1422 intel_dp_voltage_max(struct intel_dp *intel_dp)
1423 {
1424         struct drm_device *dev = intel_dp->base.base.dev;
1425
1426         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1427                 return DP_TRAIN_VOLTAGE_SWING_800;
1428         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1429                 return DP_TRAIN_VOLTAGE_SWING_1200;
1430         else
1431                 return DP_TRAIN_VOLTAGE_SWING_800;
1432 }
1433
1434 static uint8_t
1435 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1436 {
1437         struct drm_device *dev = intel_dp->base.base.dev;
1438
1439         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1440                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1441                 case DP_TRAIN_VOLTAGE_SWING_400:
1442                         return DP_TRAIN_PRE_EMPHASIS_6;
1443                 case DP_TRAIN_VOLTAGE_SWING_600:
1444                 case DP_TRAIN_VOLTAGE_SWING_800:
1445                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1446                 default:
1447                         return DP_TRAIN_PRE_EMPHASIS_0;
1448                 }
1449         } else {
1450                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1451                 case DP_TRAIN_VOLTAGE_SWING_400:
1452                         return DP_TRAIN_PRE_EMPHASIS_6;
1453                 case DP_TRAIN_VOLTAGE_SWING_600:
1454                         return DP_TRAIN_PRE_EMPHASIS_6;
1455                 case DP_TRAIN_VOLTAGE_SWING_800:
1456                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1457                 case DP_TRAIN_VOLTAGE_SWING_1200:
1458                 default:
1459                         return DP_TRAIN_PRE_EMPHASIS_0;
1460                 }
1461         }
1462 }
1463
1464 static void
1465 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1466 {
1467         uint8_t v = 0;
1468         uint8_t p = 0;
1469         int lane;
1470         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1471         uint8_t voltage_max;
1472         uint8_t preemph_max;
1473
1474         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1475                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1476                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1477
1478                 if (this_v > v)
1479                         v = this_v;
1480                 if (this_p > p)
1481                         p = this_p;
1482         }
1483
1484         voltage_max = intel_dp_voltage_max(intel_dp);
1485         if (v >= voltage_max)
1486                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1487
1488         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1489         if (p >= preemph_max)
1490                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1491
1492         for (lane = 0; lane < 4; lane++)
1493                 intel_dp->train_set[lane] = v | p;
1494 }
1495
1496 static uint32_t
1497 intel_dp_signal_levels(uint8_t train_set)
1498 {
1499         uint32_t        signal_levels = 0;
1500
1501         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1502         case DP_TRAIN_VOLTAGE_SWING_400:
1503         default:
1504                 signal_levels |= DP_VOLTAGE_0_4;
1505                 break;
1506         case DP_TRAIN_VOLTAGE_SWING_600:
1507                 signal_levels |= DP_VOLTAGE_0_6;
1508                 break;
1509         case DP_TRAIN_VOLTAGE_SWING_800:
1510                 signal_levels |= DP_VOLTAGE_0_8;
1511                 break;
1512         case DP_TRAIN_VOLTAGE_SWING_1200:
1513                 signal_levels |= DP_VOLTAGE_1_2;
1514                 break;
1515         }
1516         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1517         case DP_TRAIN_PRE_EMPHASIS_0:
1518         default:
1519                 signal_levels |= DP_PRE_EMPHASIS_0;
1520                 break;
1521         case DP_TRAIN_PRE_EMPHASIS_3_5:
1522                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1523                 break;
1524         case DP_TRAIN_PRE_EMPHASIS_6:
1525                 signal_levels |= DP_PRE_EMPHASIS_6;
1526                 break;
1527         case DP_TRAIN_PRE_EMPHASIS_9_5:
1528                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1529                 break;
1530         }
1531         return signal_levels;
1532 }
1533
1534 /* Gen6's DP voltage swing and pre-emphasis control */
1535 static uint32_t
1536 intel_gen6_edp_signal_levels(uint8_t train_set)
1537 {
1538         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1539                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1540         switch (signal_levels) {
1541         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1542         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1543                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1544         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1545                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1546         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1547         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1548                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1549         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1550         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1551                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1552         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1553         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1554                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1555         default:
1556                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1557                               "0x%x\n", signal_levels);
1558                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1559         }
1560 }
1561
1562 /* Gen7's DP voltage swing and pre-emphasis control */
1563 static uint32_t
1564 intel_gen7_edp_signal_levels(uint8_t train_set)
1565 {
1566         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1567                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1568         switch (signal_levels) {
1569         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1570                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1571         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1572                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1573         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1574                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1575
1576         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1577                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1578         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1579                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1580
1581         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1582                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1583         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1584                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1585
1586         default:
1587                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1588                               "0x%x\n", signal_levels);
1589                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1590         }
1591 }
1592
1593 static uint8_t
1594 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1595                       int lane)
1596 {
1597         int s = (lane & 1) * 4;
1598         uint8_t l = link_status[lane>>1];
1599
1600         return (l >> s) & 0xf;
1601 }
1602
1603 /* Check for clock recovery is done on all channels */
1604 static bool
1605 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1606 {
1607         int lane;
1608         uint8_t lane_status;
1609
1610         for (lane = 0; lane < lane_count; lane++) {
1611                 lane_status = intel_get_lane_status(link_status, lane);
1612                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1613                         return false;
1614         }
1615         return true;
1616 }
1617
1618 /* Check to see if channel eq is done on all channels */
1619 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1620                          DP_LANE_CHANNEL_EQ_DONE|\
1621                          DP_LANE_SYMBOL_LOCKED)
1622 static bool
1623 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1624 {
1625         uint8_t lane_align;
1626         uint8_t lane_status;
1627         int lane;
1628
1629         lane_align = intel_dp_link_status(link_status,
1630                                           DP_LANE_ALIGN_STATUS_UPDATED);
1631         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1632                 return false;
1633         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1634                 lane_status = intel_get_lane_status(link_status, lane);
1635                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1636                         return false;
1637         }
1638         return true;
1639 }
1640
1641 static bool
1642 intel_dp_set_link_train(struct intel_dp *intel_dp,
1643                         uint32_t dp_reg_value,
1644                         uint8_t dp_train_pat)
1645 {
1646         struct drm_device *dev = intel_dp->base.base.dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         int ret;
1649
1650         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1651         POSTING_READ(intel_dp->output_reg);
1652
1653         intel_dp_aux_native_write_1(intel_dp,
1654                                     DP_TRAINING_PATTERN_SET,
1655                                     dp_train_pat);
1656
1657         ret = intel_dp_aux_native_write(intel_dp,
1658                                         DP_TRAINING_LANE0_SET,
1659                                         intel_dp->train_set,
1660                                         intel_dp->lane_count);
1661         if (ret != intel_dp->lane_count)
1662                 return false;
1663
1664         return true;
1665 }
1666
1667 /* Enable corresponding port and start training pattern 1 */
1668 static void
1669 intel_dp_start_link_train(struct intel_dp *intel_dp)
1670 {
1671         struct drm_device *dev = intel_dp->base.base.dev;
1672         struct drm_i915_private *dev_priv = dev->dev_private;
1673         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1674         int i;
1675         uint8_t voltage;
1676         bool clock_recovery = false;
1677         int voltage_tries, loop_tries;
1678         u32 reg;
1679         uint32_t DP = intel_dp->DP;
1680
1681         /*
1682          * On CPT we have to enable the port in training pattern 1, which
1683          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1684          * the port and wait for it to become active.
1685          */
1686         if (!HAS_PCH_CPT(dev)) {
1687                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1688                 POSTING_READ(intel_dp->output_reg);
1689                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690         }
1691
1692         /* Write the link configuration data */
1693         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1694                                   intel_dp->link_configuration,
1695                                   DP_LINK_CONFIGURATION_SIZE);
1696
1697         DP |= DP_PORT_EN;
1698
1699         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1700                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1701         else
1702                 DP &= ~DP_LINK_TRAIN_MASK;
1703         memset(intel_dp->train_set, 0, 4);
1704         voltage = 0xff;
1705         voltage_tries = 0;
1706         loop_tries = 0;
1707         clock_recovery = false;
1708         for (;;) {
1709                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1710                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1711                 uint32_t    signal_levels;
1712
1713
1714                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1715                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1716                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1717                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1718                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1719                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1720                 } else {
1721                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1722                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1723                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1724                 }
1725
1726                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1727                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1728                 else
1729                         reg = DP | DP_LINK_TRAIN_PAT_1;
1730
1731                 if (!intel_dp_set_link_train(intel_dp, reg,
1732                                              DP_TRAINING_PATTERN_1 |
1733                                              DP_LINK_SCRAMBLING_DISABLE))
1734                         break;
1735                 /* Set training pattern 1 */
1736
1737                 udelay(100);
1738                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1739                         DRM_ERROR("failed to get link status\n");
1740                         break;
1741                 }
1742
1743                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1744                         DRM_DEBUG_KMS("clock recovery OK\n");
1745                         clock_recovery = true;
1746                         break;
1747                 }
1748
1749                 /* Check to see if we've tried the max voltage */
1750                 for (i = 0; i < intel_dp->lane_count; i++)
1751                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1752                                 break;
1753                 if (i == intel_dp->lane_count) {
1754                         ++loop_tries;
1755                         if (loop_tries == 5) {
1756                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1757                                 break;
1758                         }
1759                         memset(intel_dp->train_set, 0, 4);
1760                         voltage_tries = 0;
1761                         continue;
1762                 }
1763
1764                 /* Check to see if we've tried the same voltage 5 times */
1765                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1766                         ++voltage_tries;
1767                         if (voltage_tries == 5) {
1768                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1769                                 break;
1770                         }
1771                 } else
1772                         voltage_tries = 0;
1773                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1774
1775                 /* Compute new intel_dp->train_set as requested by target */
1776                 intel_get_adjust_train(intel_dp, link_status);
1777         }
1778
1779         intel_dp->DP = DP;
1780 }
1781
1782 static void
1783 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1784 {
1785         struct drm_device *dev = intel_dp->base.base.dev;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         bool channel_eq = false;
1788         int tries, cr_tries;
1789         u32 reg;
1790         uint32_t DP = intel_dp->DP;
1791
1792         /* channel equalization */
1793         tries = 0;
1794         cr_tries = 0;
1795         channel_eq = false;
1796         for (;;) {
1797                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1798                 uint32_t    signal_levels;
1799                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1800
1801                 if (cr_tries > 5) {
1802                         DRM_ERROR("failed to train DP, aborting\n");
1803                         intel_dp_link_down(intel_dp);
1804                         break;
1805                 }
1806
1807                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1808                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1809                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1810                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1811                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1812                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1813                 } else {
1814                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1815                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1816                 }
1817
1818                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1819                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1820                 else
1821                         reg = DP | DP_LINK_TRAIN_PAT_2;
1822
1823                 /* channel eq pattern */
1824                 if (!intel_dp_set_link_train(intel_dp, reg,
1825                                              DP_TRAINING_PATTERN_2 |
1826                                              DP_LINK_SCRAMBLING_DISABLE))
1827                         break;
1828
1829                 udelay(400);
1830                 if (!intel_dp_get_link_status(intel_dp, link_status))
1831                         break;
1832
1833                 /* Make sure clock is still ok */
1834                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1835                         intel_dp_start_link_train(intel_dp);
1836                         cr_tries++;
1837                         continue;
1838                 }
1839
1840                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1841                         channel_eq = true;
1842                         break;
1843                 }
1844
1845                 /* Try 5 times, then try clock recovery if that fails */
1846                 if (tries > 5) {
1847                         intel_dp_link_down(intel_dp);
1848                         intel_dp_start_link_train(intel_dp);
1849                         tries = 0;
1850                         cr_tries++;
1851                         continue;
1852                 }
1853
1854                 /* Compute new intel_dp->train_set as requested by target */
1855                 intel_get_adjust_train(intel_dp, link_status);
1856                 ++tries;
1857         }
1858
1859         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1860                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1861         else
1862                 reg = DP | DP_LINK_TRAIN_OFF;
1863
1864         I915_WRITE(intel_dp->output_reg, reg);
1865         POSTING_READ(intel_dp->output_reg);
1866         intel_dp_aux_native_write_1(intel_dp,
1867                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1868 }
1869
1870 static void
1871 intel_dp_link_down(struct intel_dp *intel_dp)
1872 {
1873         struct drm_device *dev = intel_dp->base.base.dev;
1874         struct drm_i915_private *dev_priv = dev->dev_private;
1875         uint32_t DP = intel_dp->DP;
1876
1877         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1878                 return;
1879
1880         DRM_DEBUG_KMS("\n");
1881
1882         if (is_edp(intel_dp)) {
1883                 DP &= ~DP_PLL_ENABLE;
1884                 I915_WRITE(intel_dp->output_reg, DP);
1885                 POSTING_READ(intel_dp->output_reg);
1886                 udelay(100);
1887         }
1888
1889         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1890                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1891                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1892         } else {
1893                 DP &= ~DP_LINK_TRAIN_MASK;
1894                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1895         }
1896         POSTING_READ(intel_dp->output_reg);
1897
1898         msleep(17);
1899
1900         if (is_edp(intel_dp)) {
1901                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1902                         DP |= DP_LINK_TRAIN_OFF_CPT;
1903                 else
1904                         DP |= DP_LINK_TRAIN_OFF;
1905         }
1906
1907         if (!HAS_PCH_CPT(dev) &&
1908             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1909                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1910
1911                 /* Hardware workaround: leaving our transcoder select
1912                  * set to transcoder B while it's off will prevent the
1913                  * corresponding HDMI output on transcoder A.
1914                  *
1915                  * Combine this with another hardware workaround:
1916                  * transcoder select bit can only be cleared while the
1917                  * port is enabled.
1918                  */
1919                 DP &= ~DP_PIPEB_SELECT;
1920                 I915_WRITE(intel_dp->output_reg, DP);
1921
1922                 /* Changes to enable or select take place the vblank
1923                  * after being written.
1924                  */
1925                 if (crtc == NULL) {
1926                         /* We can arrive here never having been attached
1927                          * to a CRTC, for instance, due to inheriting
1928                          * random state from the BIOS.
1929                          *
1930                          * If the pipe is not running, play safe and
1931                          * wait for the clocks to stabilise before
1932                          * continuing.
1933                          */
1934                         POSTING_READ(intel_dp->output_reg);
1935                         msleep(50);
1936                 } else
1937                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1938         }
1939
1940         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1941         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1942         POSTING_READ(intel_dp->output_reg);
1943         msleep(intel_dp->panel_power_down_delay);
1944 }
1945
1946 static bool
1947 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1948 {
1949         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1950                                            sizeof(intel_dp->dpcd)) &&
1951             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1952                 return true;
1953         }
1954
1955         return false;
1956 }
1957
1958 static bool
1959 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1960 {
1961         int ret;
1962
1963         ret = intel_dp_aux_native_read_retry(intel_dp,
1964                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1965                                              sink_irq_vector, 1);
1966         if (!ret)
1967                 return false;
1968
1969         return true;
1970 }
1971
1972 static void
1973 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1974 {
1975         /* NAK by default */
1976         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1977 }
1978
1979 /*
1980  * According to DP spec
1981  * 5.1.2:
1982  *  1. Read DPCD
1983  *  2. Configure link according to Receiver Capabilities
1984  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1985  *  4. Check link status on receipt of hot-plug interrupt
1986  */
1987
1988 static void
1989 intel_dp_check_link_status(struct intel_dp *intel_dp)
1990 {
1991         u8 sink_irq_vector;
1992         u8 link_status[DP_LINK_STATUS_SIZE];
1993
1994         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1995                 return;
1996
1997         if (!intel_dp->base.base.crtc)
1998                 return;
1999
2000         /* Try to read receiver status if the link appears to be up */
2001         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2002                 intel_dp_link_down(intel_dp);
2003                 return;
2004         }
2005
2006         /* Now read the DPCD to see if it's actually running */
2007         if (!intel_dp_get_dpcd(intel_dp)) {
2008                 intel_dp_link_down(intel_dp);
2009                 return;
2010         }
2011
2012         /* Try to read the source of the interrupt */
2013         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2014             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2015                 /* Clear interrupt source */
2016                 intel_dp_aux_native_write_1(intel_dp,
2017                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2018                                             sink_irq_vector);
2019
2020                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2021                         intel_dp_handle_test_request(intel_dp);
2022                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2023                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2024         }
2025
2026         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2027                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2028                               drm_get_encoder_name(&intel_dp->base.base));
2029                 intel_dp_start_link_train(intel_dp);
2030                 intel_dp_complete_link_train(intel_dp);
2031         }
2032 }
2033
2034 static enum drm_connector_status
2035 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2036 {
2037         if (intel_dp_get_dpcd(intel_dp))
2038                 return connector_status_connected;
2039         return connector_status_disconnected;
2040 }
2041
2042 static enum drm_connector_status
2043 ironlake_dp_detect(struct intel_dp *intel_dp)
2044 {
2045         enum drm_connector_status status;
2046
2047         /* Can't disconnect eDP, but you can close the lid... */
2048         if (is_edp(intel_dp)) {
2049                 status = intel_panel_detect(intel_dp->base.base.dev);
2050                 if (status == connector_status_unknown)
2051                         status = connector_status_connected;
2052                 return status;
2053         }
2054
2055         return intel_dp_detect_dpcd(intel_dp);
2056 }
2057
2058 static enum drm_connector_status
2059 g4x_dp_detect(struct intel_dp *intel_dp)
2060 {
2061         struct drm_device *dev = intel_dp->base.base.dev;
2062         struct drm_i915_private *dev_priv = dev->dev_private;
2063         uint32_t temp, bit;
2064
2065         switch (intel_dp->output_reg) {
2066         case DP_B:
2067                 bit = DPB_HOTPLUG_INT_STATUS;
2068                 break;
2069         case DP_C:
2070                 bit = DPC_HOTPLUG_INT_STATUS;
2071                 break;
2072         case DP_D:
2073                 bit = DPD_HOTPLUG_INT_STATUS;
2074                 break;
2075         default:
2076                 return connector_status_unknown;
2077         }
2078
2079         temp = I915_READ(PORT_HOTPLUG_STAT);
2080
2081         if ((temp & bit) == 0)
2082                 return connector_status_disconnected;
2083
2084         return intel_dp_detect_dpcd(intel_dp);
2085 }
2086
2087 static struct edid *
2088 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2089 {
2090         struct intel_dp *intel_dp = intel_attached_dp(connector);
2091         struct edid     *edid;
2092
2093         ironlake_edp_panel_vdd_on(intel_dp);
2094         edid = drm_get_edid(connector, adapter);
2095         ironlake_edp_panel_vdd_off(intel_dp, false);
2096         return edid;
2097 }
2098
2099 static int
2100 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2101 {
2102         struct intel_dp *intel_dp = intel_attached_dp(connector);
2103         int     ret;
2104
2105         ironlake_edp_panel_vdd_on(intel_dp);
2106         ret = intel_ddc_get_modes(connector, adapter);
2107         ironlake_edp_panel_vdd_off(intel_dp, false);
2108         return ret;
2109 }
2110
2111
2112 /**
2113  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2114  *
2115  * \return true if DP port is connected.
2116  * \return false if DP port is disconnected.
2117  */
2118 static enum drm_connector_status
2119 intel_dp_detect(struct drm_connector *connector, bool force)
2120 {
2121         struct intel_dp *intel_dp = intel_attached_dp(connector);
2122         struct drm_device *dev = intel_dp->base.base.dev;
2123         enum drm_connector_status status;
2124         struct edid *edid = NULL;
2125
2126         intel_dp->has_audio = false;
2127
2128         if (HAS_PCH_SPLIT(dev))
2129                 status = ironlake_dp_detect(intel_dp);
2130         else
2131                 status = g4x_dp_detect(intel_dp);
2132
2133         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2134                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2135                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2136                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2137
2138         if (status != connector_status_connected)
2139                 return status;
2140
2141         if (intel_dp->force_audio) {
2142                 intel_dp->has_audio = intel_dp->force_audio > 0;
2143         } else {
2144                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2145                 if (edid) {
2146                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2147                         connector->display_info.raw_edid = NULL;
2148                         kfree(edid);
2149                 }
2150         }
2151
2152         return connector_status_connected;
2153 }
2154
2155 static int intel_dp_get_modes(struct drm_connector *connector)
2156 {
2157         struct intel_dp *intel_dp = intel_attached_dp(connector);
2158         struct drm_device *dev = intel_dp->base.base.dev;
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160         int ret;
2161
2162         /* We should parse the EDID data and find out if it has an audio sink
2163          */
2164
2165         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2166         if (ret) {
2167                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2168                         struct drm_display_mode *newmode;
2169                         list_for_each_entry(newmode, &connector->probed_modes,
2170                                             head) {
2171                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2172                                         intel_dp->panel_fixed_mode =
2173                                                 drm_mode_duplicate(dev, newmode);
2174                                         break;
2175                                 }
2176                         }
2177                 }
2178                 return ret;
2179         }
2180
2181         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2182         if (is_edp(intel_dp)) {
2183                 /* initialize panel mode from VBT if available for eDP */
2184                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2185                         intel_dp->panel_fixed_mode =
2186                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2187                         if (intel_dp->panel_fixed_mode) {
2188                                 intel_dp->panel_fixed_mode->type |=
2189                                         DRM_MODE_TYPE_PREFERRED;
2190                         }
2191                 }
2192                 if (intel_dp->panel_fixed_mode) {
2193                         struct drm_display_mode *mode;
2194                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2195                         drm_mode_probed_add(connector, mode);
2196                         return 1;
2197                 }
2198         }
2199         return 0;
2200 }
2201
2202 static bool
2203 intel_dp_detect_audio(struct drm_connector *connector)
2204 {
2205         struct intel_dp *intel_dp = intel_attached_dp(connector);
2206         struct edid *edid;
2207         bool has_audio = false;
2208
2209         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2210         if (edid) {
2211                 has_audio = drm_detect_monitor_audio(edid);
2212
2213                 connector->display_info.raw_edid = NULL;
2214                 kfree(edid);
2215         }
2216
2217         return has_audio;
2218 }
2219
2220 static int
2221 intel_dp_set_property(struct drm_connector *connector,
2222                       struct drm_property *property,
2223                       uint64_t val)
2224 {
2225         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2226         struct intel_dp *intel_dp = intel_attached_dp(connector);
2227         int ret;
2228
2229         ret = drm_connector_property_set_value(connector, property, val);
2230         if (ret)
2231                 return ret;
2232
2233         if (property == dev_priv->force_audio_property) {
2234                 int i = val;
2235                 bool has_audio;
2236
2237                 if (i == intel_dp->force_audio)
2238                         return 0;
2239
2240                 intel_dp->force_audio = i;
2241
2242                 if (i == 0)
2243                         has_audio = intel_dp_detect_audio(connector);
2244                 else
2245                         has_audio = i > 0;
2246
2247                 if (has_audio == intel_dp->has_audio)
2248                         return 0;
2249
2250                 intel_dp->has_audio = has_audio;
2251                 goto done;
2252         }
2253
2254         if (property == dev_priv->broadcast_rgb_property) {
2255                 if (val == !!intel_dp->color_range)
2256                         return 0;
2257
2258                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2259                 goto done;
2260         }
2261
2262         return -EINVAL;
2263
2264 done:
2265         if (intel_dp->base.base.crtc) {
2266                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2267                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2268                                          crtc->x, crtc->y,
2269                                          crtc->fb);
2270         }
2271
2272         return 0;
2273 }
2274
2275 static void
2276 intel_dp_destroy(struct drm_connector *connector)
2277 {
2278         struct drm_device *dev = connector->dev;
2279
2280         if (intel_dpd_is_edp(dev))
2281                 intel_panel_destroy_backlight(dev);
2282
2283         drm_sysfs_connector_remove(connector);
2284         drm_connector_cleanup(connector);
2285         kfree(connector);
2286 }
2287
2288 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2289 {
2290         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2291
2292         i2c_del_adapter(&intel_dp->adapter);
2293         drm_encoder_cleanup(encoder);
2294         if (is_edp(intel_dp)) {
2295                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2296                 ironlake_panel_vdd_off_sync(intel_dp);
2297         }
2298         kfree(intel_dp);
2299 }
2300
2301 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2302         .dpms = intel_dp_dpms,
2303         .mode_fixup = intel_dp_mode_fixup,
2304         .prepare = intel_dp_prepare,
2305         .mode_set = intel_dp_mode_set,
2306         .commit = intel_dp_commit,
2307 };
2308
2309 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2310         .dpms = drm_helper_connector_dpms,
2311         .detect = intel_dp_detect,
2312         .fill_modes = drm_helper_probe_single_connector_modes,
2313         .set_property = intel_dp_set_property,
2314         .destroy = intel_dp_destroy,
2315 };
2316
2317 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2318         .get_modes = intel_dp_get_modes,
2319         .mode_valid = intel_dp_mode_valid,
2320         .best_encoder = intel_best_encoder,
2321 };
2322
2323 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2324         .destroy = intel_dp_encoder_destroy,
2325 };
2326
2327 static void
2328 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2329 {
2330         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2331
2332         intel_dp_check_link_status(intel_dp);
2333 }
2334
2335 /* Return which DP Port should be selected for Transcoder DP control */
2336 int
2337 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2338 {
2339         struct drm_device *dev = crtc->dev;
2340         struct drm_mode_config *mode_config = &dev->mode_config;
2341         struct drm_encoder *encoder;
2342
2343         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2344                 struct intel_dp *intel_dp;
2345
2346                 if (encoder->crtc != crtc)
2347                         continue;
2348
2349                 intel_dp = enc_to_intel_dp(encoder);
2350                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2351                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2352                         return intel_dp->output_reg;
2353         }
2354
2355         return -1;
2356 }
2357
2358 /* check the VBT to see whether the eDP is on DP-D port */
2359 bool intel_dpd_is_edp(struct drm_device *dev)
2360 {
2361         struct drm_i915_private *dev_priv = dev->dev_private;
2362         struct child_device_config *p_child;
2363         int i;
2364
2365         if (!dev_priv->child_dev_num)
2366                 return false;
2367
2368         for (i = 0; i < dev_priv->child_dev_num; i++) {
2369                 p_child = dev_priv->child_dev + i;
2370
2371                 if (p_child->dvo_port == PORT_IDPD &&
2372                     p_child->device_type == DEVICE_TYPE_eDP)
2373                         return true;
2374         }
2375         return false;
2376 }
2377
2378 static void
2379 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2380 {
2381         intel_attach_force_audio_property(connector);
2382         intel_attach_broadcast_rgb_property(connector);
2383 }
2384
2385 void
2386 intel_dp_init(struct drm_device *dev, int output_reg)
2387 {
2388         struct drm_i915_private *dev_priv = dev->dev_private;
2389         struct drm_connector *connector;
2390         struct intel_dp *intel_dp;
2391         struct intel_encoder *intel_encoder;
2392         struct intel_connector *intel_connector;
2393         const char *name = NULL;
2394         int type;
2395
2396         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2397         if (!intel_dp)
2398                 return;
2399
2400         intel_dp->output_reg = output_reg;
2401         intel_dp->dpms_mode = -1;
2402
2403         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2404         if (!intel_connector) {
2405                 kfree(intel_dp);
2406                 return;
2407         }
2408         intel_encoder = &intel_dp->base;
2409
2410         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2411                 if (intel_dpd_is_edp(dev))
2412                         intel_dp->is_pch_edp = true;
2413
2414         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2415                 type = DRM_MODE_CONNECTOR_eDP;
2416                 intel_encoder->type = INTEL_OUTPUT_EDP;
2417         } else {
2418                 type = DRM_MODE_CONNECTOR_DisplayPort;
2419                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2420         }
2421
2422         connector = &intel_connector->base;
2423         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2424         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2425
2426         connector->polled = DRM_CONNECTOR_POLL_HPD;
2427
2428         if (output_reg == DP_B || output_reg == PCH_DP_B)
2429                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2430         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2431                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2432         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2433                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2434
2435         if (is_edp(intel_dp)) {
2436                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2437                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2438                                   ironlake_panel_vdd_work);
2439         }
2440
2441         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2442         connector->interlace_allowed = true;
2443         connector->doublescan_allowed = 0;
2444
2445         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2446                          DRM_MODE_ENCODER_TMDS);
2447         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2448
2449         intel_connector_attach_encoder(intel_connector, intel_encoder);
2450         drm_sysfs_connector_add(connector);
2451
2452         /* Set up the DDC bus. */
2453         switch (output_reg) {
2454                 case DP_A:
2455                         name = "DPDDC-A";
2456                         break;
2457                 case DP_B:
2458                 case PCH_DP_B:
2459                         dev_priv->hotplug_supported_mask |=
2460                                 HDMIB_HOTPLUG_INT_STATUS;
2461                         name = "DPDDC-B";
2462                         break;
2463                 case DP_C:
2464                 case PCH_DP_C:
2465                         dev_priv->hotplug_supported_mask |=
2466                                 HDMIC_HOTPLUG_INT_STATUS;
2467                         name = "DPDDC-C";
2468                         break;
2469                 case DP_D:
2470                 case PCH_DP_D:
2471                         dev_priv->hotplug_supported_mask |=
2472                                 HDMID_HOTPLUG_INT_STATUS;
2473                         name = "DPDDC-D";
2474                         break;
2475         }
2476
2477         /* Cache some DPCD data in the eDP case */
2478         if (is_edp(intel_dp)) {
2479                 bool ret;
2480                 struct edp_power_seq    cur, vbt;
2481                 u32 pp_on, pp_off, pp_div;
2482
2483                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2484                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2485                 pp_div = I915_READ(PCH_PP_DIVISOR);
2486
2487                 /* Pull timing values out of registers */
2488                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2489                         PANEL_POWER_UP_DELAY_SHIFT;
2490
2491                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2492                         PANEL_LIGHT_ON_DELAY_SHIFT;
2493
2494                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2495                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2496
2497                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2498                         PANEL_POWER_DOWN_DELAY_SHIFT;
2499
2500                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2501                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2502
2503                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2504                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2505
2506                 vbt = dev_priv->edp.pps;
2507
2508                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2509                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2510
2511 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2512
2513                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2514                 intel_dp->backlight_on_delay = get_delay(t8);
2515                 intel_dp->backlight_off_delay = get_delay(t9);
2516                 intel_dp->panel_power_down_delay = get_delay(t10);
2517                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2518
2519                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2520                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2521                               intel_dp->panel_power_cycle_delay);
2522
2523                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2524                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2525
2526                 ironlake_edp_panel_vdd_on(intel_dp);
2527                 ret = intel_dp_get_dpcd(intel_dp);
2528                 ironlake_edp_panel_vdd_off(intel_dp, false);
2529
2530                 if (ret) {
2531                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2532                                 dev_priv->no_aux_handshake =
2533                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2534                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2535                 } else {
2536                         /* if this fails, presume the device is a ghost */
2537                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2538                         intel_dp_encoder_destroy(&intel_dp->base.base);
2539                         intel_dp_destroy(&intel_connector->base);
2540                         return;
2541                 }
2542         }
2543
2544         intel_dp_i2c_init(intel_dp, intel_connector, name);
2545
2546         intel_encoder->hot_plug = intel_dp_hot_plug;
2547
2548         if (is_edp(intel_dp)) {
2549                 dev_priv->int_edp_connector = connector;
2550                 intel_panel_setup_backlight(dev);
2551         }
2552
2553         intel_dp_add_properties(intel_dp, connector);
2554
2555         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2556          * 0xd.  Failure to do so will result in spurious interrupts being
2557          * generated on the port when a cable is not attached.
2558          */
2559         if (IS_G4X(dev) && !IS_GM45(dev)) {
2560                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2561                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2562         }
2563 }