1 /* bnx2x_init_ops.h: Broadcom Everest network driver.
2 * Static functions needed during the initialization.
3 * This file is "included" in bnx2x_main.c.
5 * Copyright (c) 2007-2010 Broadcom Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
12 * Written by: Vladislav Zolotarov <vladz@broadcom.com>
15 #ifndef BNX2X_INIT_OPS_H
16 #define BNX2X_INIT_OPS_H
18 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
21 static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
26 for (i = 0; i < len; i++)
27 REG_WR(bp, addr + i*4, data[i]);
30 static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
35 for (i = 0; i < len; i++)
36 REG_WR_IND(bp, addr + i*4, data[i]);
39 static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
42 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
44 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
47 static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
49 u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
50 u32 buf_len32 = buf_len/4;
53 memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
55 for (i = 0; i < len; i += buf_len32) {
56 u32 cur_len = min(buf_len32, len - i);
58 bnx2x_write_big_buf(bp, addr + i*4, cur_len);
62 static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
65 u32 buf_len32 = FW_BUF_SIZE/4;
70 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
71 data64 = HILO_U64((*(data + 1)), (*data));
73 len64 = min((u32)(FW_BUF_SIZE/8), len64);
74 for (i = 0; i < len64; i++) {
75 u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
80 for (i = 0; i < len; i += buf_len32) {
81 u32 cur_len = min(buf_len32, len - i);
83 bnx2x_write_big_buf(bp, addr + i*4, cur_len);
87 /*********************************************************
88 There are different blobs for each PRAM section.
89 In addition, each blob write operation is divided into a few operations
90 in order to decrease the amount of phys. contiguous buffer needed.
91 Thus, when we select a blob the address may be with some offset
92 from the beginning of PRAM section.
93 The same holds for the INT_TABLE sections.
94 **********************************************************/
95 #define IF_IS_INT_TABLE_ADDR(base, addr) \
96 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
98 #define IF_IS_PRAM_ADDR(base, addr) \
99 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
101 static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data)
103 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
104 data = INIT_TSEM_INT_TABLE_DATA(bp);
106 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
107 data = INIT_CSEM_INT_TABLE_DATA(bp);
109 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
110 data = INIT_USEM_INT_TABLE_DATA(bp);
112 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
113 data = INIT_XSEM_INT_TABLE_DATA(bp);
115 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
116 data = INIT_TSEM_PRAM_DATA(bp);
118 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
119 data = INIT_CSEM_PRAM_DATA(bp);
121 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
122 data = INIT_USEM_PRAM_DATA(bp);
124 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
125 data = INIT_XSEM_PRAM_DATA(bp);
130 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
133 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
135 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
138 static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
141 const u32 *old_data = data;
143 data = (const u32 *)bnx2x_sel_blob(bp, addr, (const u8 *)data);
145 if (bp->dmae_ready) {
146 if (old_data != data)
147 VIRT_WR_DMAE_LEN(bp, data, addr, len, 1);
149 VIRT_WR_DMAE_LEN(bp, data, addr, len, 0);
151 bnx2x_init_ind_wr(bp, addr, data, len);
154 static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo, u32 val_hi)
158 wb_write[0] = val_lo;
159 wb_write[1] = val_hi;
160 REG_WR_DMAE_LEN(bp, reg, wb_write, 2);
163 static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, u32 blob_off)
165 const u8 *data = NULL;
169 data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
171 rc = bnx2x_gunzip(bp, data, len);
175 /* gunzip_outlen is in dwords */
176 len = GUNZIP_OUTLEN(bp);
177 for (i = 0; i < len; i++)
178 ((u32 *)GUNZIP_BUF(bp))[i] =
179 cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
181 bnx2x_write_big_buf_wb(bp, addr, len);
184 static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
187 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_START)];
189 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_END)];
192 u32 i, op_type, addr, len;
193 const u32 *data, *data_base;
196 if (op_start == op_end)
199 if (CHIP_REV_IS_FPGA(bp))
201 else if (CHIP_REV_IS_EMUL(bp))
206 data_base = INIT_DATA(bp);
208 for (i = op_start; i < op_end; i++) {
210 op = (union init_op *)&(INIT_OPS(bp)[i]);
212 op_type = op->str_wr.op;
213 addr = op->str_wr.offset;
214 len = op->str_wr.data_len;
215 data = data_base + op->str_wr.data_off;
217 /* HW/EMUL specific */
218 if ((op_type > OP_WB) && (op_type == hw_wr))
226 REG_WR(bp, addr, op->write.val);
229 bnx2x_init_str_wr(bp, addr, data, len);
232 bnx2x_init_wr_wb(bp, addr, data, len);
235 bnx2x_init_ind_wr(bp, addr, data, len);
238 bnx2x_init_fill(bp, addr, 0, op->zero.len);
241 bnx2x_init_wr_zp(bp, addr, len,
242 op->str_wr.data_off);
245 bnx2x_init_wr_64(bp, addr, data, len);
248 /* happens whenever an op is of a diff HW */
255 /****************************************************************************
257 ****************************************************************************/
259 * This code configures the PCI read/write arbiter
260 * which implements a weighted round robin
261 * between the virtual queues in the chip.
263 * The values were derived for each PCI max payload and max request size.
264 * since max payload and max request size are only known at run time,
265 * this is done as a separate init stage.
273 /* configuration for one arbiter queue */
280 /* derived configuration for each read queue for each max request size */
281 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
282 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
283 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
284 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
285 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
286 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
287 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
288 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
289 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
290 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
291 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
292 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
293 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
294 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
295 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
296 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
297 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
298 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
299 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
300 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
301 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
302 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
303 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
304 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
305 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
306 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
307 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
308 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
309 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
310 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
313 /* derived configuration for each write queue for each max request size */
314 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
315 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
316 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
317 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
318 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
319 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
320 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
321 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
322 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
323 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
324 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
325 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
326 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
327 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
330 /* register addresses for read queues */
331 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
332 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
333 PXP2_REG_RQ_BW_RD_UBOUND0},
334 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
335 PXP2_REG_PSWRQ_BW_UB1},
336 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
337 PXP2_REG_PSWRQ_BW_UB2},
338 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
339 PXP2_REG_PSWRQ_BW_UB3},
340 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
341 PXP2_REG_RQ_BW_RD_UBOUND4},
342 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
343 PXP2_REG_RQ_BW_RD_UBOUND5},
344 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
345 PXP2_REG_PSWRQ_BW_UB6},
346 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
347 PXP2_REG_PSWRQ_BW_UB7},
348 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
349 PXP2_REG_PSWRQ_BW_UB8},
350 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
351 PXP2_REG_PSWRQ_BW_UB9},
352 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
353 PXP2_REG_PSWRQ_BW_UB10},
354 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
355 PXP2_REG_PSWRQ_BW_UB11},
356 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
357 PXP2_REG_RQ_BW_RD_UBOUND12},
358 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
359 PXP2_REG_RQ_BW_RD_UBOUND13},
360 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
361 PXP2_REG_RQ_BW_RD_UBOUND14},
362 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
363 PXP2_REG_RQ_BW_RD_UBOUND15},
364 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
365 PXP2_REG_RQ_BW_RD_UBOUND16},
366 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
367 PXP2_REG_RQ_BW_RD_UBOUND17},
368 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
369 PXP2_REG_RQ_BW_RD_UBOUND18},
370 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
371 PXP2_REG_RQ_BW_RD_UBOUND19},
372 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
373 PXP2_REG_RQ_BW_RD_UBOUND20},
374 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
375 PXP2_REG_RQ_BW_RD_UBOUND22},
376 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
377 PXP2_REG_RQ_BW_RD_UBOUND23},
378 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
379 PXP2_REG_RQ_BW_RD_UBOUND24},
380 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
381 PXP2_REG_RQ_BW_RD_UBOUND25},
382 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
383 PXP2_REG_RQ_BW_RD_UBOUND26},
384 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
385 PXP2_REG_RQ_BW_RD_UBOUND27},
386 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
387 PXP2_REG_PSWRQ_BW_UB28}
390 /* register addresses for write queues */
391 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
392 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
393 PXP2_REG_PSWRQ_BW_UB1},
394 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
395 PXP2_REG_PSWRQ_BW_UB2},
396 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
397 PXP2_REG_PSWRQ_BW_UB3},
398 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
399 PXP2_REG_PSWRQ_BW_UB6},
400 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
401 PXP2_REG_PSWRQ_BW_UB7},
402 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
403 PXP2_REG_PSWRQ_BW_UB8},
404 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
405 PXP2_REG_PSWRQ_BW_UB9},
406 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
407 PXP2_REG_PSWRQ_BW_UB10},
408 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
409 PXP2_REG_PSWRQ_BW_UB11},
410 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
411 PXP2_REG_PSWRQ_BW_UB28},
412 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
413 PXP2_REG_RQ_BW_WR_UBOUND29},
414 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
415 PXP2_REG_RQ_BW_WR_UBOUND30}
418 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, int w_order)
422 if (r_order > MAX_RD_ORD) {
423 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
424 r_order, MAX_RD_ORD);
425 r_order = MAX_RD_ORD;
427 if (w_order > MAX_WR_ORD) {
428 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
429 w_order, MAX_WR_ORD);
430 w_order = MAX_WR_ORD;
432 if (CHIP_REV_IS_FPGA(bp)) {
433 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
436 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
438 for (i = 0; i < NUM_RD_Q-1; i++) {
439 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
440 REG_WR(bp, read_arb_addr[i].add,
441 read_arb_data[i][r_order].add);
442 REG_WR(bp, read_arb_addr[i].ubound,
443 read_arb_data[i][r_order].ubound);
446 for (i = 0; i < NUM_WR_Q-1; i++) {
447 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
448 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
450 REG_WR(bp, write_arb_addr[i].l,
451 write_arb_data[i][w_order].l);
453 REG_WR(bp, write_arb_addr[i].add,
454 write_arb_data[i][w_order].add);
456 REG_WR(bp, write_arb_addr[i].ubound,
457 write_arb_data[i][w_order].ubound);
460 val = REG_RD(bp, write_arb_addr[i].l);
461 REG_WR(bp, write_arb_addr[i].l,
462 val | (write_arb_data[i][w_order].l << 10));
464 val = REG_RD(bp, write_arb_addr[i].add);
465 REG_WR(bp, write_arb_addr[i].add,
466 val | (write_arb_data[i][w_order].add << 10));
468 val = REG_RD(bp, write_arb_addr[i].ubound);
469 REG_WR(bp, write_arb_addr[i].ubound,
470 val | (write_arb_data[i][w_order].ubound << 7));
474 val = write_arb_data[NUM_WR_Q-1][w_order].add;
475 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
476 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
477 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
479 val = read_arb_data[NUM_RD_Q-1][r_order].add;
480 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
481 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
482 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
484 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
485 REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
486 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
487 REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
489 if (r_order == MAX_RD_ORD)
490 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
492 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
494 if (CHIP_IS_E1H(bp)) {
495 /* MPS w_order optimal TH presently TH
500 val = ((w_order == 0) ? 2 : 3);
501 REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
502 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
503 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
504 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
505 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
506 REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
507 REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
508 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
509 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
510 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
511 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
515 /****************************************************************************
517 ****************************************************************************/
519 * This codes hides the low level HW interaction for ILT management and
520 * configuration. The API consists of a shadow ILT table which is set by the
521 * driver and a set of routines to use it to configure the HW.
525 /* ILT HW init operations */
527 /* ILT memory management operations */
528 #define ILT_MEMOP_ALLOC 0
529 #define ILT_MEMOP_FREE 1
531 /* the phys address is shifted right 12 bits and has an added
532 * 1=valid bit added to the 53rd bit
533 * then since this is a wide register(TM)
534 * we split it into two 32 bit writes
536 #define ILT_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
537 #define ILT_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
538 #define ILT_RANGE(f, l) (((l) << 10) | f)
540 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp, struct ilt_line *line,
543 if (memop == ILT_MEMOP_FREE) {
544 BNX2X_ILT_FREE(line->page, line->page_mapping, line->size);
547 BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size);
555 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num, u8 memop)
558 struct bnx2x_ilt *ilt = BP_ILT(bp);
559 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
561 if (!ilt || !ilt->lines)
564 if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
567 for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
568 rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i],
569 ilt_cli->page_size, memop);
574 int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop)
576 int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop);
578 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop);
580 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
582 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop);
587 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx,
588 dma_addr_t page_mapping)
593 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
595 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
597 bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
600 static void bnx2x_ilt_line_init_op(struct bnx2x *bp, struct bnx2x_ilt *ilt,
603 dma_addr_t null_mapping;
604 int abs_idx = ilt->start_line + idx;
609 /* set in the init-value array */
611 bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping);
615 bnx2x_ilt_line_wr(bp, abs_idx, null_mapping);
620 void bnx2x_ilt_boundry_init_op(struct bnx2x *bp,
621 struct ilt_client_info *ilt_cli,
622 u32 ilt_start, u8 initop)
627 /* The boundary is either SET or INIT,
628 CLEAR => SET and for now SET ~~ INIT */
630 /* find the appropriate regs */
631 if (CHIP_IS_E1(bp)) {
632 switch (ilt_cli->client_num) {
634 start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
637 start_reg = PXP2_REG_PSWRQ_QM0_L2P;
640 start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
643 start_reg = PXP2_REG_PSWRQ_TM0_L2P;
646 REG_WR(bp, start_reg + BP_FUNC(bp)*4,
647 ILT_RANGE((ilt_start + ilt_cli->start),
648 (ilt_start + ilt_cli->end)));
650 switch (ilt_cli->client_num) {
652 start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
653 end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
656 start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
657 end_reg = PXP2_REG_RQ_QM_LAST_ILT;
660 start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
661 end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
664 start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
665 end_reg = PXP2_REG_RQ_TM_LAST_ILT;
668 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));
669 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
673 void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp, struct bnx2x_ilt *ilt,
674 struct ilt_client_info *ilt_cli, u8 initop)
678 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
681 for (i = ilt_cli->start; i <= ilt_cli->end; i++)
682 bnx2x_ilt_line_init_op(bp, ilt, i, initop);
684 /* init/clear the ILT boundries */
685 bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop);
688 void bnx2x_ilt_client_init_op(struct bnx2x *bp,
689 struct ilt_client_info *ilt_cli, u8 initop)
691 struct bnx2x_ilt *ilt = BP_ILT(bp);
693 bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop);
696 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp,
697 int cli_num, u8 initop)
699 struct bnx2x_ilt *ilt = BP_ILT(bp);
700 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
702 bnx2x_ilt_client_init_op(bp, ilt_cli, initop);
705 void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop)
707 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop);
708 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop);
709 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
710 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop);
713 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num,
714 u32 psz_reg, u8 initop)
716 struct bnx2x_ilt *ilt = BP_ILT(bp);
717 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
719 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
724 /* set in the init-value array */
726 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12));
734 * called during init common stage, ilt clients should be initialized
735 * prioir to calling this function
737 void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop)
739 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU,
740 PXP2_REG_RQ_CDU_P_SIZE, initop);
741 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM,
742 PXP2_REG_RQ_QM_P_SIZE, initop);
743 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC,
744 PXP2_REG_RQ_SRC_P_SIZE, initop);
745 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM,
746 PXP2_REG_RQ_TM_P_SIZE, initop);
749 /****************************************************************************
751 ****************************************************************************/
752 #define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
753 #define QM_INIT_MIN_CID_COUNT 31
754 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
756 /* called during init port stage */
757 void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count,
760 int port = BP_PORT(bp);
762 if (QM_INIT(qm_cid_count)) {
765 /* set in the init-value array */
767 REG_WR(bp, QM_REG_CONNNUM_0 + port*4,
768 qm_cid_count/16 - 1);
776 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count)
781 wb_data[0] = wb_data[1] = 0;
783 for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
784 REG_WR(bp, QM_REG_BASEADDR + i*4,
785 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
786 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8,
789 if (CHIP_IS_E1H(bp)) {
790 REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4,
791 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
792 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8,
798 /* called during init common stage */
799 void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count,
802 if (!QM_INIT(qm_cid_count))
807 /* set in the init-value array */
809 bnx2x_qm_set_ptr_table(bp, qm_cid_count);
816 /****************************************************************************
817 * SRC initializations
818 ****************************************************************************/
820 /* called during init func stage */
821 void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2,
822 dma_addr_t t2_mapping, int src_cid_count)
825 int port = BP_PORT(bp);
828 for (i = 0; i < src_cid_count-1; i++)
829 t2[i].next = (u64)(t2_mapping + (i+1)*sizeof(struct src_ent));
831 /* tell the searcher where the T2 table is */
832 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
834 bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16,
835 U64_LO(t2_mapping), U64_HI(t2_mapping));
837 bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16,
838 U64_LO((u64)t2_mapping +
839 (src_cid_count-1) * sizeof(struct src_ent)),
840 U64_HI((u64)t2_mapping +
841 (src_cid_count-1) * sizeof(struct src_ent)));
844 #endif /* BNX2X_INIT_OPS_H */