2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
72 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
78 unsigned long segment_offset;
80 if (!seg || !trb || trb < seg->trbs)
83 segment_offset = trb - seg->trbs;
84 if (segment_offset > TRBS_PER_SEGMENT)
86 return seg->dma + (segment_offset * sizeof(*trb));
89 /* Does this link TRB point to the first segment in a ring,
90 * or was the previous TRB the last TRB on the last segment in the ERST?
92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
93 struct xhci_segment *seg, union xhci_trb *trb)
95 if (ring == xhci->event_ring)
96 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
97 (seg->next == xhci->event_ring->first_seg);
99 return trb->link.control & LINK_TOGGLE;
102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
103 * segment? I.e. would the updated event TRB pointer step off the end of the
106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
107 struct xhci_segment *seg, union xhci_trb *trb)
109 if (ring == xhci->event_ring)
110 return trb == &seg->trbs[TRBS_PER_SEGMENT];
112 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
115 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
116 * TRB is in a new segment. This does not skip over link TRBs, and it does not
117 * effect the ring dequeue or enqueue pointers.
119 static void next_trb(struct xhci_hcd *xhci,
120 struct xhci_ring *ring,
121 struct xhci_segment **seg,
122 union xhci_trb **trb)
124 if (last_trb(xhci, ring, *seg, *trb)) {
126 *trb = ((*seg)->trbs);
133 * See Cycle bit rules. SW is the consumer for the event ring only.
134 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
136 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
138 union xhci_trb *next = ++(ring->dequeue);
139 unsigned long long addr;
142 /* Update the dequeue pointer further if that was a link TRB or we're at
143 * the end of an event ring segment (which doesn't have link TRBS)
145 while (last_trb(xhci, ring, ring->deq_seg, next)) {
146 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
147 ring->cycle_state = (ring->cycle_state ? 0 : 1);
149 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
151 (unsigned int) ring->cycle_state);
153 ring->deq_seg = ring->deq_seg->next;
154 ring->dequeue = ring->deq_seg->trbs;
155 next = ring->dequeue;
157 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
158 if (ring == xhci->event_ring)
159 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
160 else if (ring == xhci->cmd_ring)
161 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
163 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
167 * See Cycle bit rules. SW is the consumer for the event ring only.
168 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
170 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
171 * chain bit is set), then set the chain bit in all the following link TRBs.
172 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
173 * have their chain bit cleared (so that each Link TRB is a separate TD).
175 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
176 * set, but other sections talk about dealing with the chain bit set. This was
177 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
178 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
180 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
183 union xhci_trb *next;
184 unsigned long long addr;
186 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
187 next = ++(ring->enqueue);
190 /* Update the dequeue pointer further if that was a link TRB or we're at
191 * the end of an event ring segment (which doesn't have link TRBS)
193 while (last_trb(xhci, ring, ring->enq_seg, next)) {
195 if (ring != xhci->event_ring) {
196 /* If we're not dealing with 0.95 hardware,
197 * carry over the chain bit of the previous TRB
198 * (which may mean the chain bit is cleared).
200 if (!xhci_link_trb_quirk(xhci)) {
201 next->link.control &= ~TRB_CHAIN;
202 next->link.control |= chain;
204 /* Give this link TRB to the hardware */
206 if (next->link.control & TRB_CYCLE)
207 next->link.control &= (u32) ~TRB_CYCLE;
209 next->link.control |= (u32) TRB_CYCLE;
211 /* Toggle the cycle bit after the last ring segment. */
212 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
213 ring->cycle_state = (ring->cycle_state ? 0 : 1);
215 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
217 (unsigned int) ring->cycle_state);
220 ring->enq_seg = ring->enq_seg->next;
221 ring->enqueue = ring->enq_seg->trbs;
222 next = ring->enqueue;
224 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
225 if (ring == xhci->event_ring)
226 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
227 else if (ring == xhci->cmd_ring)
228 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
230 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
234 * Check to see if there's room to enqueue num_trbs on the ring. See rules
236 * FIXME: this would be simpler and faster if we just kept track of the number
237 * of free TRBs in a ring.
239 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
240 unsigned int num_trbs)
243 union xhci_trb *enq = ring->enqueue;
244 struct xhci_segment *enq_seg = ring->enq_seg;
245 struct xhci_segment *cur_seg;
246 unsigned int left_on_ring;
248 /* Check if ring is empty */
249 if (enq == ring->dequeue) {
250 /* Can't use link trbs */
251 left_on_ring = TRBS_PER_SEGMENT - 1;
252 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
253 cur_seg = cur_seg->next)
254 left_on_ring += TRBS_PER_SEGMENT - 1;
256 /* Always need one TRB free in the ring. */
258 if (num_trbs > left_on_ring) {
259 xhci_warn(xhci, "Not enough room on ring; "
260 "need %u TRBs, %u TRBs left\n",
261 num_trbs, left_on_ring);
266 /* Make sure there's an extra empty TRB available */
267 for (i = 0; i <= num_trbs; ++i) {
268 if (enq == ring->dequeue)
271 while (last_trb(xhci, ring, enq_seg, enq)) {
272 enq_seg = enq_seg->next;
279 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
284 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
285 xhci->event_ring->dequeue);
286 if (deq == 0 && !in_interrupt())
287 xhci_warn(xhci, "WARN something wrong with SW event ring "
289 /* Update HC event ring dequeue pointer */
290 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
291 temp &= ERST_PTR_MASK;
292 /* Don't clear the EHB bit (which is RW1C) because
293 * there might be more events to service.
296 xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
297 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
298 &xhci->ir_set->erst_dequeue);
301 /* Ring the host controller doorbell after placing a command on the ring */
302 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
306 xhci_dbg(xhci, "// Ding dong!\n");
307 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
308 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
309 /* Flush PCI posted writes */
310 xhci_readl(xhci, &xhci->dba->doorbell[0]);
313 static void ring_ep_doorbell(struct xhci_hcd *xhci,
314 unsigned int slot_id,
315 unsigned int ep_index)
317 struct xhci_virt_ep *ep;
318 unsigned int ep_state;
320 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
322 ep = &xhci->devs[slot_id]->eps[ep_index];
323 ep_state = ep->ep_state;
324 /* Don't ring the doorbell for this endpoint if there are pending
325 * cancellations because the we don't want to interrupt processing.
327 if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
328 && !(ep_state & EP_HALTED)) {
329 field = xhci_readl(xhci, db_addr) & DB_MASK;
330 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
331 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
332 * isn't time-critical and we shouldn't make the CPU wait for
335 xhci_readl(xhci, db_addr);
340 * Find the segment that trb is in. Start searching in start_seg.
341 * If we must move past a segment that has a link TRB with a toggle cycle state
342 * bit set, then we will toggle the value pointed at by cycle_state.
344 static struct xhci_segment *find_trb_seg(
345 struct xhci_segment *start_seg,
346 union xhci_trb *trb, int *cycle_state)
348 struct xhci_segment *cur_seg = start_seg;
349 struct xhci_generic_trb *generic_trb;
351 while (cur_seg->trbs > trb ||
352 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
353 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
354 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
355 (generic_trb->field[3] & LINK_TOGGLE))
356 *cycle_state = ~(*cycle_state) & 0x1;
357 cur_seg = cur_seg->next;
358 if (cur_seg == start_seg)
359 /* Looped over the entire list. Oops! */
366 * Move the xHC's endpoint ring dequeue pointer past cur_td.
367 * Record the new state of the xHC's endpoint ring dequeue segment,
368 * dequeue pointer, and new consumer cycle state in state.
369 * Update our internal representation of the ring's dequeue pointer.
371 * We do this in three jumps:
372 * - First we update our new ring state to be the same as when the xHC stopped.
373 * - Then we traverse the ring to find the segment that contains
374 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
375 * any link TRBs with the toggle cycle bit set.
376 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
377 * if we've moved it past a link TRB with the toggle cycle bit set.
379 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
380 unsigned int slot_id, unsigned int ep_index,
381 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
383 struct xhci_virt_device *dev = xhci->devs[slot_id];
384 struct xhci_ring *ep_ring = dev->eps[ep_index].ring;
385 struct xhci_generic_trb *trb;
386 struct xhci_ep_ctx *ep_ctx;
389 state->new_cycle_state = 0;
390 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
391 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
392 dev->eps[ep_index].stopped_trb,
393 &state->new_cycle_state);
394 if (!state->new_deq_seg)
396 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
397 xhci_dbg(xhci, "Finding endpoint context\n");
398 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
399 state->new_cycle_state = 0x1 & ep_ctx->deq;
401 state->new_deq_ptr = cur_td->last_trb;
402 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
403 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
405 &state->new_cycle_state);
406 if (!state->new_deq_seg)
409 trb = &state->new_deq_ptr->generic;
410 if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
411 (trb->field[3] & LINK_TOGGLE))
412 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
413 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
415 /* Don't update the ring cycle state for the producer (us). */
416 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
418 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
419 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
420 (unsigned long long) addr);
421 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
422 ep_ring->dequeue = state->new_deq_ptr;
423 ep_ring->deq_seg = state->new_deq_seg;
426 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
427 struct xhci_td *cur_td)
429 struct xhci_segment *cur_seg;
430 union xhci_trb *cur_trb;
432 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
434 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
435 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
436 TRB_TYPE(TRB_LINK)) {
437 /* Unchain any chained Link TRBs, but
438 * leave the pointers intact.
440 cur_trb->generic.field[3] &= ~TRB_CHAIN;
441 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
442 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
443 "in seg %p (0x%llx dma)\n",
445 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
447 (unsigned long long)cur_seg->dma);
449 cur_trb->generic.field[0] = 0;
450 cur_trb->generic.field[1] = 0;
451 cur_trb->generic.field[2] = 0;
452 /* Preserve only the cycle bit of this TRB */
453 cur_trb->generic.field[3] &= TRB_CYCLE;
454 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
455 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
456 "in seg %p (0x%llx dma)\n",
458 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
460 (unsigned long long)cur_seg->dma);
462 if (cur_trb == cur_td->last_trb)
467 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
468 unsigned int ep_index, struct xhci_segment *deq_seg,
469 union xhci_trb *deq_ptr, u32 cycle_state);
471 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
472 unsigned int slot_id, unsigned int ep_index,
473 struct xhci_dequeue_state *deq_state)
475 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
477 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
478 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
479 deq_state->new_deq_seg,
480 (unsigned long long)deq_state->new_deq_seg->dma,
481 deq_state->new_deq_ptr,
482 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
483 deq_state->new_cycle_state);
484 queue_set_tr_deq(xhci, slot_id, ep_index,
485 deq_state->new_deq_seg,
486 deq_state->new_deq_ptr,
487 (u32) deq_state->new_cycle_state);
488 /* Stop the TD queueing code from ringing the doorbell until
489 * this command completes. The HC won't set the dequeue pointer
490 * if the ring is running, and ringing the doorbell starts the
493 ep->ep_state |= SET_DEQ_PENDING;
496 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
497 struct xhci_virt_ep *ep)
499 ep->ep_state &= ~EP_HALT_PENDING;
500 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
501 * timer is running on another CPU, we don't decrement stop_cmds_pending
502 * (since we didn't successfully stop the watchdog timer).
504 if (del_timer(&ep->stop_cmd_timer))
505 ep->stop_cmds_pending--;
508 /* Must be called with xhci->lock held in interrupt context */
509 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
510 struct xhci_td *cur_td, int status, char *adjective)
512 struct usb_hcd *hcd = xhci_to_hcd(xhci);
514 cur_td->urb->hcpriv = NULL;
515 usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb);
516 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb);
518 spin_unlock(&xhci->lock);
519 usb_hcd_giveback_urb(hcd, cur_td->urb, status);
521 spin_lock(&xhci->lock);
522 xhci_dbg(xhci, "%s URB given back\n", adjective);
526 * When we get a command completion for a Stop Endpoint Command, we need to
527 * unlink any cancelled TDs from the ring. There are two ways to do that:
529 * 1. If the HW was in the middle of processing the TD that needs to be
530 * cancelled, then we must move the ring's dequeue pointer past the last TRB
531 * in the TD with a Set Dequeue Pointer Command.
532 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
533 * bit cleared) so that the HW will skip over them.
535 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
538 unsigned int slot_id;
539 unsigned int ep_index;
540 struct xhci_ring *ep_ring;
541 struct xhci_virt_ep *ep;
542 struct list_head *entry;
543 struct xhci_td *cur_td = 0;
544 struct xhci_td *last_unlinked_td;
546 struct xhci_dequeue_state deq_state;
548 memset(&deq_state, 0, sizeof(deq_state));
549 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
550 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
551 ep = &xhci->devs[slot_id]->eps[ep_index];
554 if (list_empty(&ep->cancelled_td_list)) {
555 xhci_stop_watchdog_timer_in_irq(xhci, ep);
556 ring_ep_doorbell(xhci, slot_id, ep_index);
560 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
561 * We have the xHCI lock, so nothing can modify this list until we drop
562 * it. We're also in the event handler, so we can't get re-interrupted
563 * if another Stop Endpoint command completes
565 list_for_each(entry, &ep->cancelled_td_list) {
566 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
567 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
569 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
571 * If we stopped on the TD we need to cancel, then we have to
572 * move the xHC endpoint ring dequeue pointer past this TD.
574 if (cur_td == ep->stopped_td)
575 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
578 td_to_noop(xhci, ep_ring, cur_td);
580 * The event handler won't see a completion for this TD anymore,
581 * so remove it from the endpoint ring's TD list. Keep it in
582 * the cancelled TD list for URB completion later.
584 list_del(&cur_td->td_list);
586 last_unlinked_td = cur_td;
587 xhci_stop_watchdog_timer_in_irq(xhci, ep);
589 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
590 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
591 xhci_queue_new_dequeue_state(xhci,
592 slot_id, ep_index, &deq_state);
593 xhci_ring_cmd_db(xhci);
595 /* Otherwise just ring the doorbell to restart the ring */
596 ring_ep_doorbell(xhci, slot_id, ep_index);
598 ep->stopped_td = NULL;
599 ep->stopped_trb = NULL;
602 * Drop the lock and complete the URBs in the cancelled TD list.
603 * New TDs to be cancelled might be added to the end of the list before
604 * we can complete all the URBs for the TDs we already unlinked.
605 * So stop when we've completed the URB for the last TD we unlinked.
608 cur_td = list_entry(ep->cancelled_td_list.next,
609 struct xhci_td, cancelled_td_list);
610 list_del(&cur_td->cancelled_td_list);
612 /* Clean up the cancelled URB */
613 /* Doesn't matter what we pass for status, since the core will
614 * just overwrite it (because the URB has been unlinked).
616 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
618 /* Stop processing the cancelled list if the watchdog timer is
621 if (xhci->xhc_state & XHCI_STATE_DYING)
623 } while (cur_td != last_unlinked_td);
625 /* Return to the event handler with xhci->lock re-acquired */
628 /* Watchdog timer function for when a stop endpoint command fails to complete.
629 * In this case, we assume the host controller is broken or dying or dead. The
630 * host may still be completing some other events, so we have to be careful to
631 * let the event ring handler and the URB dequeueing/enqueueing functions know
632 * through xhci->state.
634 * The timer may also fire if the host takes a very long time to respond to the
635 * command, and the stop endpoint command completion handler cannot delete the
636 * timer before the timer function is called. Another endpoint cancellation may
637 * sneak in before the timer function can grab the lock, and that may queue
638 * another stop endpoint command and add the timer back. So we cannot use a
639 * simple flag to say whether there is a pending stop endpoint command for a
640 * particular endpoint.
642 * Instead we use a combination of that flag and a counter for the number of
643 * pending stop endpoint commands. If the timer is the tail end of the last
644 * stop endpoint command, and the endpoint's command is still pending, we assume
647 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
649 struct xhci_hcd *xhci;
650 struct xhci_virt_ep *ep;
651 struct xhci_virt_ep *temp_ep;
652 struct xhci_ring *ring;
653 struct xhci_td *cur_td;
656 ep = (struct xhci_virt_ep *) arg;
659 spin_lock(&xhci->lock);
661 ep->stop_cmds_pending--;
662 if (xhci->xhc_state & XHCI_STATE_DYING) {
663 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
664 "xHCI as DYING, exiting.\n");
665 spin_unlock(&xhci->lock);
668 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
669 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
671 spin_unlock(&xhci->lock);
675 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
676 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
677 /* Oops, HC is dead or dying or at least not responding to the stop
680 xhci->xhc_state |= XHCI_STATE_DYING;
681 /* Disable interrupts from the host controller and start halting it */
683 spin_unlock(&xhci->lock);
685 ret = xhci_halt(xhci);
687 spin_lock(&xhci->lock);
689 /* This is bad; the host is not responding to commands and it's
690 * not allowing itself to be halted. At least interrupts are
691 * disabled, so we can set HC_STATE_HALT and notify the
692 * USB core. But if we call usb_hc_died(), it will attempt to
693 * disconnect all device drivers under this host. Those
694 * disconnect() methods will wait for all URBs to be unlinked,
695 * so we must complete them.
697 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
698 xhci_warn(xhci, "Completing active URBs anyway.\n");
699 /* We could turn all TDs on the rings to no-ops. This won't
700 * help if the host has cached part of the ring, and is slow if
701 * we want to preserve the cycle bit. Skip it and hope the host
702 * doesn't touch the memory.
705 for (i = 0; i < MAX_HC_SLOTS; i++) {
708 for (j = 0; j < 31; j++) {
709 temp_ep = &xhci->devs[i]->eps[j];
710 ring = temp_ep->ring;
713 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
714 "ep index %u\n", i, j);
715 while (!list_empty(&ring->td_list)) {
716 cur_td = list_first_entry(&ring->td_list,
719 list_del(&cur_td->td_list);
720 if (!list_empty(&cur_td->cancelled_td_list))
721 list_del(&cur_td->cancelled_td_list);
722 xhci_giveback_urb_in_irq(xhci, cur_td,
723 -ESHUTDOWN, "killed");
725 while (!list_empty(&temp_ep->cancelled_td_list)) {
726 cur_td = list_first_entry(
727 &temp_ep->cancelled_td_list,
730 list_del(&cur_td->cancelled_td_list);
731 xhci_giveback_urb_in_irq(xhci, cur_td,
732 -ESHUTDOWN, "killed");
736 spin_unlock(&xhci->lock);
737 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
738 xhci_dbg(xhci, "Calling usb_hc_died()\n");
739 usb_hc_died(xhci_to_hcd(xhci));
740 xhci_dbg(xhci, "xHCI host controller is dead.\n");
744 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
745 * we need to clear the set deq pending flag in the endpoint ring state, so that
746 * the TD queueing code can ring the doorbell again. We also need to ring the
747 * endpoint doorbell to restart the ring, but only if there aren't more
748 * cancellations pending.
750 static void handle_set_deq_completion(struct xhci_hcd *xhci,
751 struct xhci_event_cmd *event,
754 unsigned int slot_id;
755 unsigned int ep_index;
756 struct xhci_ring *ep_ring;
757 struct xhci_virt_device *dev;
758 struct xhci_ep_ctx *ep_ctx;
759 struct xhci_slot_ctx *slot_ctx;
761 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
762 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
763 dev = xhci->devs[slot_id];
764 ep_ring = dev->eps[ep_index].ring;
765 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
766 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
768 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
769 unsigned int ep_state;
770 unsigned int slot_state;
772 switch (GET_COMP_CODE(event->status)) {
774 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
775 "of stream ID configuration\n");
778 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
779 "to incorrect slot or ep state.\n");
780 ep_state = ep_ctx->ep_info;
781 ep_state &= EP_STATE_MASK;
782 slot_state = slot_ctx->dev_state;
783 slot_state = GET_SLOT_STATE(slot_state);
784 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
785 slot_state, ep_state);
788 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
789 "slot %u was not enabled.\n", slot_id);
792 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
793 "completion code of %u.\n",
794 GET_COMP_CODE(event->status));
797 /* OK what do we do now? The endpoint state is hosed, and we
798 * should never get to this point if the synchronization between
799 * queueing, and endpoint state are correct. This might happen
800 * if the device gets disconnected after we've finished
801 * cancelling URBs, which might not be an error...
804 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
808 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
809 ring_ep_doorbell(xhci, slot_id, ep_index);
812 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
813 struct xhci_event_cmd *event,
817 unsigned int ep_index;
818 struct xhci_ring *ep_ring;
820 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
821 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
822 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
823 /* This command will only fail if the endpoint wasn't halted,
826 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
827 (unsigned int) GET_COMP_CODE(event->status));
829 /* HW with the reset endpoint quirk needs to have a configure endpoint
830 * command complete before the endpoint can be used. Queue that here
831 * because the HW can't handle two commands being queued in a row.
833 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
834 xhci_dbg(xhci, "Queueing configure endpoint command\n");
835 xhci_queue_configure_endpoint(xhci,
836 xhci->devs[slot_id]->in_ctx->dma, slot_id,
838 xhci_ring_cmd_db(xhci);
840 /* Clear our internal halted state and restart the ring */
841 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
842 ring_ep_doorbell(xhci, slot_id, ep_index);
846 /* Check to see if a command in the device's command queue matches this one.
847 * Signal the completion or free the command, and return 1. Return 0 if the
848 * completed command isn't at the head of the command list.
850 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
851 struct xhci_virt_device *virt_dev,
852 struct xhci_event_cmd *event)
854 struct xhci_command *command;
856 if (list_empty(&virt_dev->cmd_list))
859 command = list_entry(virt_dev->cmd_list.next,
860 struct xhci_command, cmd_list);
861 if (xhci->cmd_ring->dequeue != command->command_trb)
865 GET_COMP_CODE(event->status);
866 list_del(&command->cmd_list);
867 if (command->completion)
868 complete(command->completion);
870 xhci_free_command(xhci, command);
874 static void handle_cmd_completion(struct xhci_hcd *xhci,
875 struct xhci_event_cmd *event)
877 int slot_id = TRB_TO_SLOT_ID(event->flags);
879 dma_addr_t cmd_dequeue_dma;
880 struct xhci_input_control_ctx *ctrl_ctx;
881 struct xhci_virt_device *virt_dev;
882 unsigned int ep_index;
883 struct xhci_ring *ep_ring;
884 unsigned int ep_state;
886 cmd_dma = event->cmd_trb;
887 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
888 xhci->cmd_ring->dequeue);
889 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
890 if (cmd_dequeue_dma == 0) {
891 xhci->error_bitmask |= 1 << 4;
894 /* Does the DMA address match our internal dequeue pointer address? */
895 if (cmd_dma != (u64) cmd_dequeue_dma) {
896 xhci->error_bitmask |= 1 << 5;
899 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
900 case TRB_TYPE(TRB_ENABLE_SLOT):
901 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
902 xhci->slot_id = slot_id;
905 complete(&xhci->addr_dev);
907 case TRB_TYPE(TRB_DISABLE_SLOT):
908 if (xhci->devs[slot_id])
909 xhci_free_virt_device(xhci, slot_id);
911 case TRB_TYPE(TRB_CONFIG_EP):
912 virt_dev = xhci->devs[slot_id];
913 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
916 * Configure endpoint commands can come from the USB core
917 * configuration or alt setting changes, or because the HW
918 * needed an extra configure endpoint command after a reset
919 * endpoint command. In the latter case, the xHCI driver is
920 * not waiting on the configure endpoint command.
922 ctrl_ctx = xhci_get_input_control_ctx(xhci,
924 /* Input ctx add_flags are the endpoint index plus one */
925 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
926 /* A usb_set_interface() call directly after clearing a halted
927 * condition may race on this quirky hardware.
928 * Not worth worrying about, since this is prototype hardware.
930 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
931 ep_index != (unsigned int) -1 &&
932 ctrl_ctx->add_flags - SLOT_FLAG ==
933 ctrl_ctx->drop_flags) {
934 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
935 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
936 if (!(ep_state & EP_HALTED))
937 goto bandwidth_change;
938 xhci_dbg(xhci, "Completed config ep cmd - "
939 "last ep index = %d, state = %d\n",
941 /* Clear our internal halted state and restart ring */
942 xhci->devs[slot_id]->eps[ep_index].ep_state &=
944 ring_ep_doorbell(xhci, slot_id, ep_index);
948 xhci_dbg(xhci, "Completed config ep cmd\n");
949 xhci->devs[slot_id]->cmd_status =
950 GET_COMP_CODE(event->status);
951 complete(&xhci->devs[slot_id]->cmd_completion);
953 case TRB_TYPE(TRB_EVAL_CONTEXT):
954 virt_dev = xhci->devs[slot_id];
955 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
957 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
958 complete(&xhci->devs[slot_id]->cmd_completion);
960 case TRB_TYPE(TRB_ADDR_DEV):
961 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
962 complete(&xhci->addr_dev);
964 case TRB_TYPE(TRB_STOP_RING):
965 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
967 case TRB_TYPE(TRB_SET_DEQ):
968 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
970 case TRB_TYPE(TRB_CMD_NOOP):
971 ++xhci->noops_handled;
973 case TRB_TYPE(TRB_RESET_EP):
974 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
976 case TRB_TYPE(TRB_RESET_DEV):
977 xhci_dbg(xhci, "Completed reset device command.\n");
978 slot_id = TRB_TO_SLOT_ID(
979 xhci->cmd_ring->dequeue->generic.field[3]);
980 virt_dev = xhci->devs[slot_id];
982 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
984 xhci_warn(xhci, "Reset device command completion "
985 "for disabled slot %u\n", slot_id);
988 /* Skip over unknown commands on the event ring */
989 xhci->error_bitmask |= 1 << 6;
992 inc_deq(xhci, xhci->cmd_ring, false);
995 static void handle_port_status(struct xhci_hcd *xhci,
996 union xhci_trb *event)
1000 /* Port status change events always have a successful completion code */
1001 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1002 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1003 xhci->error_bitmask |= 1 << 8;
1005 /* FIXME: core doesn't care about all port link state changes yet */
1006 port_id = GET_PORT_ID(event->generic.field[0]);
1007 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1009 /* Update event ring dequeue pointer before dropping the lock */
1010 inc_deq(xhci, xhci->event_ring, true);
1011 xhci_set_hc_event_deq(xhci);
1013 spin_unlock(&xhci->lock);
1014 /* Pass this up to the core */
1015 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1016 spin_lock(&xhci->lock);
1020 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1021 * at end_trb, which may be in another segment. If the suspect DMA address is a
1022 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1025 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1026 union xhci_trb *start_trb,
1027 union xhci_trb *end_trb,
1028 dma_addr_t suspect_dma)
1030 dma_addr_t start_dma;
1031 dma_addr_t end_seg_dma;
1032 dma_addr_t end_trb_dma;
1033 struct xhci_segment *cur_seg;
1035 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1036 cur_seg = start_seg;
1041 /* We may get an event for a Link TRB in the middle of a TD */
1042 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1043 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1044 /* If the end TRB isn't in this segment, this is set to 0 */
1045 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1047 if (end_trb_dma > 0) {
1048 /* The end TRB is in this segment, so suspect should be here */
1049 if (start_dma <= end_trb_dma) {
1050 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1053 /* Case for one segment with
1054 * a TD wrapped around to the top
1056 if ((suspect_dma >= start_dma &&
1057 suspect_dma <= end_seg_dma) ||
1058 (suspect_dma >= cur_seg->dma &&
1059 suspect_dma <= end_trb_dma))
1064 /* Might still be somewhere in this segment */
1065 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1068 cur_seg = cur_seg->next;
1069 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1070 } while (cur_seg != start_seg);
1075 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1076 unsigned int slot_id, unsigned int ep_index,
1077 struct xhci_td *td, union xhci_trb *event_trb)
1079 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1080 ep->ep_state |= EP_HALTED;
1081 ep->stopped_td = td;
1082 ep->stopped_trb = event_trb;
1084 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1085 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1087 ep->stopped_td = NULL;
1088 ep->stopped_trb = NULL;
1090 xhci_ring_cmd_db(xhci);
1093 /* Check if an error has halted the endpoint ring. The class driver will
1094 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1095 * However, a babble and other errors also halt the endpoint ring, and the class
1096 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1097 * Ring Dequeue Pointer command manually.
1099 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1100 struct xhci_ep_ctx *ep_ctx,
1101 unsigned int trb_comp_code)
1103 /* TRB completion codes that may require a manual halt cleanup */
1104 if (trb_comp_code == COMP_TX_ERR ||
1105 trb_comp_code == COMP_BABBLE ||
1106 trb_comp_code == COMP_SPLIT_ERR)
1107 /* The 0.96 spec says a babbling control endpoint
1108 * is not halted. The 0.96 spec says it is. Some HW
1109 * claims to be 0.95 compliant, but it halts the control
1110 * endpoint anyway. Check if a babble halted the
1113 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1119 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1121 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1122 /* Vendor defined "informational" completion code,
1123 * treat as not-an-error.
1125 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1127 xhci_dbg(xhci, "Treating code as success.\n");
1134 * If this function returns an error condition, it means it got a Transfer
1135 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1136 * At this point, the host controller is probably hosed and should be reset.
1138 static int handle_tx_event(struct xhci_hcd *xhci,
1139 struct xhci_transfer_event *event)
1141 struct xhci_virt_device *xdev;
1142 struct xhci_virt_ep *ep;
1143 struct xhci_ring *ep_ring;
1144 unsigned int slot_id;
1146 struct xhci_td *td = 0;
1147 dma_addr_t event_dma;
1148 struct xhci_segment *event_seg;
1149 union xhci_trb *event_trb;
1150 struct urb *urb = 0;
1151 int status = -EINPROGRESS;
1152 struct xhci_ep_ctx *ep_ctx;
1155 xhci_dbg(xhci, "In %s\n", __func__);
1156 slot_id = TRB_TO_SLOT_ID(event->flags);
1157 xdev = xhci->devs[slot_id];
1159 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1163 /* Endpoint ID is 1 based, our index is zero based */
1164 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1165 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1166 ep = &xdev->eps[ep_index];
1168 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1169 if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1170 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
1174 event_dma = event->buffer;
1175 /* This TRB should be in the TD at the head of this ring's TD list */
1176 xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
1177 if (list_empty(&ep_ring->td_list)) {
1178 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1179 TRB_TO_SLOT_ID(event->flags), ep_index);
1180 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1181 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1182 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1186 xhci_dbg(xhci, "%s - getting list entry\n", __func__);
1187 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1189 /* Is this a TRB in the currently executing TD? */
1190 xhci_dbg(xhci, "%s - looking for TD\n", __func__);
1191 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1192 td->last_trb, event_dma);
1193 xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
1195 /* HC is busted, give up! */
1196 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1199 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
1200 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1201 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1202 xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
1203 lower_32_bits(event->buffer));
1204 xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
1205 upper_32_bits(event->buffer));
1206 xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
1207 (unsigned int) event->transfer_len);
1208 xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
1209 (unsigned int) event->flags);
1211 /* Look for common error cases */
1212 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1213 switch (trb_comp_code) {
1214 /* Skip codes that require special handling depending on
1221 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1223 case COMP_STOP_INVAL:
1224 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1227 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1228 ep->ep_state |= EP_HALTED;
1232 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1235 case COMP_SPLIT_ERR:
1237 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1241 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1242 status = -EOVERFLOW;
1245 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1249 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1253 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
1257 /* Now update the urb's actual_length and give back to the core */
1258 /* Was this a control transfer? */
1259 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
1260 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1261 switch (trb_comp_code) {
1263 if (event_trb == ep_ring->dequeue) {
1264 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
1265 status = -ESHUTDOWN;
1266 } else if (event_trb != td->last_trb) {
1267 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
1268 status = -ESHUTDOWN;
1270 xhci_dbg(xhci, "Successful control transfer!\n");
1275 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1276 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1277 status = -EREMOTEIO;
1283 if (!xhci_requires_manual_halt_cleanup(xhci,
1284 ep_ctx, trb_comp_code))
1286 xhci_dbg(xhci, "TRB error code %u, "
1287 "halted endpoint index = %u\n",
1288 trb_comp_code, ep_index);
1289 /* else fall through */
1291 /* Did we transfer part of the data (middle) phase? */
1292 if (event_trb != ep_ring->dequeue &&
1293 event_trb != td->last_trb)
1294 td->urb->actual_length =
1295 td->urb->transfer_buffer_length
1296 - TRB_LEN(event->transfer_len);
1298 td->urb->actual_length = 0;
1300 xhci_cleanup_halted_endpoint(xhci,
1301 slot_id, ep_index, td, event_trb);
1305 * Did we transfer any data, despite the errors that might have
1306 * happened? I.e. did we get past the setup stage?
1308 if (event_trb != ep_ring->dequeue) {
1309 /* The event was for the status stage */
1310 if (event_trb == td->last_trb) {
1311 if (td->urb->actual_length != 0) {
1312 /* Don't overwrite a previously set error code */
1313 if ((status == -EINPROGRESS ||
1315 (td->urb->transfer_flags
1316 & URB_SHORT_NOT_OK))
1317 /* Did we already see a short data stage? */
1318 status = -EREMOTEIO;
1320 td->urb->actual_length =
1321 td->urb->transfer_buffer_length;
1324 /* Maybe the event was for the data stage? */
1325 if (trb_comp_code != COMP_STOP_INVAL) {
1326 /* We didn't stop on a link TRB in the middle */
1327 td->urb->actual_length =
1328 td->urb->transfer_buffer_length -
1329 TRB_LEN(event->transfer_len);
1330 xhci_dbg(xhci, "Waiting for status stage event\n");
1337 switch (trb_comp_code) {
1339 /* Double check that the HW transferred everything. */
1340 if (event_trb != td->last_trb) {
1341 xhci_warn(xhci, "WARN Successful completion "
1343 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1344 status = -EREMOTEIO;
1348 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1349 xhci_dbg(xhci, "Successful bulk "
1352 xhci_dbg(xhci, "Successful interrupt "
1358 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1359 status = -EREMOTEIO;
1364 /* Others already handled above */
1367 dev_dbg(&td->urb->dev->dev,
1368 "ep %#x - asked for %d bytes, "
1369 "%d bytes untransferred\n",
1370 td->urb->ep->desc.bEndpointAddress,
1371 td->urb->transfer_buffer_length,
1372 TRB_LEN(event->transfer_len));
1373 /* Fast path - was this the last TRB in the TD for this URB? */
1374 if (event_trb == td->last_trb) {
1375 if (TRB_LEN(event->transfer_len) != 0) {
1376 td->urb->actual_length =
1377 td->urb->transfer_buffer_length -
1378 TRB_LEN(event->transfer_len);
1379 if (td->urb->transfer_buffer_length <
1380 td->urb->actual_length) {
1381 xhci_warn(xhci, "HC gave bad length "
1382 "of %d bytes left\n",
1383 TRB_LEN(event->transfer_len));
1384 td->urb->actual_length = 0;
1385 if (td->urb->transfer_flags &
1387 status = -EREMOTEIO;
1391 /* Don't overwrite a previously set error code */
1392 if (status == -EINPROGRESS) {
1393 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1394 status = -EREMOTEIO;
1399 td->urb->actual_length = td->urb->transfer_buffer_length;
1400 /* Ignore a short packet completion if the
1401 * untransferred length was zero.
1403 if (status == -EREMOTEIO)
1407 /* Slow path - walk the list, starting from the dequeue
1408 * pointer, to get the actual length transferred.
1410 union xhci_trb *cur_trb;
1411 struct xhci_segment *cur_seg;
1413 td->urb->actual_length = 0;
1414 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1415 cur_trb != event_trb;
1416 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1417 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1418 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1419 td->urb->actual_length +=
1420 TRB_LEN(cur_trb->generic.field[2]);
1422 /* If the ring didn't stop on a Link or No-op TRB, add
1423 * in the actual bytes transferred from the Normal TRB
1425 if (trb_comp_code != COMP_STOP_INVAL)
1426 td->urb->actual_length +=
1427 TRB_LEN(cur_trb->generic.field[2]) -
1428 TRB_LEN(event->transfer_len);
1431 if (trb_comp_code == COMP_STOP_INVAL ||
1432 trb_comp_code == COMP_STOP) {
1433 /* The Endpoint Stop Command completion will take care of any
1434 * stopped TDs. A stopped TD may be restarted, so don't update
1435 * the ring dequeue pointer or take this TD off any lists yet.
1437 ep->stopped_td = td;
1438 ep->stopped_trb = event_trb;
1440 if (trb_comp_code == COMP_STALL) {
1441 /* The transfer is completed from the driver's
1442 * perspective, but we need to issue a set dequeue
1443 * command for this stalled endpoint to move the dequeue
1444 * pointer past the TD. We can't do that here because
1445 * the halt condition must be cleared first. Let the
1446 * USB class driver clear the stall later.
1448 ep->stopped_td = td;
1449 ep->stopped_trb = event_trb;
1450 } else if (xhci_requires_manual_halt_cleanup(xhci,
1451 ep_ctx, trb_comp_code)) {
1452 /* Other types of errors halt the endpoint, but the
1453 * class driver doesn't call usb_reset_endpoint() unless
1454 * the error is -EPIPE. Clear the halted status in the
1455 * xHCI hardware manually.
1457 xhci_cleanup_halted_endpoint(xhci,
1458 slot_id, ep_index, td, event_trb);
1460 /* Update ring dequeue pointer */
1461 while (ep_ring->dequeue != td->last_trb)
1462 inc_deq(xhci, ep_ring, false);
1463 inc_deq(xhci, ep_ring, false);
1467 /* Clean up the endpoint's TD list */
1469 /* Do one last check of the actual transfer length.
1470 * If the host controller said we transferred more data than
1471 * the buffer length, urb->actual_length will be a very big
1472 * number (since it's unsigned). Play it safe and say we didn't
1473 * transfer anything.
1475 if (urb->actual_length > urb->transfer_buffer_length) {
1476 xhci_warn(xhci, "URB transfer length is wrong, "
1477 "xHC issue? req. len = %u, "
1479 urb->transfer_buffer_length,
1480 urb->actual_length);
1481 urb->actual_length = 0;
1482 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1483 status = -EREMOTEIO;
1487 list_del(&td->td_list);
1488 /* Was this TD slated to be cancelled but completed anyway? */
1489 if (!list_empty(&td->cancelled_td_list))
1490 list_del(&td->cancelled_td_list);
1492 /* Leave the TD around for the reset endpoint function to use
1493 * (but only if it's not a control endpoint, since we already
1494 * queued the Set TR dequeue pointer command for stalled
1495 * control endpoints).
1497 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1498 (trb_comp_code != COMP_STALL &&
1499 trb_comp_code != COMP_BABBLE)) {
1505 inc_deq(xhci, xhci->event_ring, true);
1506 xhci_set_hc_event_deq(xhci);
1508 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1510 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1511 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1512 urb, urb->actual_length, status);
1513 spin_unlock(&xhci->lock);
1514 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1515 spin_lock(&xhci->lock);
1521 * This function handles all OS-owned events on the event ring. It may drop
1522 * xhci->lock between event processing (e.g. to pass up port status changes).
1524 void xhci_handle_event(struct xhci_hcd *xhci)
1526 union xhci_trb *event;
1527 int update_ptrs = 1;
1530 xhci_dbg(xhci, "In %s\n", __func__);
1531 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1532 xhci->error_bitmask |= 1 << 1;
1536 event = xhci->event_ring->dequeue;
1537 /* Does the HC or OS own the TRB? */
1538 if ((event->event_cmd.flags & TRB_CYCLE) !=
1539 xhci->event_ring->cycle_state) {
1540 xhci->error_bitmask |= 1 << 2;
1543 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1545 /* FIXME: Handle more event types. */
1546 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1547 case TRB_TYPE(TRB_COMPLETION):
1548 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1549 handle_cmd_completion(xhci, &event->event_cmd);
1550 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1552 case TRB_TYPE(TRB_PORT_STATUS):
1553 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1554 handle_port_status(xhci, event);
1555 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1558 case TRB_TYPE(TRB_TRANSFER):
1559 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1560 ret = handle_tx_event(xhci, &event->trans_event);
1561 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1563 xhci->error_bitmask |= 1 << 9;
1568 xhci->error_bitmask |= 1 << 3;
1570 /* Any of the above functions may drop and re-acquire the lock, so check
1571 * to make sure a watchdog timer didn't mark the host as non-responsive.
1573 if (xhci->xhc_state & XHCI_STATE_DYING) {
1574 xhci_dbg(xhci, "xHCI host dying, returning from "
1575 "event handler.\n");
1580 /* Update SW and HC event ring dequeue pointer */
1581 inc_deq(xhci, xhci->event_ring, true);
1582 xhci_set_hc_event_deq(xhci);
1584 /* Are there more items on the event ring? */
1585 xhci_handle_event(xhci);
1588 /**** Endpoint Ring Operations ****/
1591 * Generic function for queueing a TRB on a ring.
1592 * The caller must have checked to make sure there's room on the ring.
1594 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1596 u32 field1, u32 field2, u32 field3, u32 field4)
1598 struct xhci_generic_trb *trb;
1600 trb = &ring->enqueue->generic;
1601 trb->field[0] = field1;
1602 trb->field[1] = field2;
1603 trb->field[2] = field3;
1604 trb->field[3] = field4;
1605 inc_enq(xhci, ring, consumer);
1609 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1610 * FIXME allocate segments if the ring is full.
1612 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1613 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1615 /* Make sure the endpoint has been added to xHC schedule */
1616 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1618 case EP_STATE_DISABLED:
1620 * USB core changed config/interfaces without notifying us,
1621 * or hardware is reporting the wrong state.
1623 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1625 case EP_STATE_ERROR:
1626 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1627 /* FIXME event handling code for error needs to clear it */
1628 /* XXX not sure if this should be -ENOENT or not */
1630 case EP_STATE_HALTED:
1631 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1632 case EP_STATE_STOPPED:
1633 case EP_STATE_RUNNING:
1636 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1638 * FIXME issue Configure Endpoint command to try to get the HC
1639 * back into a known state.
1643 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1644 /* FIXME allocate more room */
1645 xhci_err(xhci, "ERROR no room on ep ring\n");
1651 static int prepare_transfer(struct xhci_hcd *xhci,
1652 struct xhci_virt_device *xdev,
1653 unsigned int ep_index,
1654 unsigned int num_trbs,
1656 struct xhci_td **td,
1660 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1661 ret = prepare_ring(xhci, xdev->eps[ep_index].ring,
1662 ep_ctx->ep_info & EP_STATE_MASK,
1663 num_trbs, mem_flags);
1666 *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1669 INIT_LIST_HEAD(&(*td)->td_list);
1670 INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1672 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1673 if (unlikely(ret)) {
1679 urb->hcpriv = (void *) (*td);
1680 /* Add this TD to the tail of the endpoint ring's TD list */
1681 list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list);
1682 (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg;
1683 (*td)->first_trb = xdev->eps[ep_index].ring->enqueue;
1688 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1690 int num_sgs, num_trbs, running_total, temp, i;
1691 struct scatterlist *sg;
1694 num_sgs = urb->num_sgs;
1695 temp = urb->transfer_buffer_length;
1697 xhci_dbg(xhci, "count sg list trbs: \n");
1699 for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1700 unsigned int previous_total_trbs = num_trbs;
1701 unsigned int len = sg_dma_len(sg);
1703 /* Scatter gather list entries may cross 64KB boundaries */
1704 running_total = TRB_MAX_BUFF_SIZE -
1705 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1706 if (running_total != 0)
1709 /* How many more 64KB chunks to transfer, how many more TRBs? */
1710 while (running_total < sg_dma_len(sg)) {
1712 running_total += TRB_MAX_BUFF_SIZE;
1714 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1715 i, (unsigned long long)sg_dma_address(sg),
1716 len, len, num_trbs - previous_total_trbs);
1718 len = min_t(int, len, temp);
1723 xhci_dbg(xhci, "\n");
1724 if (!in_interrupt())
1725 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1726 urb->ep->desc.bEndpointAddress,
1727 urb->transfer_buffer_length,
1732 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1735 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1736 "TRBs, %d left\n", __func__,
1737 urb->ep->desc.bEndpointAddress, num_trbs);
1738 if (running_total != urb->transfer_buffer_length)
1739 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1740 "queued %#x (%d), asked for %#x (%d)\n",
1742 urb->ep->desc.bEndpointAddress,
1743 running_total, running_total,
1744 urb->transfer_buffer_length,
1745 urb->transfer_buffer_length);
1748 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1749 unsigned int ep_index, int start_cycle,
1750 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1753 * Pass all the TRBs to the hardware at once and make sure this write
1757 start_trb->field[3] |= start_cycle;
1758 ring_ep_doorbell(xhci, slot_id, ep_index);
1762 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1763 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1764 * (comprised of sg list entries) can take several service intervals to
1767 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1768 struct urb *urb, int slot_id, unsigned int ep_index)
1770 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1771 xhci->devs[slot_id]->out_ctx, ep_index);
1775 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1776 ep_interval = urb->interval;
1777 /* Convert to microframes */
1778 if (urb->dev->speed == USB_SPEED_LOW ||
1779 urb->dev->speed == USB_SPEED_FULL)
1781 /* FIXME change this to a warning and a suggestion to use the new API
1782 * to set the polling interval (once the API is added).
1784 if (xhci_interval != ep_interval) {
1785 if (!printk_ratelimit())
1786 dev_dbg(&urb->dev->dev, "Driver uses different interval"
1787 " (%d microframe%s) than xHCI "
1788 "(%d microframe%s)\n",
1790 ep_interval == 1 ? "" : "s",
1792 xhci_interval == 1 ? "" : "s");
1793 urb->interval = xhci_interval;
1794 /* Convert back to frames for LS/FS devices */
1795 if (urb->dev->speed == USB_SPEED_LOW ||
1796 urb->dev->speed == USB_SPEED_FULL)
1799 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1803 * The TD size is the number of bytes remaining in the TD (including this TRB),
1804 * right shifted by 10.
1805 * It must fit in bits 21:17, so it can't be bigger than 31.
1807 static u32 xhci_td_remainder(unsigned int remainder)
1809 u32 max = (1 << (21 - 17 + 1)) - 1;
1811 if ((remainder >> 10) >= max)
1814 return (remainder >> 10) << 17;
1817 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1818 struct urb *urb, int slot_id, unsigned int ep_index)
1820 struct xhci_ring *ep_ring;
1821 unsigned int num_trbs;
1823 struct scatterlist *sg;
1825 int trb_buff_len, this_sg_len, running_total;
1829 struct xhci_generic_trb *start_trb;
1832 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1833 num_trbs = count_sg_trbs_needed(xhci, urb);
1834 num_sgs = urb->num_sgs;
1836 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1837 ep_index, num_trbs, urb, &td, mem_flags);
1838 if (trb_buff_len < 0)
1839 return trb_buff_len;
1841 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1842 * until we've finished creating all the other TRBs. The ring's cycle
1843 * state may change as we enqueue the other TRBs, so save it too.
1845 start_trb = &ep_ring->enqueue->generic;
1846 start_cycle = ep_ring->cycle_state;
1850 * How much data is in the first TRB?
1852 * There are three forces at work for TRB buffer pointers and lengths:
1853 * 1. We don't want to walk off the end of this sg-list entry buffer.
1854 * 2. The transfer length that the driver requested may be smaller than
1855 * the amount of memory allocated for this scatter-gather list.
1856 * 3. TRBs buffers can't cross 64KB boundaries.
1859 addr = (u64) sg_dma_address(sg);
1860 this_sg_len = sg_dma_len(sg);
1861 trb_buff_len = TRB_MAX_BUFF_SIZE -
1862 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1863 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1864 if (trb_buff_len > urb->transfer_buffer_length)
1865 trb_buff_len = urb->transfer_buffer_length;
1866 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1870 /* Queue the first TRB, even if it's zero-length */
1873 u32 length_field = 0;
1876 /* Don't change the cycle bit of the first TRB until later */
1880 field |= ep_ring->cycle_state;
1882 /* Chain all the TRBs together; clear the chain bit in the last
1883 * TRB to indicate it's the last TRB in the chain.
1888 /* FIXME - add check for ZERO_PACKET flag before this */
1889 td->last_trb = ep_ring->enqueue;
1892 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1893 "64KB boundary at %#x, end dma = %#x\n",
1894 (unsigned int) addr, trb_buff_len, trb_buff_len,
1895 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1896 (unsigned int) addr + trb_buff_len);
1897 if (TRB_MAX_BUFF_SIZE -
1898 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1899 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1900 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1901 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1902 (unsigned int) addr + trb_buff_len);
1904 remainder = xhci_td_remainder(urb->transfer_buffer_length -
1906 length_field = TRB_LEN(trb_buff_len) |
1909 queue_trb(xhci, ep_ring, false,
1910 lower_32_bits(addr),
1911 upper_32_bits(addr),
1913 /* We always want to know if the TRB was short,
1914 * or we won't get an event when it completes.
1915 * (Unless we use event data TRBs, which are a
1916 * waste of space and HC resources.)
1918 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1920 running_total += trb_buff_len;
1922 /* Calculate length for next transfer --
1923 * Are we done queueing all the TRBs for this sg entry?
1925 this_sg_len -= trb_buff_len;
1926 if (this_sg_len == 0) {
1931 addr = (u64) sg_dma_address(sg);
1932 this_sg_len = sg_dma_len(sg);
1934 addr += trb_buff_len;
1937 trb_buff_len = TRB_MAX_BUFF_SIZE -
1938 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1939 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1940 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1942 urb->transfer_buffer_length - running_total;
1943 } while (running_total < urb->transfer_buffer_length);
1945 check_trb_math(urb, num_trbs, running_total);
1946 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1950 /* This is very similar to what ehci-q.c qtd_fill() does */
1951 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1952 struct urb *urb, int slot_id, unsigned int ep_index)
1954 struct xhci_ring *ep_ring;
1957 struct xhci_generic_trb *start_trb;
1960 u32 field, length_field;
1962 int running_total, trb_buff_len, ret;
1966 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1968 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1971 /* How much data is (potentially) left before the 64KB boundary? */
1972 running_total = TRB_MAX_BUFF_SIZE -
1973 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1975 /* If there's some data on this 64KB chunk, or we have to send a
1976 * zero-length transfer, we need at least one TRB
1978 if (running_total != 0 || urb->transfer_buffer_length == 0)
1980 /* How many more 64KB chunks to transfer, how many more TRBs? */
1981 while (running_total < urb->transfer_buffer_length) {
1983 running_total += TRB_MAX_BUFF_SIZE;
1985 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1987 if (!in_interrupt())
1988 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1989 urb->ep->desc.bEndpointAddress,
1990 urb->transfer_buffer_length,
1991 urb->transfer_buffer_length,
1992 (unsigned long long)urb->transfer_dma,
1995 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1996 num_trbs, urb, &td, mem_flags);
2001 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2002 * until we've finished creating all the other TRBs. The ring's cycle
2003 * state may change as we enqueue the other TRBs, so save it too.
2005 start_trb = &ep_ring->enqueue->generic;
2006 start_cycle = ep_ring->cycle_state;
2009 /* How much data is in the first TRB? */
2010 addr = (u64) urb->transfer_dma;
2011 trb_buff_len = TRB_MAX_BUFF_SIZE -
2012 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2013 if (urb->transfer_buffer_length < trb_buff_len)
2014 trb_buff_len = urb->transfer_buffer_length;
2018 /* Queue the first TRB, even if it's zero-length */
2023 /* Don't change the cycle bit of the first TRB until later */
2027 field |= ep_ring->cycle_state;
2029 /* Chain all the TRBs together; clear the chain bit in the last
2030 * TRB to indicate it's the last TRB in the chain.
2035 /* FIXME - add check for ZERO_PACKET flag before this */
2036 td->last_trb = ep_ring->enqueue;
2039 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2041 length_field = TRB_LEN(trb_buff_len) |
2044 queue_trb(xhci, ep_ring, false,
2045 lower_32_bits(addr),
2046 upper_32_bits(addr),
2048 /* We always want to know if the TRB was short,
2049 * or we won't get an event when it completes.
2050 * (Unless we use event data TRBs, which are a
2051 * waste of space and HC resources.)
2053 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2055 running_total += trb_buff_len;
2057 /* Calculate length for next transfer */
2058 addr += trb_buff_len;
2059 trb_buff_len = urb->transfer_buffer_length - running_total;
2060 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2061 trb_buff_len = TRB_MAX_BUFF_SIZE;
2062 } while (running_total < urb->transfer_buffer_length);
2064 check_trb_math(urb, num_trbs, running_total);
2065 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
2069 /* Caller must have locked xhci->lock */
2070 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2071 struct urb *urb, int slot_id, unsigned int ep_index)
2073 struct xhci_ring *ep_ring;
2076 struct usb_ctrlrequest *setup;
2077 struct xhci_generic_trb *start_trb;
2079 u32 field, length_field;
2082 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2085 * Need to copy setup packet into setup TRB, so we can't use the setup
2088 if (!urb->setup_packet)
2091 if (!in_interrupt())
2092 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2094 /* 1 TRB for setup, 1 for status */
2097 * Don't need to check if we need additional event data and normal TRBs,
2098 * since data in control transfers will never get bigger than 16MB
2099 * XXX: can we get a buffer that crosses 64KB boundaries?
2101 if (urb->transfer_buffer_length > 0)
2103 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
2104 urb, &td, mem_flags);
2109 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2110 * until we've finished creating all the other TRBs. The ring's cycle
2111 * state may change as we enqueue the other TRBs, so save it too.
2113 start_trb = &ep_ring->enqueue->generic;
2114 start_cycle = ep_ring->cycle_state;
2116 /* Queue setup TRB - see section 6.4.1.2.1 */
2117 /* FIXME better way to translate setup_packet into two u32 fields? */
2118 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2119 queue_trb(xhci, ep_ring, false,
2120 /* FIXME endianness is probably going to bite my ass here. */
2121 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2122 setup->wIndex | setup->wLength << 16,
2123 TRB_LEN(8) | TRB_INTR_TARGET(0),
2124 /* Immediate data in pointer */
2125 TRB_IDT | TRB_TYPE(TRB_SETUP));
2127 /* If there's data, queue data TRBs */
2129 length_field = TRB_LEN(urb->transfer_buffer_length) |
2130 xhci_td_remainder(urb->transfer_buffer_length) |
2132 if (urb->transfer_buffer_length > 0) {
2133 if (setup->bRequestType & USB_DIR_IN)
2134 field |= TRB_DIR_IN;
2135 queue_trb(xhci, ep_ring, false,
2136 lower_32_bits(urb->transfer_dma),
2137 upper_32_bits(urb->transfer_dma),
2139 /* Event on short tx */
2140 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2143 /* Save the DMA address of the last TRB in the TD */
2144 td->last_trb = ep_ring->enqueue;
2146 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2147 /* If the device sent data, the status stage is an OUT transfer */
2148 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2152 queue_trb(xhci, ep_ring, false,
2156 /* Event on completion */
2157 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2159 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
2163 /**** Command Ring Operations ****/
2165 /* Generic function for queueing a command TRB on the command ring.
2166 * Check to make sure there's room on the command ring for one command TRB.
2167 * Also check that there's room reserved for commands that must not fail.
2168 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2169 * then only check for the number of reserved spots.
2170 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2171 * because the command event handler may want to resubmit a failed command.
2173 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2174 u32 field3, u32 field4, bool command_must_succeed)
2176 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2177 if (!command_must_succeed)
2180 if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
2181 if (!in_interrupt())
2182 xhci_err(xhci, "ERR: No room for command on command ring\n");
2183 if (command_must_succeed)
2184 xhci_err(xhci, "ERR: Reserved TRB counting for "
2185 "unfailable commands failed.\n");
2188 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
2189 field4 | xhci->cmd_ring->cycle_state);
2193 /* Queue a no-op command on the command ring */
2194 static int queue_cmd_noop(struct xhci_hcd *xhci)
2196 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2200 * Place a no-op command on the command ring to test the command and
2203 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2205 if (queue_cmd_noop(xhci) < 0)
2207 xhci->noops_submitted++;
2208 return xhci_ring_cmd_db;
2211 /* Queue a slot enable or disable request on the command ring */
2212 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2214 return queue_command(xhci, 0, 0, 0,
2215 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2218 /* Queue an address device command TRB */
2219 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2222 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2223 upper_32_bits(in_ctx_ptr), 0,
2224 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2228 /* Queue a reset device command TRB */
2229 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
2231 return queue_command(xhci, 0, 0, 0,
2232 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
2236 /* Queue a configure endpoint command TRB */
2237 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2238 u32 slot_id, bool command_must_succeed)
2240 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2241 upper_32_bits(in_ctx_ptr), 0,
2242 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2243 command_must_succeed);
2246 /* Queue an evaluate context command TRB */
2247 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2250 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2251 upper_32_bits(in_ctx_ptr), 0,
2252 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2256 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2257 unsigned int ep_index)
2259 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2260 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2261 u32 type = TRB_TYPE(TRB_STOP_RING);
2263 return queue_command(xhci, 0, 0, 0,
2264 trb_slot_id | trb_ep_index | type, false);
2267 /* Set Transfer Ring Dequeue Pointer command.
2268 * This should not be used for endpoints that have streams enabled.
2270 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2271 unsigned int ep_index, struct xhci_segment *deq_seg,
2272 union xhci_trb *deq_ptr, u32 cycle_state)
2275 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2276 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2277 u32 type = TRB_TYPE(TRB_SET_DEQ);
2279 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2281 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2282 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2286 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2287 upper_32_bits(addr), 0,
2288 trb_slot_id | trb_ep_index | type, false);
2291 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2292 unsigned int ep_index)
2294 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2295 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2296 u32 type = TRB_TYPE(TRB_RESET_EP);
2298 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,