drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
  70
  71 int i915_enable_fbc __read_mostly = -1;
  72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  73 MODULE_PARM_DESC(i915_enable_fbc,
  74                 "Enable frame buffer compression for power savings "
  75                 "(default: -1 (use per-chip default))");
  76
  77 unsigned int i915_lvds_downclock __read_mostly = 0;
  78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  79 MODULE_PARM_DESC(lvds_downclock,
  80                 "Use panel (LVDS/eDP) downclocking for power savings "
  81                 "(default: false)");
  82
  83 int i915_panel_use_ssc __read_mostly = -1;
  84 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  85 MODULE_PARM_DESC(lvds_use_ssc,
  86                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  87                 "(default: auto from VBT)");
  88
  89 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  90 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  91 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  92                 "Override selection of SDVO panel mode in the VBT "
  93                 "(default: auto)");
  94
  95 static bool i915_try_reset __read_mostly = true;
  96 module_param_named(reset, i915_try_reset, bool, 0600);
  97 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  98
  99 bool i915_enable_hangcheck __read_mostly = true;
 100 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 101 MODULE_PARM_DESC(enable_hangcheck,
 102                 "Periodically check GPU activity for detecting hangs. "
 103                 "WARNING: Disabling this can cause system wide hangs. "
 104                 "(default: true)");
 105
 106 static struct drm_driver driver;
 107 extern int intel_agp_enabled;
 108
 109 #define INTEL_VGA_DEVICE(id, info) {            \
 110         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 111         .class_mask = 0xff0000,                 \
 112         .vendor = 0x8086,                       \
 113         .device = id,                           \
 114         .subvendor = PCI_ANY_ID,                \
 115         .subdevice = PCI_ANY_ID,                \
 116         .driver_data = (unsigned long) info }
 117
 118 static const struct intel_device_info intel_i830_info = {
 119         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 120         .has_overlay = 1, .overlay_needs_physical = 1,
 121 };
 122
 123 static const struct intel_device_info intel_845g_info = {
 124         .gen = 2,
 125         .has_overlay = 1, .overlay_needs_physical = 1,
 126 };
 127
 128 static const struct intel_device_info intel_i85x_info = {
 129         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 130         .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132 };
 133
 134 static const struct intel_device_info intel_i865g_info = {
 135         .gen = 2,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_i915g_info = {
 140         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 141         .has_overlay = 1, .overlay_needs_physical = 1,
 142 };
 143 static const struct intel_device_info intel_i915gm_info = {
 144         .gen = 3, .is_mobile = 1,
 145         .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147         .supports_tv = 1,
 148 };
 149 static const struct intel_device_info intel_i945g_info = {
 150         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153 static const struct intel_device_info intel_i945gm_info = {
 154         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 155         .has_hotplug = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157         .supports_tv = 1,
 158 };
 159
 160 static const struct intel_device_info intel_i965g_info = {
 161         .gen = 4, .is_broadwater = 1,
 162         .has_hotplug = 1,
 163         .has_overlay = 1,
 164 };
 165
 166 static const struct intel_device_info intel_i965gm_info = {
 167         .gen = 4, .is_crestline = 1,
 168         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 169         .has_overlay = 1,
 170         .supports_tv = 1,
 171 };
 172
 173 static const struct intel_device_info intel_g33_info = {
 174         .gen = 3, .is_g33 = 1,
 175         .need_gfx_hws = 1, .has_hotplug = 1,
 176         .has_overlay = 1,
 177 };
 178
 179 static const struct intel_device_info intel_g45_info = {
 180         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 181         .has_pipe_cxsr = 1, .has_hotplug = 1,
 182         .has_bsd_ring = 1,
 183 };
 184
 185 static const struct intel_device_info intel_gm45_info = {
 186         .gen = 4, .is_g4x = 1,
 187         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 188         .has_pipe_cxsr = 1, .has_hotplug = 1,
 189         .supports_tv = 1,
 190         .has_bsd_ring = 1,
 191 };
 192
 193 static const struct intel_device_info intel_pineview_info = {
 194         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 195         .need_gfx_hws = 1, .has_hotplug = 1,
 196         .has_overlay = 1,
 197 };
 198
 199 static const struct intel_device_info intel_ironlake_d_info = {
 200         .gen = 5,
 201         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 202         .has_bsd_ring = 1,
 203 };
 204
 205 static const struct intel_device_info intel_ironlake_m_info = {
 206         .gen = 5, .is_mobile = 1,
 207         .need_gfx_hws = 1, .has_hotplug = 1,
 208         .has_fbc = 1,
 209         .has_bsd_ring = 1,
 210 };
 211
 212 static const struct intel_device_info intel_sandybridge_d_info = {
 213         .gen = 6,
 214         .need_gfx_hws = 1, .has_hotplug = 1,
 215         .has_bsd_ring = 1,
 216         .has_blt_ring = 1,
 217 };
 218
 219 static const struct intel_device_info intel_sandybridge_m_info = {
 220         .gen = 6, .is_mobile = 1,
 221         .need_gfx_hws = 1, .has_hotplug = 1,
 222         .has_fbc = 1,
 223         .has_bsd_ring = 1,
 224         .has_blt_ring = 1,
 225 };
 226
 227 static const struct intel_device_info intel_ivybridge_d_info = {
 228         .is_ivybridge = 1, .gen = 7,
 229         .need_gfx_hws = 1, .has_hotplug = 1,
 230         .has_bsd_ring = 1,
 231         .has_blt_ring = 1,
 232 };
 233
 234 static const struct intel_device_info intel_ivybridge_m_info = {
 235         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 238         .has_bsd_ring = 1,
 239         .has_blt_ring = 1,
 240 };
 241
 242 static const struct pci_device_id pciidlist[] = {               /* aka */
 243         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 244         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 245         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 246         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 247         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 248         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 249         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 250         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 251         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 252         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 253         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 254         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 255         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 256         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 257         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 258         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 259         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 260         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 261         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 262         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 263         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 264         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 265         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 266         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 267         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 268         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 269         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 270         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 271         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 272         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 273         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 274         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 275         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 276         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 277         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 278         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 279         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 280         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 281         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 282         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 283         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 284         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 285         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 286         {0, 0, 0}
 287 };
 288
 289 #if defined(CONFIG_DRM_I915_KMS)
 290 MODULE_DEVICE_TABLE(pci, pciidlist);
 291 #endif
 292
 293 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 294 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 295 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 296 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 297
 298 void intel_detect_pch(struct drm_device *dev)
 299 {
 300         struct drm_i915_private *dev_priv = dev->dev_private;
 301         struct pci_dev *pch;
 302
 303         /*
 304          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 305          * make graphics device passthrough work easy for VMM, that only
 306          * need to expose ISA bridge to let driver know the real hardware
 307          * underneath. This is a requirement from virtualization team.
 308          */
 309         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 310         if (pch) {
 311                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 312                         int id;
 313                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 314
 315                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 316                                 dev_priv->pch_type = PCH_IBX;
 317                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 318                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 319                                 dev_priv->pch_type = PCH_CPT;
 320                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 321                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 322                                 /* PantherPoint is CPT compatible */
 323                                 dev_priv->pch_type = PCH_CPT;
 324                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 325                         }
 326                 }
 327                 pci_dev_put(pch);
 328         }
 329 }
 330
 331 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 332 {
 333         int count;
 334
 335         count = 0;
 336         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 337                 udelay(10);
 338
 339         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 340         POSTING_READ(FORCEWAKE);
 341
 342         count = 0;
 343         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 344                 udelay(10);
 345 }
 346
 347 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 348 {
 349         int count;
 350
 351         count = 0;
 352         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 353                 udelay(10);
 354
 355         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 356         POSTING_READ(FORCEWAKE_MT);
 357
 358         count = 0;
 359         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 360                 udelay(10);
 361 }
 362
 363 /*
 364  * Generally this is called implicitly by the register read function. However,
 365  * if some sequence requires the GT to not power down then this function should
 366  * be called at the beginning of the sequence followed by a call to
 367  * gen6_gt_force_wake_put() at the end of the sequence.
 368  */
 369 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 370 {
 371         unsigned long irqflags;
 372
 373         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 374         if (dev_priv->forcewake_count++ == 0)
 375                 dev_priv->display.force_wake_get(dev_priv);
 376         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 377 }
 378
 379 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 380 {
 381         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 382         POSTING_READ(FORCEWAKE);
 383 }
 384
 385 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 386 {
 387         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 388         POSTING_READ(FORCEWAKE_MT);
 389 }
 390
 391 /*
 392  * see gen6_gt_force_wake_get()
 393  */
 394 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 395 {
 396         unsigned long irqflags;
 397
 398         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 399         if (--dev_priv->forcewake_count == 0)
 400                 dev_priv->display.force_wake_put(dev_priv);
 401         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 402 }
 403
 404 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 405 {
 406         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 407                 int loop = 500;
 408                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 409                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 410                         udelay(10);
 411                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 412                 }
 413                 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
 414                 dev_priv->gt_fifo_count = fifo;
 415         }
 416         dev_priv->gt_fifo_count--;
 417 }
 418
 419 static int i915_drm_freeze(struct drm_device *dev)
 420 {
 421         struct drm_i915_private *dev_priv = dev->dev_private;
 422
 423         drm_kms_helper_poll_disable(dev);
 424
 425         pci_save_state(dev->pdev);
 426
 427         /* If KMS is active, we do the leavevt stuff here */
 428         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 429                 int error = i915_gem_idle(dev);
 430                 if (error) {
 431                         dev_err(&dev->pdev->dev,
 432                                 "GEM idle failed, resume might fail\n");
 433                         return error;
 434                 }
 435                 drm_irq_uninstall(dev);
 436         }
 437
 438         i915_save_state(dev);
 439
 440         intel_opregion_fini(dev);
 441
 442         /* Modeset on resume, not lid events */
 443         dev_priv->modeset_on_lid = 0;
 444
 445         console_lock();
 446         intel_fbdev_set_suspend(dev, 1);
 447         console_unlock();
 448
 449         return 0;
 450 }
 451
 452 int i915_suspend(struct drm_device *dev, pm_message_t state)
 453 {
 454         int error;
 455
 456         if (!dev || !dev->dev_private) {
 457                 DRM_ERROR("dev: %p\n", dev);
 458                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 459                 return -ENODEV;
 460         }
 461
 462         if (state.event == PM_EVENT_PRETHAW)
 463                 return 0;
 464
 465
 466         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 467                 return 0;
 468
 469         error = i915_drm_freeze(dev);
 470         if (error)
 471                 return error;
 472
 473         if (state.event == PM_EVENT_SUSPEND) {
 474                 /* Shut down the device */
 475                 pci_disable_device(dev->pdev);
 476                 pci_set_power_state(dev->pdev, PCI_D3hot);
 477         }
 478
 479         return 0;
 480 }
 481
 482 static int i915_drm_thaw(struct drm_device *dev)
 483 {
 484         struct drm_i915_private *dev_priv = dev->dev_private;
 485         int error = 0;
 486
 487         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 488                 mutex_lock(&dev->struct_mutex);
 489                 i915_gem_restore_gtt_mappings(dev);
 490                 mutex_unlock(&dev->struct_mutex);
 491         }
 492
 493         i915_restore_state(dev);
 494         intel_opregion_setup(dev);
 495
 496         /* KMS EnterVT equivalent */
 497         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 498                 mutex_lock(&dev->struct_mutex);
 499                 dev_priv->mm.suspended = 0;
 500
 501                 error = i915_gem_init_ringbuffer(dev);
 502                 mutex_unlock(&dev->struct_mutex);
 503
 504                 if (HAS_PCH_SPLIT(dev))
 505                         ironlake_init_pch_refclk(dev);
 506
 507                 drm_mode_config_reset(dev);
 508                 drm_irq_install(dev);
 509
 510                 /* Resume the modeset for every activated CRTC */
 511                 mutex_lock(&dev->mode_config.mutex);
 512                 drm_helper_resume_force_mode(dev);
 513                 mutex_unlock(&dev->mode_config.mutex);
 514
 515                 if (IS_IRONLAKE_M(dev))
 516                         ironlake_enable_rc6(dev);
 517         }
 518
 519         intel_opregion_init(dev);
 520
 521         dev_priv->modeset_on_lid = 0;
 522
 523         console_lock();
 524         intel_fbdev_set_suspend(dev, 0);
 525         console_unlock();
 526         return error;
 527 }
 528
 529 int i915_resume(struct drm_device *dev)
 530 {
 531         int ret;
 532
 533         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 534                 return 0;
 535
 536         if (pci_enable_device(dev->pdev))
 537                 return -EIO;
 538
 539         pci_set_master(dev->pdev);
 540
 541         ret = i915_drm_thaw(dev);
 542         if (ret)
 543                 return ret;
 544
 545         drm_kms_helper_poll_enable(dev);
 546         return 0;
 547 }
 548
 549 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 550 {
 551         struct drm_i915_private *dev_priv = dev->dev_private;
 552
 553         if (IS_I85X(dev))
 554                 return -ENODEV;
 555
 556         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 557         POSTING_READ(D_STATE);
 558
 559         if (IS_I830(dev) || IS_845G(dev)) {
 560                 I915_WRITE(DEBUG_RESET_I830,
 561                            DEBUG_RESET_DISPLAY |
 562                            DEBUG_RESET_RENDER |
 563                            DEBUG_RESET_FULL);
 564                 POSTING_READ(DEBUG_RESET_I830);
 565                 msleep(1);
 566
 567                 I915_WRITE(DEBUG_RESET_I830, 0);
 568                 POSTING_READ(DEBUG_RESET_I830);
 569         }
 570
 571         msleep(1);
 572
 573         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 574         POSTING_READ(D_STATE);
 575
 576         return 0;
 577 }
 578
 579 static int i965_reset_complete(struct drm_device *dev)
 580 {
 581         u8 gdrst;
 582         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 583         return gdrst & 0x1;
 584 }
 585
 586 static int i965_do_reset(struct drm_device *dev, u8 flags)
 587 {
 588         u8 gdrst;
 589
 590         /*
 591          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 592          * well as the reset bit (GR/bit 0).  Setting the GR bit
 593          * triggers the reset; when done, the hardware will clear it.
 594          */
 595         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 596         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 597
 598         return wait_for(i965_reset_complete(dev), 500);
 599 }
 600
 601 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 602 {
 603         struct drm_i915_private *dev_priv = dev->dev_private;
 604         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 605         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 606         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 607 }
 608
 609 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 610 {
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612
 613         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 614         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 615 }
 616
 617 /**
 618  * i965_reset - reset chip after a hang
 619  * @dev: drm device to reset
 620  * @flags: reset domains
 621  *
 622  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 623  * reset or otherwise an error code.
 624  *
 625  * Procedure is fairly simple:
 626  *   - reset the chip using the reset reg
 627  *   - re-init context state
 628  *   - re-init hardware status page
 629  *   - re-init ring buffer
 630  *   - re-init interrupt state
 631  *   - re-init display
 632  */
 633 int i915_reset(struct drm_device *dev, u8 flags)
 634 {
 635         drm_i915_private_t *dev_priv = dev->dev_private;
 636         /*
 637          * We really should only reset the display subsystem if we actually
 638          * need to
 639          */
 640         bool need_display = true;
 641         unsigned long irqflags;
 642         int ret;
 643
 644         if (!i915_try_reset)
 645                 return 0;
 646
 647         if (!mutex_trylock(&dev->struct_mutex))
 648                 return -EBUSY;
 649
 650         i915_gem_reset(dev);
 651
 652         ret = -ENODEV;
 653         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 654                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 655         } else switch (INTEL_INFO(dev)->gen) {
 656         case 7:
 657         case 6:
 658                 ret = gen6_do_reset(dev, flags);
 659                 /* If reset with a user forcewake, try to restore */
 660                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 661                 if (dev_priv->forcewake_count)
 662                         dev_priv->display.force_wake_get(dev_priv);
 663                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 664                 break;
 665         case 5:
 666                 ret = ironlake_do_reset(dev, flags);
 667                 break;
 668         case 4:
 669                 ret = i965_do_reset(dev, flags);
 670                 break;
 671         case 2:
 672                 ret = i8xx_do_reset(dev, flags);
 673                 break;
 674         }
 675         dev_priv->last_gpu_reset = get_seconds();
 676         if (ret) {
 677                 DRM_ERROR("Failed to reset chip.\n");
 678                 mutex_unlock(&dev->struct_mutex);
 679                 return ret;
 680         }
 681
 682         /* Ok, now get things going again... */
 683
 684         /*
 685          * Everything depends on having the GTT running, so we need to start
 686          * there.  Fortunately we don't need to do this unless we reset the
 687          * chip at a PCI level.
 688          *
 689          * Next we need to restore the context, but we don't use those
 690          * yet either...
 691          *
 692          * Ring buffer needs to be re-initialized in the KMS case, or if X
 693          * was running at the time of the reset (i.e. we weren't VT
 694          * switched away).
 695          */
 696         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 697                         !dev_priv->mm.suspended) {
 698                 dev_priv->mm.suspended = 0;
 699
 700                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 701                 if (HAS_BSD(dev))
 702                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 703                 if (HAS_BLT(dev))
 704                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 705
 706                 mutex_unlock(&dev->struct_mutex);
 707                 drm_irq_uninstall(dev);
 708                 drm_mode_config_reset(dev);
 709                 drm_irq_install(dev);
 710                 mutex_lock(&dev->struct_mutex);
 711         }
 712
 713         mutex_unlock(&dev->struct_mutex);
 714
 715         /*
 716          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 717          * need to retrain the display link and cannot just restore the register
 718          * values.
 719          */
 720         if (need_display) {
 721                 mutex_lock(&dev->mode_config.mutex);
 722                 drm_helper_resume_force_mode(dev);
 723                 mutex_unlock(&dev->mode_config.mutex);
 724         }
 725
 726         return 0;
 727 }
 728
 729
 730 static int __devinit
 731 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 732 {
 733         /* Only bind to function 0 of the device. Early generations
 734          * used function 1 as a placeholder for multi-head. This causes
 735          * us confusion instead, especially on the systems where both
 736          * functions have the same PCI-ID!
 737          */
 738         if (PCI_FUNC(pdev->devfn))
 739                 return -ENODEV;
 740
 741         return drm_get_pci_dev(pdev, ent, &driver);
 742 }
 743
 744 static void
 745 i915_pci_remove(struct pci_dev *pdev)
 746 {
 747         struct drm_device *dev = pci_get_drvdata(pdev);
 748
 749         drm_put_dev(dev);
 750 }
 751
 752 static int i915_pm_suspend(struct device *dev)
 753 {
 754         struct pci_dev *pdev = to_pci_dev(dev);
 755         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 756         int error;
 757
 758         if (!drm_dev || !drm_dev->dev_private) {
 759                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 760                 return -ENODEV;
 761         }
 762
 763         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 764                 return 0;
 765
 766         error = i915_drm_freeze(drm_dev);
 767         if (error)
 768                 return error;
 769
 770         pci_disable_device(pdev);
 771         pci_set_power_state(pdev, PCI_D3hot);
 772
 773         return 0;
 774 }
 775
 776 static int i915_pm_resume(struct device *dev)
 777 {
 778         struct pci_dev *pdev = to_pci_dev(dev);
 779         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 780
 781         return i915_resume(drm_dev);
 782 }
 783
 784 static int i915_pm_freeze(struct device *dev)
 785 {
 786         struct pci_dev *pdev = to_pci_dev(dev);
 787         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 788
 789         if (!drm_dev || !drm_dev->dev_private) {
 790                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 791                 return -ENODEV;
 792         }
 793
 794         return i915_drm_freeze(drm_dev);
 795 }
 796
 797 static int i915_pm_thaw(struct device *dev)
 798 {
 799         struct pci_dev *pdev = to_pci_dev(dev);
 800         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 801
 802         return i915_drm_thaw(drm_dev);
 803 }
 804
 805 static int i915_pm_poweroff(struct device *dev)
 806 {
 807         struct pci_dev *pdev = to_pci_dev(dev);
 808         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 809
 810         return i915_drm_freeze(drm_dev);
 811 }
 812
 813 static const struct dev_pm_ops i915_pm_ops = {
 814         .suspend = i915_pm_suspend,
 815         .resume = i915_pm_resume,
 816         .freeze = i915_pm_freeze,
 817         .thaw = i915_pm_thaw,
 818         .poweroff = i915_pm_poweroff,
 819         .restore = i915_pm_resume,
 820 };
 821
 822 static struct vm_operations_struct i915_gem_vm_ops = {
 823         .fault = i915_gem_fault,
 824         .open = drm_gem_vm_open,
 825         .close = drm_gem_vm_close,
 826 };
 827
 828 static struct drm_driver driver = {
 829         /* Don't use MTRRs here; the Xserver or userspace app should
 830          * deal with them for Intel hardware.
 831          */
 832         .driver_features =
 833             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 834             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 835         .load = i915_driver_load,
 836         .unload = i915_driver_unload,
 837         .open = i915_driver_open,
 838         .lastclose = i915_driver_lastclose,
 839         .preclose = i915_driver_preclose,
 840         .postclose = i915_driver_postclose,
 841
 842         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 843         .suspend = i915_suspend,
 844         .resume = i915_resume,
 845
 846         .device_is_agp = i915_driver_device_is_agp,
 847         .reclaim_buffers = drm_core_reclaim_buffers,
 848         .master_create = i915_master_create,
 849         .master_destroy = i915_master_destroy,
 850 #if defined(CONFIG_DEBUG_FS)
 851         .debugfs_init = i915_debugfs_init,
 852         .debugfs_cleanup = i915_debugfs_cleanup,
 853 #endif
 854         .gem_init_object = i915_gem_init_object,
 855         .gem_free_object = i915_gem_free_object,
 856         .gem_vm_ops = &i915_gem_vm_ops,
 857         .dumb_create = i915_gem_dumb_create,
 858         .dumb_map_offset = i915_gem_mmap_gtt,
 859         .dumb_destroy = i915_gem_dumb_destroy,
 860         .ioctls = i915_ioctls,
 861         .fops = {
 862                  .owner = THIS_MODULE,
 863                  .open = drm_open,
 864                  .release = drm_release,
 865                  .unlocked_ioctl = drm_ioctl,
 866                  .mmap = drm_gem_mmap,
 867                  .poll = drm_poll,
 868                  .fasync = drm_fasync,
 869                  .read = drm_read,
 870 #ifdef CONFIG_COMPAT
 871                  .compat_ioctl = i915_compat_ioctl,
 872 #endif
 873                  .llseek = noop_llseek,
 874         },
 875
 876         .name = DRIVER_NAME,
 877         .desc = DRIVER_DESC,
 878         .date = DRIVER_DATE,
 879         .major = DRIVER_MAJOR,
 880         .minor = DRIVER_MINOR,
 881         .patchlevel = DRIVER_PATCHLEVEL,
 882 };
 883
 884 static struct pci_driver i915_pci_driver = {
 885         .name = DRIVER_NAME,
 886         .id_table = pciidlist,
 887         .probe = i915_pci_probe,
 888         .remove = i915_pci_remove,
 889         .driver.pm = &i915_pm_ops,
 890 };
 891
 892 static int __init i915_init(void)
 893 {
 894         if (!intel_agp_enabled) {
 895                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 896                 return -ENODEV;
 897         }
 898
 899         driver.num_ioctls = i915_max_ioctl;
 900
 901         /*
 902          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 903          * explicitly disabled with the module pararmeter.
 904          *
 905          * Otherwise, just follow the parameter (defaulting to off).
 906          *
 907          * Allow optional vga_text_mode_force boot option to override
 908          * the default behavior.
 909          */
 910 #if defined(CONFIG_DRM_I915_KMS)
 911         if (i915_modeset != 0)
 912                 driver.driver_features |= DRIVER_MODESET;
 913 #endif
 914         if (i915_modeset == 1)
 915                 driver.driver_features |= DRIVER_MODESET;
 916
 917 #ifdef CONFIG_VGA_CONSOLE
 918         if (vgacon_text_force() && i915_modeset == -1)
 919                 driver.driver_features &= ~DRIVER_MODESET;
 920 #endif
 921
 922         if (!(driver.driver_features & DRIVER_MODESET))
 923                 driver.get_vblank_timestamp = NULL;
 924
 925         return drm_pci_init(&driver, &i915_pci_driver);
 926 }
 927
 928 static void __exit i915_exit(void)
 929 {
 930         drm_pci_exit(&driver, &i915_pci_driver);
 931 }
 932
 933 module_init(i915_init);
 934 module_exit(i915_exit);
 935
 936 MODULE_AUTHOR(DRIVER_AUTHOR);
 937 MODULE_DESCRIPTION(DRIVER_DESC);
 938 MODULE_LICENSE("GPL and additional rights");
 939
 940 /* We give fast paths for the really cool registers */
 941 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 942         (((dev_priv)->info->gen >= 6) && \
 943          ((reg) < 0x40000) &&            \
 944          ((reg) != FORCEWAKE) &&         \
 945          ((reg) != ECOBUS))
 946
 947 #define __i915_read(x, y) \
 948 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 949         u##x val = 0; \
 950         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 951                 gen6_gt_force_wake_get(dev_priv); \
 952                 val = read##y(dev_priv->regs + reg); \
 953                 gen6_gt_force_wake_put(dev_priv); \
 954         } else { \
 955                 val = read##y(dev_priv->regs + reg); \
 956         } \
 957         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 958         return val; \
 959 }
 960
 961 __i915_read(8, b)
 962 __i915_read(16, w)
 963 __i915_read(32, l)
 964 __i915_read(64, q)
 965 #undef __i915_read
 966
 967 #define __i915_write(x, y) \
 968 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 969         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 970         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 971                 __gen6_gt_wait_for_fifo(dev_priv); \
 972         } \
 973         write##y(val, dev_priv->regs + reg); \
 974 }
 975 __i915_write(8, b)
 976 __i915_write(16, w)
 977 __i915_write(32, l)
 978 __i915_write(64, q)
 979 #undef __i915_write