1 #include <linux/init.h>
3 #include <linux/topology.h>
5 #include <linux/range.h>
7 #include <asm/pci_x86.h>
10 #include <asm/pci-direct.h>
16 * This discovers the pcibus <-> node mapping on AMD K8.
17 * also get peer root bus resource for io,mmio
22 struct pci_hostbridge_probe {
29 static struct pci_hostbridge_probe pci_probes[] __initdata = {
30 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
31 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
32 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
33 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
36 static u64 __initdata fam10h_mmconf_start;
37 static u64 __initdata fam10h_mmconf_end;
38 static void __init get_pci_mmcfg_amd_fam10h_range(void)
42 unsigned segn_busn_bits;
44 /* assume all cpus from fam10h have mmconf */
45 if (boot_cpu_data.x86 < 0x10)
48 address = MSR_FAM10H_MMIO_CONF_BASE;
51 /* mmconfig is not enable */
52 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
55 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
57 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
58 FAM10H_MMIO_CONF_BUSRANGE_MASK;
60 fam10h_mmconf_start = base;
61 fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
67 * early_fill_mp_bus_to_node()
68 * called before pcibios_scan_root and pci_scan_bus
69 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
70 * Registers found in the K8 northbridge
72 static int __init early_fill_mp_bus_info(void)
82 struct pci_root_info *info;
87 struct range range[RANGE_NUM];
92 if (!early_pci_allowed())
96 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
101 bus = pci_probes[i].bus;
102 slot = pci_probes[i].slot;
103 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
105 vendor = id & 0xffff;
106 device = (id>>16) & 0xffff;
107 if (pci_probes[i].vendor == vendor &&
108 pci_probes[i].device == device) {
118 for (i = 0; i < 4; i++) {
121 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
123 /* Check if that register is enabled for bus range */
127 min_bus = (reg >> 16) & 0xff;
128 max_bus = (reg >> 24) & 0xff;
129 node = (reg >> 4) & 0x07;
131 for (j = min_bus; j <= max_bus; j++)
132 set_mp_bus_to_node(j, node);
134 link = (reg >> 8) & 0x03;
136 info = &pci_root_info[pci_root_num];
137 info->bus_min = min_bus;
138 info->bus_max = max_bus;
141 sprintf(info->name, "PCI Bus #%02x", min_bus);
145 /* get the default node and link for left over res */
146 reg = read_pci_config(bus, slot, 0, 0x60);
147 def_node = (reg >> 8) & 0x07;
148 reg = read_pci_config(bus, slot, 0, 0x64);
149 def_link = (reg >> 8) & 0x03;
151 memset(range, 0, sizeof(range));
152 range[0].end = 0xffff;
153 /* io port resource */
154 for (i = 0; i < 4; i++) {
155 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
159 start = reg & 0xfff000;
160 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
162 link = (reg >> 4) & 0x03;
163 end = (reg & 0xfff000) | 0xfff;
165 /* find the position */
166 for (j = 0; j < pci_root_num; j++) {
167 info = &pci_root_info[j];
168 if (info->node == node && info->link == link)
171 if (j == pci_root_num)
172 continue; /* not found */
174 info = &pci_root_info[j];
175 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
176 node, link, (u64)start, (u64)end);
178 /* kernel only handle 16 bit only */
181 update_res(info, start, end, IORESOURCE_IO, 1);
182 subtract_range(range, RANGE_NUM, start, end);
184 /* add left over io port range to def node/link, [0, 0xffff] */
185 /* find the position */
186 for (j = 0; j < pci_root_num; j++) {
187 info = &pci_root_info[j];
188 if (info->node == def_node && info->link == def_link)
191 if (j < pci_root_num) {
192 info = &pci_root_info[j];
193 for (i = 0; i < RANGE_NUM; i++) {
197 update_res(info, range[i].start, range[i].end,
202 memset(range, 0, sizeof(range));
203 /* 0xfd00000000-0xffffffffff for HT */
204 range[0].end = (0xfdULL<<32) - 1;
206 /* need to take out [0, TOM) for RAM*/
207 address = MSR_K8_TOP_MEM1;
208 rdmsrl(address, val);
209 end = (val & 0xffffff800000ULL);
210 printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
211 if (end < (1ULL<<32))
212 subtract_range(range, RANGE_NUM, 0, end - 1);
215 get_pci_mmcfg_amd_fam10h_range();
216 /* need to take out mmconf range */
217 if (fam10h_mmconf_end) {
218 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
219 subtract_range(range, RANGE_NUM, fam10h_mmconf_start, fam10h_mmconf_end);
223 for (i = 0; i < 8; i++) {
224 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
228 start = reg & 0xffffff00; /* 39:16 on 31:8*/
230 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
232 link = (reg >> 4) & 0x03;
233 end = (reg & 0xffffff00);
237 /* find the position */
238 for (j = 0; j < pci_root_num; j++) {
239 info = &pci_root_info[j];
240 if (info->node == node && info->link == link)
243 if (j == pci_root_num)
244 continue; /* not found */
246 info = &pci_root_info[j];
248 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
249 node, link, (u64)start, (u64)end);
251 * some sick allocation would have range overlap with fam10h
252 * mmconf range, so need to update start and end.
254 if (fam10h_mmconf_end) {
257 if (start >= fam10h_mmconf_start &&
258 start <= fam10h_mmconf_end) {
259 start = fam10h_mmconf_end + 1;
263 if (end >= fam10h_mmconf_start &&
264 end <= fam10h_mmconf_end) {
265 end = fam10h_mmconf_start - 1;
269 if (start < fam10h_mmconf_start &&
270 end > fam10h_mmconf_end) {
272 endx = fam10h_mmconf_start - 1;
273 update_res(info, start, endx, IORESOURCE_MEM, 0);
274 subtract_range(range, RANGE_NUM, start, endx);
275 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
276 start = fam10h_mmconf_end + 1;
281 printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
283 printk(KERN_CONT "%s\n", endx?"":" ==> none");
289 update_res(info, start, end, IORESOURCE_MEM, 1);
290 subtract_range(range, RANGE_NUM, start, end);
291 printk(KERN_CONT "\n");
294 /* need to take out [4G, TOM2) for RAM*/
296 address = MSR_K8_SYSCFG;
297 rdmsrl(address, val);
298 /* TOP_MEM2 is enabled? */
301 address = MSR_K8_TOP_MEM2;
302 rdmsrl(address, val);
303 end = (val & 0xffffff800000ULL);
304 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
305 subtract_range(range, RANGE_NUM, 1ULL<<32, end - 1);
309 * add left over mmio range to def node/link ?
310 * that is tricky, just record range in from start_min to 4G
312 for (j = 0; j < pci_root_num; j++) {
313 info = &pci_root_info[j];
314 if (info->node == def_node && info->link == def_link)
317 if (j < pci_root_num) {
318 info = &pci_root_info[j];
320 for (i = 0; i < RANGE_NUM; i++) {
324 update_res(info, range[i].start, range[i].end,
329 for (i = 0; i < pci_root_num; i++) {
333 info = &pci_root_info[i];
334 res_num = info->res_num;
335 busnum = info->bus_min;
336 printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
337 info->bus_min, info->bus_max, info->node, info->link);
338 for (j = 0; j < res_num; j++) {
340 printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
342 (res->flags & IORESOURCE_IO)?"io port":"mmio",
343 res->start, res->end);
350 #else /* !CONFIG_X86_64 */
352 static int __init early_fill_mp_bus_info(void) { return 0; }
354 #endif /* !CONFIG_X86_64 */
356 /* common 32/64 bit code */
358 #define ENABLE_CF8_EXT_CFG (1ULL << 46)
360 static void enable_pci_io_ecs(void *unused)
363 rdmsrl(MSR_AMD64_NB_CFG, reg);
364 if (!(reg & ENABLE_CF8_EXT_CFG)) {
365 reg |= ENABLE_CF8_EXT_CFG;
366 wrmsrl(MSR_AMD64_NB_CFG, reg);
370 static int __cpuinit amd_cpu_notify(struct notifier_block *self,
371 unsigned long action, void *hcpu)
373 int cpu = (long)hcpu;
376 case CPU_ONLINE_FROZEN:
377 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
385 static struct notifier_block __cpuinitdata amd_cpu_notifier = {
386 .notifier_call = amd_cpu_notify,
389 static int __init pci_io_ecs_init(void)
393 /* assume all cpus from fam10h have IO ECS */
394 if (boot_cpu_data.x86 < 0x10)
397 register_cpu_notifier(&amd_cpu_notifier);
398 for_each_online_cpu(cpu)
399 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
401 pci_probe |= PCI_HAS_IO_ECS;
406 static int __init amd_postcore_init(void)
408 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
411 early_fill_mp_bus_info();
417 postcore_initcall(amd_postcore_init);