2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/dmaengine.h>
26 #include <linux/init.h>
27 #include <linux/dmapool.h>
28 #include <linux/cache.h>
29 #include <linux/pci_ids.h>
32 #define IOAT_DMA_VERSION "3.64"
34 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
35 #define IOAT_DMA_DCA_ANY_CPU ~0
36 #define IOAT_WATCHDOG_PERIOD (2 * HZ)
38 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
39 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
40 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
41 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
45 #define RESET_DELAY msecs_to_jiffies(100)
46 #define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000))
49 * workaround for IOAT ver.3.0 null descriptor issue
50 * (channel returns error when size is 0)
52 #define NULL_DESC_BUFFER_SIZE 1
55 * struct ioatdma_device - internal representation of a IOAT device
56 * @pdev: PCI-Express device
57 * @reg_base: MMIO register space base address
58 * @dma_pool: for allocating DMA descriptors
59 * @common: embedded struct dma_device
60 * @version: version of ioatdma device
61 * @msix_entries: irq handlers
62 * @idx: per channel data
63 * @dca: direct cache access context
64 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
65 * @enumerate_channels: hw version specific channel enumeration
68 struct ioatdma_device {
70 void __iomem *reg_base;
71 struct pci_pool *dma_pool;
72 struct pci_pool *completion_pool;
73 struct dma_device common;
75 struct delayed_work work;
76 struct msix_entry msix_entries[4];
77 struct ioat_chan_common *idx[4];
78 struct dca_provider *dca;
79 void (*intr_quirk)(struct ioatdma_device *device);
80 int (*enumerate_channels)(struct ioatdma_device *device);
83 struct ioat_chan_common {
84 void __iomem *reg_base;
86 unsigned long last_completion;
87 unsigned long last_completion_time;
89 spinlock_t cleanup_lock;
90 dma_cookie_t completed_cookie;
91 unsigned long watchdog_completion;
92 int watchdog_tcp_cookie;
93 u32 watchdog_last_tcp_cookie;
94 struct delayed_work work;
96 struct ioatdma_device *device;
97 struct dma_chan common;
99 dma_addr_t completion_addr;
101 u64 full; /* HW completion writeback */
107 unsigned long last_compl_desc_addr_hw;
108 struct tasklet_struct cleanup_task;
113 * struct ioat_dma_chan - internal representation of a DMA channel
115 struct ioat_dma_chan {
116 struct ioat_chan_common base;
118 size_t xfercap; /* XFERCAP register value expanded out */
120 spinlock_t desc_lock;
121 struct list_head free_desc;
122 struct list_head used_desc;
128 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
130 return container_of(c, struct ioat_chan_common, common);
133 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
135 struct ioat_chan_common *chan = to_chan_common(c);
137 return container_of(chan, struct ioat_dma_chan, base);
141 * ioat_is_complete - poll the status of an ioat transaction
143 * @cookie: transaction identifier
144 * @done: if set, updated with last completed transaction
145 * @used: if set, updated with last used transaction
147 static inline enum dma_status
148 ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
149 dma_cookie_t *done, dma_cookie_t *used)
151 struct ioat_chan_common *chan = to_chan_common(c);
152 dma_cookie_t last_used;
153 dma_cookie_t last_complete;
155 last_used = c->cookie;
156 last_complete = chan->completed_cookie;
157 chan->watchdog_tcp_cookie = cookie;
160 *done = last_complete;
164 return dma_async_is_complete(cookie, last_complete, last_used);
167 /* wrapper around hardware descriptor format + additional software fields */
170 * struct ioat_desc_sw - wrapper around hardware descriptor
171 * @hw: hardware DMA descriptor
172 * @node: this descriptor will either be on the free list,
173 * or attached to a transaction list (async_tx.tx_list)
174 * @tx_cnt: number of descriptors required to complete the transaction
175 * @txd: the generic software descriptor for all engines
177 struct ioat_desc_sw {
178 struct ioat_dma_descriptor *hw;
179 struct list_head node;
182 struct dma_async_tx_descriptor txd;
185 static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
187 #ifdef CONFIG_NET_DMA
188 sysctl_tcp_dma_copybreak = copybreak;
192 static inline struct ioat_chan_common *
193 ioat_chan_by_index(struct ioatdma_device *device, int index)
195 return device->idx[index];
198 int ioat_probe(struct ioatdma_device *device);
199 int ioat_register(struct ioatdma_device *device);
200 int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
201 void ioat_dma_remove(struct ioatdma_device *device);
202 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
203 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
204 void ioat_init_channel(struct ioatdma_device *device,
205 struct ioat_chan_common *chan, int idx,
206 work_func_t work_fn, void (*tasklet)(unsigned long),
207 unsigned long tasklet_data);
208 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
209 size_t len, struct ioat_dma_descriptor *hw);
210 #endif /* IOATDMA_H */