drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /*
  38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  39  * over cache flushing.
  40  */
  41 struct pipe_control {
  42         struct drm_i915_gem_object *obj;
  43         volatile u32 *cpu_page;
  44         u32 gtt_offset;
  45 };
  46
  47 static inline int ring_space(struct intel_ring_buffer *ring)
  48 {
  49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  50         if (space < 0)
  51                 space += ring->size;
  52         return space;
  53 }
  54
  55 static u32 i915_gem_get_seqno(struct drm_device *dev)
  56 {
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 seqno;
  59
  60         seqno = dev_priv->next_seqno;
  61
  62         /* reserve 0 for non-seqno */
  63         if (++dev_priv->next_seqno == 0)
  64                 dev_priv->next_seqno = 1;
  65
  66         return seqno;
  67 }
  68
  69 static int
  70 render_ring_flush(struct intel_ring_buffer *ring,
  71                   u32   invalidate_domains,
  72                   u32   flush_domains)
  73 {
  74         struct drm_device *dev = ring->dev;
  75         u32 cmd;
  76         int ret;
  77
  78         /*
  79          * read/write caches:
  80          *
  81          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  82          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  83          * also flushed at 2d versus 3d pipeline switches.
  84          *
  85          * read-only caches:
  86          *
  87          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  88          * MI_READ_FLUSH is set, and is always flushed on 965.
  89          *
  90          * I915_GEM_DOMAIN_COMMAND may not exist?
  91          *
  92          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  93          * invalidated when MI_EXE_FLUSH is set.
  94          *
  95          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  96          * invalidated with every MI_FLUSH.
  97          *
  98          * TLBs:
  99          *
 100          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 101          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 102          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 103          * are flushed at any MI_FLUSH.
 104          */
 105
 106         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 107         if ((invalidate_domains|flush_domains) &
 108             I915_GEM_DOMAIN_RENDER)
 109                 cmd &= ~MI_NO_WRITE_FLUSH;
 110         if (INTEL_INFO(dev)->gen < 4) {
 111                 /*
 112                  * On the 965, the sampler cache always gets flushed
 113                  * and this bit is reserved.
 114                  */
 115                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 116                         cmd |= MI_READ_FLUSH;
 117         }
 118         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 119                 cmd |= MI_EXE_FLUSH;
 120
 121         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 122             (IS_G4X(dev) || IS_GEN5(dev)))
 123                 cmd |= MI_INVALIDATE_ISP;
 124
 125         ret = intel_ring_begin(ring, 2);
 126         if (ret)
 127                 return ret;
 128
 129         intel_ring_emit(ring, cmd);
 130         intel_ring_emit(ring, MI_NOOP);
 131         intel_ring_advance(ring);
 132
 133         return 0;
 134 }
 135
 136 /**
 137  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 138  * implementing two workarounds on gen6.  From section 1.4.7.1
 139  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 140  *
 141  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 142  * produced by non-pipelined state commands), software needs to first
 143  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 144  * 0.
 145  *
 146  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 147  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 148  *
 149  * And the workaround for these two requires this workaround first:
 150  *
 151  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 152  * BEFORE the pipe-control with a post-sync op and no write-cache
 153  * flushes.
 154  *
 155  * And this last workaround is tricky because of the requirements on
 156  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 157  * volume 2 part 1:
 158  *
 159  *     "1 of the following must also be set:
 160  *      - Render Target Cache Flush Enable ([12] of DW1)
 161  *      - Depth Cache Flush Enable ([0] of DW1)
 162  *      - Stall at Pixel Scoreboard ([1] of DW1)
 163  *      - Depth Stall ([13] of DW1)
 164  *      - Post-Sync Operation ([13] of DW1)
 165  *      - Notify Enable ([8] of DW1)"
 166  *
 167  * The cache flushes require the workaround flush that triggered this
 168  * one, so we can't use it.  Depth stall would trigger the same.
 169  * Post-sync nonzero is what triggered this second workaround, so we
 170  * can't use that one either.  Notify enable is IRQs, which aren't
 171  * really our business.  That leaves only stall at scoreboard.
 172  */
 173 static int
 174 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 175 {
 176         struct pipe_control *pc = ring->private;
 177         u32 scratch_addr = pc->gtt_offset + 128;
 178         int ret;
 179
 180
 181         ret = intel_ring_begin(ring, 6);
 182         if (ret)
 183                 return ret;
 184
 185         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 186         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 187                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 188         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 189         intel_ring_emit(ring, 0); /* low dword */
 190         intel_ring_emit(ring, 0); /* high dword */
 191         intel_ring_emit(ring, MI_NOOP);
 192         intel_ring_advance(ring);
 193
 194         ret = intel_ring_begin(ring, 6);
 195         if (ret)
 196                 return ret;
 197
 198         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 199         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 200         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 201         intel_ring_emit(ring, 0);
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, MI_NOOP);
 204         intel_ring_advance(ring);
 205
 206         return 0;
 207 }
 208
 209 static int
 210 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 211                          u32 invalidate_domains, u32 flush_domains)
 212 {
 213         u32 flags = 0;
 214         struct pipe_control *pc = ring->private;
 215         u32 scratch_addr = pc->gtt_offset + 128;
 216         int ret;
 217
 218         /* Force SNB workarounds for PIPE_CONTROL flushes */
 219         intel_emit_post_sync_nonzero_flush(ring);
 220
 221         /* Just flush everything.  Experiments have shown that reducing the
 222          * number of bits based on the write domains has little performance
 223          * impact.
 224          */
 225         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 226         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 227         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 228         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 229         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 230         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 231         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 232
 233         ret = intel_ring_begin(ring, 6);
 234         if (ret)
 235                 return ret;
 236
 237         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 238         intel_ring_emit(ring, flags);
 239         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 240         intel_ring_emit(ring, 0); /* lower dword */
 241         intel_ring_emit(ring, 0); /* uppwer dword */
 242         intel_ring_emit(ring, MI_NOOP);
 243         intel_ring_advance(ring);
 244
 245         return 0;
 246 }
 247
 248 static void ring_write_tail(struct intel_ring_buffer *ring,
 249                             u32 value)
 250 {
 251         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 252         I915_WRITE_TAIL(ring, value);
 253 }
 254
 255 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 256 {
 257         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 258         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 259                         RING_ACTHD(ring->mmio_base) : ACTHD;
 260
 261         return I915_READ(acthd_reg);
 262 }
 263
 264 static int init_ring_common(struct intel_ring_buffer *ring)
 265 {
 266         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 267         struct drm_i915_gem_object *obj = ring->obj;
 268         u32 head;
 269
 270         /* Stop the ring if it's running. */
 271         I915_WRITE_CTL(ring, 0);
 272         I915_WRITE_HEAD(ring, 0);
 273         ring->write_tail(ring, 0);
 274
 275         /* Initialize the ring. */
 276         I915_WRITE_START(ring, obj->gtt_offset);
 277         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 278
 279         /* G45 ring initialization fails to reset head to zero */
 280         if (head != 0) {
 281                 DRM_DEBUG_KMS("%s head not reset to zero "
 282                               "ctl %08x head %08x tail %08x start %08x\n",
 283                               ring->name,
 284                               I915_READ_CTL(ring),
 285                               I915_READ_HEAD(ring),
 286                               I915_READ_TAIL(ring),
 287                               I915_READ_START(ring));
 288
 289                 I915_WRITE_HEAD(ring, 0);
 290
 291                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 292                         DRM_ERROR("failed to set %s head to zero "
 293                                   "ctl %08x head %08x tail %08x start %08x\n",
 294                                   ring->name,
 295                                   I915_READ_CTL(ring),
 296                                   I915_READ_HEAD(ring),
 297                                   I915_READ_TAIL(ring),
 298                                   I915_READ_START(ring));
 299                 }
 300         }
 301
 302         I915_WRITE_CTL(ring,
 303                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 304                         | RING_REPORT_64K | RING_VALID);
 305
 306         /* If the head is still not zero, the ring is dead */
 307         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 308             I915_READ_START(ring) != obj->gtt_offset ||
 309             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 310                 DRM_ERROR("%s initialization failed "
 311                                 "ctl %08x head %08x tail %08x start %08x\n",
 312                                 ring->name,
 313                                 I915_READ_CTL(ring),
 314                                 I915_READ_HEAD(ring),
 315                                 I915_READ_TAIL(ring),
 316                                 I915_READ_START(ring));
 317                 return -EIO;
 318         }
 319
 320         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 321                 i915_kernel_lost_context(ring->dev);
 322         else {
 323                 ring->head = I915_READ_HEAD(ring);
 324                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 325                 ring->space = ring_space(ring);
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int
 332 init_pipe_control(struct intel_ring_buffer *ring)
 333 {
 334         struct pipe_control *pc;
 335         struct drm_i915_gem_object *obj;
 336         int ret;
 337
 338         if (ring->private)
 339                 return 0;
 340
 341         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 342         if (!pc)
 343                 return -ENOMEM;
 344
 345         obj = i915_gem_alloc_object(ring->dev, 4096);
 346         if (obj == NULL) {
 347                 DRM_ERROR("Failed to allocate seqno page\n");
 348                 ret = -ENOMEM;
 349                 goto err;
 350         }
 351
 352         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 353
 354         ret = i915_gem_object_pin(obj, 4096, true);
 355         if (ret)
 356                 goto err_unref;
 357
 358         pc->gtt_offset = obj->gtt_offset;
 359         pc->cpu_page =  kmap(obj->pages[0]);
 360         if (pc->cpu_page == NULL)
 361                 goto err_unpin;
 362
 363         pc->obj = obj;
 364         ring->private = pc;
 365         return 0;
 366
 367 err_unpin:
 368         i915_gem_object_unpin(obj);
 369 err_unref:
 370         drm_gem_object_unreference(&obj->base);
 371 err:
 372         kfree(pc);
 373         return ret;
 374 }
 375
 376 static void
 377 cleanup_pipe_control(struct intel_ring_buffer *ring)
 378 {
 379         struct pipe_control *pc = ring->private;
 380         struct drm_i915_gem_object *obj;
 381
 382         if (!ring->private)
 383                 return;
 384
 385         obj = pc->obj;
 386         kunmap(obj->pages[0]);
 387         i915_gem_object_unpin(obj);
 388         drm_gem_object_unreference(&obj->base);
 389
 390         kfree(pc);
 391         ring->private = NULL;
 392 }
 393
 394 static int init_render_ring(struct intel_ring_buffer *ring)
 395 {
 396         struct drm_device *dev = ring->dev;
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         int ret = init_ring_common(ring);
 399
 400         if (INTEL_INFO(dev)->gen > 3) {
 401                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 402                 if (IS_GEN6(dev) || IS_GEN7(dev))
 403                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 404                 I915_WRITE(MI_MODE, mode);
 405                 if (IS_GEN7(dev))
 406                         I915_WRITE(GFX_MODE_GEN7,
 407                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 408                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
 409         }
 410
 411         if (INTEL_INFO(dev)->gen >= 5) {
 412                 ret = init_pipe_control(ring);
 413                 if (ret)
 414                         return ret;
 415         }
 416
 417         return ret;
 418 }
 419
 420 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 421 {
 422         if (!ring->private)
 423                 return;
 424
 425         cleanup_pipe_control(ring);
 426 }
 427
 428 static void
 429 update_mboxes(struct intel_ring_buffer *ring,
 430             u32 seqno,
 431             u32 mmio_offset)
 432 {
 433         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 434                               MI_SEMAPHORE_GLOBAL_GTT |
 435                               MI_SEMAPHORE_REGISTER |
 436                               MI_SEMAPHORE_UPDATE);
 437         intel_ring_emit(ring, seqno);
 438         intel_ring_emit(ring, mmio_offset);
 439 }
 440
 441 /**
 442  * gen6_add_request - Update the semaphore mailbox registers
 443  *
 444  * @ring - ring that is adding a request
 445  * @seqno - return seqno stuck into the ring
 446  *
 447  * Update the mailbox registers in the *other* rings with the current seqno.
 448  * This acts like a signal in the canonical semaphore.
 449  */
 450 static int
 451 gen6_add_request(struct intel_ring_buffer *ring,
 452                  u32 *seqno)
 453 {
 454         u32 mbox1_reg;
 455         u32 mbox2_reg;
 456         int ret;
 457
 458         ret = intel_ring_begin(ring, 10);
 459         if (ret)
 460                 return ret;
 461
 462         mbox1_reg = ring->signal_mbox[0];
 463         mbox2_reg = ring->signal_mbox[1];
 464
 465         *seqno = i915_gem_get_seqno(ring->dev);
 466
 467         update_mboxes(ring, *seqno, mbox1_reg);
 468         update_mboxes(ring, *seqno, mbox2_reg);
 469         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 470         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 471         intel_ring_emit(ring, *seqno);
 472         intel_ring_emit(ring, MI_USER_INTERRUPT);
 473         intel_ring_advance(ring);
 474
 475         return 0;
 476 }
 477
 478 /**
 479  * intel_ring_sync - sync the waiter to the signaller on seqno
 480  *
 481  * @waiter - ring that is waiting
 482  * @signaller - ring which has, or will signal
 483  * @seqno - seqno which the waiter will block on
 484  */
 485 static int
 486 intel_ring_sync(struct intel_ring_buffer *waiter,
 487                 struct intel_ring_buffer *signaller,
 488                 int ring,
 489                 u32 seqno)
 490 {
 491         int ret;
 492         u32 dw1 = MI_SEMAPHORE_MBOX |
 493                   MI_SEMAPHORE_COMPARE |
 494                   MI_SEMAPHORE_REGISTER;
 495
 496         ret = intel_ring_begin(waiter, 4);
 497         if (ret)
 498                 return ret;
 499
 500         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
 501         intel_ring_emit(waiter, seqno);
 502         intel_ring_emit(waiter, 0);
 503         intel_ring_emit(waiter, MI_NOOP);
 504         intel_ring_advance(waiter);
 505
 506         return 0;
 507 }
 508
 509 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
 510 int
 511 render_ring_sync_to(struct intel_ring_buffer *waiter,
 512                     struct intel_ring_buffer *signaller,
 513                     u32 seqno)
 514 {
 515         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
 516         return intel_ring_sync(waiter,
 517                                signaller,
 518                                RCS,
 519                                seqno);
 520 }
 521
 522 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
 523 int
 524 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
 525                       struct intel_ring_buffer *signaller,
 526                       u32 seqno)
 527 {
 528         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
 529         return intel_ring_sync(waiter,
 530                                signaller,
 531                                VCS,
 532                                seqno);
 533 }
 534
 535 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
 536 int
 537 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
 538                       struct intel_ring_buffer *signaller,
 539                       u32 seqno)
 540 {
 541         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
 542         return intel_ring_sync(waiter,
 543                                signaller,
 544                                BCS,
 545                                seqno);
 546 }
 547
 548
 549
 550 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 551 do {                                                                    \
 552         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 553                  PIPE_CONTROL_DEPTH_STALL);                             \
 554         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 555         intel_ring_emit(ring__, 0);                                                     \
 556         intel_ring_emit(ring__, 0);                                                     \
 557 } while (0)
 558
 559 static int
 560 pc_render_add_request(struct intel_ring_buffer *ring,
 561                       u32 *result)
 562 {
 563         struct drm_device *dev = ring->dev;
 564         u32 seqno = i915_gem_get_seqno(dev);
 565         struct pipe_control *pc = ring->private;
 566         u32 scratch_addr = pc->gtt_offset + 128;
 567         int ret;
 568
 569         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 570          * incoherent with writes to memory, i.e. completely fubar,
 571          * so we need to use PIPE_NOTIFY instead.
 572          *
 573          * However, we also need to workaround the qword write
 574          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 575          * memory before requesting an interrupt.
 576          */
 577         ret = intel_ring_begin(ring, 32);
 578         if (ret)
 579                 return ret;
 580
 581         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 582                         PIPE_CONTROL_WRITE_FLUSH |
 583                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 584         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 585         intel_ring_emit(ring, seqno);
 586         intel_ring_emit(ring, 0);
 587         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 588         scratch_addr += 128; /* write to separate cachelines */
 589         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 590         scratch_addr += 128;
 591         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 592         scratch_addr += 128;
 593         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 594         scratch_addr += 128;
 595         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 596         scratch_addr += 128;
 597         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 598         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 599                         PIPE_CONTROL_WRITE_FLUSH |
 600                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 601                         PIPE_CONTROL_NOTIFY);
 602         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 603         intel_ring_emit(ring, seqno);
 604         intel_ring_emit(ring, 0);
 605         intel_ring_advance(ring);
 606
 607         *result = seqno;
 608         return 0;
 609 }
 610
 611 static int
 612 render_ring_add_request(struct intel_ring_buffer *ring,
 613                         u32 *result)
 614 {
 615         struct drm_device *dev = ring->dev;
 616         u32 seqno = i915_gem_get_seqno(dev);
 617         int ret;
 618
 619         ret = intel_ring_begin(ring, 4);
 620         if (ret)
 621                 return ret;
 622
 623         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 624         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 625         intel_ring_emit(ring, seqno);
 626         intel_ring_emit(ring, MI_USER_INTERRUPT);
 627         intel_ring_advance(ring);
 628
 629         *result = seqno;
 630         return 0;
 631 }
 632
 633 static u32
 634 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
 635 {
 636         struct drm_device *dev = ring->dev;
 637
 638         /* Workaround to force correct ordering between irq and seqno writes on
 639          * ivb (and maybe also on snb) by reading from a CS register (like
 640          * ACTHD) before reading the status page. */
 641         if (IS_GEN7(dev))
 642                 intel_ring_get_active_head(ring);
 643         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 644 }
 645
 646 static u32
 647 ring_get_seqno(struct intel_ring_buffer *ring)
 648 {
 649         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 650 }
 651
 652 static u32
 653 pc_render_get_seqno(struct intel_ring_buffer *ring)
 654 {
 655         struct pipe_control *pc = ring->private;
 656         return pc->cpu_page[0];
 657 }
 658
 659 static void
 660 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 661 {
 662         dev_priv->gt_irq_mask &= ~mask;
 663         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 664         POSTING_READ(GTIMR);
 665 }
 666
 667 static void
 668 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 669 {
 670         dev_priv->gt_irq_mask |= mask;
 671         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 672         POSTING_READ(GTIMR);
 673 }
 674
 675 static void
 676 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 677 {
 678         dev_priv->irq_mask &= ~mask;
 679         I915_WRITE(IMR, dev_priv->irq_mask);
 680         POSTING_READ(IMR);
 681 }
 682
 683 static void
 684 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 685 {
 686         dev_priv->irq_mask |= mask;
 687         I915_WRITE(IMR, dev_priv->irq_mask);
 688         POSTING_READ(IMR);
 689 }
 690
 691 static bool
 692 render_ring_get_irq(struct intel_ring_buffer *ring)
 693 {
 694         struct drm_device *dev = ring->dev;
 695         drm_i915_private_t *dev_priv = dev->dev_private;
 696
 697         if (!dev->irq_enabled)
 698                 return false;
 699
 700         spin_lock(&ring->irq_lock);
 701         if (ring->irq_refcount++ == 0) {
 702                 if (HAS_PCH_SPLIT(dev))
 703                         ironlake_enable_irq(dev_priv,
 704                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 705                 else
 706                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 707         }
 708         spin_unlock(&ring->irq_lock);
 709
 710         return true;
 711 }
 712
 713 static void
 714 render_ring_put_irq(struct intel_ring_buffer *ring)
 715 {
 716         struct drm_device *dev = ring->dev;
 717         drm_i915_private_t *dev_priv = dev->dev_private;
 718
 719         spin_lock(&ring->irq_lock);
 720         if (--ring->irq_refcount == 0) {
 721                 if (HAS_PCH_SPLIT(dev))
 722                         ironlake_disable_irq(dev_priv,
 723                                              GT_USER_INTERRUPT |
 724                                              GT_PIPE_NOTIFY);
 725                 else
 726                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 727         }
 728         spin_unlock(&ring->irq_lock);
 729 }
 730
 731 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 732 {
 733         struct drm_device *dev = ring->dev;
 734         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 735         u32 mmio = 0;
 736
 737         /* The ring status page addresses are no longer next to the rest of
 738          * the ring registers as of gen7.
 739          */
 740         if (IS_GEN7(dev)) {
 741                 switch (ring->id) {
 742                 case RING_RENDER:
 743                         mmio = RENDER_HWS_PGA_GEN7;
 744                         break;
 745                 case RING_BLT:
 746                         mmio = BLT_HWS_PGA_GEN7;
 747                         break;
 748                 case RING_BSD:
 749                         mmio = BSD_HWS_PGA_GEN7;
 750                         break;
 751                 }
 752         } else if (IS_GEN6(ring->dev)) {
 753                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 754         } else {
 755                 mmio = RING_HWS_PGA(ring->mmio_base);
 756         }
 757
 758         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 759         POSTING_READ(mmio);
 760 }
 761
 762 static int
 763 bsd_ring_flush(struct intel_ring_buffer *ring,
 764                u32     invalidate_domains,
 765                u32     flush_domains)
 766 {
 767         int ret;
 768
 769         ret = intel_ring_begin(ring, 2);
 770         if (ret)
 771                 return ret;
 772
 773         intel_ring_emit(ring, MI_FLUSH);
 774         intel_ring_emit(ring, MI_NOOP);
 775         intel_ring_advance(ring);
 776         return 0;
 777 }
 778
 779 static int
 780 ring_add_request(struct intel_ring_buffer *ring,
 781                  u32 *result)
 782 {
 783         u32 seqno;
 784         int ret;
 785
 786         ret = intel_ring_begin(ring, 4);
 787         if (ret)
 788                 return ret;
 789
 790         seqno = i915_gem_get_seqno(ring->dev);
 791
 792         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 793         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 794         intel_ring_emit(ring, seqno);
 795         intel_ring_emit(ring, MI_USER_INTERRUPT);
 796         intel_ring_advance(ring);
 797
 798         *result = seqno;
 799         return 0;
 800 }
 801
 802 static bool
 803 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 804 {
 805         struct drm_device *dev = ring->dev;
 806         drm_i915_private_t *dev_priv = dev->dev_private;
 807
 808         if (!dev->irq_enabled)
 809                return false;
 810
 811         /* It looks like we need to prevent the gt from suspending while waiting
 812          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 813          * blt/bsd rings on ivb. */
 814         if (IS_GEN7(dev))
 815                 gen6_gt_force_wake_get(dev_priv);
 816
 817         spin_lock(&ring->irq_lock);
 818         if (ring->irq_refcount++ == 0) {
 819                 ring->irq_mask &= ~rflag;
 820                 I915_WRITE_IMR(ring, ring->irq_mask);
 821                 ironlake_enable_irq(dev_priv, gflag);
 822         }
 823         spin_unlock(&ring->irq_lock);
 824
 825         return true;
 826 }
 827
 828 static void
 829 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 830 {
 831         struct drm_device *dev = ring->dev;
 832         drm_i915_private_t *dev_priv = dev->dev_private;
 833
 834         spin_lock(&ring->irq_lock);
 835         if (--ring->irq_refcount == 0) {
 836                 ring->irq_mask |= rflag;
 837                 I915_WRITE_IMR(ring, ring->irq_mask);
 838                 ironlake_disable_irq(dev_priv, gflag);
 839         }
 840         spin_unlock(&ring->irq_lock);
 841
 842         if (IS_GEN7(dev))
 843                 gen6_gt_force_wake_put(dev_priv);
 844 }
 845
 846 static bool
 847 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 848 {
 849         struct drm_device *dev = ring->dev;
 850         drm_i915_private_t *dev_priv = dev->dev_private;
 851
 852         if (!dev->irq_enabled)
 853                 return false;
 854
 855         spin_lock(&ring->irq_lock);
 856         if (ring->irq_refcount++ == 0) {
 857                 if (IS_G4X(dev))
 858                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 859                 else
 860                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 861         }
 862         spin_unlock(&ring->irq_lock);
 863
 864         return true;
 865 }
 866 static void
 867 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 868 {
 869         struct drm_device *dev = ring->dev;
 870         drm_i915_private_t *dev_priv = dev->dev_private;
 871
 872         spin_lock(&ring->irq_lock);
 873         if (--ring->irq_refcount == 0) {
 874                 if (IS_G4X(dev))
 875                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 876                 else
 877                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 878         }
 879         spin_unlock(&ring->irq_lock);
 880 }
 881
 882 static int
 883 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 884 {
 885         int ret;
 886
 887         ret = intel_ring_begin(ring, 2);
 888         if (ret)
 889                 return ret;
 890
 891         intel_ring_emit(ring,
 892                         MI_BATCH_BUFFER_START | (2 << 6) |
 893                         MI_BATCH_NON_SECURE_I965);
 894         intel_ring_emit(ring, offset);
 895         intel_ring_advance(ring);
 896
 897         return 0;
 898 }
 899
 900 static int
 901 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 902                                 u32 offset, u32 len)
 903 {
 904         struct drm_device *dev = ring->dev;
 905         int ret;
 906
 907         if (IS_I830(dev) || IS_845G(dev)) {
 908                 ret = intel_ring_begin(ring, 4);
 909                 if (ret)
 910                         return ret;
 911
 912                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 913                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 914                 intel_ring_emit(ring, offset + len - 8);
 915                 intel_ring_emit(ring, 0);
 916         } else {
 917                 ret = intel_ring_begin(ring, 2);
 918                 if (ret)
 919                         return ret;
 920
 921                 if (INTEL_INFO(dev)->gen >= 4) {
 922                         intel_ring_emit(ring,
 923                                         MI_BATCH_BUFFER_START | (2 << 6) |
 924                                         MI_BATCH_NON_SECURE_I965);
 925                         intel_ring_emit(ring, offset);
 926                 } else {
 927                         intel_ring_emit(ring,
 928                                         MI_BATCH_BUFFER_START | (2 << 6));
 929                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 930                 }
 931         }
 932         intel_ring_advance(ring);
 933
 934         return 0;
 935 }
 936
 937 static void cleanup_status_page(struct intel_ring_buffer *ring)
 938 {
 939         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 940         struct drm_i915_gem_object *obj;
 941
 942         obj = ring->status_page.obj;
 943         if (obj == NULL)
 944                 return;
 945
 946         kunmap(obj->pages[0]);
 947         i915_gem_object_unpin(obj);
 948         drm_gem_object_unreference(&obj->base);
 949         ring->status_page.obj = NULL;
 950
 951         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 952 }
 953
 954 static int init_status_page(struct intel_ring_buffer *ring)
 955 {
 956         struct drm_device *dev = ring->dev;
 957         drm_i915_private_t *dev_priv = dev->dev_private;
 958         struct drm_i915_gem_object *obj;
 959         int ret;
 960
 961         obj = i915_gem_alloc_object(dev, 4096);
 962         if (obj == NULL) {
 963                 DRM_ERROR("Failed to allocate status page\n");
 964                 ret = -ENOMEM;
 965                 goto err;
 966         }
 967
 968         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 969
 970         ret = i915_gem_object_pin(obj, 4096, true);
 971         if (ret != 0) {
 972                 goto err_unref;
 973         }
 974
 975         ring->status_page.gfx_addr = obj->gtt_offset;
 976         ring->status_page.page_addr = kmap(obj->pages[0]);
 977         if (ring->status_page.page_addr == NULL) {
 978                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 979                 goto err_unpin;
 980         }
 981         ring->status_page.obj = obj;
 982         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 983
 984         intel_ring_setup_status_page(ring);
 985         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 986                         ring->name, ring->status_page.gfx_addr);
 987
 988         return 0;
 989
 990 err_unpin:
 991         i915_gem_object_unpin(obj);
 992 err_unref:
 993         drm_gem_object_unreference(&obj->base);
 994 err:
 995         return ret;
 996 }
 997
 998 int intel_init_ring_buffer(struct drm_device *dev,
 999                            struct intel_ring_buffer *ring)
1000 {
1001         struct drm_i915_gem_object *obj;
1002         int ret;
1003
1004         ring->dev = dev;
1005         INIT_LIST_HEAD(&ring->active_list);
1006         INIT_LIST_HEAD(&ring->request_list);
1007         INIT_LIST_HEAD(&ring->gpu_write_list);
1008
1009         init_waitqueue_head(&ring->irq_queue);
1010         spin_lock_init(&ring->irq_lock);
1011         ring->irq_mask = ~0;
1012
1013         if (I915_NEED_GFX_HWS(dev)) {
1014                 ret = init_status_page(ring);
1015                 if (ret)
1016                         return ret;
1017         }
1018
1019         obj = i915_gem_alloc_object(dev, ring->size);
1020         if (obj == NULL) {
1021                 DRM_ERROR("Failed to allocate ringbuffer\n");
1022                 ret = -ENOMEM;
1023                 goto err_hws;
1024         }
1025
1026         ring->obj = obj;
1027
1028         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1029         if (ret)
1030                 goto err_unref;
1031
1032         ring->map.size = ring->size;
1033         ring->map.offset = dev->agp->base + obj->gtt_offset;
1034         ring->map.type = 0;
1035         ring->map.flags = 0;
1036         ring->map.mtrr = 0;
1037
1038         drm_core_ioremap_wc(&ring->map, dev);
1039         if (ring->map.handle == NULL) {
1040                 DRM_ERROR("Failed to map ringbuffer.\n");
1041                 ret = -EINVAL;
1042                 goto err_unpin;
1043         }
1044
1045         ring->virtual_start = ring->map.handle;
1046         ret = ring->init(ring);
1047         if (ret)
1048                 goto err_unmap;
1049
1050         /* Workaround an erratum on the i830 which causes a hang if
1051          * the TAIL pointer points to within the last 2 cachelines
1052          * of the buffer.
1053          */
1054         ring->effective_size = ring->size;
1055         if (IS_I830(ring->dev))
1056                 ring->effective_size -= 128;
1057
1058         return 0;
1059
1060 err_unmap:
1061         drm_core_ioremapfree(&ring->map, dev);
1062 err_unpin:
1063         i915_gem_object_unpin(obj);
1064 err_unref:
1065         drm_gem_object_unreference(&obj->base);
1066         ring->obj = NULL;
1067 err_hws:
1068         cleanup_status_page(ring);
1069         return ret;
1070 }
1071
1072 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1073 {
1074         struct drm_i915_private *dev_priv;
1075         int ret;
1076
1077         if (ring->obj == NULL)
1078                 return;
1079
1080         /* Disable the ring buffer. The ring must be idle at this point */
1081         dev_priv = ring->dev->dev_private;
1082         ret = intel_wait_ring_idle(ring);
1083         if (ret)
1084                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1085                           ring->name, ret);
1086
1087         I915_WRITE_CTL(ring, 0);
1088
1089         drm_core_ioremapfree(&ring->map, ring->dev);
1090
1091         i915_gem_object_unpin(ring->obj);
1092         drm_gem_object_unreference(&ring->obj->base);
1093         ring->obj = NULL;
1094
1095         if (ring->cleanup)
1096                 ring->cleanup(ring);
1097
1098         cleanup_status_page(ring);
1099 }
1100
1101 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1102 {
1103         unsigned int *virt;
1104         int rem = ring->size - ring->tail;
1105
1106         if (ring->space < rem) {
1107                 int ret = intel_wait_ring_buffer(ring, rem);
1108                 if (ret)
1109                         return ret;
1110         }
1111
1112         virt = (unsigned int *)(ring->virtual_start + ring->tail);
1113         rem /= 8;
1114         while (rem--) {
1115                 *virt++ = MI_NOOP;
1116                 *virt++ = MI_NOOP;
1117         }
1118
1119         ring->tail = 0;
1120         ring->space = ring_space(ring);
1121
1122         return 0;
1123 }
1124
1125 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1126 {
1127         struct drm_device *dev = ring->dev;
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129         unsigned long end;
1130         u32 head;
1131
1132         /* If the reported head position has wrapped or hasn't advanced,
1133          * fallback to the slow and accurate path.
1134          */
1135         head = intel_read_status_page(ring, 4);
1136         if (head > ring->head) {
1137                 ring->head = head;
1138                 ring->space = ring_space(ring);
1139                 if (ring->space >= n)
1140                         return 0;
1141         }
1142
1143         trace_i915_ring_wait_begin(ring);
1144         end = jiffies + 3 * HZ;
1145         do {
1146                 ring->head = I915_READ_HEAD(ring);
1147                 ring->space = ring_space(ring);
1148                 if (ring->space >= n) {
1149                         trace_i915_ring_wait_end(ring);
1150                         return 0;
1151                 }
1152
1153                 if (dev->primary->master) {
1154                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1155                         if (master_priv->sarea_priv)
1156                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1157                 }
1158
1159                 msleep(1);
1160                 if (atomic_read(&dev_priv->mm.wedged))
1161                         return -EAGAIN;
1162         } while (!time_after(jiffies, end));
1163         trace_i915_ring_wait_end(ring);
1164         return -EBUSY;
1165 }
1166
1167 int intel_ring_begin(struct intel_ring_buffer *ring,
1168                      int num_dwords)
1169 {
1170         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1171         int n = 4*num_dwords;
1172         int ret;
1173
1174         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1175                 return -EIO;
1176
1177         if (unlikely(ring->tail + n > ring->effective_size)) {
1178                 ret = intel_wrap_ring_buffer(ring);
1179                 if (unlikely(ret))
1180                         return ret;
1181         }
1182
1183         if (unlikely(ring->space < n)) {
1184                 ret = intel_wait_ring_buffer(ring, n);
1185                 if (unlikely(ret))
1186                         return ret;
1187         }
1188
1189         ring->space -= n;
1190         return 0;
1191 }
1192
1193 void intel_ring_advance(struct intel_ring_buffer *ring)
1194 {
1195         ring->tail &= ring->size - 1;
1196         ring->write_tail(ring, ring->tail);
1197 }
1198
1199 static const struct intel_ring_buffer render_ring = {
1200         .name                   = "render ring",
1201         .id                     = RING_RENDER,
1202         .mmio_base              = RENDER_RING_BASE,
1203         .size                   = 32 * PAGE_SIZE,
1204         .init                   = init_render_ring,
1205         .write_tail             = ring_write_tail,
1206         .flush                  = render_ring_flush,
1207         .add_request            = render_ring_add_request,
1208         .get_seqno              = ring_get_seqno,
1209         .irq_get                = render_ring_get_irq,
1210         .irq_put                = render_ring_put_irq,
1211         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1212         .cleanup                = render_ring_cleanup,
1213         .sync_to                = render_ring_sync_to,
1214         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1215                                    MI_SEMAPHORE_SYNC_RV,
1216                                    MI_SEMAPHORE_SYNC_RB},
1217         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1218 };
1219
1220 /* ring buffer for bit-stream decoder */
1221
1222 static const struct intel_ring_buffer bsd_ring = {
1223         .name                   = "bsd ring",
1224         .id                     = RING_BSD,
1225         .mmio_base              = BSD_RING_BASE,
1226         .size                   = 32 * PAGE_SIZE,
1227         .init                   = init_ring_common,
1228         .write_tail             = ring_write_tail,
1229         .flush                  = bsd_ring_flush,
1230         .add_request            = ring_add_request,
1231         .get_seqno              = ring_get_seqno,
1232         .irq_get                = bsd_ring_get_irq,
1233         .irq_put                = bsd_ring_put_irq,
1234         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1235 };
1236
1237
1238 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1239                                      u32 value)
1240 {
1241         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1242
1243        /* Every tail move must follow the sequence below */
1244         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1245                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1246                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1247         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1248
1249         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1250                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1251                 50))
1252         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1253
1254         I915_WRITE_TAIL(ring, value);
1255         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1256                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1257                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1258 }
1259
1260 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1261                            u32 invalidate, u32 flush)
1262 {
1263         uint32_t cmd;
1264         int ret;
1265
1266         ret = intel_ring_begin(ring, 4);
1267         if (ret)
1268                 return ret;
1269
1270         cmd = MI_FLUSH_DW;
1271         if (invalidate & I915_GEM_GPU_DOMAINS)
1272                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1273         intel_ring_emit(ring, cmd);
1274         intel_ring_emit(ring, 0);
1275         intel_ring_emit(ring, 0);
1276         intel_ring_emit(ring, MI_NOOP);
1277         intel_ring_advance(ring);
1278         return 0;
1279 }
1280
1281 static int
1282 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1283                               u32 offset, u32 len)
1284 {
1285         int ret;
1286
1287         ret = intel_ring_begin(ring, 2);
1288         if (ret)
1289                 return ret;
1290
1291         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1292         /* bit0-7 is the length on GEN6+ */
1293         intel_ring_emit(ring, offset);
1294         intel_ring_advance(ring);
1295
1296         return 0;
1297 }
1298
1299 static bool
1300 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1301 {
1302         return gen6_ring_get_irq(ring,
1303                                  GT_USER_INTERRUPT,
1304                                  GEN6_RENDER_USER_INTERRUPT);
1305 }
1306
1307 static void
1308 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1309 {
1310         return gen6_ring_put_irq(ring,
1311                                  GT_USER_INTERRUPT,
1312                                  GEN6_RENDER_USER_INTERRUPT);
1313 }
1314
1315 static bool
1316 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1317 {
1318         return gen6_ring_get_irq(ring,
1319                                  GT_GEN6_BSD_USER_INTERRUPT,
1320                                  GEN6_BSD_USER_INTERRUPT);
1321 }
1322
1323 static void
1324 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1325 {
1326         return gen6_ring_put_irq(ring,
1327                                  GT_GEN6_BSD_USER_INTERRUPT,
1328                                  GEN6_BSD_USER_INTERRUPT);
1329 }
1330
1331 /* ring buffer for Video Codec for Gen6+ */
1332 static const struct intel_ring_buffer gen6_bsd_ring = {
1333         .name                   = "gen6 bsd ring",
1334         .id                     = RING_BSD,
1335         .mmio_base              = GEN6_BSD_RING_BASE,
1336         .size                   = 32 * PAGE_SIZE,
1337         .init                   = init_ring_common,
1338         .write_tail             = gen6_bsd_ring_write_tail,
1339         .flush                  = gen6_ring_flush,
1340         .add_request            = gen6_add_request,
1341         .get_seqno              = gen6_ring_get_seqno,
1342         .irq_get                = gen6_bsd_ring_get_irq,
1343         .irq_put                = gen6_bsd_ring_put_irq,
1344         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1345         .sync_to                = gen6_bsd_ring_sync_to,
1346         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1347                                    MI_SEMAPHORE_SYNC_INVALID,
1348                                    MI_SEMAPHORE_SYNC_VB},
1349         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1350 };
1351
1352 /* Blitter support (SandyBridge+) */
1353
1354 static bool
1355 blt_ring_get_irq(struct intel_ring_buffer *ring)
1356 {
1357         return gen6_ring_get_irq(ring,
1358                                  GT_BLT_USER_INTERRUPT,
1359                                  GEN6_BLITTER_USER_INTERRUPT);
1360 }
1361
1362 static void
1363 blt_ring_put_irq(struct intel_ring_buffer *ring)
1364 {
1365         gen6_ring_put_irq(ring,
1366                           GT_BLT_USER_INTERRUPT,
1367                           GEN6_BLITTER_USER_INTERRUPT);
1368 }
1369
1370
1371 /* Workaround for some stepping of SNB,
1372  * each time when BLT engine ring tail moved,
1373  * the first command in the ring to be parsed
1374  * should be MI_BATCH_BUFFER_START
1375  */
1376 #define NEED_BLT_WORKAROUND(dev) \
1377         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1378
1379 static inline struct drm_i915_gem_object *
1380 to_blt_workaround(struct intel_ring_buffer *ring)
1381 {
1382         return ring->private;
1383 }
1384
1385 static int blt_ring_init(struct intel_ring_buffer *ring)
1386 {
1387         if (NEED_BLT_WORKAROUND(ring->dev)) {
1388                 struct drm_i915_gem_object *obj;
1389                 u32 *ptr;
1390                 int ret;
1391
1392                 obj = i915_gem_alloc_object(ring->dev, 4096);
1393                 if (obj == NULL)
1394                         return -ENOMEM;
1395
1396                 ret = i915_gem_object_pin(obj, 4096, true);
1397                 if (ret) {
1398                         drm_gem_object_unreference(&obj->base);
1399                         return ret;
1400                 }
1401
1402                 ptr = kmap(obj->pages[0]);
1403                 *ptr++ = MI_BATCH_BUFFER_END;
1404                 *ptr++ = MI_NOOP;
1405                 kunmap(obj->pages[0]);
1406
1407                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1408                 if (ret) {
1409                         i915_gem_object_unpin(obj);
1410                         drm_gem_object_unreference(&obj->base);
1411                         return ret;
1412                 }
1413
1414                 ring->private = obj;
1415         }
1416
1417         return init_ring_common(ring);
1418 }
1419
1420 static int blt_ring_begin(struct intel_ring_buffer *ring,
1421                           int num_dwords)
1422 {
1423         if (ring->private) {
1424                 int ret = intel_ring_begin(ring, num_dwords+2);
1425                 if (ret)
1426                         return ret;
1427
1428                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1429                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1430
1431                 return 0;
1432         } else
1433                 return intel_ring_begin(ring, 4);
1434 }
1435
1436 static int blt_ring_flush(struct intel_ring_buffer *ring,
1437                           u32 invalidate, u32 flush)
1438 {
1439         uint32_t cmd;
1440         int ret;
1441
1442         ret = blt_ring_begin(ring, 4);
1443         if (ret)
1444                 return ret;
1445
1446         cmd = MI_FLUSH_DW;
1447         if (invalidate & I915_GEM_DOMAIN_RENDER)
1448                 cmd |= MI_INVALIDATE_TLB;
1449         intel_ring_emit(ring, cmd);
1450         intel_ring_emit(ring, 0);
1451         intel_ring_emit(ring, 0);
1452         intel_ring_emit(ring, MI_NOOP);
1453         intel_ring_advance(ring);
1454         return 0;
1455 }
1456
1457 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1458 {
1459         if (!ring->private)
1460                 return;
1461
1462         i915_gem_object_unpin(ring->private);
1463         drm_gem_object_unreference(ring->private);
1464         ring->private = NULL;
1465 }
1466
1467 static const struct intel_ring_buffer gen6_blt_ring = {
1468         .name                   = "blt ring",
1469         .id                     = RING_BLT,
1470         .mmio_base              = BLT_RING_BASE,
1471         .size                   = 32 * PAGE_SIZE,
1472         .init                   = blt_ring_init,
1473         .write_tail             = ring_write_tail,
1474         .flush                  = blt_ring_flush,
1475         .add_request            = gen6_add_request,
1476         .get_seqno              = gen6_ring_get_seqno,
1477         .irq_get                = blt_ring_get_irq,
1478         .irq_put                = blt_ring_put_irq,
1479         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1480         .cleanup                = blt_ring_cleanup,
1481         .sync_to                = gen6_blt_ring_sync_to,
1482         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1483                                    MI_SEMAPHORE_SYNC_BV,
1484                                    MI_SEMAPHORE_SYNC_INVALID},
1485         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1486 };
1487
1488 int intel_init_render_ring_buffer(struct drm_device *dev)
1489 {
1490         drm_i915_private_t *dev_priv = dev->dev_private;
1491         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1492
1493         *ring = render_ring;
1494         if (INTEL_INFO(dev)->gen >= 6) {
1495                 ring->add_request = gen6_add_request;
1496                 ring->flush = gen6_render_ring_flush;
1497                 ring->irq_get = gen6_render_ring_get_irq;
1498                 ring->irq_put = gen6_render_ring_put_irq;
1499                 ring->get_seqno = gen6_ring_get_seqno;
1500         } else if (IS_GEN5(dev)) {
1501                 ring->add_request = pc_render_add_request;
1502                 ring->get_seqno = pc_render_get_seqno;
1503         }
1504
1505         if (!I915_NEED_GFX_HWS(dev)) {
1506                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1507                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1508         }
1509
1510         return intel_init_ring_buffer(dev, ring);
1511 }
1512
1513 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1514 {
1515         drm_i915_private_t *dev_priv = dev->dev_private;
1516         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1517
1518         *ring = render_ring;
1519         if (INTEL_INFO(dev)->gen >= 6) {
1520                 ring->add_request = gen6_add_request;
1521                 ring->irq_get = gen6_render_ring_get_irq;
1522                 ring->irq_put = gen6_render_ring_put_irq;
1523         } else if (IS_GEN5(dev)) {
1524                 ring->add_request = pc_render_add_request;
1525                 ring->get_seqno = pc_render_get_seqno;
1526         }
1527
1528         if (!I915_NEED_GFX_HWS(dev))
1529                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1530
1531         ring->dev = dev;
1532         INIT_LIST_HEAD(&ring->active_list);
1533         INIT_LIST_HEAD(&ring->request_list);
1534         INIT_LIST_HEAD(&ring->gpu_write_list);
1535
1536         ring->size = size;
1537         ring->effective_size = ring->size;
1538         if (IS_I830(ring->dev))
1539                 ring->effective_size -= 128;
1540
1541         ring->map.offset = start;
1542         ring->map.size = size;
1543         ring->map.type = 0;
1544         ring->map.flags = 0;
1545         ring->map.mtrr = 0;
1546
1547         drm_core_ioremap_wc(&ring->map, dev);
1548         if (ring->map.handle == NULL) {
1549                 DRM_ERROR("can not ioremap virtual address for"
1550                           " ring buffer\n");
1551                 return -ENOMEM;
1552         }
1553
1554         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1555         return 0;
1556 }
1557
1558 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1559 {
1560         drm_i915_private_t *dev_priv = dev->dev_private;
1561         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1562
1563         if (IS_GEN6(dev) || IS_GEN7(dev))
1564                 *ring = gen6_bsd_ring;
1565         else
1566                 *ring = bsd_ring;
1567
1568         return intel_init_ring_buffer(dev, ring);
1569 }
1570
1571 int intel_init_blt_ring_buffer(struct drm_device *dev)
1572 {
1573         drm_i915_private_t *dev_priv = dev->dev_private;
1574         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1575
1576         *ring = gen6_blt_ring;
1577
1578         return intel_init_ring_buffer(dev, ring);
1579 }