2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/config.h>
12 #include <linux/linkage.h>
17 * Note that these macros must not contain any code which is not
18 * 100% relocatable. Any attempt to do so will result in a crash.
19 * Please select one of the following when turning on debugging.
23 #if defined(CONFIG_DEBUG_ICEDCC)
27 mcr p14, 0, \ch, c0, c1, 0
31 #include <asm/arch/debug-macro.S>
37 #if defined(CONFIG_ARCH_SA1100)
39 mov \rb, #0x80000000 @ physical base address
40 #ifdef CONFIG_DEBUG_LL_SER3
41 add \rb, \rb, #0x00050000 @ Ser3
43 add \rb, \rb, #0x00010000 @ Ser1
46 #elif defined(CONFIG_ARCH_IOP331)
49 orr \rb, \rb, #0x00ff0000
50 orr \rb, \rb, #0x0000f700 @ location of the UART
52 #elif defined(CONFIG_ARCH_S3C2410)
55 add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
76 .macro debug_reloc_start
79 kphex r6, 8 /* processor id */
81 kphex r7, 8 /* architecture id */
83 mrc p15, 0, r0, c1, c0
84 kphex r0, 8 /* control reg */
86 kphex r5, 8 /* decompressed kernel start */
88 kphex r9, 8 /* decompressed kernel end */
90 kphex r4, 8 /* kernel execution address */
95 .macro debug_reloc_end
97 kphex r5, 8 /* end of kernel */
100 bl memdump /* dump 256 bytes at start of kernel */
104 .section ".start", #alloc, #execinstr
106 * sort out different calling conventions
110 .type start,#function
116 .word 0x016f2818 @ Magic numbers to help the loader
117 .word start @ absolute load/run zImage address
118 .word _edata @ zImage end address
119 1: mov r7, r1 @ save architecture ID
120 mov r8, r2 @ save atags pointer
122 #ifndef __ARM_ARCH_2__
124 * Booting from Angel - need to enter SVC mode and disable
125 * FIQs/IRQs (numeric definitions from angel arm.h source).
126 * We only do this if we were in user mode on entry.
128 mrs r2, cpsr @ get current mode
129 tst r2, #3 @ not user?
131 mov r0, #0x17 @ angel_SWIreason_EnterSVC
132 swi 0x123456 @ angel_SWI_ARM
134 mrs r2, cpsr @ turn off interrupts to
135 orr r2, r2, #0xc0 @ prevent angel from running
138 teqp pc, #0x0c000003 @ turn off interrupts
142 * Note that some cache flushing and other stuff may
143 * be needed here - is there an Angel SWI call for this?
147 * some architecture specific code can be inserted
148 * by the linker here, but it should preserve r7, r8, and r9.
153 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
154 subs r0, r0, r1 @ calculate the delta offset
156 @ if delta is zero, we are
157 beq not_relocated @ running at the address we
161 * We're running at a different address. We need to fix
162 * up various pointers:
163 * r5 - zImage base address
171 #ifndef CONFIG_ZBOOT_ROM
173 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
174 * we need to fix up pointers into the BSS region.
184 * Relocate all entries in the GOT table.
186 1: ldr r1, [r6, #0] @ relocate entries in the GOT
187 add r1, r1, r0 @ table. This fixes up the
188 str r1, [r6], #4 @ C references.
194 * Relocate entries in the GOT table. We only relocate
195 * the entries that are outside the (relocated) BSS region.
197 1: ldr r1, [r6, #0] @ relocate entries in the GOT
198 cmp r1, r2 @ entry < bss_start ||
199 cmphs r3, r1 @ _end < entry
200 addlo r1, r1, r0 @ table. This fixes up the
201 str r1, [r6], #4 @ C references.
206 not_relocated: mov r0, #0
207 1: str r0, [r2], #4 @ clear bss
215 * The C runtime environment should now be setup
216 * sufficiently. Turn the cache on, set up some
217 * pointers, and start decompressing.
221 mov r1, sp @ malloc space above stack
222 add r2, sp, #0x10000 @ 64k max
225 * Check to see if we will overwrite ourselves.
226 * r4 = final kernel address
227 * r5 = start of this image
228 * r2 = end of malloc space (and therefore this image)
231 * r4 + image length <= r5 -> OK
235 add r0, r4, #4096*1024 @ 4MB largest kernel size
239 mov r5, r2 @ decompress after malloc space
245 bic r0, r0, #127 @ align the kernel length
247 * r0 = decompressed kernel length
249 * r4 = kernel execution address
250 * r5 = decompressed kernel start
252 * r7 = architecture ID
256 add r1, r5, r0 @ end of decompressed kernel
260 1: ldmia r2!, {r9 - r14} @ copy relocation code
261 stmia r1!, {r9 - r14}
262 ldmia r2!, {r9 - r14}
263 stmia r1!, {r9 - r14}
268 add pc, r5, r0 @ call relocation code
271 * We're not in danger of overwriting ourselves. Do this the simple way.
273 * r4 = kernel execution address
274 * r7 = architecture ID
276 wont_overwrite: mov r0, r4
283 .word __bss_start @ r2
287 .word _got_start @ r6
289 .word user_stack+4096 @ sp
290 LC1: .word reloc_end - reloc_start
293 #ifdef CONFIG_ARCH_RPC
295 params: ldr r0, =params_phys
302 * Turn on the cache. We need to setup some page tables so that we
303 * can have both the I and D caches on.
305 * We place the page tables 16k down from the kernel execution address,
306 * and we hope that nothing else is using it. If we're using it, we
310 * r4 = kernel execution address
312 * r7 = architecture number
314 * r9 = run-time address of "start" (???)
316 * r1, r2, r3, r9, r10, r12 corrupted
317 * This routine must preserve:
321 cache_on: mov r3, #8 @ cache_on function
325 * Initialize the highest priority protection region, PR7
326 * to cover all 32bit address and cacheable and bufferable.
328 __armv4_mpu_cache_on:
329 mov r0, #0x3f @ 4G, the whole
330 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
331 mcr p15, 0, r0, c6, c7, 1
334 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
335 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
336 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
339 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
340 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
343 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
344 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
345 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
346 mrc p15, 0, r0, c1, c0, 0 @ read control reg
347 @ ...I .... ..D. WC.M
348 orr r0, r0, #0x002d @ .... .... ..1. 11.1
349 orr r0, r0, #0x1000 @ ...1 .... .... ....
351 mcr p15, 0, r0, c1, c0, 0 @ write control reg
354 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
355 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
358 __armv3_mpu_cache_on:
359 mov r0, #0x3f @ 4G, the whole
360 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
363 mcr p15, 0, r0, c2, c0, 0 @ cache on
364 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
367 mcr p15, 0, r0, c5, c0, 0 @ access permission
370 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
371 mrc p15, 0, r0, c1, c0, 0 @ read control reg
372 @ .... .... .... WC.M
373 orr r0, r0, #0x000d @ .... .... .... 11.1
375 mcr p15, 0, r0, c1, c0, 0 @ write control reg
377 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
380 __setup_mmu: sub r3, r4, #16384 @ Page directory size
381 bic r3, r3, #0xff @ Align the pointer
384 * Initialise the page tables, turning on the cacheable and bufferable
385 * bits for the RAM area only.
389 mov r9, r9, lsl #18 @ start of RAM
390 add r10, r9, #0x10000000 @ a reasonable RAM size
394 1: cmp r1, r9 @ if virt > start of RAM
395 orrhs r1, r1, #0x0c @ set cacheable, bufferable
396 cmp r1, r10 @ if virt > end of RAM
397 bichs r1, r1, #0x0c @ clear cacheable, bufferable
398 str r1, [r0], #4 @ 1:1 mapping
403 * If ever we are running from Flash, then we surely want the cache
404 * to be enabled also for our execution instance... We map 2MB of it
405 * so there is no map overlap problem for up to 1 MB compressed kernel.
406 * If the execution is in RAM then we would only be duplicating the above.
411 orr r1, r1, r2, lsl #20
412 add r0, r3, r2, lsl #2
418 __armv4_mmu_cache_on:
422 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
423 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
424 mrc p15, 0, r0, c1, c0, 0 @ read control reg
425 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
427 bl __common_mmu_cache_on
429 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
436 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
437 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
439 bl __common_mmu_cache_on
441 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
444 __common_mmu_cache_on:
446 orr r0, r0, #0x000d @ Write buffer, mmu
449 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
450 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
452 .align 5 @ cache line aligned
453 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
454 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
455 sub pc, lr, r0, lsr #32 @ properly flush pipeline
458 * All code following this line is relocatable. It is relocated by
459 * the above code to the end of the decompressed kernel image and
460 * executed there. During this time, we have no stacks.
462 * r0 = decompressed kernel length
464 * r4 = kernel execution address
465 * r5 = decompressed kernel start
467 * r7 = architecture ID
472 reloc_start: add r9, r5, r0
477 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
478 stmia r1!, {r0, r2, r3, r10 - r14}
485 call_kernel: bl cache_clean_flush
487 mov r0, #0 @ must be zero
488 mov r1, r7 @ restore architecture number
489 mov r2, r8 @ restore atags pointer
490 mov pc, r4 @ call kernel
493 * Here follow the relocatable cache support functions for the
494 * various processors. This is a generic hook for locating an
495 * entry and jumping to an instruction at the specified offset
496 * from the start of the block. Please note this is all position
506 call_cache_fn: adr r12, proc_types
507 mrc p15, 0, r6, c0, c0 @ get processor ID
508 1: ldr r1, [r12, #0] @ get value
509 ldr r2, [r12, #4] @ get mask
510 eor r1, r1, r6 @ (real ^ match)
512 addeq pc, r12, r3 @ call cache function
517 * Table for cache operations. This is basically:
520 * - 'cache on' method instruction
521 * - 'cache off' method instruction
522 * - 'cache flush' method instruction
524 * We match an entry using: ((real_id ^ match) & mask) == 0
526 * Writethrough caches generally only need 'on' and 'off'
527 * methods. Writeback caches _must_ have the flush method
530 .type proc_types,#object
532 .word 0x41560600 @ ARM6/610
534 b __arm6_mmu_cache_off @ works, but slow
535 b __arm6_mmu_cache_off
537 @ b __arm6_mmu_cache_on @ untested
538 @ b __arm6_mmu_cache_off
539 @ b __armv3_mmu_cache_flush
541 .word 0x00000000 @ old ARM ID
547 .word 0x41007000 @ ARM7/710
549 b __arm7_mmu_cache_off
550 b __arm7_mmu_cache_off
553 .word 0x41807200 @ ARM720T (writethrough)
555 b __armv4_mmu_cache_on
556 b __armv4_mmu_cache_off
559 .word 0x41007400 @ ARM74x
561 b __armv3_mpu_cache_on
562 b __armv3_mpu_cache_off
563 b __armv3_mpu_cache_flush
565 .word 0x41009400 @ ARM94x
567 b __armv4_mpu_cache_on
568 b __armv4_mpu_cache_off
569 b __armv4_mpu_cache_flush
571 .word 0x00007000 @ ARM7 IDs
577 @ Everything from here on will be the new ID system.
579 .word 0x4401a100 @ sa110 / sa1100
581 b __armv4_mmu_cache_on
582 b __armv4_mmu_cache_off
583 b __armv4_mmu_cache_flush
585 .word 0x6901b110 @ sa1110
587 b __armv4_mmu_cache_on
588 b __armv4_mmu_cache_off
589 b __armv4_mmu_cache_flush
591 @ These match on the architecture ID
593 .word 0x00020000 @ ARMv4T
595 b __armv4_mmu_cache_on
596 b __armv4_mmu_cache_off
597 b __armv4_mmu_cache_flush
599 .word 0x00050000 @ ARMv5TE
601 b __armv4_mmu_cache_on
602 b __armv4_mmu_cache_off
603 b __armv4_mmu_cache_flush
605 .word 0x00060000 @ ARMv5TEJ
607 b __armv4_mmu_cache_on
608 b __armv4_mmu_cache_off
609 b __armv4_mmu_cache_flush
611 .word 0x0007b000 @ ARMv6
613 b __armv4_mmu_cache_on
614 b __armv4_mmu_cache_off
615 b __armv6_mmu_cache_flush
617 .word 0 @ unrecognised type
623 .size proc_types, . - proc_types
626 * Turn off the Cache and MMU. ARMv3 does not support
627 * reading the control register, but ARMv4 does.
629 * On entry, r6 = processor ID
630 * On exit, r0, r1, r2, r3, r12 corrupted
631 * This routine must preserve: r4, r6, r7
634 cache_off: mov r3, #12 @ cache_off function
637 __armv4_mpu_cache_off:
638 mrc p15, 0, r0, c1, c0
640 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
642 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
643 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
644 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
647 __armv3_mpu_cache_off:
648 mrc p15, 0, r0, c1, c0
650 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
652 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
655 __armv4_mmu_cache_off:
656 mrc p15, 0, r0, c1, c0
658 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
660 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
661 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
664 __arm6_mmu_cache_off:
665 mov r0, #0x00000030 @ ARM6 control reg.
666 b __armv3_mmu_cache_off
668 __arm7_mmu_cache_off:
669 mov r0, #0x00000070 @ ARM7 control reg.
670 b __armv3_mmu_cache_off
672 __armv3_mmu_cache_off:
673 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
675 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
676 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
680 * Clean and flush the cache to maintain consistency.
685 * r1, r2, r3, r11, r12 corrupted
686 * This routine must preserve:
694 __armv4_mpu_cache_flush:
697 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
698 mov r1, #7 << 5 @ 8 segments
699 1: orr r3, r1, #63 << 26 @ 64 entries
700 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
701 subs r3, r3, #1 << 26
702 bcs 2b @ entries 63 to 0
704 bcs 1b @ segments 7 to 0
707 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
708 mcr p15, 0, ip, c7, c10, 4 @ drain WB
712 __armv6_mmu_cache_flush:
714 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
715 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
716 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
717 mcr p15, 0, r1, c7, c10, 4 @ drain WB
720 __armv4_mmu_cache_flush:
721 mov r2, #64*1024 @ default: 32K dcache size (*2)
722 mov r11, #32 @ default: 32 byte line size
723 mrc p15, 0, r3, c0, c0, 1 @ read cache type
724 teq r3, r6 @ cache ID register present?
729 mov r2, r2, lsl r1 @ base dcache size *2
730 tst r3, #1 << 14 @ test M bit
731 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
735 mov r11, r11, lsl r3 @ cache line size in bytes
737 bic r1, pc, #63 @ align to longest cache line
739 1: ldr r3, [r1], r11 @ s/w flush D cache
743 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
744 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
745 mcr p15, 0, r1, c7, c10, 4 @ drain WB
748 __armv3_mmu_cache_flush:
749 __armv3_mpu_cache_flush:
751 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
755 * Various debugging routines for printing hex characters and
756 * memory, which again must be relocatable.
759 .type phexbuf,#object
761 .size phexbuf, . - phexbuf
763 phex: adr r3, phexbuf
800 2: mov r0, r11, lsl #2
808 ldr r0, [r12, r11, lsl #2]
829 .section ".stack", "w"
830 user_stack: .space 4096