drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/serial_reg.h>
  18 #include <linux/pci.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24
  25 #include <linux/dmaengine.h>
  26 #include <linux/pch_dma.h>
  27
  28 enum {
  29         PCH_UART_HANDLED_RX_INT_SHIFT,
  30         PCH_UART_HANDLED_TX_INT_SHIFT,
  31         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  33         PCH_UART_HANDLED_MS_INT_SHIFT,
  34 };
  35
  36 enum {
  37         PCH_UART_8LINE,
  38         PCH_UART_2LINE,
  39 };
  40
  41 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  42
  43 /* Set the max number of UART port
  44  * Intel EG20T PCH: 4 port
  45  * OKI SEMICONDUCTOR ML7213 IOH: 3 port
  46 */
  47 #define PCH_UART_NR     4
  48
  49 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  50 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  51 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  52                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  53 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  54                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  55 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  56
  57 #define PCH_UART_RBR            0x00
  58 #define PCH_UART_THR            0x00
  59
  60 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  61                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  62 #define PCH_UART_IER_ERBFI      0x00000001
  63 #define PCH_UART_IER_ETBEI      0x00000002
  64 #define PCH_UART_IER_ELSI       0x00000004
  65 #define PCH_UART_IER_EDSSI      0x00000008
  66
  67 #define PCH_UART_IIR_IP                 0x00000001
  68 #define PCH_UART_IIR_IID                0x00000006
  69 #define PCH_UART_IIR_MSI                0x00000000
  70 #define PCH_UART_IIR_TRI                0x00000002
  71 #define PCH_UART_IIR_RRI                0x00000004
  72 #define PCH_UART_IIR_REI                0x00000006
  73 #define PCH_UART_IIR_TOI                0x00000008
  74 #define PCH_UART_IIR_FIFO256            0x00000020
  75 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  76 #define PCH_UART_IIR_FE                 0x000000C0
  77
  78 #define PCH_UART_FCR_FIFOE              0x00000001
  79 #define PCH_UART_FCR_RFR                0x00000002
  80 #define PCH_UART_FCR_TFR                0x00000004
  81 #define PCH_UART_FCR_DMS                0x00000008
  82 #define PCH_UART_FCR_FIFO256            0x00000020
  83 #define PCH_UART_FCR_RFTL               0x000000C0
  84
  85 #define PCH_UART_FCR_RFTL1              0x00000000
  86 #define PCH_UART_FCR_RFTL64             0x00000040
  87 #define PCH_UART_FCR_RFTL128            0x00000080
  88 #define PCH_UART_FCR_RFTL224            0x000000C0
  89 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  90 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  91 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  92 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  93 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  94 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  95 #define PCH_UART_FCR_RFTL_SHIFT         6
  96
  97 #define PCH_UART_LCR_WLS        0x00000003
  98 #define PCH_UART_LCR_STB        0x00000004
  99 #define PCH_UART_LCR_PEN        0x00000008
 100 #define PCH_UART_LCR_EPS        0x00000010
 101 #define PCH_UART_LCR_SP         0x00000020
 102 #define PCH_UART_LCR_SB         0x00000040
 103 #define PCH_UART_LCR_DLAB       0x00000080
 104 #define PCH_UART_LCR_NP         0x00000000
 105 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 106 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 107 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 108 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 109                                 PCH_UART_LCR_SP)
 110
 111 #define PCH_UART_LCR_5BIT       0x00000000
 112 #define PCH_UART_LCR_6BIT       0x00000001
 113 #define PCH_UART_LCR_7BIT       0x00000002
 114 #define PCH_UART_LCR_8BIT       0x00000003
 115
 116 #define PCH_UART_MCR_DTR        0x00000001
 117 #define PCH_UART_MCR_RTS        0x00000002
 118 #define PCH_UART_MCR_OUT        0x0000000C
 119 #define PCH_UART_MCR_LOOP       0x00000010
 120 #define PCH_UART_MCR_AFE        0x00000020
 121
 122 #define PCH_UART_LSR_DR         0x00000001
 123 #define PCH_UART_LSR_ERR        (1<<7)
 124
 125 #define PCH_UART_MSR_DCTS       0x00000001
 126 #define PCH_UART_MSR_DDSR       0x00000002
 127 #define PCH_UART_MSR_TERI       0x00000004
 128 #define PCH_UART_MSR_DDCD       0x00000008
 129 #define PCH_UART_MSR_CTS        0x00000010
 130 #define PCH_UART_MSR_DSR        0x00000020
 131 #define PCH_UART_MSR_RI         0x00000040
 132 #define PCH_UART_MSR_DCD        0x00000080
 133 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 134                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 135
 136 #define PCH_UART_DLL            0x00
 137 #define PCH_UART_DLM            0x01
 138
 139 #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
 140
 141 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 142 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 143 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 144 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 145 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 146
 147 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 148 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 149 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 150 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 151 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 152 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 153 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 154 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 155 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 156 #define PCH_UART_HAL_STB1               0
 157 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 158
 159 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 160 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 161 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 162                                         PCH_UART_HAL_CLR_RX_FIFO)
 163
 164 #define PCH_UART_HAL_DMA_MODE0          0
 165 #define PCH_UART_HAL_FIFO_DIS           0
 166 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 167 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 168                                         PCH_UART_FCR_FIFO256)
 169 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 170 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 171 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 172 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 173 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 174 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 175 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 176 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 177 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 178 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 179 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 180 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 181 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 182 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 183
 184 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 185 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 186 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 187 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 188 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 189
 190 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 191 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 192 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 193 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 194 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 195
 196 #define PCI_VENDOR_ID_ROHM              0x10DB
 197
 198 struct pch_uart_buffer {
 199         unsigned char *buf;
 200         int size;
 201 };
 202
 203 struct eg20t_port {
 204         struct uart_port port;
 205         int port_type;
 206         void __iomem *membase;
 207         resource_size_t mapbase;
 208         unsigned int iobase;
 209         struct pci_dev *pdev;
 210         int fifo_size;
 211         int base_baud;
 212         int start_tx;
 213         int start_rx;
 214         int tx_empty;
 215         int int_dis_flag;
 216         int trigger;
 217         int trigger_level;
 218         struct pch_uart_buffer rxbuf;
 219         unsigned int dmsr;
 220         unsigned int fcr;
 221         unsigned int use_dma;
 222         unsigned int use_dma_flag;
 223         struct dma_async_tx_descriptor  *desc_tx;
 224         struct dma_async_tx_descriptor  *desc_rx;
 225         struct pch_dma_slave            param_tx;
 226         struct pch_dma_slave            param_rx;
 227         struct dma_chan                 *chan_tx;
 228         struct dma_chan                 *chan_rx;
 229         struct scatterlist              *sg_tx_p;
 230         int                             nent;
 231         struct scatterlist              sg_rx;
 232         int                             tx_dma_use;
 233         void                            *rx_buf_virt;
 234         dma_addr_t                      rx_buf_dma;
 235 };
 236
 237 static unsigned int default_baud = 9600;
 238 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 239 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 240 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 241 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 242
 243 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 244                                  int base_baud)
 245 {
 246         struct eg20t_port *priv = pci_get_drvdata(pdev);
 247
 248         priv->trigger_level = 1;
 249         priv->fcr = 0;
 250 }
 251
 252 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 253 {
 254         unsigned int msr = ioread8(base + UART_MSR);
 255         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 256
 257         return msr;
 258 }
 259
 260 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 261                                           unsigned int flag)
 262 {
 263         u8 ier = ioread8(priv->membase + UART_IER);
 264         ier |= flag & PCH_UART_IER_MASK;
 265         iowrite8(ier, priv->membase + UART_IER);
 266 }
 267
 268 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 269                                            unsigned int flag)
 270 {
 271         u8 ier = ioread8(priv->membase + UART_IER);
 272         ier &= ~(flag & PCH_UART_IER_MASK);
 273         iowrite8(ier, priv->membase + UART_IER);
 274 }
 275
 276 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 277                                  unsigned int parity, unsigned int bits,
 278                                  unsigned int stb)
 279 {
 280         unsigned int dll, dlm, lcr;
 281         int div;
 282
 283         div = DIV_ROUND(priv->base_baud / 16, baud);
 284         if (div < 0 || USHRT_MAX <= div) {
 285                 pr_err("Invalid Baud(div=0x%x)\n", div);
 286                 return -EINVAL;
 287         }
 288
 289         dll = (unsigned int)div & 0x00FFU;
 290         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 291
 292         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 293                 pr_err("Invalid parity(0x%x)\n", parity);
 294                 return -EINVAL;
 295         }
 296
 297         if (bits & ~PCH_UART_LCR_WLS) {
 298                 pr_err("Invalid bits(0x%x)\n", bits);
 299                 return -EINVAL;
 300         }
 301
 302         if (stb & ~PCH_UART_LCR_STB) {
 303                 pr_err("Invalid STB(0x%x)\n", stb);
 304                 return -EINVAL;
 305         }
 306
 307         lcr = parity;
 308         lcr |= bits;
 309         lcr |= stb;
 310
 311         pr_debug("%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 312                  __func__, baud, div, lcr, jiffies);
 313         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 314         iowrite8(dll, priv->membase + PCH_UART_DLL);
 315         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 316         iowrite8(lcr, priv->membase + UART_LCR);
 317
 318         return 0;
 319 }
 320
 321 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 322                                     unsigned int flag)
 323 {
 324         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 325                 pr_err("%s:Invalid flag(0x%x)\n", __func__, flag);
 326                 return -EINVAL;
 327         }
 328
 329         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 330         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 331                  priv->membase + UART_FCR);
 332         iowrite8(priv->fcr, priv->membase + UART_FCR);
 333
 334         return 0;
 335 }
 336
 337 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 338                                  unsigned int dmamode,
 339                                  unsigned int fifo_size, unsigned int trigger)
 340 {
 341         u8 fcr;
 342
 343         if (dmamode & ~PCH_UART_FCR_DMS) {
 344                 pr_err("%s:Invalid DMA Mode(0x%x)\n", __func__, dmamode);
 345                 return -EINVAL;
 346         }
 347
 348         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 349                 pr_err("%s:Invalid FIFO SIZE(0x%x)\n", __func__, fifo_size);
 350                 return -EINVAL;
 351         }
 352
 353         if (trigger & ~PCH_UART_FCR_RFTL) {
 354                 pr_err("%s:Invalid TRIGGER(0x%x)\n", __func__, trigger);
 355                 return -EINVAL;
 356         }
 357
 358         switch (priv->fifo_size) {
 359         case 256:
 360                 priv->trigger_level =
 361                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 362                 break;
 363         case 64:
 364                 priv->trigger_level =
 365                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 366                 break;
 367         case 16:
 368                 priv->trigger_level =
 369                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 370                 break;
 371         default:
 372                 priv->trigger_level =
 373                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 374                 break;
 375         }
 376         fcr =
 377             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 378         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 379         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 380                  priv->membase + UART_FCR);
 381         iowrite8(fcr, priv->membase + UART_FCR);
 382         priv->fcr = fcr;
 383
 384         return 0;
 385 }
 386
 387 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 388 {
 389         priv->dmsr = 0;
 390         return get_msr(priv, priv->membase);
 391 }
 392
 393 static void pch_uart_hal_write(struct eg20t_port *priv,
 394                               const unsigned char *buf, int tx_size)
 395 {
 396         int i;
 397         unsigned int thr;
 398
 399         for (i = 0; i < tx_size;) {
 400                 thr = buf[i++];
 401                 iowrite8(thr, priv->membase + PCH_UART_THR);
 402         }
 403 }
 404
 405 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 406                              int rx_size)
 407 {
 408         int i;
 409         u8 rbr, lsr;
 410
 411         lsr = ioread8(priv->membase + UART_LSR);
 412         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 413              i < rx_size && lsr & UART_LSR_DR;
 414              lsr = ioread8(priv->membase + UART_LSR)) {
 415                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 416                 buf[i++] = rbr;
 417         }
 418         return i;
 419 }
 420
 421 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 422 {
 423         unsigned int iir;
 424         int ret;
 425
 426         iir = ioread8(priv->membase + UART_IIR);
 427         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 428         return ret;
 429 }
 430
 431 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 432 {
 433         return ioread8(priv->membase + UART_LSR);
 434 }
 435
 436 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 437 {
 438         unsigned int lcr;
 439
 440         lcr = ioread8(priv->membase + UART_LCR);
 441         if (on)
 442                 lcr |= PCH_UART_LCR_SB;
 443         else
 444                 lcr &= ~PCH_UART_LCR_SB;
 445
 446         iowrite8(lcr, priv->membase + UART_LCR);
 447 }
 448
 449 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 450                    int size)
 451 {
 452         struct uart_port *port;
 453         struct tty_struct *tty;
 454
 455         port = &priv->port;
 456         tty = tty_port_tty_get(&port->state->port);
 457         if (!tty) {
 458                 pr_debug("%s:tty is busy now", __func__);
 459                 return -EBUSY;
 460         }
 461
 462         tty_insert_flip_string(tty, buf, size);
 463         tty_flip_buffer_push(tty);
 464         tty_kref_put(tty);
 465
 466         return 0;
 467 }
 468
 469 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 470 {
 471         int ret;
 472         struct uart_port *port = &priv->port;
 473
 474         if (port->x_char) {
 475                 pr_debug("%s:X character send %02x (%lu)\n", __func__,
 476                         port->x_char, jiffies);
 477                 buf[0] = port->x_char;
 478                 port->x_char = 0;
 479                 ret = 1;
 480         } else {
 481                 ret = 0;
 482         }
 483
 484         return ret;
 485 }
 486
 487 static int dma_push_rx(struct eg20t_port *priv, int size)
 488 {
 489         struct tty_struct *tty;
 490         int room;
 491         struct uart_port *port = &priv->port;
 492
 493         port = &priv->port;
 494         tty = tty_port_tty_get(&port->state->port);
 495         if (!tty) {
 496                 pr_debug("%s:tty is busy now", __func__);
 497                 return 0;
 498         }
 499
 500         room = tty_buffer_request_room(tty, size);
 501
 502         if (room < size)
 503                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 504                          size - room);
 505         if (!room)
 506                 return room;
 507
 508         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 509
 510         port->icount.rx += room;
 511         tty_kref_put(tty);
 512
 513         return room;
 514 }
 515
 516 static void pch_free_dma(struct uart_port *port)
 517 {
 518         struct eg20t_port *priv;
 519         priv = container_of(port, struct eg20t_port, port);
 520
 521         if (priv->chan_tx) {
 522                 dma_release_channel(priv->chan_tx);
 523                 priv->chan_tx = NULL;
 524         }
 525         if (priv->chan_rx) {
 526                 dma_release_channel(priv->chan_rx);
 527                 priv->chan_rx = NULL;
 528         }
 529         if (sg_dma_address(&priv->sg_rx))
 530                 dma_free_coherent(port->dev, port->fifosize,
 531                                   sg_virt(&priv->sg_rx),
 532                                   sg_dma_address(&priv->sg_rx));
 533
 534         return;
 535 }
 536
 537 static bool filter(struct dma_chan *chan, void *slave)
 538 {
 539         struct pch_dma_slave *param = slave;
 540
 541         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 542                                                   chan->device->dev)) {
 543                 chan->private = param;
 544                 return true;
 545         } else {
 546                 return false;
 547         }
 548 }
 549
 550 static void pch_request_dma(struct uart_port *port)
 551 {
 552         dma_cap_mask_t mask;
 553         struct dma_chan *chan;
 554         struct pci_dev *dma_dev;
 555         struct pch_dma_slave *param;
 556         struct eg20t_port *priv =
 557                                 container_of(port, struct eg20t_port, port);
 558         dma_cap_zero(mask);
 559         dma_cap_set(DMA_SLAVE, mask);
 560
 561         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 562                                                                 information */
 563         /* Set Tx DMA */
 564         param = &priv->param_tx;
 565         param->dma_dev = &dma_dev->dev;
 566         param->chan_id = priv->port.line;
 567         param->tx_reg = port->mapbase + UART_TX;
 568         chan = dma_request_channel(mask, filter, param);
 569         if (!chan) {
 570                 pr_err("%s:dma_request_channel FAILS(Tx)\n", __func__);
 571                 return;
 572         }
 573         priv->chan_tx = chan;
 574
 575         /* Set Rx DMA */
 576         param = &priv->param_rx;
 577         param->dma_dev = &dma_dev->dev;
 578         param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */
 579         param->rx_reg = port->mapbase + UART_RX;
 580         chan = dma_request_channel(mask, filter, param);
 581         if (!chan) {
 582                 pr_err("%s:dma_request_channel FAILS(Rx)\n", __func__);
 583                 dma_release_channel(priv->chan_tx);
 584                 return;
 585         }
 586
 587         /* Get Consistent memory for DMA */
 588         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 589                                     &priv->rx_buf_dma, GFP_KERNEL);
 590         priv->chan_rx = chan;
 591 }
 592
 593 static void pch_dma_rx_complete(void *arg)
 594 {
 595         struct eg20t_port *priv = arg;
 596         struct uart_port *port = &priv->port;
 597         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 598         int count;
 599
 600         if (!tty) {
 601                 pr_debug("%s:tty is busy now", __func__);
 602                 return;
 603         }
 604
 605         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 606         count = dma_push_rx(priv, priv->trigger_level);
 607         if (count)
 608                 tty_flip_buffer_push(tty);
 609         tty_kref_put(tty);
 610         async_tx_ack(priv->desc_rx);
 611         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
 612 }
 613
 614 static void pch_dma_tx_complete(void *arg)
 615 {
 616         struct eg20t_port *priv = arg;
 617         struct uart_port *port = &priv->port;
 618         struct circ_buf *xmit = &port->state->xmit;
 619         struct scatterlist *sg = priv->sg_tx_p;
 620         int i;
 621
 622         for (i = 0; i < priv->nent; i++, sg++) {
 623                 xmit->tail += sg_dma_len(sg);
 624                 port->icount.tx += sg_dma_len(sg);
 625         }
 626         xmit->tail &= UART_XMIT_SIZE - 1;
 627         async_tx_ack(priv->desc_tx);
 628         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 629         priv->tx_dma_use = 0;
 630         priv->nent = 0;
 631         kfree(priv->sg_tx_p);
 632         if (uart_circ_chars_pending(xmit))
 633                 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 634 }
 635
 636 static int pop_tx(struct eg20t_port *priv, int size)
 637 {
 638         int count = 0;
 639         struct uart_port *port = &priv->port;
 640         struct circ_buf *xmit = &port->state->xmit;
 641
 642         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 643                 goto pop_tx_end;
 644
 645         do {
 646                 int cnt_to_end =
 647                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 648                 int sz = min(size - count, cnt_to_end);
 649                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 650                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 651                 count += sz;
 652         } while (!uart_circ_empty(xmit) && count < size);
 653
 654 pop_tx_end:
 655         pr_debug("%d characters. Remained %d characters. (%lu)\n",
 656                  count, size - count, jiffies);
 657
 658         return count;
 659 }
 660
 661 static int handle_rx_to(struct eg20t_port *priv)
 662 {
 663         struct pch_uart_buffer *buf;
 664         int rx_size;
 665         int ret;
 666         if (!priv->start_rx) {
 667                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 668                 return 0;
 669         }
 670         buf = &priv->rxbuf;
 671         do {
 672                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 673                 ret = push_rx(priv, buf->buf, rx_size);
 674                 if (ret)
 675                         return 0;
 676         } while (rx_size == buf->size);
 677
 678         return PCH_UART_HANDLED_RX_INT;
 679 }
 680
 681 static int handle_rx(struct eg20t_port *priv)
 682 {
 683         return handle_rx_to(priv);
 684 }
 685
 686 static int dma_handle_rx(struct eg20t_port *priv)
 687 {
 688         struct uart_port *port = &priv->port;
 689         struct dma_async_tx_descriptor *desc;
 690         struct scatterlist *sg;
 691
 692         priv = container_of(port, struct eg20t_port, port);
 693         sg = &priv->sg_rx;
 694
 695         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 696
 697         sg_dma_len(sg) = priv->trigger_level;
 698
 699         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 700                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 701                      ~PAGE_MASK);
 702
 703         sg_dma_address(sg) = priv->rx_buf_dma;
 704
 705         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 706                         sg, 1, DMA_FROM_DEVICE,
 707                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 708
 709         if (!desc)
 710                 return 0;
 711
 712         priv->desc_rx = desc;
 713         desc->callback = pch_dma_rx_complete;
 714         desc->callback_param = priv;
 715         desc->tx_submit(desc);
 716         dma_async_issue_pending(priv->chan_rx);
 717
 718         return PCH_UART_HANDLED_RX_INT;
 719 }
 720
 721 static unsigned int handle_tx(struct eg20t_port *priv)
 722 {
 723         struct uart_port *port = &priv->port;
 724         struct circ_buf *xmit = &port->state->xmit;
 725         int fifo_size;
 726         int tx_size;
 727         int size;
 728         int tx_empty;
 729
 730         if (!priv->start_tx) {
 731                 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
 732                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 733                 priv->tx_empty = 1;
 734                 return 0;
 735         }
 736
 737         fifo_size = max(priv->fifo_size, 1);
 738         tx_empty = 1;
 739         if (pop_tx_x(priv, xmit->buf)) {
 740                 pch_uart_hal_write(priv, xmit->buf, 1);
 741                 port->icount.tx++;
 742                 tx_empty = 0;
 743                 fifo_size--;
 744         }
 745         size = min(xmit->head - xmit->tail, fifo_size);
 746         if (size < 0)
 747                 size = fifo_size;
 748
 749         tx_size = pop_tx(priv, size);
 750         if (tx_size > 0) {
 751                 port->icount.tx += tx_size;
 752                 tx_empty = 0;
 753         }
 754
 755         priv->tx_empty = tx_empty;
 756
 757         if (tx_empty) {
 758                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 759                 uart_write_wakeup(port);
 760         }
 761
 762         return PCH_UART_HANDLED_TX_INT;
 763 }
 764
 765 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 766 {
 767         struct uart_port *port = &priv->port;
 768         struct circ_buf *xmit = &port->state->xmit;
 769         struct scatterlist *sg;
 770         int nent;
 771         int fifo_size;
 772         int tx_empty;
 773         struct dma_async_tx_descriptor *desc;
 774         int num;
 775         int i;
 776         int bytes;
 777         int size;
 778         int rem;
 779
 780         if (!priv->start_tx) {
 781                 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
 782                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 783                 priv->tx_empty = 1;
 784                 return 0;
 785         }
 786
 787         fifo_size = max(priv->fifo_size, 1);
 788         tx_empty = 1;
 789         if (pop_tx_x(priv, xmit->buf)) {
 790                 pch_uart_hal_write(priv, xmit->buf, 1);
 791                 port->icount.tx++;
 792                 tx_empty = 0;
 793                 fifo_size--;
 794         }
 795
 796         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 797                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 798                              xmit->tail, UART_XMIT_SIZE));
 799         if (!bytes) {
 800                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 801                 uart_write_wakeup(port);
 802                 return 0;
 803         }
 804
 805         if (bytes > fifo_size) {
 806                 num = bytes / fifo_size + 1;
 807                 size = fifo_size;
 808                 rem = bytes % fifo_size;
 809         } else {
 810                 num = 1;
 811                 size = bytes;
 812                 rem = bytes;
 813         }
 814
 815         priv->tx_dma_use = 1;
 816
 817         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 818
 819         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 820         sg = priv->sg_tx_p;
 821
 822         for (i = 0; i < num; i++, sg++) {
 823                 if (i == (num - 1))
 824                         sg_set_page(sg, virt_to_page(xmit->buf),
 825                                     rem, fifo_size * i);
 826                 else
 827                         sg_set_page(sg, virt_to_page(xmit->buf),
 828                                     size, fifo_size * i);
 829         }
 830
 831         sg = priv->sg_tx_p;
 832         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 833         if (!nent) {
 834                 pr_err("%s:dma_map_sg Failed\n", __func__);
 835                 return 0;
 836         }
 837         priv->nent = nent;
 838
 839         for (i = 0; i < nent; i++, sg++) {
 840                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 841                               fifo_size * i;
 842                 sg_dma_address(sg) = (sg_dma_address(sg) &
 843                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 844                 if (i == (nent - 1))
 845                         sg_dma_len(sg) = rem;
 846                 else
 847                         sg_dma_len(sg) = size;
 848         }
 849
 850         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 851                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 852                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 853         if (!desc) {
 854                 pr_err("%s:device_prep_slave_sg Failed\n", __func__);
 855                 return 0;
 856         }
 857         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 858         priv->desc_tx = desc;
 859         desc->callback = pch_dma_tx_complete;
 860         desc->callback_param = priv;
 861
 862         desc->tx_submit(desc);
 863
 864         dma_async_issue_pending(priv->chan_tx);
 865
 866         return PCH_UART_HANDLED_TX_INT;
 867 }
 868
 869 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 870 {
 871         u8 fcr = ioread8(priv->membase + UART_FCR);
 872
 873         /* Reset FIFO */
 874         fcr |= UART_FCR_CLEAR_RCVR;
 875         iowrite8(fcr, priv->membase + UART_FCR);
 876
 877         if (lsr & PCH_UART_LSR_ERR)
 878                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 879
 880         if (lsr & UART_LSR_FE)
 881                 dev_err(&priv->pdev->dev, "Framing Error\n");
 882
 883         if (lsr & UART_LSR_PE)
 884                 dev_err(&priv->pdev->dev, "Parity Error\n");
 885
 886         if (lsr & UART_LSR_OE)
 887                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 888 }
 889
 890 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 891 {
 892         struct eg20t_port *priv = dev_id;
 893         unsigned int handled;
 894         u8 lsr;
 895         int ret = 0;
 896         unsigned int iid;
 897         unsigned long flags;
 898
 899         spin_lock_irqsave(&priv->port.lock, flags);
 900         handled = 0;
 901         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 902                 switch (iid) {
 903                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 904                         lsr = pch_uart_hal_get_line_status(priv);
 905                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 906                                                 UART_LSR_PE | UART_LSR_OE)) {
 907                                 pch_uart_err_ir(priv, lsr);
 908                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 909                         }
 910                         break;
 911                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 912                         if (priv->use_dma) {
 913                                 pch_uart_hal_disable_interrupt(priv,
 914                                                         PCH_UART_HAL_RX_INT);
 915                                 ret = dma_handle_rx(priv);
 916                                 if (!ret)
 917                                         pch_uart_hal_enable_interrupt(priv,
 918                                                         PCH_UART_HAL_RX_INT);
 919                         } else {
 920                                 ret = handle_rx(priv);
 921                         }
 922                         break;
 923                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 924                                                    (FIFO Timeout) */
 925                         ret = handle_rx_to(priv);
 926                         break;
 927                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
 928                                                    Empty */
 929                         if (priv->use_dma)
 930                                 ret = dma_handle_tx(priv);
 931                         else
 932                                 ret = handle_tx(priv);
 933                         break;
 934                 case PCH_UART_IID_MS:   /* Modem Status */
 935                         ret = PCH_UART_HANDLED_MS_INT;
 936                         break;
 937                 default:        /* Never junp to this label */
 938                         pr_err("%s:iid=%d (%lu)\n", __func__, iid, jiffies);
 939                         ret = -1;
 940                         break;
 941                 }
 942                 handled |= (unsigned int)ret;
 943         }
 944         if (handled == 0 && iid <= 1) {
 945                 if (priv->int_dis_flag)
 946                         priv->int_dis_flag = 0;
 947         }
 948
 949         spin_unlock_irqrestore(&priv->port.lock, flags);
 950         return IRQ_RETVAL(handled);
 951 }
 952
 953 /* This function tests whether the transmitter fifo and shifter for the port
 954                                                 described by 'port' is empty. */
 955 static unsigned int pch_uart_tx_empty(struct uart_port *port)
 956 {
 957         struct eg20t_port *priv;
 958         int ret;
 959         priv = container_of(port, struct eg20t_port, port);
 960         if (priv->tx_empty)
 961                 ret = TIOCSER_TEMT;
 962         else
 963                 ret = 0;
 964
 965         return ret;
 966 }
 967
 968 /* Returns the current state of modem control inputs. */
 969 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
 970 {
 971         struct eg20t_port *priv;
 972         u8 modem;
 973         unsigned int ret = 0;
 974
 975         priv = container_of(port, struct eg20t_port, port);
 976         modem = pch_uart_hal_get_modem(priv);
 977
 978         if (modem & UART_MSR_DCD)
 979                 ret |= TIOCM_CAR;
 980
 981         if (modem & UART_MSR_RI)
 982                 ret |= TIOCM_RNG;
 983
 984         if (modem & UART_MSR_DSR)
 985                 ret |= TIOCM_DSR;
 986
 987         if (modem & UART_MSR_CTS)
 988                 ret |= TIOCM_CTS;
 989
 990         return ret;
 991 }
 992
 993 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 994 {
 995         u32 mcr = 0;
 996         unsigned int dat;
 997         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
 998
 999         if (mctrl & TIOCM_DTR)
1000                 mcr |= UART_MCR_DTR;
1001         if (mctrl & TIOCM_RTS)
1002                 mcr |= UART_MCR_RTS;
1003         if (mctrl & TIOCM_LOOP)
1004                 mcr |= UART_MCR_LOOP;
1005
1006         if (mctrl) {
1007                 dat = pch_uart_get_mctrl(port);
1008                 dat |= mcr;
1009                 iowrite8(dat, priv->membase + UART_MCR);
1010         }
1011 }
1012
1013 static void pch_uart_stop_tx(struct uart_port *port)
1014 {
1015         struct eg20t_port *priv;
1016         priv = container_of(port, struct eg20t_port, port);
1017         priv->start_tx = 0;
1018         priv->tx_dma_use = 0;
1019 }
1020
1021 static void pch_uart_start_tx(struct uart_port *port)
1022 {
1023         struct eg20t_port *priv;
1024
1025         priv = container_of(port, struct eg20t_port, port);
1026
1027         if (priv->use_dma)
1028                 if (priv->tx_dma_use)
1029                         return;
1030
1031         priv->start_tx = 1;
1032         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1033 }
1034
1035 static void pch_uart_stop_rx(struct uart_port *port)
1036 {
1037         struct eg20t_port *priv;
1038         priv = container_of(port, struct eg20t_port, port);
1039         priv->start_rx = 0;
1040         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1041         priv->int_dis_flag = 1;
1042 }
1043
1044 /* Enable the modem status interrupts. */
1045 static void pch_uart_enable_ms(struct uart_port *port)
1046 {
1047         struct eg20t_port *priv;
1048         priv = container_of(port, struct eg20t_port, port);
1049         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1050 }
1051
1052 /* Control the transmission of a break signal. */
1053 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1054 {
1055         struct eg20t_port *priv;
1056         unsigned long flags;
1057
1058         priv = container_of(port, struct eg20t_port, port);
1059         spin_lock_irqsave(&port->lock, flags);
1060         pch_uart_hal_set_break(priv, ctl);
1061         spin_unlock_irqrestore(&port->lock, flags);
1062 }
1063
1064 /* Grab any interrupt resources and initialise any low level driver state. */
1065 static int pch_uart_startup(struct uart_port *port)
1066 {
1067         struct eg20t_port *priv;
1068         int ret;
1069         int fifo_size;
1070         int trigger_level;
1071
1072         priv = container_of(port, struct eg20t_port, port);
1073         priv->tx_empty = 1;
1074         port->uartclk = priv->base_baud;
1075         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1076         ret = pch_uart_hal_set_line(priv, default_baud,
1077                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1078                               PCH_UART_HAL_STB1);
1079         if (ret)
1080                 return ret;
1081
1082         switch (priv->fifo_size) {
1083         case 256:
1084                 fifo_size = PCH_UART_HAL_FIFO256;
1085                 break;
1086         case 64:
1087                 fifo_size = PCH_UART_HAL_FIFO64;
1088                 break;
1089         case 16:
1090                 fifo_size = PCH_UART_HAL_FIFO16;
1091         case 1:
1092         default:
1093                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1094                 break;
1095         }
1096
1097         switch (priv->trigger) {
1098         case PCH_UART_HAL_TRIGGER1:
1099                 trigger_level = 1;
1100                 break;
1101         case PCH_UART_HAL_TRIGGER_L:
1102                 trigger_level = priv->fifo_size / 4;
1103                 break;
1104         case PCH_UART_HAL_TRIGGER_M:
1105                 trigger_level = priv->fifo_size / 2;
1106                 break;
1107         case PCH_UART_HAL_TRIGGER_H:
1108         default:
1109                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1110                 break;
1111         }
1112
1113         priv->trigger_level = trigger_level;
1114         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1115                                     fifo_size, priv->trigger);
1116         if (ret < 0)
1117                 return ret;
1118
1119         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1120                         KBUILD_MODNAME, priv);
1121         if (ret < 0)
1122                 return ret;
1123
1124         if (priv->use_dma)
1125                 pch_request_dma(port);
1126
1127         priv->start_rx = 1;
1128         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1129         uart_update_timeout(port, CS8, default_baud);
1130
1131         return 0;
1132 }
1133
1134 static void pch_uart_shutdown(struct uart_port *port)
1135 {
1136         struct eg20t_port *priv;
1137         int ret;
1138
1139         priv = container_of(port, struct eg20t_port, port);
1140         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1141         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1142         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1143                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1144         if (ret)
1145                 pr_err("pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1146
1147         if (priv->use_dma_flag)
1148                 pch_free_dma(port);
1149
1150         free_irq(priv->port.irq, priv);
1151 }
1152
1153 /* Change the port parameters, including word length, parity, stop
1154  *bits.  Update read_status_mask and ignore_status_mask to indicate
1155  *the types of events we are interested in receiving.  */
1156 static void pch_uart_set_termios(struct uart_port *port,
1157                                  struct ktermios *termios, struct ktermios *old)
1158 {
1159         int baud;
1160         int rtn;
1161         unsigned int parity, bits, stb;
1162         struct eg20t_port *priv;
1163         unsigned long flags;
1164
1165         priv = container_of(port, struct eg20t_port, port);
1166         switch (termios->c_cflag & CSIZE) {
1167         case CS5:
1168                 bits = PCH_UART_HAL_5BIT;
1169                 break;
1170         case CS6:
1171                 bits = PCH_UART_HAL_6BIT;
1172                 break;
1173         case CS7:
1174                 bits = PCH_UART_HAL_7BIT;
1175                 break;
1176         default:                /* CS8 */
1177                 bits = PCH_UART_HAL_8BIT;
1178                 break;
1179         }
1180         if (termios->c_cflag & CSTOPB)
1181                 stb = PCH_UART_HAL_STB2;
1182         else
1183                 stb = PCH_UART_HAL_STB1;
1184
1185         if (termios->c_cflag & PARENB) {
1186                 if (!(termios->c_cflag & PARODD))
1187                         parity = PCH_UART_HAL_PARITY_ODD;
1188                 else
1189                         parity = PCH_UART_HAL_PARITY_EVEN;
1190
1191         } else {
1192                 parity = PCH_UART_HAL_PARITY_NONE;
1193         }
1194         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1195
1196         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1197
1198         spin_lock_irqsave(&port->lock, flags);
1199
1200         uart_update_timeout(port, termios->c_cflag, baud);
1201         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1202         if (rtn)
1203                 goto out;
1204
1205         /* Don't rewrite B0 */
1206         if (tty_termios_baud_rate(termios))
1207                 tty_termios_encode_baud_rate(termios, baud, baud);
1208
1209 out:
1210         spin_unlock_irqrestore(&port->lock, flags);
1211 }
1212
1213 static const char *pch_uart_type(struct uart_port *port)
1214 {
1215         return KBUILD_MODNAME;
1216 }
1217
1218 static void pch_uart_release_port(struct uart_port *port)
1219 {
1220         struct eg20t_port *priv;
1221
1222         priv = container_of(port, struct eg20t_port, port);
1223         pci_iounmap(priv->pdev, priv->membase);
1224         pci_release_regions(priv->pdev);
1225 }
1226
1227 static int pch_uart_request_port(struct uart_port *port)
1228 {
1229         struct eg20t_port *priv;
1230         int ret;
1231         void __iomem *membase;
1232
1233         priv = container_of(port, struct eg20t_port, port);
1234         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1235         if (ret < 0)
1236                 return -EBUSY;
1237
1238         membase = pci_iomap(priv->pdev, 1, 0);
1239         if (!membase) {
1240                 pci_release_regions(priv->pdev);
1241                 return -EBUSY;
1242         }
1243         priv->membase = port->membase = membase;
1244
1245         return 0;
1246 }
1247
1248 static void pch_uart_config_port(struct uart_port *port, int type)
1249 {
1250         struct eg20t_port *priv;
1251
1252         priv = container_of(port, struct eg20t_port, port);
1253         if (type & UART_CONFIG_TYPE) {
1254                 port->type = priv->port_type;
1255                 pch_uart_request_port(port);
1256         }
1257 }
1258
1259 static int pch_uart_verify_port(struct uart_port *port,
1260                                 struct serial_struct *serinfo)
1261 {
1262         struct eg20t_port *priv;
1263
1264         priv = container_of(port, struct eg20t_port, port);
1265         if (serinfo->flags & UPF_LOW_LATENCY) {
1266                 pr_info("PCH UART : Use PIO Mode (without DMA)\n");
1267                 priv->use_dma = 0;
1268                 serinfo->flags &= ~UPF_LOW_LATENCY;
1269         } else {
1270 #ifndef CONFIG_PCH_DMA
1271                 pr_err("%s : PCH DMA is not Loaded.\n", __func__);
1272                 return -EOPNOTSUPP;
1273 #endif
1274                 priv->use_dma = 1;
1275                 priv->use_dma_flag = 1;
1276                 pr_info("PCH UART : Use DMA Mode\n");
1277         }
1278
1279         return 0;
1280 }
1281
1282 static struct uart_ops pch_uart_ops = {
1283         .tx_empty = pch_uart_tx_empty,
1284         .set_mctrl = pch_uart_set_mctrl,
1285         .get_mctrl = pch_uart_get_mctrl,
1286         .stop_tx = pch_uart_stop_tx,
1287         .start_tx = pch_uart_start_tx,
1288         .stop_rx = pch_uart_stop_rx,
1289         .enable_ms = pch_uart_enable_ms,
1290         .break_ctl = pch_uart_break_ctl,
1291         .startup = pch_uart_startup,
1292         .shutdown = pch_uart_shutdown,
1293         .set_termios = pch_uart_set_termios,
1294 /*      .pm             = pch_uart_pm,          Not supported yet */
1295 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1296         .type = pch_uart_type,
1297         .release_port = pch_uart_release_port,
1298         .request_port = pch_uart_request_port,
1299         .config_port = pch_uart_config_port,
1300         .verify_port = pch_uart_verify_port
1301 };
1302
1303 static struct uart_driver pch_uart_driver = {
1304         .owner = THIS_MODULE,
1305         .driver_name = KBUILD_MODNAME,
1306         .dev_name = PCH_UART_DRIVER_DEVICE,
1307         .major = 0,
1308         .minor = 0,
1309         .nr = PCH_UART_NR,
1310 };
1311
1312 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1313                                              const struct pci_device_id *id)
1314 {
1315         struct eg20t_port *priv;
1316         int ret;
1317         unsigned int iobase;
1318         unsigned int mapbase;
1319         unsigned char *rxbuf;
1320         int fifosize, base_baud;
1321         static int num;
1322         int port_type = id->driver_data;
1323
1324         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1325         if (priv == NULL)
1326                 goto init_port_alloc_err;
1327
1328         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1329         if (!rxbuf)
1330                 goto init_port_free_txbuf;
1331
1332         switch (port_type) {
1333         case PORT_UNKNOWN:
1334                 fifosize = 256; /* EG20T/ML7213: UART0 */
1335                 base_baud = 1843200; /* 1.8432MHz */
1336                 break;
1337         case PORT_8250:
1338                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1339                 base_baud = 1843200; /* 1.8432MHz */
1340                 break;
1341         default:
1342                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1343                 goto init_port_hal_free;
1344         }
1345
1346         iobase = pci_resource_start(pdev, 0);
1347         mapbase = pci_resource_start(pdev, 1);
1348         priv->mapbase = mapbase;
1349         priv->iobase = iobase;
1350         priv->pdev = pdev;
1351         priv->tx_empty = 1;
1352         priv->rxbuf.buf = rxbuf;
1353         priv->rxbuf.size = PAGE_SIZE;
1354
1355         priv->fifo_size = fifosize;
1356         priv->base_baud = base_baud;
1357         priv->port_type = PORT_MAX_8250 + port_type + 1;
1358         priv->port.dev = &pdev->dev;
1359         priv->port.iobase = iobase;
1360         priv->port.membase = NULL;
1361         priv->port.mapbase = mapbase;
1362         priv->port.irq = pdev->irq;
1363         priv->port.iotype = UPIO_PORT;
1364         priv->port.ops = &pch_uart_ops;
1365         priv->port.flags = UPF_BOOT_AUTOCONF;
1366         priv->port.fifosize = fifosize;
1367         priv->port.line = num++;
1368         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1369
1370         spin_lock_init(&priv->port.lock);
1371
1372         pci_set_drvdata(pdev, priv);
1373         pch_uart_hal_request(pdev, fifosize, base_baud);
1374
1375         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1376         if (ret < 0)
1377                 goto init_port_hal_free;
1378
1379         return priv;
1380
1381 init_port_hal_free:
1382         free_page((unsigned long)rxbuf);
1383 init_port_free_txbuf:
1384         kfree(priv);
1385 init_port_alloc_err:
1386
1387         return NULL;
1388 }
1389
1390 static void pch_uart_exit_port(struct eg20t_port *priv)
1391 {
1392         uart_remove_one_port(&pch_uart_driver, &priv->port);
1393         pci_set_drvdata(priv->pdev, NULL);
1394         free_page((unsigned long)priv->rxbuf.buf);
1395 }
1396
1397 static void pch_uart_pci_remove(struct pci_dev *pdev)
1398 {
1399         struct eg20t_port *priv;
1400
1401         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1402         pch_uart_exit_port(priv);
1403         pci_disable_device(pdev);
1404         kfree(priv);
1405         return;
1406 }
1407 #ifdef CONFIG_PM
1408 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1409 {
1410         struct eg20t_port *priv = pci_get_drvdata(pdev);
1411
1412         uart_suspend_port(&pch_uart_driver, &priv->port);
1413
1414         pci_save_state(pdev);
1415         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1416         return 0;
1417 }
1418
1419 static int pch_uart_pci_resume(struct pci_dev *pdev)
1420 {
1421         struct eg20t_port *priv = pci_get_drvdata(pdev);
1422         int ret;
1423
1424         pci_set_power_state(pdev, PCI_D0);
1425         pci_restore_state(pdev);
1426
1427         ret = pci_enable_device(pdev);
1428         if (ret) {
1429                 dev_err(&pdev->dev,
1430                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1431                 return ret;
1432         }
1433
1434         uart_resume_port(&pch_uart_driver, &priv->port);
1435
1436         return 0;
1437 }
1438 #else
1439 #define pch_uart_pci_suspend NULL
1440 #define pch_uart_pci_resume NULL
1441 #endif
1442
1443 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1444         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1445          .driver_data = PCH_UART_8LINE},
1446         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1447          .driver_data = PCH_UART_2LINE},
1448         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1449          .driver_data = PCH_UART_2LINE},
1450         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1451          .driver_data = PCH_UART_2LINE},
1452         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1453          .driver_data = PCH_UART_8LINE},
1454         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1455          .driver_data = PCH_UART_2LINE},
1456         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1457          .driver_data = PCH_UART_2LINE},
1458         {0,},
1459 };
1460
1461 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1462                                         const struct pci_device_id *id)
1463 {
1464         int ret;
1465         struct eg20t_port *priv;
1466
1467         ret = pci_enable_device(pdev);
1468         if (ret < 0)
1469                 goto probe_error;
1470
1471         priv = pch_uart_init_port(pdev, id);
1472         if (!priv) {
1473                 ret = -EBUSY;
1474                 goto probe_disable_device;
1475         }
1476         pci_set_drvdata(pdev, priv);
1477
1478         return ret;
1479
1480 probe_disable_device:
1481         pci_disable_device(pdev);
1482 probe_error:
1483         return ret;
1484 }
1485
1486 static struct pci_driver pch_uart_pci_driver = {
1487         .name = "pch_uart",
1488         .id_table = pch_uart_pci_id,
1489         .probe = pch_uart_pci_probe,
1490         .remove = __devexit_p(pch_uart_pci_remove),
1491         .suspend = pch_uart_pci_suspend,
1492         .resume = pch_uart_pci_resume,
1493 };
1494
1495 static int __init pch_uart_module_init(void)
1496 {
1497         int ret;
1498
1499         /* register as UART driver */
1500         ret = uart_register_driver(&pch_uart_driver);
1501         if (ret < 0)
1502                 return ret;
1503
1504         /* register as PCI driver */
1505         ret = pci_register_driver(&pch_uart_pci_driver);
1506         if (ret < 0)
1507                 uart_unregister_driver(&pch_uart_driver);
1508
1509         return ret;
1510 }
1511 module_init(pch_uart_module_init);
1512
1513 static void __exit pch_uart_module_exit(void)
1514 {
1515         pci_unregister_driver(&pch_uart_pci_driver);
1516         uart_unregister_driver(&pch_uart_driver);
1517 }
1518 module_exit(pch_uart_module_exit);
1519
1520 MODULE_LICENSE("GPL v2");
1521 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1522 module_param(default_baud, uint, S_IRUGO);