drivers/usb/gadget/pch_udc.c

   1 /*
   2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/list.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/usb/ch9.h>
  26 #include <linux/usb/gadget.h>
  27
  28 /* Address offset of Registers */
  29 #define UDC_EP_REG_SHIFT        0x20    /* Offset to next EP */
  30
  31 #define UDC_EPCTL_ADDR          0x00    /* Endpoint control */
  32 #define UDC_EPSTS_ADDR          0x04    /* Endpoint status */
  33 #define UDC_BUFIN_FRAMENUM_ADDR 0x08    /* buffer size in / frame number out */
  34 #define UDC_BUFOUT_MAXPKT_ADDR  0x0C    /* buffer size out / maxpkt in */
  35 #define UDC_SUBPTR_ADDR         0x10    /* setup buffer pointer */
  36 #define UDC_DESPTR_ADDR         0x14    /* Data descriptor pointer */
  37 #define UDC_CONFIRM_ADDR        0x18    /* Write/Read confirmation */
  38
  39 #define UDC_DEVCFG_ADDR         0x400   /* Device configuration */
  40 #define UDC_DEVCTL_ADDR         0x404   /* Device control */
  41 #define UDC_DEVSTS_ADDR         0x408   /* Device status */
  42 #define UDC_DEVIRQSTS_ADDR      0x40C   /* Device irq status */
  43 #define UDC_DEVIRQMSK_ADDR      0x410   /* Device irq mask */
  44 #define UDC_EPIRQSTS_ADDR       0x414   /* Endpoint irq status */
  45 #define UDC_EPIRQMSK_ADDR       0x418   /* Endpoint irq mask */
  46 #define UDC_DEVLPM_ADDR         0x41C   /* LPM control / status */
  47 #define UDC_CSR_BUSY_ADDR       0x4f0   /* UDC_CSR_BUSY Status register */
  48 #define UDC_SRST_ADDR           0x4fc   /* SOFT RESET register */
  49 #define UDC_CSR_ADDR            0x500   /* USB_DEVICE endpoint register */
  50
  51 /* Endpoint control register */
  52 /* Bit position */
  53 #define UDC_EPCTL_MRXFLUSH              (1 << 12)
  54 #define UDC_EPCTL_RRDY                  (1 << 9)
  55 #define UDC_EPCTL_CNAK                  (1 << 8)
  56 #define UDC_EPCTL_SNAK                  (1 << 7)
  57 #define UDC_EPCTL_NAK                   (1 << 6)
  58 #define UDC_EPCTL_P                     (1 << 3)
  59 #define UDC_EPCTL_F                     (1 << 1)
  60 #define UDC_EPCTL_S                     (1 << 0)
  61 #define UDC_EPCTL_ET_SHIFT              4
  62 /* Mask patern */
  63 #define UDC_EPCTL_ET_MASK               0x00000030
  64 /* Value for ET field */
  65 #define UDC_EPCTL_ET_CONTROL            0
  66 #define UDC_EPCTL_ET_ISO                1
  67 #define UDC_EPCTL_ET_BULK               2
  68 #define UDC_EPCTL_ET_INTERRUPT          3
  69
  70 /* Endpoint status register */
  71 /* Bit position */
  72 #define UDC_EPSTS_XFERDONE              (1 << 27)
  73 #define UDC_EPSTS_RSS                   (1 << 26)
  74 #define UDC_EPSTS_RCS                   (1 << 25)
  75 #define UDC_EPSTS_TXEMPTY               (1 << 24)
  76 #define UDC_EPSTS_TDC                   (1 << 10)
  77 #define UDC_EPSTS_HE                    (1 << 9)
  78 #define UDC_EPSTS_MRXFIFO_EMP           (1 << 8)
  79 #define UDC_EPSTS_BNA                   (1 << 7)
  80 #define UDC_EPSTS_IN                    (1 << 6)
  81 #define UDC_EPSTS_OUT_SHIFT             4
  82 /* Mask patern */
  83 #define UDC_EPSTS_OUT_MASK              0x00000030
  84 #define UDC_EPSTS_ALL_CLR_MASK          0x1F0006F0
  85 /* Value for OUT field */
  86 #define UDC_EPSTS_OUT_SETUP             2
  87 #define UDC_EPSTS_OUT_DATA              1
  88
  89 /* Device configuration register */
  90 /* Bit position */
  91 #define UDC_DEVCFG_CSR_PRG              (1 << 17)
  92 #define UDC_DEVCFG_SP                   (1 << 3)
  93 /* SPD Valee */
  94 #define UDC_DEVCFG_SPD_HS               0x0
  95 #define UDC_DEVCFG_SPD_FS               0x1
  96 #define UDC_DEVCFG_SPD_LS               0x2
  97
  98 /* Device control register */
  99 /* Bit position */
 100 #define UDC_DEVCTL_THLEN_SHIFT          24
 101 #define UDC_DEVCTL_BRLEN_SHIFT          16
 102 #define UDC_DEVCTL_CSR_DONE             (1 << 13)
 103 #define UDC_DEVCTL_SD                   (1 << 10)
 104 #define UDC_DEVCTL_MODE                 (1 << 9)
 105 #define UDC_DEVCTL_BREN                 (1 << 8)
 106 #define UDC_DEVCTL_THE                  (1 << 7)
 107 #define UDC_DEVCTL_DU                   (1 << 4)
 108 #define UDC_DEVCTL_TDE                  (1 << 3)
 109 #define UDC_DEVCTL_RDE                  (1 << 2)
 110 #define UDC_DEVCTL_RES                  (1 << 0)
 111
 112 /* Device status register */
 113 /* Bit position */
 114 #define UDC_DEVSTS_TS_SHIFT             18
 115 #define UDC_DEVSTS_ENUM_SPEED_SHIFT     13
 116 #define UDC_DEVSTS_ALT_SHIFT            8
 117 #define UDC_DEVSTS_INTF_SHIFT           4
 118 #define UDC_DEVSTS_CFG_SHIFT            0
 119 /* Mask patern */
 120 #define UDC_DEVSTS_TS_MASK              0xfffc0000
 121 #define UDC_DEVSTS_ENUM_SPEED_MASK      0x00006000
 122 #define UDC_DEVSTS_ALT_MASK             0x00000f00
 123 #define UDC_DEVSTS_INTF_MASK            0x000000f0
 124 #define UDC_DEVSTS_CFG_MASK             0x0000000f
 125 /* value for maximum speed for SPEED field */
 126 #define UDC_DEVSTS_ENUM_SPEED_FULL      1
 127 #define UDC_DEVSTS_ENUM_SPEED_HIGH      0
 128 #define UDC_DEVSTS_ENUM_SPEED_LOW       2
 129 #define UDC_DEVSTS_ENUM_SPEED_FULLX     3
 130
 131 /* Device irq register */
 132 /* Bit position */
 133 #define UDC_DEVINT_RWKP                 (1 << 7)
 134 #define UDC_DEVINT_ENUM                 (1 << 6)
 135 #define UDC_DEVINT_SOF                  (1 << 5)
 136 #define UDC_DEVINT_US                   (1 << 4)
 137 #define UDC_DEVINT_UR                   (1 << 3)
 138 #define UDC_DEVINT_ES                   (1 << 2)
 139 #define UDC_DEVINT_SI                   (1 << 1)
 140 #define UDC_DEVINT_SC                   (1 << 0)
 141 /* Mask patern */
 142 #define UDC_DEVINT_MSK                  0x7f
 143
 144 /* Endpoint irq register */
 145 /* Bit position */
 146 #define UDC_EPINT_IN_SHIFT              0
 147 #define UDC_EPINT_OUT_SHIFT             16
 148 #define UDC_EPINT_IN_EP0                (1 << 0)
 149 #define UDC_EPINT_OUT_EP0               (1 << 16)
 150 /* Mask patern */
 151 #define UDC_EPINT_MSK_DISABLE_ALL       0xffffffff
 152
 153 /* UDC_CSR_BUSY Status register */
 154 /* Bit position */
 155 #define UDC_CSR_BUSY                    (1 << 0)
 156
 157 /* SOFT RESET register */
 158 /* Bit position */
 159 #define UDC_PSRST                       (1 << 1)
 160 #define UDC_SRST                        (1 << 0)
 161
 162 /* USB_DEVICE endpoint register */
 163 /* Bit position */
 164 #define UDC_CSR_NE_NUM_SHIFT            0
 165 #define UDC_CSR_NE_DIR_SHIFT            4
 166 #define UDC_CSR_NE_TYPE_SHIFT           5
 167 #define UDC_CSR_NE_CFG_SHIFT            7
 168 #define UDC_CSR_NE_INTF_SHIFT           11
 169 #define UDC_CSR_NE_ALT_SHIFT            15
 170 #define UDC_CSR_NE_MAX_PKT_SHIFT        19
 171 /* Mask patern */
 172 #define UDC_CSR_NE_NUM_MASK             0x0000000f
 173 #define UDC_CSR_NE_DIR_MASK             0x00000010
 174 #define UDC_CSR_NE_TYPE_MASK            0x00000060
 175 #define UDC_CSR_NE_CFG_MASK             0x00000780
 176 #define UDC_CSR_NE_INTF_MASK            0x00007800
 177 #define UDC_CSR_NE_ALT_MASK             0x00078000
 178 #define UDC_CSR_NE_MAX_PKT_MASK         0x3ff80000
 179
 180 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
 181 #define PCH_UDC_EPINT(in, num)\
 182                 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
 183
 184 /* Index of endpoint */
 185 #define UDC_EP0IN_IDX           0
 186 #define UDC_EP0OUT_IDX          1
 187 #define UDC_EPIN_IDX(ep)        (ep * 2)
 188 #define UDC_EPOUT_IDX(ep)       (ep * 2 + 1)
 189 #define PCH_UDC_EP0             0
 190 #define PCH_UDC_EP1             1
 191 #define PCH_UDC_EP2             2
 192 #define PCH_UDC_EP3             3
 193
 194 /* Number of endpoint */
 195 #define PCH_UDC_EP_NUM          32      /* Total number of EPs (16 IN,16 OUT) */
 196 #define PCH_UDC_USED_EP_NUM     4       /* EP number of EP's really used */
 197 /* Length Value */
 198 #define PCH_UDC_BRLEN           0x0F    /* Burst length */
 199 #define PCH_UDC_THLEN           0x1F    /* Threshold length */
 200 /* Value of EP Buffer Size */
 201 #define UDC_EP0IN_BUFF_SIZE     16
 202 #define UDC_EPIN_BUFF_SIZE      256
 203 #define UDC_EP0OUT_BUFF_SIZE    16
 204 #define UDC_EPOUT_BUFF_SIZE     256
 205 /* Value of EP maximum packet size */
 206 #define UDC_EP0IN_MAX_PKT_SIZE  64
 207 #define UDC_EP0OUT_MAX_PKT_SIZE 64
 208 #define UDC_BULK_MAX_PKT_SIZE   512
 209
 210 /* DMA */
 211 #define DMA_DIR_RX              1       /* DMA for data receive */
 212 #define DMA_DIR_TX              2       /* DMA for data transmit */
 213 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
 214 #define UDC_DMA_MAXPACKET       65536   /* maximum packet size for DMA */
 215
 216 /**
 217  * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
 218  *                                for data
 219  * @status:             Status quadlet
 220  * @reserved:           Reserved
 221  * @dataptr:            Buffer descriptor
 222  * @next:               Next descriptor
 223  */
 224 struct pch_udc_data_dma_desc {
 225         u32 status;
 226         u32 reserved;
 227         u32 dataptr;
 228         u32 next;
 229 };
 230
 231 /**
 232  * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
 233  *                               for control data
 234  * @status:     Status
 235  * @reserved:   Reserved
 236  * @data12:     First setup word
 237  * @data34:     Second setup word
 238  */
 239 struct pch_udc_stp_dma_desc {
 240         u32 status;
 241         u32 reserved;
 242         struct usb_ctrlrequest request;
 243 } __attribute((packed));
 244
 245 /* DMA status definitions */
 246 /* Buffer status */
 247 #define PCH_UDC_BUFF_STS        0xC0000000
 248 #define PCH_UDC_BS_HST_RDY      0x00000000
 249 #define PCH_UDC_BS_DMA_BSY      0x40000000
 250 #define PCH_UDC_BS_DMA_DONE     0x80000000
 251 #define PCH_UDC_BS_HST_BSY      0xC0000000
 252 /*  Rx/Tx Status */
 253 #define PCH_UDC_RXTX_STS        0x30000000
 254 #define PCH_UDC_RTS_SUCC        0x00000000
 255 #define PCH_UDC_RTS_DESERR      0x10000000
 256 #define PCH_UDC_RTS_BUFERR      0x30000000
 257 /* Last Descriptor Indication */
 258 #define PCH_UDC_DMA_LAST        0x08000000
 259 /* Number of Rx/Tx Bytes Mask */
 260 #define PCH_UDC_RXTX_BYTES      0x0000ffff
 261
 262 /**
 263  * struct pch_udc_cfg_data - Structure to hold current configuration
 264  *                           and interface information
 265  * @cur_cfg:    current configuration in use
 266  * @cur_intf:   current interface in use
 267  * @cur_alt:    current alt interface in use
 268  */
 269 struct pch_udc_cfg_data {
 270         u16 cur_cfg;
 271         u16 cur_intf;
 272         u16 cur_alt;
 273 };
 274
 275 /**
 276  * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
 277  * @ep:                 embedded ep request
 278  * @td_stp_phys:        for setup request
 279  * @td_data_phys:       for data request
 280  * @td_stp:             for setup request
 281  * @td_data:            for data request
 282  * @dev:                reference to device struct
 283  * @offset_addr:        offset address of ep register
 284  * @desc:               for this ep
 285  * @queue:              queue for requests
 286  * @num:                endpoint number
 287  * @in:                 endpoint is IN
 288  * @halted:             endpoint halted?
 289  * @epsts:              Endpoint status
 290  */
 291 struct pch_udc_ep {
 292         struct usb_ep                   ep;
 293         dma_addr_t                      td_stp_phys;
 294         dma_addr_t                      td_data_phys;
 295         struct pch_udc_stp_dma_desc     *td_stp;
 296         struct pch_udc_data_dma_desc    *td_data;
 297         struct pch_udc_dev              *dev;
 298         unsigned long                   offset_addr;
 299         const struct usb_endpoint_descriptor    *desc;
 300         struct list_head                queue;
 301         unsigned                        num:5,
 302                                         in:1,
 303                                         halted:1;
 304         unsigned long                   epsts;
 305 };
 306
 307 /**
 308  * struct pch_udc_dev - Structure holding complete information
 309  *                      of the PCH USB device
 310  * @gadget:             gadget driver data
 311  * @driver:             reference to gadget driver bound
 312  * @pdev:               reference to the PCI device
 313  * @ep:                 array of endpoints
 314  * @lock:               protects all state
 315  * @active:             enabled the PCI device
 316  * @stall:              stall requested
 317  * @prot_stall:         protcol stall requested
 318  * @irq_registered:     irq registered with system
 319  * @mem_region:         device memory mapped
 320  * @registered:         driver regsitered with system
 321  * @suspended:          driver in suspended state
 322  * @connected:          gadget driver associated
 323  * @set_cfg_not_acked:  pending acknowledgement 4 setup
 324  * @waiting_zlp_ack:    pending acknowledgement 4 ZLP
 325  * @data_requests:      DMA pool for data requests
 326  * @stp_requests:       DMA pool for setup requests
 327  * @dma_addr:           DMA pool for received
 328  * @ep0out_buf:         Buffer for DMA
 329  * @setup_data:         Received setup data
 330  * @phys_addr:          of device memory
 331  * @base_addr:          for mapped device memory
 332  * @irq:                IRQ line for the device
 333  * @cfg_data:           current cfg, intf, and alt in use
 334  */
 335 struct pch_udc_dev {
 336         struct usb_gadget               gadget;
 337         struct usb_gadget_driver        *driver;
 338         struct pci_dev                  *pdev;
 339         struct pch_udc_ep               ep[PCH_UDC_EP_NUM];
 340         spinlock_t                      lock; /* protects all state */
 341         unsigned        active:1,
 342                         stall:1,
 343                         prot_stall:1,
 344                         irq_registered:1,
 345                         mem_region:1,
 346                         registered:1,
 347                         suspended:1,
 348                         connected:1,
 349                         set_cfg_not_acked:1,
 350                         waiting_zlp_ack:1;
 351         struct pci_pool         *data_requests;
 352         struct pci_pool         *stp_requests;
 353         dma_addr_t                      dma_addr;
 354         void                            *ep0out_buf;
 355         struct usb_ctrlrequest          setup_data;
 356         unsigned long                   phys_addr;
 357         void __iomem                    *base_addr;
 358         unsigned                        irq;
 359         struct pch_udc_cfg_data cfg_data;
 360 };
 361
 362 #define PCH_UDC_PCI_BAR                 1
 363 #define PCI_DEVICE_ID_INTEL_EG20T_UDC   0x8808
 364 #define PCI_VENDOR_ID_ROHM              0x10DB
 365 #define PCI_DEVICE_ID_ML7213_IOH_UDC    0x801D
 366
 367 static const char       ep0_string[] = "ep0in";
 368 static DEFINE_SPINLOCK(udc_stall_spinlock);     /* stall spin lock */
 369 struct pch_udc_dev *pch_udc;            /* pointer to device object */
 370 static int speed_fs;
 371 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
 372 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
 373
 374 /**
 375  * struct pch_udc_request - Structure holding a PCH USB device request packet
 376  * @req:                embedded ep request
 377  * @td_data_phys:       phys. address
 378  * @td_data:            first dma desc. of chain
 379  * @td_data_last:       last dma desc. of chain
 380  * @queue:              associated queue
 381  * @dma_going:          DMA in progress for request
 382  * @dma_mapped:         DMA memory mapped for request
 383  * @dma_done:           DMA completed for request
 384  * @chain_len:          chain length
 385  * @buf:                Buffer memory for align adjustment
 386  * @dma:                DMA memory for align adjustment
 387  */
 388 struct pch_udc_request {
 389         struct usb_request              req;
 390         dma_addr_t                      td_data_phys;
 391         struct pch_udc_data_dma_desc    *td_data;
 392         struct pch_udc_data_dma_desc    *td_data_last;
 393         struct list_head                queue;
 394         unsigned                        dma_going:1,
 395                                         dma_mapped:1,
 396                                         dma_done:1;
 397         unsigned                        chain_len;
 398         void                            *buf;
 399         dma_addr_t                      dma;
 400 };
 401
 402 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
 403 {
 404         return ioread32(dev->base_addr + reg);
 405 }
 406
 407 static inline void pch_udc_writel(struct pch_udc_dev *dev,
 408                                     unsigned long val, unsigned long reg)
 409 {
 410         iowrite32(val, dev->base_addr + reg);
 411 }
 412
 413 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
 414                                      unsigned long reg,
 415                                      unsigned long bitmask)
 416 {
 417         pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
 418 }
 419
 420 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
 421                                      unsigned long reg,
 422                                      unsigned long bitmask)
 423 {
 424         pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
 425 }
 426
 427 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
 428 {
 429         return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
 430 }
 431
 432 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
 433                                     unsigned long val, unsigned long reg)
 434 {
 435         iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
 436 }
 437
 438 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
 439                                      unsigned long reg,
 440                                      unsigned long bitmask)
 441 {
 442         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
 443 }
 444
 445 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
 446                                      unsigned long reg,
 447                                      unsigned long bitmask)
 448 {
 449         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
 450 }
 451
 452 /**
 453  * pch_udc_csr_busy() - Wait till idle.
 454  * @dev:        Reference to pch_udc_dev structure
 455  */
 456 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
 457 {
 458         unsigned int count = 200;
 459
 460         /* Wait till idle */
 461         while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
 462                 && --count)
 463                 cpu_relax();
 464         if (!count)
 465                 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
 466 }
 467
 468 /**
 469  * pch_udc_write_csr() - Write the command and status registers.
 470  * @dev:        Reference to pch_udc_dev structure
 471  * @val:        value to be written to CSR register
 472  * @addr:       address of CSR register
 473  */
 474 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
 475                                unsigned int ep)
 476 {
 477         unsigned long reg = PCH_UDC_CSR(ep);
 478
 479         pch_udc_csr_busy(dev);          /* Wait till idle */
 480         pch_udc_writel(dev, val, reg);
 481         pch_udc_csr_busy(dev);          /* Wait till idle */
 482 }
 483
 484 /**
 485  * pch_udc_read_csr() - Read the command and status registers.
 486  * @dev:        Reference to pch_udc_dev structure
 487  * @addr:       address of CSR register
 488  *
 489  * Return codes:        content of CSR register
 490  */
 491 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
 492 {
 493         unsigned long reg = PCH_UDC_CSR(ep);
 494
 495         pch_udc_csr_busy(dev);          /* Wait till idle */
 496         pch_udc_readl(dev, reg);        /* Dummy read */
 497         pch_udc_csr_busy(dev);          /* Wait till idle */
 498         return pch_udc_readl(dev, reg);
 499 }
 500
 501 /**
 502  * pch_udc_rmt_wakeup() - Initiate for remote wakeup
 503  * @dev:        Reference to pch_udc_dev structure
 504  */
 505 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
 506 {
 507         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 508         mdelay(1);
 509         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 510 }
 511
 512 /**
 513  * pch_udc_get_frame() - Get the current frame from device status register
 514  * @dev:        Reference to pch_udc_dev structure
 515  * Retern       current frame
 516  */
 517 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
 518 {
 519         u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 520         return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
 521 }
 522
 523 /**
 524  * pch_udc_clear_selfpowered() - Clear the self power control
 525  * @dev:        Reference to pch_udc_regs structure
 526  */
 527 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
 528 {
 529         pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 530 }
 531
 532 /**
 533  * pch_udc_set_selfpowered() - Set the self power control
 534  * @dev:        Reference to pch_udc_regs structure
 535  */
 536 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
 537 {
 538         pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 539 }
 540
 541 /**
 542  * pch_udc_set_disconnect() - Set the disconnect status.
 543  * @dev:        Reference to pch_udc_regs structure
 544  */
 545 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
 546 {
 547         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 548 }
 549
 550 /**
 551  * pch_udc_clear_disconnect() - Clear the disconnect status.
 552  * @dev:        Reference to pch_udc_regs structure
 553  */
 554 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
 555 {
 556         /* Clear the disconnect */
 557         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 558         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 559         mdelay(1);
 560         /* Resume USB signalling */
 561         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 562 }
 563
 564 /**
 565  * pch_udc_vbus_session() - set or clearr the disconnect status.
 566  * @dev:        Reference to pch_udc_regs structure
 567  * @is_active:  Parameter specifying the action
 568  *                0:   indicating VBUS power is ending
 569  *                !0:  indicating VBUS power is starting
 570  */
 571 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
 572                                           int is_active)
 573 {
 574         if (is_active)
 575                 pch_udc_clear_disconnect(dev);
 576         else
 577                 pch_udc_set_disconnect(dev);
 578 }
 579
 580 /**
 581  * pch_udc_ep_set_stall() - Set the stall of endpoint
 582  * @ep:         Reference to structure of type pch_udc_ep_regs
 583  */
 584 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
 585 {
 586         if (ep->in) {
 587                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 588                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 589         } else {
 590                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 591         }
 592 }
 593
 594 /**
 595  * pch_udc_ep_clear_stall() - Clear the stall of endpoint
 596  * @ep:         Reference to structure of type pch_udc_ep_regs
 597  */
 598 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
 599 {
 600         /* Clear the stall */
 601         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 602         /* Clear NAK by writing CNAK */
 603         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 604 }
 605
 606 /**
 607  * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
 608  * @ep:         Reference to structure of type pch_udc_ep_regs
 609  * @type:       Type of endpoint
 610  */
 611 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
 612                                         u8 type)
 613 {
 614         pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
 615                                 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
 616 }
 617
 618 /**
 619  * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
 620  * @ep:         Reference to structure of type pch_udc_ep_regs
 621  * @buf_size:   The buffer word size
 622  */
 623 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
 624                                                  u32 buf_size, u32 ep_in)
 625 {
 626         u32 data;
 627         if (ep_in) {
 628                 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
 629                 data = (data & 0xffff0000) | (buf_size & 0xffff);
 630                 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
 631         } else {
 632                 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 633                 data = (buf_size << 16) | (data & 0xffff);
 634                 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 635         }
 636 }
 637
 638 /**
 639  * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
 640  * @ep:         Reference to structure of type pch_udc_ep_regs
 641  * @pkt_size:   The packet byte size
 642  */
 643 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
 644 {
 645         u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 646         data = (data & 0xffff0000) | (pkt_size & 0xffff);
 647         pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 648 }
 649
 650 /**
 651  * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
 652  * @ep:         Reference to structure of type pch_udc_ep_regs
 653  * @addr:       Address of the register
 654  */
 655 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
 656 {
 657         pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
 658 }
 659
 660 /**
 661  * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
 662  * @ep:         Reference to structure of type pch_udc_ep_regs
 663  * @addr:       Address of the register
 664  */
 665 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
 666 {
 667         pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
 668 }
 669
 670 /**
 671  * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
 672  * @ep:         Reference to structure of type pch_udc_ep_regs
 673  */
 674 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
 675 {
 676         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
 677 }
 678
 679 /**
 680  * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
 681  * @ep:         Reference to structure of type pch_udc_ep_regs
 682  */
 683 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
 684 {
 685         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 686 }
 687
 688 /**
 689  * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
 690  * @ep:         Reference to structure of type pch_udc_ep_regs
 691  */
 692 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
 693 {
 694         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 695 }
 696
 697 /**
 698  * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
 699  *                      register depending on the direction specified
 700  * @dev:        Reference to structure of type pch_udc_regs
 701  * @dir:        whether Tx or Rx
 702  *                DMA_DIR_RX: Receive
 703  *                DMA_DIR_TX: Transmit
 704  */
 705 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
 706 {
 707         if (dir == DMA_DIR_RX)
 708                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 709         else if (dir == DMA_DIR_TX)
 710                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 711 }
 712
 713 /**
 714  * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
 715  *                               register depending on the direction specified
 716  * @dev:        Reference to structure of type pch_udc_regs
 717  * @dir:        Whether Tx or Rx
 718  *                DMA_DIR_RX: Receive
 719  *                DMA_DIR_TX: Transmit
 720  */
 721 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
 722 {
 723         if (dir == DMA_DIR_RX)
 724                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 725         else if (dir == DMA_DIR_TX)
 726                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 727 }
 728
 729 /**
 730  * pch_udc_set_csr_done() - Set the device control register
 731  *                              CSR done field (bit 13)
 732  * @dev:        reference to structure of type pch_udc_regs
 733  */
 734 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
 735 {
 736         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
 737 }
 738
 739 /**
 740  * pch_udc_disable_interrupts() - Disables the specified interrupts
 741  * @dev:        Reference to structure of type pch_udc_regs
 742  * @mask:       Mask to disable interrupts
 743  */
 744 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
 745                                             u32 mask)
 746 {
 747         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
 748 }
 749
 750 /**
 751  * pch_udc_enable_interrupts() - Enable the specified interrupts
 752  * @dev:        Reference to structure of type pch_udc_regs
 753  * @mask:       Mask to enable interrupts
 754  */
 755 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
 756                                            u32 mask)
 757 {
 758         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
 759 }
 760
 761 /**
 762  * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
 763  * @dev:        Reference to structure of type pch_udc_regs
 764  * @mask:       Mask to disable interrupts
 765  */
 766 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
 767                                                 u32 mask)
 768 {
 769         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
 770 }
 771
 772 /**
 773  * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
 774  * @dev:        Reference to structure of type pch_udc_regs
 775  * @mask:       Mask to enable interrupts
 776  */
 777 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
 778                                               u32 mask)
 779 {
 780         pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
 781 }
 782
 783 /**
 784  * pch_udc_read_device_interrupts() - Read the device interrupts
 785  * @dev:        Reference to structure of type pch_udc_regs
 786  * Retern       The device interrupts
 787  */
 788 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
 789 {
 790         return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
 791 }
 792
 793 /**
 794  * pch_udc_write_device_interrupts() - Write device interrupts
 795  * @dev:        Reference to structure of type pch_udc_regs
 796  * @val:        The value to be written to interrupt register
 797  */
 798 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
 799                                                      u32 val)
 800 {
 801         pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
 802 }
 803
 804 /**
 805  * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
 806  * @dev:        Reference to structure of type pch_udc_regs
 807  * Retern       The endpoint interrupt
 808  */
 809 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
 810 {
 811         return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
 812 }
 813
 814 /**
 815  * pch_udc_write_ep_interrupts() - Clear endpoint interupts
 816  * @dev:        Reference to structure of type pch_udc_regs
 817  * @val:        The value to be written to interrupt register
 818  */
 819 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
 820                                              u32 val)
 821 {
 822         pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
 823 }
 824
 825 /**
 826  * pch_udc_read_device_status() - Read the device status
 827  * @dev:        Reference to structure of type pch_udc_regs
 828  * Retern       The device status
 829  */
 830 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
 831 {
 832         return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 833 }
 834
 835 /**
 836  * pch_udc_read_ep_control() - Read the endpoint control
 837  * @ep:         Reference to structure of type pch_udc_ep_regs
 838  * Retern       The endpoint control register value
 839  */
 840 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
 841 {
 842         return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
 843 }
 844
 845 /**
 846  * pch_udc_clear_ep_control() - Clear the endpoint control register
 847  * @ep:         Reference to structure of type pch_udc_ep_regs
 848  * Retern       The endpoint control register value
 849  */
 850 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
 851 {
 852         return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
 853 }
 854
 855 /**
 856  * pch_udc_read_ep_status() - Read the endpoint status
 857  * @ep:         Reference to structure of type pch_udc_ep_regs
 858  * Retern       The endpoint status
 859  */
 860 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
 861 {
 862         return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
 863 }
 864
 865 /**
 866  * pch_udc_clear_ep_status() - Clear the endpoint status
 867  * @ep:         Reference to structure of type pch_udc_ep_regs
 868  * @stat:       Endpoint status
 869  */
 870 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
 871                                          u32 stat)
 872 {
 873         return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
 874 }
 875
 876 /**
 877  * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
 878  *                              of the endpoint control register
 879  * @ep:         Reference to structure of type pch_udc_ep_regs
 880  */
 881 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
 882 {
 883         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
 884 }
 885
 886 /**
 887  * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
 888  *                              of the endpoint control register
 889  * @ep:         reference to structure of type pch_udc_ep_regs
 890  */
 891 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
 892 {
 893         unsigned int loopcnt = 0;
 894         struct pch_udc_dev *dev = ep->dev;
 895
 896         if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
 897                 return;
 898         if (!ep->in) {
 899                 loopcnt = 10000;
 900                 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
 901                         --loopcnt)
 902                         udelay(5);
 903                 if (!loopcnt)
 904                         dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
 905                                 __func__);
 906         }
 907         loopcnt = 10000;
 908         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
 909                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 910                 udelay(5);
 911         }
 912         if (!loopcnt)
 913                 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
 914                         __func__, ep->num, (ep->in ? "in" : "out"));
 915 }
 916
 917 /**
 918  * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
 919  * @ep: reference to structure of type pch_udc_ep_regs
 920  * @dir:        direction of endpoint
 921  *                0:  endpoint is OUT
 922  *                !0: endpoint is IN
 923  */
 924 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
 925 {
 926         if (dir) {      /* IN ep */
 927                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 928                 return;
 929         }
 930 }
 931
 932 /**
 933  * pch_udc_ep_enable() - This api enables endpoint
 934  * @regs:       Reference to structure pch_udc_ep_regs
 935  * @desc:       endpoint descriptor
 936  */
 937 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
 938                                struct pch_udc_cfg_data *cfg,
 939                                const struct usb_endpoint_descriptor *desc)
 940 {
 941         u32 val = 0;
 942         u32 buff_size = 0;
 943
 944         pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
 945         if (ep->in)
 946                 buff_size = UDC_EPIN_BUFF_SIZE;
 947         else
 948                 buff_size = UDC_EPOUT_BUFF_SIZE;
 949         pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
 950         pch_udc_ep_set_maxpkt(ep, le16_to_cpu(desc->wMaxPacketSize));
 951         pch_udc_ep_set_nak(ep);
 952         pch_udc_ep_fifo_flush(ep, ep->in);
 953         /* Configure the endpoint */
 954         val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
 955               ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
 956                 UDC_CSR_NE_TYPE_SHIFT) |
 957               (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
 958               (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
 959               (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
 960               le16_to_cpu(desc->wMaxPacketSize) << UDC_CSR_NE_MAX_PKT_SHIFT;
 961
 962         if (ep->in)
 963                 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
 964         else
 965                 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
 966 }
 967
 968 /**
 969  * pch_udc_ep_disable() - This api disables endpoint
 970  * @regs:       Reference to structure pch_udc_ep_regs
 971  */
 972 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
 973 {
 974         if (ep->in) {
 975                 /* flush the fifo */
 976                 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
 977                 /* set NAK */
 978                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
 979                 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
 980         } else {
 981                 /* set NAK */
 982                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
 983         }
 984         /* reset desc pointer */
 985         pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
 986 }
 987
 988 /**
 989  * pch_udc_wait_ep_stall() - Wait EP stall.
 990  * @dev:        Reference to pch_udc_dev structure
 991  */
 992 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
 993 {
 994         unsigned int count = 10000;
 995
 996         /* Wait till idle */
 997         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
 998                 udelay(5);
 999         if (!count)
1000                 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1001 }
1002
1003 /**
1004  * pch_udc_init() - This API initializes usb device controller
1005  * @dev:        Rreference to pch_udc_regs structure
1006  */
1007 static void pch_udc_init(struct pch_udc_dev *dev)
1008 {
1009         if (NULL == dev) {
1010                 pr_err("%s: Invalid address\n", __func__);
1011                 return;
1012         }
1013         /* Soft Reset and Reset PHY */
1014         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1015         pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1016         mdelay(1);
1017         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1018         pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1019         mdelay(1);
1020         /* mask and clear all device interrupts */
1021         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1022         pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1023
1024         /* mask and clear all ep interrupts */
1025         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1026         pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1027
1028         /* enable dynamic CSR programmingi, self powered and device speed */
1029         if (speed_fs)
1030                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1031                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1032         else /* defaul high speed */
1033                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1034                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1035         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1036                         (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1037                         (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1038                         UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1039                         UDC_DEVCTL_THE);
1040 }
1041
1042 /**
1043  * pch_udc_exit() - This API exit usb device controller
1044  * @dev:        Reference to pch_udc_regs structure
1045  */
1046 static void pch_udc_exit(struct pch_udc_dev *dev)
1047 {
1048         /* mask all device interrupts */
1049         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1050         /* mask all ep interrupts */
1051         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1052         /* put device in disconnected state */
1053         pch_udc_set_disconnect(dev);
1054 }
1055
1056 /**
1057  * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1058  * @gadget:     Reference to the gadget driver
1059  *
1060  * Return codes:
1061  *      0:              Success
1062  *      -EINVAL:        If the gadget passed is NULL
1063  */
1064 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1065 {
1066         struct pch_udc_dev      *dev;
1067
1068         if (!gadget)
1069                 return -EINVAL;
1070         dev = container_of(gadget, struct pch_udc_dev, gadget);
1071         return pch_udc_get_frame(dev);
1072 }
1073
1074 /**
1075  * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1076  * @gadget:     Reference to the gadget driver
1077  *
1078  * Return codes:
1079  *      0:              Success
1080  *      -EINVAL:        If the gadget passed is NULL
1081  */
1082 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1083 {
1084         struct pch_udc_dev      *dev;
1085         unsigned long           flags;
1086
1087         if (!gadget)
1088                 return -EINVAL;
1089         dev = container_of(gadget, struct pch_udc_dev, gadget);
1090         spin_lock_irqsave(&dev->lock, flags);
1091         pch_udc_rmt_wakeup(dev);
1092         spin_unlock_irqrestore(&dev->lock, flags);
1093         return 0;
1094 }
1095
1096 /**
1097  * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1098  *                              is self powered or not
1099  * @gadget:     Reference to the gadget driver
1100  * @value:      Specifies self powered or not
1101  *
1102  * Return codes:
1103  *      0:              Success
1104  *      -EINVAL:        If the gadget passed is NULL
1105  */
1106 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1107 {
1108         struct pch_udc_dev      *dev;
1109
1110         if (!gadget)
1111                 return -EINVAL;
1112         dev = container_of(gadget, struct pch_udc_dev, gadget);
1113         if (value)
1114                 pch_udc_set_selfpowered(dev);
1115         else
1116                 pch_udc_clear_selfpowered(dev);
1117         return 0;
1118 }
1119
1120 /**
1121  * pch_udc_pcd_pullup() - This API is invoked to make the device
1122  *                              visible/invisible to the host
1123  * @gadget:     Reference to the gadget driver
1124  * @is_on:      Specifies whether the pull up is made active or inactive
1125  *
1126  * Return codes:
1127  *      0:              Success
1128  *      -EINVAL:        If the gadget passed is NULL
1129  */
1130 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1131 {
1132         struct pch_udc_dev      *dev;
1133
1134         if (!gadget)
1135                 return -EINVAL;
1136         dev = container_of(gadget, struct pch_udc_dev, gadget);
1137         pch_udc_vbus_session(dev, is_on);
1138         return 0;
1139 }
1140
1141 /**
1142  * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1143  *                              transceiver (or GPIO) that
1144  *                              detects a VBUS power session starting/ending
1145  * @gadget:     Reference to the gadget driver
1146  * @is_active:  specifies whether the session is starting or ending
1147  *
1148  * Return codes:
1149  *      0:              Success
1150  *      -EINVAL:        If the gadget passed is NULL
1151  */
1152 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1153 {
1154         struct pch_udc_dev      *dev;
1155
1156         if (!gadget)
1157                 return -EINVAL;
1158         dev = container_of(gadget, struct pch_udc_dev, gadget);
1159         pch_udc_vbus_session(dev, is_active);
1160         return 0;
1161 }
1162
1163 /**
1164  * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1165  *                              SET_CONFIGURATION calls to
1166  *                              specify how much power the device can consume
1167  * @gadget:     Reference to the gadget driver
1168  * @mA:         specifies the current limit in 2mA unit
1169  *
1170  * Return codes:
1171  *      -EINVAL:        If the gadget passed is NULL
1172  *      -EOPNOTSUPP:
1173  */
1174 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1175 {
1176         return -EOPNOTSUPP;
1177 }
1178
1179 static int pch_udc_start(struct usb_gadget_driver *driver,
1180         int (*bind)(struct usb_gadget *));
1181 static int pch_udc_stop(struct usb_gadget_driver *driver);
1182 static const struct usb_gadget_ops pch_udc_ops = {
1183         .get_frame = pch_udc_pcd_get_frame,
1184         .wakeup = pch_udc_pcd_wakeup,
1185         .set_selfpowered = pch_udc_pcd_selfpowered,
1186         .pullup = pch_udc_pcd_pullup,
1187         .vbus_session = pch_udc_pcd_vbus_session,
1188         .vbus_draw = pch_udc_pcd_vbus_draw,
1189         .start  = pch_udc_start,
1190         .stop   = pch_udc_stop,
1191 };
1192
1193 /**
1194  * complete_req() - This API is invoked from the driver when processing
1195  *                      of a request is complete
1196  * @ep:         Reference to the endpoint structure
1197  * @req:        Reference to the request structure
1198  * @status:     Indicates the success/failure of completion
1199  */
1200 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1201                                                                  int status)
1202 {
1203         struct pch_udc_dev      *dev;
1204         unsigned halted = ep->halted;
1205
1206         list_del_init(&req->queue);
1207
1208         /* set new status if pending */
1209         if (req->req.status == -EINPROGRESS)
1210                 req->req.status = status;
1211         else
1212                 status = req->req.status;
1213
1214         dev = ep->dev;
1215         if (req->dma_mapped) {
1216                 if (req->dma == DMA_ADDR_INVALID) {
1217                         if (ep->in)
1218                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1219                                                  req->req.length,
1220                                                  DMA_TO_DEVICE);
1221                         else
1222                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1223                                                  req->req.length,
1224                                                  DMA_FROM_DEVICE);
1225                         req->req.dma = DMA_ADDR_INVALID;
1226                 } else {
1227                         if (ep->in)
1228                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1229                                                  req->req.length,
1230                                                  DMA_TO_DEVICE);
1231                         else {
1232                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1233                                                  req->req.length,
1234                                                  DMA_FROM_DEVICE);
1235                                 memcpy(req->req.buf, req->buf, req->req.length);
1236                         }
1237                         kfree(req->buf);
1238                         req->dma = DMA_ADDR_INVALID;
1239                 }
1240                 req->dma_mapped = 0;
1241         }
1242         ep->halted = 1;
1243         spin_unlock(&dev->lock);
1244         if (!ep->in)
1245                 pch_udc_ep_clear_rrdy(ep);
1246         req->req.complete(&ep->ep, &req->req);
1247         spin_lock(&dev->lock);
1248         ep->halted = halted;
1249 }
1250
1251 /**
1252  * empty_req_queue() - This API empties the request queue of an endpoint
1253  * @ep:         Reference to the endpoint structure
1254  */
1255 static void empty_req_queue(struct pch_udc_ep *ep)
1256 {
1257         struct pch_udc_request  *req;
1258
1259         ep->halted = 1;
1260         while (!list_empty(&ep->queue)) {
1261                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1262                 complete_req(ep, req, -ESHUTDOWN);      /* Remove from list */
1263         }
1264 }
1265
1266 /**
1267  * pch_udc_free_dma_chain() - This function frees the DMA chain created
1268  *                              for the request
1269  * @dev         Reference to the driver structure
1270  * @req         Reference to the request to be freed
1271  *
1272  * Return codes:
1273  *      0: Success
1274  */
1275 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1276                                    struct pch_udc_request *req)
1277 {
1278         struct pch_udc_data_dma_desc *td = req->td_data;
1279         unsigned i = req->chain_len;
1280
1281         dma_addr_t addr2;
1282         dma_addr_t addr = (dma_addr_t)td->next;
1283         td->next = 0x00;
1284         for (; i > 1; --i) {
1285                 /* do not free first desc., will be done by free for request */
1286                 td = phys_to_virt(addr);
1287                 addr2 = (dma_addr_t)td->next;
1288                 pci_pool_free(dev->data_requests, td, addr);
1289                 td->next = 0x00;
1290                 addr = addr2;
1291         }
1292         req->chain_len = 1;
1293 }
1294
1295 /**
1296  * pch_udc_create_dma_chain() - This function creates or reinitializes
1297  *                              a DMA chain
1298  * @ep:         Reference to the endpoint structure
1299  * @req:        Reference to the request
1300  * @buf_len:    The buffer length
1301  * @gfp_flags:  Flags to be used while mapping the data buffer
1302  *
1303  * Return codes:
1304  *      0:              success,
1305  *      -ENOMEM:        pci_pool_alloc invocation fails
1306  */
1307 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1308                                     struct pch_udc_request *req,
1309                                     unsigned long buf_len,
1310                                     gfp_t gfp_flags)
1311 {
1312         struct pch_udc_data_dma_desc *td = req->td_data, *last;
1313         unsigned long bytes = req->req.length, i = 0;
1314         dma_addr_t dma_addr;
1315         unsigned len = 1;
1316
1317         if (req->chain_len > 1)
1318                 pch_udc_free_dma_chain(ep->dev, req);
1319
1320         if (req->dma == DMA_ADDR_INVALID)
1321                 td->dataptr = req->req.dma;
1322         else
1323                 td->dataptr = req->dma;
1324
1325         td->status = PCH_UDC_BS_HST_BSY;
1326         for (; ; bytes -= buf_len, ++len) {
1327                 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1328                 if (bytes <= buf_len)
1329                         break;
1330                 last = td;
1331                 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1332                                     &dma_addr);
1333                 if (!td)
1334                         goto nomem;
1335                 i += buf_len;
1336                 td->dataptr = req->td_data->dataptr + i;
1337                 last->next = dma_addr;
1338         }
1339
1340         req->td_data_last = td;
1341         td->status |= PCH_UDC_DMA_LAST;
1342         td->next = req->td_data_phys;
1343         req->chain_len = len;
1344         return 0;
1345
1346 nomem:
1347         if (len > 1) {
1348                 req->chain_len = len;
1349                 pch_udc_free_dma_chain(ep->dev, req);
1350         }
1351         req->chain_len = 1;
1352         return -ENOMEM;
1353 }
1354
1355 /**
1356  * prepare_dma() - This function creates and initializes the DMA chain
1357  *                      for the request
1358  * @ep:         Reference to the endpoint structure
1359  * @req:        Reference to the request
1360  * @gfp:        Flag to be used while mapping the data buffer
1361  *
1362  * Return codes:
1363  *      0:              Success
1364  *      Other 0:        linux error number on failure
1365  */
1366 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1367                           gfp_t gfp)
1368 {
1369         int     retval;
1370
1371         /* Allocate and create a DMA chain */
1372         retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1373         if (retval) {
1374                 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1375                 return retval;
1376         }
1377         if (ep->in)
1378                 req->td_data->status = (req->td_data->status &
1379                                 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1380         return 0;
1381 }
1382
1383 /**
1384  * process_zlp() - This function process zero length packets
1385  *                      from the gadget driver
1386  * @ep:         Reference to the endpoint structure
1387  * @req:        Reference to the request
1388  */
1389 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1390 {
1391         struct pch_udc_dev      *dev = ep->dev;
1392
1393         /* IN zlp's are handled by hardware */
1394         complete_req(ep, req, 0);
1395
1396         /* if set_config or set_intf is waiting for ack by zlp
1397          * then set CSR_DONE
1398          */
1399         if (dev->set_cfg_not_acked) {
1400                 pch_udc_set_csr_done(dev);
1401                 dev->set_cfg_not_acked = 0;
1402         }
1403         /* setup command is ACK'ed now by zlp */
1404         if (!dev->stall && dev->waiting_zlp_ack) {
1405                 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1406                 dev->waiting_zlp_ack = 0;
1407         }
1408 }
1409
1410 /**
1411  * pch_udc_start_rxrequest() - This function starts the receive requirement.
1412  * @ep:         Reference to the endpoint structure
1413  * @req:        Reference to the request structure
1414  */
1415 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1416                                          struct pch_udc_request *req)
1417 {
1418         struct pch_udc_data_dma_desc *td_data;
1419
1420         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1421         td_data = req->td_data;
1422         /* Set the status bits for all descriptors */
1423         while (1) {
1424                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1425                                     PCH_UDC_BS_HST_RDY;
1426                 if ((td_data->status & PCH_UDC_DMA_LAST) ==  PCH_UDC_DMA_LAST)
1427                         break;
1428                 td_data = phys_to_virt(td_data->next);
1429         }
1430         /* Write the descriptor pointer */
1431         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1432         req->dma_going = 1;
1433         pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1434         pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1435         pch_udc_ep_clear_nak(ep);
1436         pch_udc_ep_set_rrdy(ep);
1437 }
1438
1439 /**
1440  * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1441  *                              from gadget driver
1442  * @usbep:      Reference to the USB endpoint structure
1443  * @desc:       Reference to the USB endpoint descriptor structure
1444  *
1445  * Return codes:
1446  *      0:              Success
1447  *      -EINVAL:
1448  *      -ESHUTDOWN:
1449  */
1450 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1451                                     const struct usb_endpoint_descriptor *desc)
1452 {
1453         struct pch_udc_ep       *ep;
1454         struct pch_udc_dev      *dev;
1455         unsigned long           iflags;
1456
1457         if (!usbep || (usbep->name == ep0_string) || !desc ||
1458             (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1459                 return -EINVAL;
1460
1461         ep = container_of(usbep, struct pch_udc_ep, ep);
1462         dev = ep->dev;
1463         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1464                 return -ESHUTDOWN;
1465         spin_lock_irqsave(&dev->lock, iflags);
1466         ep->desc = desc;
1467         ep->halted = 0;
1468         pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1469         ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
1470         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1471         spin_unlock_irqrestore(&dev->lock, iflags);
1472         return 0;
1473 }
1474
1475 /**
1476  * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1477  *                              from gadget driver
1478  * @usbep       Reference to the USB endpoint structure
1479  *
1480  * Return codes:
1481  *      0:              Success
1482  *      -EINVAL:
1483  */
1484 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1485 {
1486         struct pch_udc_ep       *ep;
1487         struct pch_udc_dev      *dev;
1488         unsigned long   iflags;
1489
1490         if (!usbep)
1491                 return -EINVAL;
1492
1493         ep = container_of(usbep, struct pch_udc_ep, ep);
1494         dev = ep->dev;
1495         if ((usbep->name == ep0_string) || !ep->desc)
1496                 return -EINVAL;
1497
1498         spin_lock_irqsave(&ep->dev->lock, iflags);
1499         empty_req_queue(ep);
1500         ep->halted = 1;
1501         pch_udc_ep_disable(ep);
1502         pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1503         ep->desc = NULL;
1504         INIT_LIST_HEAD(&ep->queue);
1505         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1506         return 0;
1507 }
1508
1509 /**
1510  * pch_udc_alloc_request() - This function allocates request structure.
1511  *                              It is called by gadget driver
1512  * @usbep:      Reference to the USB endpoint structure
1513  * @gfp:        Flag to be used while allocating memory
1514  *
1515  * Return codes:
1516  *      NULL:                   Failure
1517  *      Allocated address:      Success
1518  */
1519 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1520                                                   gfp_t gfp)
1521 {
1522         struct pch_udc_request          *req;
1523         struct pch_udc_ep               *ep;
1524         struct pch_udc_data_dma_desc    *dma_desc;
1525         struct pch_udc_dev              *dev;
1526
1527         if (!usbep)
1528                 return NULL;
1529         ep = container_of(usbep, struct pch_udc_ep, ep);
1530         dev = ep->dev;
1531         req = kzalloc(sizeof *req, gfp);
1532         if (!req)
1533                 return NULL;
1534         req->req.dma = DMA_ADDR_INVALID;
1535         req->dma = DMA_ADDR_INVALID;
1536         INIT_LIST_HEAD(&req->queue);
1537         if (!ep->dev->dma_addr)
1538                 return &req->req;
1539         /* ep0 in requests are allocated from data pool here */
1540         dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1541                                   &req->td_data_phys);
1542         if (NULL == dma_desc) {
1543                 kfree(req);
1544                 return NULL;
1545         }
1546         /* prevent from using desc. - set HOST BUSY */
1547         dma_desc->status |= PCH_UDC_BS_HST_BSY;
1548         dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1549         req->td_data = dma_desc;
1550         req->td_data_last = dma_desc;
1551         req->chain_len = 1;
1552         return &req->req;
1553 }
1554
1555 /**
1556  * pch_udc_free_request() - This function frees request structure.
1557  *                              It is called by gadget driver
1558  * @usbep:      Reference to the USB endpoint structure
1559  * @usbreq:     Reference to the USB request
1560  */
1561 static void pch_udc_free_request(struct usb_ep *usbep,
1562                                   struct usb_request *usbreq)
1563 {
1564         struct pch_udc_ep       *ep;
1565         struct pch_udc_request  *req;
1566         struct pch_udc_dev      *dev;
1567
1568         if (!usbep || !usbreq)
1569                 return;
1570         ep = container_of(usbep, struct pch_udc_ep, ep);
1571         req = container_of(usbreq, struct pch_udc_request, req);
1572         dev = ep->dev;
1573         if (!list_empty(&req->queue))
1574                 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1575                         __func__, usbep->name, req);
1576         if (req->td_data != NULL) {
1577                 if (req->chain_len > 1)
1578                         pch_udc_free_dma_chain(ep->dev, req);
1579                 pci_pool_free(ep->dev->data_requests, req->td_data,
1580                               req->td_data_phys);
1581         }
1582         kfree(req);
1583 }
1584
1585 /**
1586  * pch_udc_pcd_queue() - This function queues a request packet. It is called
1587  *                      by gadget driver
1588  * @usbep:      Reference to the USB endpoint structure
1589  * @usbreq:     Reference to the USB request
1590  * @gfp:        Flag to be used while mapping the data buffer
1591  *
1592  * Return codes:
1593  *      0:                      Success
1594  *      linux error number:     Failure
1595  */
1596 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1597                                                                  gfp_t gfp)
1598 {
1599         int retval = 0;
1600         struct pch_udc_ep       *ep;
1601         struct pch_udc_dev      *dev;
1602         struct pch_udc_request  *req;
1603         unsigned long   iflags;
1604
1605         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1606                 return -EINVAL;
1607         ep = container_of(usbep, struct pch_udc_ep, ep);
1608         dev = ep->dev;
1609         if (!ep->desc && ep->num)
1610                 return -EINVAL;
1611         req = container_of(usbreq, struct pch_udc_request, req);
1612         if (!list_empty(&req->queue))
1613                 return -EINVAL;
1614         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1615                 return -ESHUTDOWN;
1616         spin_lock_irqsave(&dev->lock, iflags);
1617         /* map the buffer for dma */
1618         if (usbreq->length &&
1619             ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1620                 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1621                         if (ep->in)
1622                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1623                                                              usbreq->buf,
1624                                                              usbreq->length,
1625                                                              DMA_TO_DEVICE);
1626                         else
1627                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1628                                                              usbreq->buf,
1629                                                              usbreq->length,
1630                                                              DMA_FROM_DEVICE);
1631                 } else {
1632                         req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1633                         if (!req->buf) {
1634                                 retval = -ENOMEM;
1635                                 goto probe_end;
1636                         }
1637                         if (ep->in) {
1638                                 memcpy(req->buf, usbreq->buf, usbreq->length);
1639                                 req->dma = dma_map_single(&dev->pdev->dev,
1640                                                           req->buf,
1641                                                           usbreq->length,
1642                                                           DMA_TO_DEVICE);
1643                         } else
1644                                 req->dma = dma_map_single(&dev->pdev->dev,
1645                                                           req->buf,
1646                                                           usbreq->length,
1647                                                           DMA_FROM_DEVICE);
1648                 }
1649                 req->dma_mapped = 1;
1650         }
1651         if (usbreq->length > 0) {
1652                 retval = prepare_dma(ep, req, GFP_ATOMIC);
1653                 if (retval)
1654                         goto probe_end;
1655         }
1656         usbreq->actual = 0;
1657         usbreq->status = -EINPROGRESS;
1658         req->dma_done = 0;
1659         if (list_empty(&ep->queue) && !ep->halted) {
1660                 /* no pending transfer, so start this req */
1661                 if (!usbreq->length) {
1662                         process_zlp(ep, req);
1663                         retval = 0;
1664                         goto probe_end;
1665                 }
1666                 if (!ep->in) {
1667                         pch_udc_start_rxrequest(ep, req);
1668                 } else {
1669                         /*
1670                         * For IN trfr the descriptors will be programmed and
1671                         * P bit will be set when
1672                         * we get an IN token
1673                         */
1674                         pch_udc_wait_ep_stall(ep);
1675                         pch_udc_ep_clear_nak(ep);
1676                         pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1677                 }
1678         }
1679         /* Now add this request to the ep's pending requests */
1680         if (req != NULL)
1681                 list_add_tail(&req->queue, &ep->queue);
1682
1683 probe_end:
1684         spin_unlock_irqrestore(&dev->lock, iflags);
1685         return retval;
1686 }
1687
1688 /**
1689  * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1690  *                              It is called by gadget driver
1691  * @usbep:      Reference to the USB endpoint structure
1692  * @usbreq:     Reference to the USB request
1693  *
1694  * Return codes:
1695  *      0:                      Success
1696  *      linux error number:     Failure
1697  */
1698 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1699                                 struct usb_request *usbreq)
1700 {
1701         struct pch_udc_ep       *ep;
1702         struct pch_udc_request  *req;
1703         struct pch_udc_dev      *dev;
1704         unsigned long           flags;
1705         int ret = -EINVAL;
1706
1707         ep = container_of(usbep, struct pch_udc_ep, ep);
1708         dev = ep->dev;
1709         if (!usbep || !usbreq || (!ep->desc && ep->num))
1710                 return ret;
1711         req = container_of(usbreq, struct pch_udc_request, req);
1712         spin_lock_irqsave(&ep->dev->lock, flags);
1713         /* make sure it's still queued on this endpoint */
1714         list_for_each_entry(req, &ep->queue, queue) {
1715                 if (&req->req == usbreq) {
1716                         pch_udc_ep_set_nak(ep);
1717                         if (!list_empty(&req->queue))
1718                                 complete_req(ep, req, -ECONNRESET);
1719                         ret = 0;
1720                         break;
1721                 }
1722         }
1723         spin_unlock_irqrestore(&ep->dev->lock, flags);
1724         return ret;
1725 }
1726
1727 /**
1728  * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1729  *                          feature
1730  * @usbep:      Reference to the USB endpoint structure
1731  * @halt:       Specifies whether to set or clear the feature
1732  *
1733  * Return codes:
1734  *      0:                      Success
1735  *      linux error number:     Failure
1736  */
1737 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1738 {
1739         struct pch_udc_ep       *ep;
1740         struct pch_udc_dev      *dev;
1741         unsigned long iflags;
1742         int ret;
1743
1744         if (!usbep)
1745                 return -EINVAL;
1746         ep = container_of(usbep, struct pch_udc_ep, ep);
1747         dev = ep->dev;
1748         if (!ep->desc && !ep->num)
1749                 return -EINVAL;
1750         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1751                 return -ESHUTDOWN;
1752         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1753         if (list_empty(&ep->queue)) {
1754                 if (halt) {
1755                         if (ep->num == PCH_UDC_EP0)
1756                                 ep->dev->stall = 1;
1757                         pch_udc_ep_set_stall(ep);
1758                         pch_udc_enable_ep_interrupts(ep->dev,
1759                                                      PCH_UDC_EPINT(ep->in,
1760                                                                    ep->num));
1761                 } else {
1762                         pch_udc_ep_clear_stall(ep);
1763                 }
1764                 ret = 0;
1765         } else {
1766                 ret = -EAGAIN;
1767         }
1768         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1769         return ret;
1770 }
1771
1772 /**
1773  * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1774  *                              halt feature
1775  * @usbep:      Reference to the USB endpoint structure
1776  * @halt:       Specifies whether to set or clear the feature
1777  *
1778  * Return codes:
1779  *      0:                      Success
1780  *      linux error number:     Failure
1781  */
1782 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1783 {
1784         struct pch_udc_ep       *ep;
1785         struct pch_udc_dev      *dev;
1786         unsigned long iflags;
1787         int ret;
1788
1789         if (!usbep)
1790                 return -EINVAL;
1791         ep = container_of(usbep, struct pch_udc_ep, ep);
1792         dev = ep->dev;
1793         if (!ep->desc && !ep->num)
1794                 return -EINVAL;
1795         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1796                 return -ESHUTDOWN;
1797         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1798         if (!list_empty(&ep->queue)) {
1799                 ret = -EAGAIN;
1800         } else {
1801                 if (ep->num == PCH_UDC_EP0)
1802                         ep->dev->stall = 1;
1803                 pch_udc_ep_set_stall(ep);
1804                 pch_udc_enable_ep_interrupts(ep->dev,
1805                                              PCH_UDC_EPINT(ep->in, ep->num));
1806                 ep->dev->prot_stall = 1;
1807                 ret = 0;
1808         }
1809         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1810         return ret;
1811 }
1812
1813 /**
1814  * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1815  * @usbep:      Reference to the USB endpoint structure
1816  */
1817 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1818 {
1819         struct pch_udc_ep  *ep;
1820
1821         if (!usbep)
1822                 return;
1823
1824         ep = container_of(usbep, struct pch_udc_ep, ep);
1825         if (ep->desc || !ep->num)
1826                 pch_udc_ep_fifo_flush(ep, ep->in);
1827 }
1828
1829 static const struct usb_ep_ops pch_udc_ep_ops = {
1830         .enable         = pch_udc_pcd_ep_enable,
1831         .disable        = pch_udc_pcd_ep_disable,
1832         .alloc_request  = pch_udc_alloc_request,
1833         .free_request   = pch_udc_free_request,
1834         .queue          = pch_udc_pcd_queue,
1835         .dequeue        = pch_udc_pcd_dequeue,
1836         .set_halt       = pch_udc_pcd_set_halt,
1837         .set_wedge      = pch_udc_pcd_set_wedge,
1838         .fifo_status    = NULL,
1839         .fifo_flush     = pch_udc_pcd_fifo_flush,
1840 };
1841
1842 /**
1843  * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1844  * @td_stp:     Reference to the SETP buffer structure
1845  */
1846 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1847 {
1848         static u32      pky_marker;
1849
1850         if (!td_stp)
1851                 return;
1852         td_stp->reserved = ++pky_marker;
1853         memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1854         td_stp->status = PCH_UDC_BS_HST_RDY;
1855 }
1856
1857 /**
1858  * pch_udc_start_next_txrequest() - This function starts
1859  *                                      the next transmission requirement
1860  * @ep: Reference to the endpoint structure
1861  */
1862 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1863 {
1864         struct pch_udc_request *req;
1865         struct pch_udc_data_dma_desc *td_data;
1866
1867         if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1868                 return;
1869
1870         if (list_empty(&ep->queue))
1871                 return;
1872
1873         /* next request */
1874         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1875         if (req->dma_going)
1876                 return;
1877         if (!req->td_data)
1878                 return;
1879         pch_udc_wait_ep_stall(ep);
1880         req->dma_going = 1;
1881         pch_udc_ep_set_ddptr(ep, 0);
1882         td_data = req->td_data;
1883         while (1) {
1884                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1885                                    PCH_UDC_BS_HST_RDY;
1886                 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1887                         break;
1888                 td_data = phys_to_virt(td_data->next);
1889         }
1890         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1891         pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1892         pch_udc_ep_set_pd(ep);
1893         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1894         pch_udc_ep_clear_nak(ep);
1895 }
1896
1897 /**
1898  * pch_udc_complete_transfer() - This function completes a transfer
1899  * @ep:         Reference to the endpoint structure
1900  */
1901 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1902 {
1903         struct pch_udc_request *req;
1904         struct pch_udc_dev *dev = ep->dev;
1905
1906         if (list_empty(&ep->queue))
1907                 return;
1908         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1909         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1910             PCH_UDC_BS_DMA_DONE)
1911                 return;
1912         if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1913              PCH_UDC_RTS_SUCC) {
1914                 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1915                         "epstatus=0x%08x\n",
1916                        (req->td_data_last->status & PCH_UDC_RXTX_STS),
1917                        (int)(ep->epsts));
1918                 return;
1919         }
1920
1921         req->req.actual = req->req.length;
1922         req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1923         req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1924         complete_req(ep, req, 0);
1925         req->dma_going = 0;
1926         if (!list_empty(&ep->queue)) {
1927                 pch_udc_wait_ep_stall(ep);
1928                 pch_udc_ep_clear_nak(ep);
1929                 pch_udc_enable_ep_interrupts(ep->dev,
1930                                              PCH_UDC_EPINT(ep->in, ep->num));
1931         } else {
1932                 pch_udc_disable_ep_interrupts(ep->dev,
1933                                               PCH_UDC_EPINT(ep->in, ep->num));
1934         }
1935 }
1936
1937 /**
1938  * pch_udc_complete_receiver() - This function completes a receiver
1939  * @ep:         Reference to the endpoint structure
1940  */
1941 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1942 {
1943         struct pch_udc_request *req;
1944         struct pch_udc_dev *dev = ep->dev;
1945         unsigned int count;
1946         struct pch_udc_data_dma_desc *td;
1947         dma_addr_t addr;
1948
1949         if (list_empty(&ep->queue))
1950                 return;
1951         /* next request */
1952         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1953         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1954         pch_udc_ep_set_ddptr(ep, 0);
1955         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
1956             PCH_UDC_BS_DMA_DONE)
1957                 td = req->td_data_last;
1958         else
1959                 td = req->td_data;
1960
1961         while (1) {
1962                 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
1963                         dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
1964                                 "epstatus=0x%08x\n",
1965                                 (req->td_data->status & PCH_UDC_RXTX_STS),
1966                                 (int)(ep->epsts));
1967                         return;
1968                 }
1969                 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
1970                         if (td->status | PCH_UDC_DMA_LAST) {
1971                                 count = td->status & PCH_UDC_RXTX_BYTES;
1972                                 break;
1973                         }
1974                 if (td == req->td_data_last) {
1975                         dev_err(&dev->pdev->dev, "Not complete RX descriptor");
1976                         return;
1977                 }
1978                 addr = (dma_addr_t)td->next;
1979                 td = phys_to_virt(addr);
1980         }
1981         /* on 64k packets the RXBYTES field is zero */
1982         if (!count && (req->req.length == UDC_DMA_MAXPACKET))
1983                 count = UDC_DMA_MAXPACKET;
1984         req->td_data->status |= PCH_UDC_DMA_LAST;
1985         td->status |= PCH_UDC_BS_HST_BSY;
1986
1987         req->dma_going = 0;
1988         req->req.actual = count;
1989         complete_req(ep, req, 0);
1990         /* If there is a new/failed requests try that now */
1991         if (!list_empty(&ep->queue)) {
1992                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1993                 pch_udc_start_rxrequest(ep, req);
1994         }
1995 }
1996
1997 /**
1998  * pch_udc_svc_data_in() - This function process endpoint interrupts
1999  *                              for IN endpoints
2000  * @dev:        Reference to the device structure
2001  * @ep_num:     Endpoint that generated the interrupt
2002  */
2003 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2004 {
2005         u32     epsts;
2006         struct pch_udc_ep       *ep;
2007
2008         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2009         epsts = ep->epsts;
2010         ep->epsts = 0;
2011
2012         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA  | UDC_EPSTS_HE |
2013                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2014                        UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2015                 return;
2016         if ((epsts & UDC_EPSTS_BNA))
2017                 return;
2018         if (epsts & UDC_EPSTS_HE)
2019                 return;
2020         if (epsts & UDC_EPSTS_RSS) {
2021                 pch_udc_ep_set_stall(ep);
2022                 pch_udc_enable_ep_interrupts(ep->dev,
2023                                              PCH_UDC_EPINT(ep->in, ep->num));
2024         }
2025         if (epsts & UDC_EPSTS_RCS) {
2026                 if (!dev->prot_stall) {
2027                         pch_udc_ep_clear_stall(ep);
2028                 } else {
2029                         pch_udc_ep_set_stall(ep);
2030                         pch_udc_enable_ep_interrupts(ep->dev,
2031                                                 PCH_UDC_EPINT(ep->in, ep->num));
2032                 }
2033         }
2034         if (epsts & UDC_EPSTS_TDC)
2035                 pch_udc_complete_transfer(ep);
2036         /* On IN interrupt, provide data if we have any */
2037         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2038             !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2039                 pch_udc_start_next_txrequest(ep);
2040 }
2041
2042 /**
2043  * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2044  * @dev:        Reference to the device structure
2045  * @ep_num:     Endpoint that generated the interrupt
2046  */
2047 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2048 {
2049         u32                     epsts;
2050         struct pch_udc_ep               *ep;
2051         struct pch_udc_request          *req = NULL;
2052
2053         ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2054         epsts = ep->epsts;
2055         ep->epsts = 0;
2056
2057         if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2058                 /* next request */
2059                 req = list_entry(ep->queue.next, struct pch_udc_request,
2060                                  queue);
2061                 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2062                      PCH_UDC_BS_DMA_DONE) {
2063                         if (!req->dma_going)
2064                                 pch_udc_start_rxrequest(ep, req);
2065                         return;
2066                 }
2067         }
2068         if (epsts & UDC_EPSTS_HE)
2069                 return;
2070         if (epsts & UDC_EPSTS_RSS) {
2071                 pch_udc_ep_set_stall(ep);
2072                 pch_udc_enable_ep_interrupts(ep->dev,
2073                                              PCH_UDC_EPINT(ep->in, ep->num));
2074         }
2075         if (epsts & UDC_EPSTS_RCS) {
2076                 if (!dev->prot_stall) {
2077                         pch_udc_ep_clear_stall(ep);
2078                 } else {
2079                         pch_udc_ep_set_stall(ep);
2080                         pch_udc_enable_ep_interrupts(ep->dev,
2081                                                 PCH_UDC_EPINT(ep->in, ep->num));
2082                 }
2083         }
2084         if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2085             UDC_EPSTS_OUT_DATA) {
2086                 if (ep->dev->prot_stall == 1) {
2087                         pch_udc_ep_set_stall(ep);
2088                         pch_udc_enable_ep_interrupts(ep->dev,
2089                                                 PCH_UDC_EPINT(ep->in, ep->num));
2090                 } else {
2091                         pch_udc_complete_receiver(ep);
2092                 }
2093         }
2094         if (list_empty(&ep->queue))
2095                 pch_udc_set_dma(dev, DMA_DIR_RX);
2096 }
2097
2098 /**
2099  * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2100  * @dev:        Reference to the device structure
2101  */
2102 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2103 {
2104         u32     epsts;
2105         struct pch_udc_ep       *ep;
2106         struct pch_udc_ep       *ep_out;
2107
2108         ep = &dev->ep[UDC_EP0IN_IDX];
2109         ep_out = &dev->ep[UDC_EP0OUT_IDX];
2110         epsts = ep->epsts;
2111         ep->epsts = 0;
2112
2113         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2114                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2115                        UDC_EPSTS_XFERDONE)))
2116                 return;
2117         if ((epsts & UDC_EPSTS_BNA))
2118                 return;
2119         if (epsts & UDC_EPSTS_HE)
2120                 return;
2121         if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2122                 pch_udc_complete_transfer(ep);
2123                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2124                 ep_out->td_data->status = (ep_out->td_data->status &
2125                                         ~PCH_UDC_BUFF_STS) |
2126                                         PCH_UDC_BS_HST_RDY;
2127                 pch_udc_ep_clear_nak(ep_out);
2128                 pch_udc_set_dma(dev, DMA_DIR_RX);
2129                 pch_udc_ep_set_rrdy(ep_out);
2130         }
2131         /* On IN interrupt, provide data if we have any */
2132         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2133              !(epsts & UDC_EPSTS_TXEMPTY))
2134                 pch_udc_start_next_txrequest(ep);
2135 }
2136
2137 /**
2138  * pch_udc_svc_control_out() - Routine that handle Control
2139  *                                      OUT endpoint interrupts
2140  * @dev:        Reference to the device structure
2141  */
2142 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2143 {
2144         u32     stat;
2145         int setup_supported;
2146         struct pch_udc_ep       *ep;
2147
2148         ep = &dev->ep[UDC_EP0OUT_IDX];
2149         stat = ep->epsts;
2150         ep->epsts = 0;
2151
2152         /* If setup data */
2153         if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2154             UDC_EPSTS_OUT_SETUP) {
2155                 dev->stall = 0;
2156                 dev->ep[UDC_EP0IN_IDX].halted = 0;
2157                 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2158                 dev->setup_data = ep->td_stp->request;
2159                 pch_udc_init_setup_buff(ep->td_stp);
2160                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2161                 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2162                                       dev->ep[UDC_EP0IN_IDX].in);
2163                 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2164                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2165                 else /* OUT */
2166                         dev->gadget.ep0 = &ep->ep;
2167                 spin_unlock(&dev->lock);
2168                 /* If Mass storage Reset */
2169                 if ((dev->setup_data.bRequestType == 0x21) &&
2170                     (dev->setup_data.bRequest == 0xFF))
2171                         dev->prot_stall = 0;
2172                 /* call gadget with setup data received */
2173                 setup_supported = dev->driver->setup(&dev->gadget,
2174                                                      &dev->setup_data);
2175                 spin_lock(&dev->lock);
2176
2177                 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2178                         ep->td_data->status = (ep->td_data->status &
2179                                                 ~PCH_UDC_BUFF_STS) |
2180                                                 PCH_UDC_BS_HST_RDY;
2181                         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2182                 }
2183                 /* ep0 in returns data on IN phase */
2184                 if (setup_supported >= 0 && setup_supported <
2185                                             UDC_EP0IN_MAX_PKT_SIZE) {
2186                         pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2187                         /* Gadget would have queued a request when
2188                          * we called the setup */
2189                         if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2190                                 pch_udc_set_dma(dev, DMA_DIR_RX);
2191                                 pch_udc_ep_clear_nak(ep);
2192                         }
2193                 } else if (setup_supported < 0) {
2194                         /* if unsupported request, then stall */
2195                         pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2196                         pch_udc_enable_ep_interrupts(ep->dev,
2197                                                 PCH_UDC_EPINT(ep->in, ep->num));
2198                         dev->stall = 0;
2199                         pch_udc_set_dma(dev, DMA_DIR_RX);
2200                 } else {
2201                         dev->waiting_zlp_ack = 1;
2202                 }
2203         } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2204                      UDC_EPSTS_OUT_DATA) && !dev->stall) {
2205                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2206                 pch_udc_ep_set_ddptr(ep, 0);
2207                 if (!list_empty(&ep->queue)) {
2208                         ep->epsts = stat;
2209                         pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2210                 }
2211                 pch_udc_set_dma(dev, DMA_DIR_RX);
2212         }
2213         pch_udc_ep_set_rrdy(ep);
2214 }
2215
2216
2217 /**
2218  * pch_udc_postsvc_epinters() - This function enables end point interrupts
2219  *                              and clears NAK status
2220  * @dev:        Reference to the device structure
2221  * @ep_num:     End point number
2222  */
2223 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2224 {
2225         struct pch_udc_ep       *ep;
2226         struct pch_udc_request *req;
2227
2228         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2229         if (!list_empty(&ep->queue)) {
2230                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2231                 pch_udc_enable_ep_interrupts(ep->dev,
2232                                              PCH_UDC_EPINT(ep->in, ep->num));
2233                 pch_udc_ep_clear_nak(ep);
2234         }
2235 }
2236
2237 /**
2238  * pch_udc_read_all_epstatus() - This function read all endpoint status
2239  * @dev:        Reference to the device structure
2240  * @ep_intr:    Status of endpoint interrupt
2241  */
2242 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2243 {
2244         int i;
2245         struct pch_udc_ep       *ep;
2246
2247         for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2248                 /* IN */
2249                 if (ep_intr & (0x1 << i)) {
2250                         ep = &dev->ep[UDC_EPIN_IDX(i)];
2251                         ep->epsts = pch_udc_read_ep_status(ep);
2252                         pch_udc_clear_ep_status(ep, ep->epsts);
2253                 }
2254                 /* OUT */
2255                 if (ep_intr & (0x10000 << i)) {
2256                         ep = &dev->ep[UDC_EPOUT_IDX(i)];
2257                         ep->epsts = pch_udc_read_ep_status(ep);
2258                         pch_udc_clear_ep_status(ep, ep->epsts);
2259                 }
2260         }
2261 }
2262
2263 /**
2264  * pch_udc_activate_control_ep() - This function enables the control endpoints
2265  *                                      for traffic after a reset
2266  * @dev:        Reference to the device structure
2267  */
2268 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2269 {
2270         struct pch_udc_ep       *ep;
2271         u32 val;
2272
2273         /* Setup the IN endpoint */
2274         ep = &dev->ep[UDC_EP0IN_IDX];
2275         pch_udc_clear_ep_control(ep);
2276         pch_udc_ep_fifo_flush(ep, ep->in);
2277         pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2278         pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2279         /* Initialize the IN EP Descriptor */
2280         ep->td_data      = NULL;
2281         ep->td_stp       = NULL;
2282         ep->td_data_phys = 0;
2283         ep->td_stp_phys  = 0;
2284
2285         /* Setup the OUT endpoint */
2286         ep = &dev->ep[UDC_EP0OUT_IDX];
2287         pch_udc_clear_ep_control(ep);
2288         pch_udc_ep_fifo_flush(ep, ep->in);
2289         pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2290         pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2291         val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2292         pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2293
2294         /* Initialize the SETUP buffer */
2295         pch_udc_init_setup_buff(ep->td_stp);
2296         /* Write the pointer address of dma descriptor */
2297         pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2298         /* Write the pointer address of Setup descriptor */
2299         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2300
2301         /* Initialize the dma descriptor */
2302         ep->td_data->status  = PCH_UDC_DMA_LAST;
2303         ep->td_data->dataptr = dev->dma_addr;
2304         ep->td_data->next    = ep->td_data_phys;
2305
2306         pch_udc_ep_clear_nak(ep);
2307 }
2308
2309
2310 /**
2311  * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2312  * @dev:        Reference to driver structure
2313  */
2314 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2315 {
2316         struct pch_udc_ep       *ep;
2317         int i;
2318
2319         pch_udc_clear_dma(dev, DMA_DIR_TX);
2320         pch_udc_clear_dma(dev, DMA_DIR_RX);
2321         /* Mask all endpoint interrupts */
2322         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2323         /* clear all endpoint interrupts */
2324         pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2325
2326         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2327                 ep = &dev->ep[i];
2328                 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2329                 pch_udc_clear_ep_control(ep);
2330                 pch_udc_ep_set_ddptr(ep, 0);
2331                 pch_udc_write_csr(ep->dev, 0x00, i);
2332         }
2333         dev->stall = 0;
2334         dev->prot_stall = 0;
2335         dev->waiting_zlp_ack = 0;
2336         dev->set_cfg_not_acked = 0;
2337
2338         /* disable ep to empty req queue. Skip the control EP's */
2339         for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2340                 ep = &dev->ep[i];
2341                 pch_udc_ep_set_nak(ep);
2342                 pch_udc_ep_fifo_flush(ep, ep->in);
2343                 /* Complete request queue */
2344                 empty_req_queue(ep);
2345         }
2346         if (dev->driver && dev->driver->disconnect)
2347                 dev->driver->disconnect(&dev->gadget);
2348 }
2349
2350 /**
2351  * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2352  *                              done interrupt
2353  * @dev:        Reference to driver structure
2354  */
2355 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2356 {
2357         u32 dev_stat, dev_speed;
2358         u32 speed = USB_SPEED_FULL;
2359
2360         dev_stat = pch_udc_read_device_status(dev);
2361         dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2362                                                  UDC_DEVSTS_ENUM_SPEED_SHIFT;
2363         switch (dev_speed) {
2364         case UDC_DEVSTS_ENUM_SPEED_HIGH:
2365                 speed = USB_SPEED_HIGH;
2366                 break;
2367         case  UDC_DEVSTS_ENUM_SPEED_FULL:
2368                 speed = USB_SPEED_FULL;
2369                 break;
2370         case  UDC_DEVSTS_ENUM_SPEED_LOW:
2371                 speed = USB_SPEED_LOW;
2372                 break;
2373         default:
2374                 BUG();
2375         }
2376         dev->gadget.speed = speed;
2377         pch_udc_activate_control_ep(dev);
2378         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2379         pch_udc_set_dma(dev, DMA_DIR_TX);
2380         pch_udc_set_dma(dev, DMA_DIR_RX);
2381         pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2382 }
2383
2384 /**
2385  * pch_udc_svc_intf_interrupt() - This function handles a set interface
2386  *                                interrupt
2387  * @dev:        Reference to driver structure
2388  */
2389 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2390 {
2391         u32 reg, dev_stat = 0;
2392         int i, ret;
2393
2394         dev_stat = pch_udc_read_device_status(dev);
2395         dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2396                                                          UDC_DEVSTS_INTF_SHIFT;
2397         dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2398                                                          UDC_DEVSTS_ALT_SHIFT;
2399         dev->set_cfg_not_acked = 1;
2400         /* Construct the usb request for gadget driver and inform it */
2401         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2402         dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2403         dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2404         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2405         dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2406         /* programm the Endpoint Cfg registers */
2407         /* Only one end point cfg register */
2408         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2409         reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2410               (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2411         reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2412               (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2413         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2414         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2415                 /* clear stall bits */
2416                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2417                 dev->ep[i].halted = 0;
2418         }
2419         dev->stall = 0;
2420         spin_unlock(&dev->lock);
2421         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2422         spin_lock(&dev->lock);
2423 }
2424
2425 /**
2426  * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2427  *                              interrupt
2428  * @dev:        Reference to driver structure
2429  */
2430 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2431 {
2432         int i, ret;
2433         u32 reg, dev_stat = 0;
2434
2435         dev_stat = pch_udc_read_device_status(dev);
2436         dev->set_cfg_not_acked = 1;
2437         dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2438                                 UDC_DEVSTS_CFG_SHIFT;
2439         /* make usb request for gadget driver */
2440         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2441         dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2442         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2443         /* program the NE registers */
2444         /* Only one end point cfg register */
2445         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2446         reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2447               (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2448         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2449         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2450                 /* clear stall bits */
2451                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2452                 dev->ep[i].halted = 0;
2453         }
2454         dev->stall = 0;
2455
2456         /* call gadget zero with setup data received */
2457         spin_unlock(&dev->lock);
2458         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2459         spin_lock(&dev->lock);
2460 }
2461
2462 /**
2463  * pch_udc_dev_isr() - This function services device interrupts
2464  *                      by invoking appropriate routines.
2465  * @dev:        Reference to the device structure
2466  * @dev_intr:   The Device interrupt status.
2467  */
2468 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2469 {
2470         /* USB Reset Interrupt */
2471         if (dev_intr & UDC_DEVINT_UR)
2472                 pch_udc_svc_ur_interrupt(dev);
2473         /* Enumeration Done Interrupt */
2474         if (dev_intr & UDC_DEVINT_ENUM)
2475                 pch_udc_svc_enum_interrupt(dev);
2476         /* Set Interface Interrupt */
2477         if (dev_intr & UDC_DEVINT_SI)
2478                 pch_udc_svc_intf_interrupt(dev);
2479         /* Set Config Interrupt */
2480         if (dev_intr & UDC_DEVINT_SC)
2481                 pch_udc_svc_cfg_interrupt(dev);
2482         /* USB Suspend interrupt */
2483         if (dev_intr & UDC_DEVINT_US)
2484                 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2485         /* Clear the SOF interrupt, if enabled */
2486         if (dev_intr & UDC_DEVINT_SOF)
2487                 dev_dbg(&dev->pdev->dev, "SOF\n");
2488         /* ES interrupt, IDLE > 3ms on the USB */
2489         if (dev_intr & UDC_DEVINT_ES)
2490                 dev_dbg(&dev->pdev->dev, "ES\n");
2491         /* RWKP interrupt */
2492         if (dev_intr & UDC_DEVINT_RWKP)
2493                 dev_dbg(&dev->pdev->dev, "RWKP\n");
2494 }
2495
2496 /**
2497  * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2498  * @irq:        Interrupt request number
2499  * @dev:        Reference to the device structure
2500  */
2501 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2502 {
2503         struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2504         u32 dev_intr, ep_intr;
2505         int i;
2506
2507         dev_intr = pch_udc_read_device_interrupts(dev);
2508         ep_intr = pch_udc_read_ep_interrupts(dev);
2509
2510         if (dev_intr)
2511                 /* Clear device interrupts */
2512                 pch_udc_write_device_interrupts(dev, dev_intr);
2513         if (ep_intr)
2514                 /* Clear ep interrupts */
2515                 pch_udc_write_ep_interrupts(dev, ep_intr);
2516         if (!dev_intr && !ep_intr)
2517                 return IRQ_NONE;
2518         spin_lock(&dev->lock);
2519         if (dev_intr)
2520                 pch_udc_dev_isr(dev, dev_intr);
2521         if (ep_intr) {
2522                 pch_udc_read_all_epstatus(dev, ep_intr);
2523                 /* Process Control In interrupts, if present */
2524                 if (ep_intr & UDC_EPINT_IN_EP0) {
2525                         pch_udc_svc_control_in(dev);
2526                         pch_udc_postsvc_epinters(dev, 0);
2527                 }
2528                 /* Process Control Out interrupts, if present */
2529                 if (ep_intr & UDC_EPINT_OUT_EP0)
2530                         pch_udc_svc_control_out(dev);
2531                 /* Process data in end point interrupts */
2532                 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2533                         if (ep_intr & (1 <<  i)) {
2534                                 pch_udc_svc_data_in(dev, i);
2535                                 pch_udc_postsvc_epinters(dev, i);
2536                         }
2537                 }
2538                 /* Process data out end point interrupts */
2539                 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2540                                                  PCH_UDC_USED_EP_NUM); i++)
2541                         if (ep_intr & (1 <<  i))
2542                                 pch_udc_svc_data_out(dev, i -
2543                                                          UDC_EPINT_OUT_SHIFT);
2544         }
2545         spin_unlock(&dev->lock);
2546         return IRQ_HANDLED;
2547 }
2548
2549 /**
2550  * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2551  * @dev:        Reference to the device structure
2552  */
2553 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2554 {
2555         /* enable ep0 interrupts */
2556         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2557                                                 UDC_EPINT_OUT_EP0);
2558         /* enable device interrupts */
2559         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2560                                        UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2561                                        UDC_DEVINT_SI | UDC_DEVINT_SC);
2562 }
2563
2564 /**
2565  * gadget_release() - Free the gadget driver private data
2566  * @pdev        reference to struct pci_dev
2567  */
2568 static void gadget_release(struct device *pdev)
2569 {
2570         struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2571
2572         kfree(dev);
2573 }
2574
2575 /**
2576  * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2577  * @dev:        Reference to the driver structure
2578  */
2579 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2580 {
2581         const char *const ep_string[] = {
2582                 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2583                 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2584                 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2585                 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2586                 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2587                 "ep15in", "ep15out",
2588         };
2589         int i;
2590
2591         dev->gadget.speed = USB_SPEED_UNKNOWN;
2592         INIT_LIST_HEAD(&dev->gadget.ep_list);
2593
2594         /* Initialize the endpoints structures */
2595         memset(dev->ep, 0, sizeof dev->ep);
2596         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2597                 struct pch_udc_ep *ep = &dev->ep[i];
2598                 ep->dev = dev;
2599                 ep->halted = 1;
2600                 ep->num = i / 2;
2601                 ep->in = ~i & 1;
2602                 ep->ep.name = ep_string[i];
2603                 ep->ep.ops = &pch_udc_ep_ops;
2604                 if (ep->in)
2605                         ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2606                 else
2607                         ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2608                                           UDC_EP_REG_SHIFT;
2609                 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2610                 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2611                 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2612                 INIT_LIST_HEAD(&ep->queue);
2613         }
2614         dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2615         dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2616
2617         /* remove ep0 in and out from the list.  They have own pointer */
2618         list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2619         list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2620
2621         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2622         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2623 }
2624
2625 /**
2626  * pch_udc_pcd_init() - This API initializes the driver structure
2627  * @dev:        Reference to the driver structure
2628  *
2629  * Return codes:
2630  *      0: Success
2631  */
2632 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2633 {
2634         pch_udc_init(dev);
2635         pch_udc_pcd_reinit(dev);
2636         return 0;
2637 }
2638
2639 /**
2640  * init_dma_pools() - create dma pools during initialization
2641  * @pdev:       reference to struct pci_dev
2642  */
2643 static int init_dma_pools(struct pch_udc_dev *dev)
2644 {
2645         struct pch_udc_stp_dma_desc     *td_stp;
2646         struct pch_udc_data_dma_desc    *td_data;
2647
2648         /* DMA setup */
2649         dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2650                 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2651         if (!dev->data_requests) {
2652                 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2653                         __func__);
2654                 return -ENOMEM;
2655         }
2656
2657         /* dma desc for setup data */
2658         dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2659                 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2660         if (!dev->stp_requests) {
2661                 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2662                         __func__);
2663                 return -ENOMEM;
2664         }
2665         /* setup */
2666         td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2667                                 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2668         if (!td_stp) {
2669                 dev_err(&dev->pdev->dev,
2670                         "%s: can't allocate setup dma descriptor\n", __func__);
2671                 return -ENOMEM;
2672         }
2673         dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2674
2675         /* data: 0 packets !? */
2676         td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2677                                 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2678         if (!td_data) {
2679                 dev_err(&dev->pdev->dev,
2680                         "%s: can't allocate data dma descriptor\n", __func__);
2681                 return -ENOMEM;
2682         }
2683         dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2684         dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2685         dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2686         dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2687         dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2688
2689         dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2690         if (!dev->ep0out_buf)
2691                 return -ENOMEM;
2692         dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2693                                        UDC_EP0OUT_BUFF_SIZE * 4,
2694                                        DMA_FROM_DEVICE);
2695         return 0;
2696 }
2697
2698 static int pch_udc_start(struct usb_gadget_driver *driver,
2699         int (*bind)(struct usb_gadget *))
2700 {
2701         struct pch_udc_dev      *dev = pch_udc;
2702         int                     retval;
2703
2704         if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
2705             !driver->setup || !driver->unbind || !driver->disconnect) {
2706                 dev_err(&dev->pdev->dev,
2707                         "%s: invalid driver parameter\n", __func__);
2708                 return -EINVAL;
2709         }
2710
2711         if (!dev)
2712                 return -ENODEV;
2713
2714         if (dev->driver) {
2715                 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2716                 return -EBUSY;
2717         }
2718         driver->driver.bus = NULL;
2719         dev->driver = driver;
2720         dev->gadget.dev.driver = &driver->driver;
2721
2722         /* Invoke the bind routine of the gadget driver */
2723         retval = bind(&dev->gadget);
2724
2725         if (retval) {
2726                 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2727                        __func__, driver->driver.name, retval);
2728                 dev->driver = NULL;
2729                 dev->gadget.dev.driver = NULL;
2730                 return retval;
2731         }
2732         /* get ready for ep0 traffic */
2733         pch_udc_setup_ep0(dev);
2734
2735         /* clear SD */
2736         pch_udc_clear_disconnect(dev);
2737
2738         dev->connected = 1;
2739         return 0;
2740 }
2741
2742 static int pch_udc_stop(struct usb_gadget_driver *driver)
2743 {
2744         struct pch_udc_dev      *dev = pch_udc;
2745
2746         if (!dev)
2747                 return -ENODEV;
2748
2749         if (!driver || (driver != dev->driver)) {
2750                 dev_err(&dev->pdev->dev,
2751                         "%s: invalid driver parameter\n", __func__);
2752                 return -EINVAL;
2753         }
2754
2755         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2756
2757         /* Assures that there are no pending requests with this driver */
2758         driver->disconnect(&dev->gadget);
2759         driver->unbind(&dev->gadget);
2760         dev->gadget.dev.driver = NULL;
2761         dev->driver = NULL;
2762         dev->connected = 0;
2763
2764         /* set SD */
2765         pch_udc_set_disconnect(dev);
2766         return 0;
2767 }
2768
2769 static void pch_udc_shutdown(struct pci_dev *pdev)
2770 {
2771         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2772
2773         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2774         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2775
2776         /* disable the pullup so the host will think we're gone */
2777         pch_udc_set_disconnect(dev);
2778 }
2779
2780 static void pch_udc_remove(struct pci_dev *pdev)
2781 {
2782         struct pch_udc_dev      *dev = pci_get_drvdata(pdev);
2783
2784         usb_del_gadget_udc(&dev->gadget);
2785
2786         /* gadget driver must not be registered */
2787         if (dev->driver)
2788                 dev_err(&pdev->dev,
2789                         "%s: gadget driver still bound!!!\n", __func__);
2790         /* dma pool cleanup */
2791         if (dev->data_requests)
2792                 pci_pool_destroy(dev->data_requests);
2793
2794         if (dev->stp_requests) {
2795                 /* cleanup DMA desc's for ep0in */
2796                 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2797                         pci_pool_free(dev->stp_requests,
2798                                 dev->ep[UDC_EP0OUT_IDX].td_stp,
2799                                 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2800                 }
2801                 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2802                         pci_pool_free(dev->stp_requests,
2803                                 dev->ep[UDC_EP0OUT_IDX].td_data,
2804                                 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2805                 }
2806                 pci_pool_destroy(dev->stp_requests);
2807         }
2808
2809         if (dev->dma_addr)
2810                 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
2811                                  UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
2812         kfree(dev->ep0out_buf);
2813
2814         pch_udc_exit(dev);
2815
2816         if (dev->irq_registered)
2817                 free_irq(pdev->irq, dev);
2818         if (dev->base_addr)
2819                 iounmap(dev->base_addr);
2820         if (dev->mem_region)
2821                 release_mem_region(dev->phys_addr,
2822                                    pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2823         if (dev->active)
2824                 pci_disable_device(pdev);
2825         if (dev->registered)
2826                 device_unregister(&dev->gadget.dev);
2827         kfree(dev);
2828         pci_set_drvdata(pdev, NULL);
2829 }
2830
2831 #ifdef CONFIG_PM
2832 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2833 {
2834         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2835
2836         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2837         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2838
2839         pci_disable_device(pdev);
2840         pci_enable_wake(pdev, PCI_D3hot, 0);
2841
2842         if (pci_save_state(pdev)) {
2843                 dev_err(&pdev->dev,
2844                         "%s: could not save PCI config state\n", __func__);
2845                 return -ENOMEM;
2846         }
2847         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2848         return 0;
2849 }
2850
2851 static int pch_udc_resume(struct pci_dev *pdev)
2852 {
2853         int ret;
2854
2855         pci_set_power_state(pdev, PCI_D0);
2856         pci_restore_state(pdev);
2857         ret = pci_enable_device(pdev);
2858         if (ret) {
2859                 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2860                 return ret;
2861         }
2862         pci_enable_wake(pdev, PCI_D3hot, 0);
2863         return 0;
2864 }
2865 #else
2866 #define pch_udc_suspend NULL
2867 #define pch_udc_resume  NULL
2868 #endif /* CONFIG_PM */
2869
2870 static int pch_udc_probe(struct pci_dev *pdev,
2871                           const struct pci_device_id *id)
2872 {
2873         unsigned long           resource;
2874         unsigned long           len;
2875         int                     retval;
2876         struct pch_udc_dev      *dev;
2877
2878         /* one udc only */
2879         if (pch_udc) {
2880                 pr_err("%s: already probed\n", __func__);
2881                 return -EBUSY;
2882         }
2883         /* init */
2884         dev = kzalloc(sizeof *dev, GFP_KERNEL);
2885         if (!dev) {
2886                 pr_err("%s: no memory for device structure\n", __func__);
2887                 return -ENOMEM;
2888         }
2889         /* pci setup */
2890         if (pci_enable_device(pdev) < 0) {
2891                 kfree(dev);
2892                 pr_err("%s: pci_enable_device failed\n", __func__);
2893                 return -ENODEV;
2894         }
2895         dev->active = 1;
2896         pci_set_drvdata(pdev, dev);
2897
2898         /* PCI resource allocation */
2899         resource = pci_resource_start(pdev, 1);
2900         len = pci_resource_len(pdev, 1);
2901
2902         if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2903                 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2904                 retval = -EBUSY;
2905                 goto finished;
2906         }
2907         dev->phys_addr = resource;
2908         dev->mem_region = 1;
2909
2910         dev->base_addr = ioremap_nocache(resource, len);
2911         if (!dev->base_addr) {
2912                 pr_err("%s: device memory cannot be mapped\n", __func__);
2913                 retval = -ENOMEM;
2914                 goto finished;
2915         }
2916         if (!pdev->irq) {
2917                 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2918                 retval = -ENODEV;
2919                 goto finished;
2920         }
2921         pch_udc = dev;
2922         /* initialize the hardware */
2923         if (pch_udc_pcd_init(dev))
2924                 goto finished;
2925         if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2926                         dev)) {
2927                 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2928                         pdev->irq);
2929                 retval = -ENODEV;
2930                 goto finished;
2931         }
2932         dev->irq = pdev->irq;
2933         dev->irq_registered = 1;
2934
2935         pci_set_master(pdev);
2936         pci_try_set_mwi(pdev);
2937
2938         /* device struct setup */
2939         spin_lock_init(&dev->lock);
2940         dev->pdev = pdev;
2941         dev->gadget.ops = &pch_udc_ops;
2942
2943         retval = init_dma_pools(dev);
2944         if (retval)
2945                 goto finished;
2946
2947         dev_set_name(&dev->gadget.dev, "gadget");
2948         dev->gadget.dev.parent = &pdev->dev;
2949         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2950         dev->gadget.dev.release = gadget_release;
2951         dev->gadget.name = KBUILD_MODNAME;
2952         dev->gadget.is_dualspeed = 1;
2953
2954         retval = device_register(&dev->gadget.dev);
2955         if (retval)
2956                 goto finished;
2957         dev->registered = 1;
2958
2959         /* Put the device in disconnected state till a driver is bound */
2960         pch_udc_set_disconnect(dev);
2961         retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
2962         if (retval)
2963                 goto finished;
2964         return 0;
2965
2966 finished:
2967         pch_udc_remove(pdev);
2968         return retval;
2969 }
2970
2971 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
2972         {
2973                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
2974                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2975                 .class_mask = 0xffffffff,
2976         },
2977         {
2978                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
2979                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2980                 .class_mask = 0xffffffff,
2981         },
2982         { 0 },
2983 };
2984
2985 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
2986
2987
2988 static struct pci_driver pch_udc_driver = {
2989         .name = KBUILD_MODNAME,
2990         .id_table =     pch_udc_pcidev_id,
2991         .probe =        pch_udc_probe,
2992         .remove =       pch_udc_remove,
2993         .suspend =      pch_udc_suspend,
2994         .resume =       pch_udc_resume,
2995         .shutdown =     pch_udc_shutdown,
2996 };
2997
2998 static int __init pch_udc_pci_init(void)
2999 {
3000         return pci_register_driver(&pch_udc_driver);
3001 }
3002 module_init(pch_udc_pci_init);
3003
3004 static void __exit pch_udc_pci_exit(void)
3005 {
3006         pci_unregister_driver(&pch_udc_driver);
3007 }
3008 module_exit(pch_udc_pci_exit);
3009
3010 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3011 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
3012 MODULE_LICENSE("GPL");